Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	13772	1			T8	1		T9	1		T41	1452
alert[0x1]	8326	1			T9	1		T16	23		T25	80
alert[0x2]	7232	1			T11	1		T41	1927		T59	40
alert[0x3]	12570	1			T142	1		T33	2890		T143	1
alert[0x4]	5498	1			T11	1		T41	1019		T142	1
alert[0x5]	12610	1			T16	590		T11	2		T142	1
alert[0x6]	5981	1			T16	621		T59	6		T34	9
alert[0x7]	8173	1			T41	577		T59	142		T129	1
alert[0x8]	5717	1			T16	33		T11	1		T142	1
alert[0x9]	10626	1			T25	79		T59	403		T33	43
alert[0xa]	8287	1			T8	1		T41	11		T142	1
alert[0xb]	14597	1			T245	1		T28	6		T47	683
alert[0xc]	9868	1			T8	1		T59	924		T143	1
alert[0xd]	5154	1			T142	1		T25	28		T59	28
alert[0xe]	3494	1			T41	113		T245	1		T25	414
alert[0xf]	14184	1			T41	3295		T25	325		T59	171
alert[0x10]	1194	1			T25	23		T59	40		T44	10
alert[0x11]	9530	1			T8	1		T59	245		T143	1
alert[0x12]	10591	1			T8	1		T16	22		T59	21
alert[0x13]	9116	1			T8	1		T41	113		T25	295
alert[0x14]	11999	1			T16	19		T31	1		T41	33
alert[0x15]	5582	1			T16	2		T17	1		T102	1
alert[0x16]	4183	1			T17	1		T245	1		T25	25
alert[0x17]	7971	1			T11	1		T142	1		T245	2
alert[0x18]	8419	1			T16	209		T11	1		T41	616
alert[0x19]	6543	1			T41	128		T25	18		T143	1
alert[0x1a]	11868	1			T11	1		T41	79		T142	1
alert[0x1b]	6109	1			T33	27		T143	1		T34	8
alert[0x1c]	12842	1			T11	2		T142	1		T245	1
alert[0x1d]	5776	1			T37	1		T245	1		T33	15
alert[0x1e]	3467	1			T16	29		T44	30		T46	1
alert[0x1f]	6715	1			T41	115		T245	1		T25	31
alert[0x20]	8338	1			T31	1		T41	35		T25	3
alert[0x21]	4444	1			T11	1		T25	112		T59	10
alert[0x22]	11188	1			T16	44		T41	2		T142	1
alert[0x23]	8394	1			T16	18		T142	1		T245	2
alert[0x24]	10347	1			T16	106		T41	269		T25	289
alert[0x25]	14234	1			T8	1		T25	22		T59	388
alert[0x26]	7181	1			T142	1		T24	1		T59	30
alert[0x27]	12651	1			T41	71		T142	2		T25	3223
alert[0x28]	6696	1			T245	1		T59	124		T33	114
alert[0x29]	9804	1			T41	1		T142	2		T101	2
alert[0x2a]	9360	1			T41	87		T24	1		T59	47
alert[0x2b]	9812	1			T11	1		T41	10		T245	1
alert[0x2c]	10821	1			T8	1		T9	1		T41	32
alert[0x2d]	7608	1			T10	2		T16	197		T37	1
alert[0x2e]	5575	1			T59	54		T33	29		T44	19
alert[0x2f]	13796	1			T16	28		T41	23		T34	9
alert[0x30]	7193	1			T8	1		T11	1		T59	27
alert[0x31]	8654	1			T41	23		T25	51		T59	1426
alert[0x32]	7058	1			T11	1		T25	382		T59	18
alert[0x33]	15501	1			T8	1		T41	284		T245	1
alert[0x34]	8573	1			T33	7		T47	173		T82	154
alert[0x35]	15362	1			T9	1		T25	2413		T33	9
alert[0x36]	8353	1			T8	1		T16	16		T41	102
alert[0x37]	5871	1			T41	21		T101	2		T25	87
alert[0x38]	4461	1			T16	10		T25	11		T34	15
alert[0x39]	7754	1			T41	15		T245	1		T101	4
alert[0x3a]	6130	1			T9	1		T11	1		T142	1
alert[0x3b]	3742	1			T8	1		T16	24		T11	1
alert[0x3c]	6518	1			T41	62		T25	108		T59	99
alert[0x3d]	6050	1			T11	1		T44	1		T132	162
alert[0x3e]	7742	1			T8	1		T16	10		T41	54
alert[0x3f]	5114	1			T142	1		T245	1		T33	136
alert[0x40]	17826	1			T142	1		T245	1		T25	18

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	197307	1			T9	1		T11	1		T101	4
class_i[0x1]	151765	1			T8	12		T9	1		T16	1994
class_i[0x2]	100776	1			T10	2		T17	2		T31	2
class_i[0x3]	110297	1			T8	1		T9	3		T16	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

559493

1

T16

2001

T41

10875

T101

8

alert_ping_fail

652

1

T8

13

T9

5

T10

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	13759	1			T41	1452		T25	2		T59	1130
alert_integrity_fail	alert[0x1]	8318	1			T16	23		T25	80		T33	157
alert_integrity_fail	alert[0x2]	7226	1			T41	1927		T59	40		T34	3
alert_integrity_fail	alert[0x3]	12557	1			T33	2890		T132	274		T82	10
alert_integrity_fail	alert[0x4]	5491	1			T41	1019		T25	15		T59	32
alert_integrity_fail	alert[0x5]	12593	1			T16	590		T25	44		T28	2
alert_integrity_fail	alert[0x6]	5968	1			T16	621		T59	6		T34	9
alert_integrity_fail	alert[0x7]	8153	1			T41	577		T59	142		T130	1
alert_integrity_fail	alert[0x8]	5708	1			T16	33		T25	43		T59	474
alert_integrity_fail	alert[0x9]	10619	1			T25	79		T59	403		T33	43
alert_integrity_fail	alert[0xa]	8279	1			T41	11		T59	367		T33	32
alert_integrity_fail	alert[0xb]	14588	1			T28	6		T47	683		T82	233
alert_integrity_fail	alert[0xc]	9859	1			T59	924		T34	28		T130	11
alert_integrity_fail	alert[0xd]	5145	1			T25	28		T59	28		T33	308
alert_integrity_fail	alert[0xe]	3481	1			T41	113		T25	414		T34	31
alert_integrity_fail	alert[0xf]	14180	1			T41	3295		T25	325		T59	171
alert_integrity_fail	alert[0x10]	1189	1			T25	23		T59	40		T44	10
alert_integrity_fail	alert[0x11]	9523	1			T59	245		T132	7		T116	25
alert_integrity_fail	alert[0x12]	10584	1			T16	22		T59	21		T33	2052
alert_integrity_fail	alert[0x13]	9092	1			T41	113		T25	295		T59	27
alert_integrity_fail	alert[0x14]	11984	1			T16	19		T41	33		T59	19
alert_integrity_fail	alert[0x15]	5574	1			T16	2		T59	329		T33	41
alert_integrity_fail	alert[0x16]	4163	1			T25	25		T34	5		T132	2251
alert_integrity_fail	alert[0x17]	7959	1			T24	6		T59	1631		T34	18
alert_integrity_fail	alert[0x18]	8411	1			T16	209		T41	616		T44	264
alert_integrity_fail	alert[0x19]	6537	1			T41	128		T25	18		T34	30
alert_integrity_fail	alert[0x1a]	11858	1			T41	79		T59	150		T33	39
alert_integrity_fail	alert[0x1b]	6102	1			T33	27		T34	8		T28	14
alert_integrity_fail	alert[0x1c]	12828	1			T25	6		T59	38		T33	131
alert_integrity_fail	alert[0x1d]	5768	1			T33	15		T132	22		T116	17
alert_integrity_fail	alert[0x1e]	3462	1			T16	29		T44	30		T46	1
alert_integrity_fail	alert[0x1f]	6703	1			T41	115		T25	31		T59	232
alert_integrity_fail	alert[0x20]	8325	1			T41	35		T25	3		T33	20
alert_integrity_fail	alert[0x21]	4434	1			T25	112		T59	10		T34	71
alert_integrity_fail	alert[0x22]	11180	1			T16	44		T41	2		T25	3
alert_integrity_fail	alert[0x23]	8382	1			T16	18		T59	24		T44	12
alert_integrity_fail	alert[0x24]	10340	1			T16	106		T41	269		T25	289
alert_integrity_fail	alert[0x25]	14224	1			T25	22		T59	388		T34	113
alert_integrity_fail	alert[0x26]	7174	1			T24	1		T59	30		T33	1315
alert_integrity_fail	alert[0x27]	12637	1			T41	71		T25	3223		T59	70
alert_integrity_fail	alert[0x28]	6675	1			T59	124		T33	114		T44	7
alert_integrity_fail	alert[0x29]	9792	1			T41	1		T101	2		T59	201
alert_integrity_fail	alert[0x2a]	9349	1			T41	87		T24	1		T59	47
alert_integrity_fail	alert[0x2b]	9800	1			T41	10		T25	83		T34	19
alert_integrity_fail	alert[0x2c]	10815	1			T41	32		T25	34		T59	46
alert_integrity_fail	alert[0x2d]	7595	1			T16	197		T41	269		T33	16
alert_integrity_fail	alert[0x2e]	5567	1			T59	54		T33	29		T44	19
alert_integrity_fail	alert[0x2f]	13789	1			T16	28		T41	23		T34	9
alert_integrity_fail	alert[0x30]	7182	1			T59	27		T82	49		T75	1
alert_integrity_fail	alert[0x31]	8644	1			T41	23		T25	51		T59	1426
alert_integrity_fail	alert[0x32]	7045	1			T25	382		T59	18		T33	1259
alert_integrity_fail	alert[0x33]	15493	1			T41	284		T33	500		T28	5
alert_integrity_fail	alert[0x34]	8570	1			T33	7		T47	173		T82	154
alert_integrity_fail	alert[0x35]	15353	1			T25	2413		T33	9		T34	76
alert_integrity_fail	alert[0x36]	8348	1			T16	16		T41	102		T25	17
alert_integrity_fail	alert[0x37]	5858	1			T41	21		T101	2		T25	87
alert_integrity_fail	alert[0x38]	4458	1			T16	10		T25	11		T34	15
alert_integrity_fail	alert[0x39]	7746	1			T41	15		T101	4		T34	159
alert_integrity_fail	alert[0x3a]	6113	1			T25	19		T59	26		T34	44
alert_integrity_fail	alert[0x3b]	3733	1			T16	24		T41	37		T24	1
alert_integrity_fail	alert[0x3c]	6511	1			T41	62		T25	108		T59	99
alert_integrity_fail	alert[0x3d]	6042	1			T44	1		T132	162		T46	1
alert_integrity_fail	alert[0x3e]	7733	1			T16	10		T41	54		T59	5
alert_integrity_fail	alert[0x3f]	5109	1			T33	136		T34	60		T44	151
alert_integrity_fail	alert[0x40]	17816	1			T25	18		T33	136		T34	53
alert_ping_fail	alert[0x0]	13	1			T8	1		T9	1		T121	1
alert_ping_fail	alert[0x1]	8	1			T9	1		T118	1		T295	1
alert_ping_fail	alert[0x2]	6	1			T11	1		T68	1		T137	1
alert_ping_fail	alert[0x3]	13	1			T142	1		T143	1		T129	1
alert_ping_fail	alert[0x4]	7	1			T11	1		T142	1		T121	1
alert_ping_fail	alert[0x5]	17	1			T11	2		T142	1		T118	1
alert_ping_fail	alert[0x6]	13	1			T127	1		T296	1		T137	1
alert_ping_fail	alert[0x7]	20	1			T129	1		T68	1		T72	1
alert_ping_fail	alert[0x8]	9	1			T11	1		T142	1		T68	1
alert_ping_fail	alert[0x9]	7	1			T297	1		T282	2		T298	1
alert_ping_fail	alert[0xa]	8	1			T8	1		T142	1		T93	1
alert_ping_fail	alert[0xb]	9	1			T245	1		T299	1		T137	1
alert_ping_fail	alert[0xc]	9	1			T8	1		T143	1		T300	2
alert_ping_fail	alert[0xd]	9	1			T142	1		T299	1		T297	2
alert_ping_fail	alert[0xe]	13	1			T245	1		T121	1		T301	1
alert_ping_fail	alert[0xf]	4	1			T298	1		T302	1		T303	1
alert_ping_fail	alert[0x10]	5	1			T299	1		T298	1		T304	1
alert_ping_fail	alert[0x11]	7	1			T8	1		T143	1		T72	1
alert_ping_fail	alert[0x12]	7	1			T8	1		T296	1		T137	1
alert_ping_fail	alert[0x13]	24	1			T8	1		T127	1		T121	1
alert_ping_fail	alert[0x14]	15	1			T31	1		T60	1		T301	1
alert_ping_fail	alert[0x15]	8	1			T17	1		T102	1		T245	1
alert_ping_fail	alert[0x16]	20	1			T17	1		T245	1		T66	1
alert_ping_fail	alert[0x17]	12	1			T11	1		T142	1		T245	2
alert_ping_fail	alert[0x18]	8	1			T11	1		T245	1		T301	1
alert_ping_fail	alert[0x19]	6	1			T143	1		T121	1		T305	1
alert_ping_fail	alert[0x1a]	10	1			T11	1		T142	1		T121	1
alert_ping_fail	alert[0x1b]	7	1			T143	1		T306	1		T137	1
alert_ping_fail	alert[0x1c]	14	1			T11	2		T142	1		T245	1
alert_ping_fail	alert[0x1d]	8	1			T37	1		T245	1		T306	1
alert_ping_fail	alert[0x1e]	5	1			T306	1		T300	1		T307	1
alert_ping_fail	alert[0x1f]	12	1			T245	1		T306	1		T308	1
alert_ping_fail	alert[0x20]	13	1			T31	1		T118	1		T301	1
alert_ping_fail	alert[0x21]	10	1			T11	1		T295	1		T309	1
alert_ping_fail	alert[0x22]	8	1			T142	1		T310	1		T137	1
alert_ping_fail	alert[0x23]	12	1			T142	1		T245	2		T295	1
alert_ping_fail	alert[0x24]	7	1			T306	1		T311	1		T312	1
alert_ping_fail	alert[0x25]	10	1			T8	1		T121	1		T298	2
alert_ping_fail	alert[0x26]	7	1			T142	1		T72	1		T301	1
alert_ping_fail	alert[0x27]	14	1			T142	2		T121	1		T68	1
alert_ping_fail	alert[0x28]	21	1			T245	1		T121	1		T311	1
alert_ping_fail	alert[0x29]	12	1			T142	2		T68	1		T72	1
alert_ping_fail	alert[0x2a]	11	1			T121	1		T68	1		T296	1
alert_ping_fail	alert[0x2b]	12	1			T11	1		T245	1		T68	1
alert_ping_fail	alert[0x2c]	6	1			T8	1		T9	1		T60	1
alert_ping_fail	alert[0x2d]	13	1			T10	2		T37	1		T143	1
alert_ping_fail	alert[0x2e]	8	1			T310	1		T313	1		T137	2
alert_ping_fail	alert[0x2f]	7	1			T68	1		T72	2		T314	1
alert_ping_fail	alert[0x30]	11	1			T8	1		T11	1		T118	1
alert_ping_fail	alert[0x31]	10	1			T121	2		T306	1		T296	1
alert_ping_fail	alert[0x32]	13	1			T11	1		T311	1		T296	1
alert_ping_fail	alert[0x33]	8	1			T8	1		T245	1		T68	1
alert_ping_fail	alert[0x34]	3	1			T306	1		T299	1		T315	1
alert_ping_fail	alert[0x35]	9	1			T9	1		T299	1		T300	1
alert_ping_fail	alert[0x36]	5	1			T8	1		T129	1		T298	1
alert_ping_fail	alert[0x37]	13	1			T306	1		T137	1		T300	3
alert_ping_fail	alert[0x38]	3	1			T295	1		T300	1		T302	1
alert_ping_fail	alert[0x39]	8	1			T245	1		T143	1		T121	1
alert_ping_fail	alert[0x3a]	17	1			T9	1		T11	1		T142	1
alert_ping_fail	alert[0x3b]	9	1			T8	1		T11	1		T301	1
alert_ping_fail	alert[0x3c]	7	1			T297	2		T137	1		T316	2
alert_ping_fail	alert[0x3d]	8	1			T11	1		T306	1		T317	1
alert_ping_fail	alert[0x3e]	9	1			T8	1		T121	1		T306	1
alert_ping_fail	alert[0x3f]	5	1			T142	1		T245	1		T137	1
alert_ping_fail	alert[0x40]	10	1			T142	1		T245	1		T306	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	197188	1			T101	4		T24	3		T25	106
alert_integrity_fail	class_i[0x1]	151589	1			T16	1994		T25	8049		T59	9
alert_integrity_fail	class_i[0x2]	100604	1			T25	232		T59	1		T34	683
alert_integrity_fail	class_i[0x3]	110112	1			T16	7		T41	10875		T101	4
alert_ping_fail	class_i[0x0]	119	1			T9	1		T11	1		T143	6
alert_ping_fail	class_i[0x1]	176	1			T8	12		T9	1		T11	14
alert_ping_fail	class_i[0x2]	172	1			T10	2		T17	2		T31	2
alert_ping_fail	class_i[0x3]	185	1			T8	1		T9	3		T37	2