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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.68 100.00 100.00 100.00 99.38 99.48


Total test records in report: 830
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T777 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4186569919 May 05 02:57:51 PM PDT 24 May 05 02:59:34 PM PDT 24 9076153931 ps
T195 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.868825321 May 05 02:57:54 PM PDT 24 May 05 02:59:00 PM PDT 24 3693750298 ps
T153 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3159718800 May 05 02:58:09 PM PDT 24 May 05 03:02:44 PM PDT 24 7930374153 ps
T778 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3775981853 May 05 02:58:25 PM PDT 24 May 05 02:58:33 PM PDT 24 170243311 ps
T169 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3326244621 May 05 02:58:22 PM PDT 24 May 05 03:02:44 PM PDT 24 2159570448 ps
T779 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2940111127 May 05 02:57:54 PM PDT 24 May 05 02:58:04 PM PDT 24 501136623 ps
T780 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3021345386 May 05 02:58:37 PM PDT 24 May 05 02:58:58 PM PDT 24 345238093 ps
T781 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3407912454 May 05 02:58:49 PM PDT 24 May 05 02:58:51 PM PDT 24 8118891 ps
T782 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4009769707 May 05 02:58:37 PM PDT 24 May 05 02:59:24 PM PDT 24 1445693053 ps
T783 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2991157946 May 05 02:58:22 PM PDT 24 May 05 02:58:24 PM PDT 24 9065079 ps
T174 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1379585859 May 05 02:57:57 PM PDT 24 May 05 03:03:01 PM PDT 24 2367596485 ps
T784 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4046231542 May 05 02:58:45 PM PDT 24 May 05 02:58:51 PM PDT 24 114797534 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2499510776 May 05 02:57:45 PM PDT 24 May 05 02:57:51 PM PDT 24 69762958 ps
T786 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.449722403 May 05 02:58:44 PM PDT 24 May 05 02:59:07 PM PDT 24 364604647 ps
T787 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3655243557 May 05 02:58:50 PM PDT 24 May 05 02:58:52 PM PDT 24 9859140 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4059526400 May 05 02:57:45 PM PDT 24 May 05 02:57:51 PM PDT 24 75899213 ps
T157 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.440018639 May 05 02:58:24 PM PDT 24 May 05 03:10:20 PM PDT 24 27161440678 ps
T789 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.574901842 May 05 02:57:45 PM PDT 24 May 05 02:57:51 PM PDT 24 37530331 ps
T194 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1945859713 May 05 02:58:31 PM PDT 24 May 05 02:59:13 PM PDT 24 1388756443 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.990652769 May 05 02:58:35 PM PDT 24 May 05 02:59:13 PM PDT 24 1243060585 ps
T791 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2298931293 May 05 02:58:44 PM PDT 24 May 05 02:58:46 PM PDT 24 12000963 ps
T154 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2263224445 May 05 02:57:50 PM PDT 24 May 05 03:02:27 PM PDT 24 7852253304 ps
T200 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2103681535 May 05 02:58:35 PM PDT 24 May 05 02:58:39 PM PDT 24 59585363 ps
T163 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3457128432 May 05 02:58:10 PM PDT 24 May 05 03:17:05 PM PDT 24 31379113338 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4226483325 May 05 02:57:44 PM PDT 24 May 05 02:57:47 PM PDT 24 79326226 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.42996002 May 05 02:57:44 PM PDT 24 May 05 02:57:46 PM PDT 24 8673975 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.628701091 May 05 02:58:22 PM PDT 24 May 05 02:58:28 PM PDT 24 38470116 ps
T160 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1348423884 May 05 02:58:25 PM PDT 24 May 05 03:00:55 PM PDT 24 10201556893 ps
T795 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2768623584 May 05 02:58:14 PM PDT 24 May 05 02:58:19 PM PDT 24 240294670 ps
T796 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3007728366 May 05 02:58:13 PM PDT 24 May 05 02:58:18 PM PDT 24 36046783 ps
T178 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.641514908 May 05 02:58:41 PM PDT 24 May 05 03:01:52 PM PDT 24 6375643334 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1141034865 May 05 02:58:03 PM PDT 24 May 05 02:58:05 PM PDT 24 12866616 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2367859216 May 05 02:58:10 PM PDT 24 May 05 02:58:17 PM PDT 24 129434680 ps
T799 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2970722165 May 05 02:58:11 PM PDT 24 May 05 02:58:20 PM PDT 24 2036828395 ps
T176 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1692637824 May 05 02:58:40 PM PDT 24 May 05 03:17:51 PM PDT 24 67759264991 ps
T161 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3615771900 May 05 02:58:15 PM PDT 24 May 05 02:59:52 PM PDT 24 881643543 ps
T800 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1838444406 May 05 02:58:19 PM PDT 24 May 05 02:58:21 PM PDT 24 14358804 ps
T801 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2951350927 May 05 02:58:53 PM PDT 24 May 05 02:58:55 PM PDT 24 16382584 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3786505301 May 05 02:57:55 PM PDT 24 May 05 02:58:01 PM PDT 24 59965798 ps
T187 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1028294595 May 05 02:58:24 PM PDT 24 May 05 02:58:56 PM PDT 24 4025870827 ps
T342 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1446183582 May 05 02:57:45 PM PDT 24 May 05 03:05:55 PM PDT 24 29652711622 ps
T803 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3491644954 May 05 02:58:18 PM PDT 24 May 05 03:01:12 PM PDT 24 19233516701 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3951970916 May 05 02:57:47 PM PDT 24 May 05 03:06:17 PM PDT 24 30490657746 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.90759315 May 05 02:57:56 PM PDT 24 May 05 02:58:01 PM PDT 24 136708833 ps
T806 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1019922371 May 05 02:58:38 PM PDT 24 May 05 02:58:44 PM PDT 24 67488134 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3557094128 May 05 02:57:47 PM PDT 24 May 05 02:57:59 PM PDT 24 85230366 ps
T808 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1699428682 May 05 02:58:53 PM PDT 24 May 05 02:58:55 PM PDT 24 13805629 ps
T809 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1789900621 May 05 02:57:44 PM PDT 24 May 05 02:58:57 PM PDT 24 1191164591 ps
T196 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1682190521 May 05 02:57:56 PM PDT 24 May 05 02:59:16 PM PDT 24 7370467746 ps
T810 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3070027119 May 05 02:58:42 PM PDT 24 May 05 02:58:44 PM PDT 24 9540692 ps
T811 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.594488391 May 05 02:57:58 PM PDT 24 May 05 02:58:11 PM PDT 24 294264806 ps
T812 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3802488762 May 05 02:58:42 PM PDT 24 May 05 02:59:27 PM PDT 24 1362705622 ps
T813 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1034097635 May 05 02:58:17 PM PDT 24 May 05 02:58:20 PM PDT 24 172648105 ps
T814 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2346452905 May 05 02:58:23 PM PDT 24 May 05 02:58:25 PM PDT 24 15325940 ps
T815 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.787549907 May 05 02:57:57 PM PDT 24 May 05 02:58:08 PM PDT 24 92928766 ps
T816 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3820893457 May 05 02:57:48 PM PDT 24 May 05 03:01:10 PM PDT 24 15440889262 ps
T177 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.859252249 May 05 02:58:06 PM PDT 24 May 05 03:14:41 PM PDT 24 24064917847 ps
T817 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1967878975 May 05 02:58:50 PM PDT 24 May 05 02:58:52 PM PDT 24 6500045 ps
T170 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3136826334 May 05 02:58:31 PM PDT 24 May 05 03:08:22 PM PDT 24 8210500563 ps
T818 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4020070777 May 05 02:58:18 PM PDT 24 May 05 02:58:50 PM PDT 24 2180973812 ps
T162 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.182514727 May 05 02:58:35 PM PDT 24 May 05 03:02:57 PM PDT 24 7694167552 ps
T190 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2317634564 May 05 02:58:32 PM PDT 24 May 05 02:58:39 PM PDT 24 143100017 ps
T188 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.407944774 May 05 02:57:47 PM PDT 24 May 05 02:58:06 PM PDT 24 641602554 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2210860168 May 05 02:57:56 PM PDT 24 May 05 02:58:15 PM PDT 24 1292116137 ps
T820 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1229404253 May 05 02:58:38 PM PDT 24 May 05 02:58:48 PM PDT 24 122321301 ps
T343 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.883315311 May 05 02:58:36 PM PDT 24 May 05 03:07:10 PM PDT 24 25666501999 ps
T821 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.506646218 May 05 02:58:37 PM PDT 24 May 05 02:59:16 PM PDT 24 3446415519 ps
T822 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3324187541 May 05 02:58:50 PM PDT 24 May 05 02:58:52 PM PDT 24 20897998 ps
T340 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1623353334 May 05 02:58:10 PM PDT 24 May 05 03:02:59 PM PDT 24 4640651680 ps
T823 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1158445054 May 05 02:58:06 PM PDT 24 May 05 02:58:15 PM PDT 24 96394995 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1247784242 May 05 02:58:43 PM PDT 24 May 05 02:58:49 PM PDT 24 273740257 ps
T192 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3238861863 May 05 02:58:02 PM PDT 24 May 05 02:58:06 PM PDT 24 110907344 ps
T825 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2575461451 May 05 02:58:48 PM PDT 24 May 05 02:58:50 PM PDT 24 6244351 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4013247536 May 05 02:57:48 PM PDT 24 May 05 02:57:56 PM PDT 24 111350588 ps
T179 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2514856635 May 05 02:57:48 PM PDT 24 May 05 03:06:52 PM PDT 24 30431379277 ps
T827 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1261157784 May 05 02:57:46 PM PDT 24 May 05 02:58:05 PM PDT 24 657476452 ps
T828 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.329119190 May 05 02:58:03 PM PDT 24 May 05 02:58:12 PM PDT 24 365193581 ps
T829 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1758678780 May 05 02:58:26 PM PDT 24 May 05 02:58:36 PM PDT 24 1469336366 ps
T341 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1601947839 May 05 02:58:31 PM PDT 24 May 05 03:07:16 PM PDT 24 8044196499 ps
T830 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2849799121 May 05 02:58:47 PM PDT 24 May 05 02:58:49 PM PDT 24 8483965 ps

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.820580370
Short name T6
Test name
Test status
Simulation time 57086916723 ps
CPU time 725.69 seconds
Started May 05 02:24:39 PM PDT 24
Finished May 05 02:36:45 PM PDT 24
Peak memory 265180 kb
Host smart-fd95575b-f812-4fd1-95ef-267292eec3a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820580370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.820580370
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.804258873
Short name T25
Test name
Test status
Simulation time 318248354996 ps
CPU time 7509.24 seconds
Started May 05 02:18:45 PM PDT 24
Finished May 05 04:23:56 PM PDT 24
Peak memory 371680 kb
Host smart-bca83e02-b370-48d2-b29b-42ee4ec39708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804258873 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.804258873
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2489277922
Short name T4
Test name
Test status
Simulation time 708402789 ps
CPU time 21.61 seconds
Started May 05 02:18:38 PM PDT 24
Finished May 05 02:19:01 PM PDT 24
Peak memory 277456 kb
Host smart-782ca9b8-f098-4507-83d3-d223990e14c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2489277922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2489277922
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1067759239
Short name T15
Test name
Test status
Simulation time 469234258224 ps
CPU time 1364.64 seconds
Started May 05 02:20:17 PM PDT 24
Finished May 05 02:43:02 PM PDT 24
Peak memory 273336 kb
Host smart-b69c95ca-8cd5-41a3-869b-a519bbff440f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067759239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1067759239
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3550787393
Short name T180
Test name
Test status
Simulation time 1203406631 ps
CPU time 40.05 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 02:59:23 PM PDT 24
Peak memory 239816 kb
Host smart-583df3a2-7a62-4f60-bb0f-d77d014e1dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3550787393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3550787393
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.493283333
Short name T86
Test name
Test status
Simulation time 329370514676 ps
CPU time 3903.19 seconds
Started May 05 02:18:57 PM PDT 24
Finished May 05 03:24:01 PM PDT 24
Peak memory 306208 kb
Host smart-b47b7a47-1616-487b-ae4a-9b01d78bf316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493283333 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.493283333
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2217524579
Short name T28
Test name
Test status
Simulation time 201080457248 ps
CPU time 2993.7 seconds
Started May 05 02:24:18 PM PDT 24
Finished May 05 03:14:12 PM PDT 24
Peak memory 289256 kb
Host smart-5eb50e19-1f95-4bd9-88a6-dbbfe5dd1ca5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217524579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2217524579
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2112176835
Short name T12
Test name
Test status
Simulation time 599800646 ps
CPU time 28.14 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:19:13 PM PDT 24
Peak memory 270444 kb
Host smart-117464ab-caa9-4084-b685-5869eb42fbce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2112176835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2112176835
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3084915169
Short name T99
Test name
Test status
Simulation time 29741550871 ps
CPU time 1642.28 seconds
Started May 05 02:22:43 PM PDT 24
Finished May 05 02:50:06 PM PDT 24
Peak memory 305968 kb
Host smart-b54659d0-1fea-4914-8520-4869553cdd33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084915169 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3084915169
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2961421578
Short name T148
Test name
Test status
Simulation time 9935335205 ps
CPU time 179.23 seconds
Started May 05 02:57:56 PM PDT 24
Finished May 05 03:00:56 PM PDT 24
Peak memory 265436 kb
Host smart-bd391f98-0593-4021-88cc-93d6b6f838b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2961421578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2961421578
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2381166196
Short name T47
Test name
Test status
Simulation time 11179925696 ps
CPU time 1140.28 seconds
Started May 05 02:25:28 PM PDT 24
Finished May 05 02:44:29 PM PDT 24
Peak memory 289728 kb
Host smart-3f5113f4-00ff-41c4-903b-9a63b8e6451e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381166196 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2381166196
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4274889291
Short name T8
Test name
Test status
Simulation time 11578897312 ps
CPU time 459.97 seconds
Started May 05 02:26:26 PM PDT 24
Finished May 05 02:34:07 PM PDT 24
Peak memory 255728 kb
Host smart-feef6d5f-1011-481c-b04b-ae35323c316c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274889291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4274889291
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2108984817
Short name T17
Test name
Test status
Simulation time 111694889712 ps
CPU time 1503.56 seconds
Started May 05 02:18:51 PM PDT 24
Finished May 05 02:43:55 PM PDT 24
Peak memory 265420 kb
Host smart-ef2e1241-126a-494d-ad9f-f312bc2cdf98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108984817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2108984817
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.606418103
Short name T165
Test name
Test status
Simulation time 14861048763 ps
CPU time 962.22 seconds
Started May 05 02:57:50 PM PDT 24
Finished May 05 03:13:53 PM PDT 24
Peak memory 265420 kb
Host smart-d20729c1-1433-40eb-8e46-3cb5e5981119
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606418103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.606418103
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2998212155
Short name T5
Test name
Test status
Simulation time 177556896 ps
CPU time 10.46 seconds
Started May 05 02:18:33 PM PDT 24
Finished May 05 02:18:45 PM PDT 24
Peak memory 248704 kb
Host smart-9d8fdc68-7f17-4f00-98fb-f78269a49f51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2998212155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2998212155
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1084337231
Short name T156
Test name
Test status
Simulation time 23455783993 ps
CPU time 284.87 seconds
Started May 05 02:58:38 PM PDT 24
Finished May 05 03:03:24 PM PDT 24
Peak memory 265404 kb
Host smart-b3375e9e-b122-416d-9d92-49d493da1ce5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1084337231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1084337231
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2149845591
Short name T104
Test name
Test status
Simulation time 257809971217 ps
CPU time 4256.92 seconds
Started May 05 02:20:08 PM PDT 24
Finished May 05 03:31:06 PM PDT 24
Peak memory 305420 kb
Host smart-30983c15-2770-45a3-ae88-1166240c263f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149845591 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2149845591
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.748382408
Short name T94
Test name
Test status
Simulation time 148519754916 ps
CPU time 2119.17 seconds
Started May 05 02:20:57 PM PDT 24
Finished May 05 02:56:17 PM PDT 24
Peak memory 281592 kb
Host smart-80284cfe-711a-475a-8be1-789a7dc5e9ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748382408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.748382408
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.440018639
Short name T157
Test name
Test status
Simulation time 27161440678 ps
CPU time 715.77 seconds
Started May 05 02:58:24 PM PDT 24
Finished May 05 03:10:20 PM PDT 24
Peak memory 265444 kb
Host smart-5e5fa676-7df2-42ff-bb14-32f3dfe42b44
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440018639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.440018639
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1217244526
Short name T37
Test name
Test status
Simulation time 55936988947 ps
CPU time 3095.74 seconds
Started May 05 02:20:33 PM PDT 24
Finished May 05 03:12:09 PM PDT 24
Peak memory 281548 kb
Host smart-b4a2fd28-a840-42f8-9abd-25fc4671077c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217244526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1217244526
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4000363642
Short name T41
Test name
Test status
Simulation time 44145202870 ps
CPU time 1180.16 seconds
Started May 05 02:24:17 PM PDT 24
Finished May 05 02:43:57 PM PDT 24
Peak memory 265240 kb
Host smart-80922bc7-3d89-4594-ad18-6d5371cc8896
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000363642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4000363642
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.22456114
Short name T250
Test name
Test status
Simulation time 9800938 ps
CPU time 1.58 seconds
Started May 05 02:58:32 PM PDT 24
Finished May 05 02:58:34 PM PDT 24
Peak memory 235988 kb
Host smart-f08229c3-3079-4a97-9a3a-345e3e90180a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=22456114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.22456114
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3384026968
Short name T142
Test name
Test status
Simulation time 26292182438 ps
CPU time 523.95 seconds
Started May 05 02:18:50 PM PDT 24
Finished May 05 02:27:34 PM PDT 24
Peak memory 248020 kb
Host smart-eb362c99-669e-405f-9389-2f6f8a356738
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384026968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3384026968
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3136826334
Short name T170
Test name
Test status
Simulation time 8210500563 ps
CPU time 589.89 seconds
Started May 05 02:58:31 PM PDT 24
Finished May 05 03:08:22 PM PDT 24
Peak memory 272656 kb
Host smart-3b65c9e0-a420-4161-b0f5-229fa8449db4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136826334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3136826334
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2040652171
Short name T149
Test name
Test status
Simulation time 3366979087 ps
CPU time 200.28 seconds
Started May 05 02:58:24 PM PDT 24
Finished May 05 03:01:45 PM PDT 24
Peak memory 265424 kb
Host smart-1281b89e-77fd-4818-b42f-f0e395a5692a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2040652171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2040652171
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.508737212
Short name T10
Test name
Test status
Simulation time 175918356320 ps
CPU time 2301.32 seconds
Started May 05 02:26:01 PM PDT 24
Finished May 05 03:04:23 PM PDT 24
Peak memory 288636 kb
Host smart-aa645024-0e66-4c67-ae8a-c56c0e6fbbb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508737212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.508737212
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1692637824
Short name T176
Test name
Test status
Simulation time 67759264991 ps
CPU time 1150.22 seconds
Started May 05 02:58:40 PM PDT 24
Finished May 05 03:17:51 PM PDT 24
Peak memory 265208 kb
Host smart-eb92e487-8821-46b3-b130-e75d84be4906
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692637824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1692637824
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2762452230
Short name T306
Test name
Test status
Simulation time 14199800729 ps
CPU time 543.86 seconds
Started May 05 02:21:25 PM PDT 24
Finished May 05 02:30:29 PM PDT 24
Peak memory 248068 kb
Host smart-84577f8d-656a-4558-87d9-8350c3de909b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762452230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2762452230
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4264116502
Short name T310
Test name
Test status
Simulation time 824876940598 ps
CPU time 2735.72 seconds
Started May 05 02:23:49 PM PDT 24
Finished May 05 03:09:25 PM PDT 24
Peak memory 286612 kb
Host smart-6f01a631-3294-4cda-82d4-f52f4116fb37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264116502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4264116502
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2860554426
Short name T82
Test name
Test status
Simulation time 138176468628 ps
CPU time 1268.12 seconds
Started May 05 02:19:44 PM PDT 24
Finished May 05 02:40:52 PM PDT 24
Peak memory 281528 kb
Host smart-3e1261cc-b4f5-43f3-ab21-ed71b63f0f67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860554426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2860554426
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1424349014
Short name T309
Test name
Test status
Simulation time 102874962751 ps
CPU time 319.82 seconds
Started May 05 02:25:16 PM PDT 24
Finished May 05 02:30:36 PM PDT 24
Peak memory 256432 kb
Host smart-a2250ea3-54cb-4c58-b950-ebf9c9fc3721
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424349014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1424349014
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3159718800
Short name T153
Test name
Test status
Simulation time 7930374153 ps
CPU time 274.95 seconds
Started May 05 02:58:09 PM PDT 24
Finished May 05 03:02:44 PM PDT 24
Peak memory 266468 kb
Host smart-8310d5ec-e9b9-4c51-9861-c64e50efcdc8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3159718800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3159718800
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4178567104
Short name T730
Test name
Test status
Simulation time 12301294 ps
CPU time 1.34 seconds
Started May 05 02:58:50 PM PDT 24
Finished May 05 02:58:52 PM PDT 24
Peak memory 236904 kb
Host smart-c064662d-1c83-4c2c-b4fc-d4023057edc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4178567104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4178567104
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2413750103
Short name T113
Test name
Test status
Simulation time 145955200681 ps
CPU time 6844.05 seconds
Started May 05 02:18:31 PM PDT 24
Finished May 05 04:12:37 PM PDT 24
Peak memory 394920 kb
Host smart-fca9d857-754f-4e69-8817-211f378d06fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413750103 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2413750103
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3326244621
Short name T169
Test name
Test status
Simulation time 2159570448 ps
CPU time 261.61 seconds
Started May 05 02:58:22 PM PDT 24
Finished May 05 03:02:44 PM PDT 24
Peak memory 265404 kb
Host smart-7597b70f-df34-4df9-99f5-2dc7dd4809a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326244621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3326244621
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1265173821
Short name T100
Test name
Test status
Simulation time 49277302447 ps
CPU time 2592.61 seconds
Started May 05 02:18:55 PM PDT 24
Finished May 05 03:02:09 PM PDT 24
Peak memory 280784 kb
Host smart-3811c09c-4930-4320-8ec1-22923ec5fe3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265173821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1265173821
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3212873712
Short name T18
Test name
Test status
Simulation time 1861810404 ps
CPU time 28.98 seconds
Started May 05 02:23:45 PM PDT 24
Finished May 05 02:24:14 PM PDT 24
Peak memory 248776 kb
Host smart-f41517f3-569b-421b-8a0a-3abee6d3472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32128
73712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3212873712
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2302452069
Short name T57
Test name
Test status
Simulation time 1049929831843 ps
CPU time 3466.32 seconds
Started May 05 02:21:49 PM PDT 24
Finished May 05 03:19:36 PM PDT 24
Peak memory 306284 kb
Host smart-419a2283-5d9d-407d-936e-6a3459a3ec62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302452069 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2302452069
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1654283921
Short name T31
Test name
Test status
Simulation time 161514995141 ps
CPU time 2302.8 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 02:57:02 PM PDT 24
Peak memory 289660 kb
Host smart-c4ba4d1a-d966-4281-be65-676bca2592f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654283921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1654283921
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3210020749
Short name T150
Test name
Test status
Simulation time 76824024946 ps
CPU time 1038.99 seconds
Started May 05 02:58:19 PM PDT 24
Finished May 05 03:15:39 PM PDT 24
Peak memory 265516 kb
Host smart-a3e68fc6-3080-4e77-a59a-42357b38321c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210020749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3210020749
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1797746100
Short name T299
Test name
Test status
Simulation time 10863273803 ps
CPU time 242.77 seconds
Started May 05 02:19:11 PM PDT 24
Finished May 05 02:23:14 PM PDT 24
Peak memory 247828 kb
Host smart-5e97fd00-9c8f-4776-b12e-7016356927b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797746100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1797746100
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.879328928
Short name T325
Test name
Test status
Simulation time 57502529816 ps
CPU time 2061.66 seconds
Started May 05 02:20:08 PM PDT 24
Finished May 05 02:54:30 PM PDT 24
Peak memory 271348 kb
Host smart-d4b532fa-29ce-47c9-a3ec-1bd84ee8c297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879328928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.879328928
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2535304203
Short name T146
Test name
Test status
Simulation time 23829227857 ps
CPU time 572.36 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 03:08:15 PM PDT 24
Peak memory 267880 kb
Host smart-ff55ae96-5271-4a9f-868b-9621268c8134
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535304203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2535304203
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1951890693
Short name T302
Test name
Test status
Simulation time 49864016637 ps
CPU time 489.13 seconds
Started May 05 02:23:46 PM PDT 24
Finished May 05 02:31:56 PM PDT 24
Peak memory 248312 kb
Host smart-f71ef4b5-ab54-4dfb-b0d5-25bf5af33b92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951890693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1951890693
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3921732637
Short name T44
Test name
Test status
Simulation time 382644648458 ps
CPU time 6876.07 seconds
Started May 05 02:19:13 PM PDT 24
Finished May 05 04:13:50 PM PDT 24
Peak memory 339028 kb
Host smart-e3c0345f-d674-4ed4-a73b-febaaa356ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921732637 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3921732637
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2169370433
Short name T151
Test name
Test status
Simulation time 4586309898 ps
CPU time 348 seconds
Started May 05 02:58:34 PM PDT 24
Finished May 05 03:04:23 PM PDT 24
Peak memory 266432 kb
Host smart-67196795-07fa-492e-9afa-769448151b6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2169370433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2169370433
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.883833428
Short name T182
Test name
Test status
Simulation time 104138800 ps
CPU time 3.63 seconds
Started May 05 02:57:50 PM PDT 24
Finished May 05 02:57:54 PM PDT 24
Peak memory 237248 kb
Host smart-47d1ac96-02e3-4957-9f23-756ec0e82f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=883833428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.883833428
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3670894910
Short name T294
Test name
Test status
Simulation time 461880372601 ps
CPU time 2561.82 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 03:01:27 PM PDT 24
Peak memory 289128 kb
Host smart-b6839faa-1329-4622-8bf0-08af92f38342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670894910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3670894910
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.49344847
Short name T159
Test name
Test status
Simulation time 8748797571 ps
CPU time 145.56 seconds
Started May 05 02:57:50 PM PDT 24
Finished May 05 03:00:16 PM PDT 24
Peak memory 265124 kb
Host smart-5440f15c-2aee-43fe-b756-8a48ca3ec4fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49344847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors
.49344847
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3464839392
Short name T152
Test name
Test status
Simulation time 7582983962 ps
CPU time 503.03 seconds
Started May 05 02:58:45 PM PDT 24
Finished May 05 03:07:08 PM PDT 24
Peak memory 268700 kb
Host smart-8f179590-9900-4334-ab3e-796ffb188790
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464839392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3464839392
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1601947839
Short name T341
Test name
Test status
Simulation time 8044196499 ps
CPU time 525.12 seconds
Started May 05 02:58:31 PM PDT 24
Finished May 05 03:07:16 PM PDT 24
Peak memory 265368 kb
Host smart-42b82639-b264-4b8c-8fbf-822639d0604c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601947839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1601947839
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4110037493
Short name T231
Test name
Test status
Simulation time 56620966 ps
CPU time 4.63 seconds
Started May 05 02:18:35 PM PDT 24
Finished May 05 02:18:40 PM PDT 24
Peak memory 248916 kb
Host smart-ad4229af-5819-4760-91b4-f907377fd193
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4110037493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4110037493
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4123122156
Short name T233
Test name
Test status
Simulation time 109189478 ps
CPU time 3.07 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:19:13 PM PDT 24
Peak memory 248940 kb
Host smart-ecce5150-a283-4a94-801c-e9ac79fb248b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4123122156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4123122156
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3400460815
Short name T238
Test name
Test status
Simulation time 77914971 ps
CPU time 2.38 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:19:12 PM PDT 24
Peak memory 248928 kb
Host smart-f65a7882-9faa-4479-b127-67a636556c0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3400460815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3400460815
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.916668888
Short name T234
Test name
Test status
Simulation time 191952972 ps
CPU time 4.12 seconds
Started May 05 02:19:42 PM PDT 24
Finished May 05 02:19:46 PM PDT 24
Peak memory 248900 kb
Host smart-210e4b98-e7d3-4a95-9f32-34491f85fcb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=916668888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.916668888
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.44650738
Short name T127
Test name
Test status
Simulation time 67384253046 ps
CPU time 1544.93 seconds
Started May 05 02:18:38 PM PDT 24
Finished May 05 02:44:23 PM PDT 24
Peak memory 273184 kb
Host smart-34d81d81-27ac-4ba4-b0c3-e13264b3ddc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44650738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.44650738
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2334717303
Short name T690
Test name
Test status
Simulation time 27800503881 ps
CPU time 1698.89 seconds
Started May 05 02:19:15 PM PDT 24
Finished May 05 02:47:34 PM PDT 24
Peak memory 283968 kb
Host smart-d46529ff-2d79-4ccb-b69f-53a29d461c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334717303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2334717303
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4162584574
Short name T143
Test name
Test status
Simulation time 19142810694 ps
CPU time 192.35 seconds
Started May 05 02:19:12 PM PDT 24
Finished May 05 02:22:25 PM PDT 24
Peak memory 248184 kb
Host smart-a542c2cf-d164-4ae7-8230-8f1f57c4e008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162584574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4162584574
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2102626507
Short name T255
Test name
Test status
Simulation time 2071441375 ps
CPU time 55.95 seconds
Started May 05 02:20:00 PM PDT 24
Finished May 05 02:20:56 PM PDT 24
Peak memory 248740 kb
Host smart-9af9412a-dba0-452f-9166-8e362cc5a51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21026
26507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2102626507
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1730921748
Short name T260
Test name
Test status
Simulation time 193116327022 ps
CPU time 4476.09 seconds
Started May 05 02:20:34 PM PDT 24
Finished May 05 03:35:11 PM PDT 24
Peak memory 316024 kb
Host smart-18590db1-b20e-4d35-b81a-32312f92814c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730921748 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1730921748
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1708872188
Short name T267
Test name
Test status
Simulation time 670480092 ps
CPU time 40.03 seconds
Started May 05 02:23:15 PM PDT 24
Finished May 05 02:23:55 PM PDT 24
Peak memory 256460 kb
Host smart-5a22c268-2798-430e-a5f3-8961f52a6e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088
72188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1708872188
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3615771900
Short name T161
Test name
Test status
Simulation time 881643543 ps
CPU time 96.49 seconds
Started May 05 02:58:15 PM PDT 24
Finished May 05 02:59:52 PM PDT 24
Peak memory 265332 kb
Host smart-a1574963-3740-4336-b112-1460e6aabdf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3615771900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3615771900
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1980054618
Short name T276
Test name
Test status
Simulation time 47360862416 ps
CPU time 2570.03 seconds
Started May 05 02:22:24 PM PDT 24
Finished May 05 03:05:14 PM PDT 24
Peak memory 289672 kb
Host smart-603b6718-2559-4bf3-b5a3-7c03c2c58220
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980054618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1980054618
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.868825321
Short name T195
Test name
Test status
Simulation time 3693750298 ps
CPU time 65.87 seconds
Started May 05 02:57:54 PM PDT 24
Finished May 05 02:59:00 PM PDT 24
Peak memory 240528 kb
Host smart-ad9e00df-3bf3-4e4f-87bf-07d45161d5db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=868825321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.868825321
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1336915289
Short name T171
Test name
Test status
Simulation time 69570384299 ps
CPU time 556.95 seconds
Started May 05 02:58:19 PM PDT 24
Finished May 05 03:07:36 PM PDT 24
Peak memory 265520 kb
Host smart-5657585c-98e0-4641-a134-469805020db1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336915289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1336915289
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3913116646
Short name T22
Test name
Test status
Simulation time 13141147452 ps
CPU time 1054.48 seconds
Started May 05 02:18:45 PM PDT 24
Finished May 05 02:36:21 PM PDT 24
Peak memory 288196 kb
Host smart-37def89f-237d-411b-88f8-15b36a53646f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913116646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3913116646
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.100924261
Short name T334
Test name
Test status
Simulation time 7667061 ps
CPU time 1.44 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:45 PM PDT 24
Peak memory 234992 kb
Host smart-2ffc0491-b6f6-4834-bed7-8f30af801e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=100924261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.100924261
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3568516545
Short name T88
Test name
Test status
Simulation time 549512583 ps
CPU time 33.83 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:19:43 PM PDT 24
Peak memory 255872 kb
Host smart-ae88a9b5-4d12-4e8a-86c2-2e37315065fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685
16545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3568516545
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.567054593
Short name T471
Test name
Test status
Simulation time 91509228198 ps
CPU time 2409.38 seconds
Started May 05 02:19:33 PM PDT 24
Finished May 05 02:59:43 PM PDT 24
Peak memory 288240 kb
Host smart-ec29dbc8-d2d9-4fff-b536-389549759aa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567054593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.567054593
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2621443487
Short name T320
Test name
Test status
Simulation time 51350444076 ps
CPU time 2653.95 seconds
Started May 05 02:19:32 PM PDT 24
Finished May 05 03:03:47 PM PDT 24
Peak memory 285092 kb
Host smart-03271b23-1a8b-4795-9eb2-339048e708c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621443487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2621443487
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1198971680
Short name T682
Test name
Test status
Simulation time 18441146400 ps
CPU time 170.84 seconds
Started May 05 02:19:34 PM PDT 24
Finished May 05 02:22:25 PM PDT 24
Peak memory 247912 kb
Host smart-774df584-6999-4bf3-a7e0-86594935e788
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198971680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1198971680
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.658587675
Short name T268
Test name
Test status
Simulation time 3939835947 ps
CPU time 60.02 seconds
Started May 05 02:19:27 PM PDT 24
Finished May 05 02:20:28 PM PDT 24
Peak memory 247948 kb
Host smart-3c65c088-3764-4e78-9a49-142ec43342ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65858
7675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.658587675
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.738146835
Short name T277
Test name
Test status
Simulation time 9072191931 ps
CPU time 879.02 seconds
Started May 05 02:21:07 PM PDT 24
Finished May 05 02:35:46 PM PDT 24
Peak memory 287316 kb
Host smart-adcf8ecf-0a59-4b58-ba32-f8e0735a98a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738146835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.738146835
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.251149917
Short name T264
Test name
Test status
Simulation time 69528965965 ps
CPU time 3837.47 seconds
Started May 05 02:21:24 PM PDT 24
Finished May 05 03:25:22 PM PDT 24
Peak memory 300004 kb
Host smart-49abe6d3-f05a-418d-a4ba-8afd0d94a2d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251149917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.251149917
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3282467209
Short name T287
Test name
Test status
Simulation time 1771424348 ps
CPU time 50.37 seconds
Started May 05 02:21:29 PM PDT 24
Finished May 05 02:22:20 PM PDT 24
Peak memory 255716 kb
Host smart-07961f4c-be11-49a9-b17e-b3392c1b41a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
67209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3282467209
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3713568862
Short name T139
Test name
Test status
Simulation time 99412096040 ps
CPU time 1464.3 seconds
Started May 05 02:21:35 PM PDT 24
Finished May 05 02:46:00 PM PDT 24
Peak memory 273356 kb
Host smart-e4b3b7d7-f2b9-45e3-9900-6b213060c7ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713568862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3713568862
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.554378829
Short name T105
Test name
Test status
Simulation time 154139123934 ps
CPU time 2123.88 seconds
Started May 05 02:22:53 PM PDT 24
Finished May 05 02:58:17 PM PDT 24
Peak memory 282996 kb
Host smart-f08b885d-64e0-44f6-bfe7-9778732a4af8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554378829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.554378829
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.364237601
Short name T275
Test name
Test status
Simulation time 16162833321 ps
CPU time 1243.06 seconds
Started May 05 02:23:57 PM PDT 24
Finished May 05 02:44:41 PM PDT 24
Peak memory 281244 kb
Host smart-25d98bbe-0d1a-413c-9928-67e1b029b8bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364237601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.364237601
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1807459999
Short name T254
Test name
Test status
Simulation time 67249761699 ps
CPU time 7740.35 seconds
Started May 05 02:25:19 PM PDT 24
Finished May 05 04:34:20 PM PDT 24
Peak memory 371388 kb
Host smart-6d8e2c7c-ae2e-40c1-9f47-f55df3bc09ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807459999 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1807459999
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3817199484
Short name T103
Test name
Test status
Simulation time 13705940529 ps
CPU time 1123.45 seconds
Started May 05 02:20:08 PM PDT 24
Finished May 05 02:38:52 PM PDT 24
Peak memory 288852 kb
Host smart-e9b938af-ecae-427c-8a52-ffb6cf714a3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817199484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3817199484
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2263224445
Short name T154
Test name
Test status
Simulation time 7852253304 ps
CPU time 276.19 seconds
Started May 05 02:57:50 PM PDT 24
Finished May 05 03:02:27 PM PDT 24
Peak memory 265376 kb
Host smart-c552d4ba-02c5-4f67-8d18-8af184545bd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2263224445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2263224445
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1969685144
Short name T145
Test name
Test status
Simulation time 1565473345 ps
CPU time 175.07 seconds
Started May 05 02:58:21 PM PDT 24
Finished May 05 03:01:17 PM PDT 24
Peak memory 273640 kb
Host smart-41127366-13ff-4d59-84ad-cec2e5d8e8d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1969685144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1969685144
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3238861863
Short name T192
Test name
Test status
Simulation time 110907344 ps
CPU time 2.82 seconds
Started May 05 02:58:02 PM PDT 24
Finished May 05 02:58:06 PM PDT 24
Peak memory 236920 kb
Host smart-52c3e56c-b140-455a-9870-1225f1442655
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3238861863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3238861863
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1028294595
Short name T187
Test name
Test status
Simulation time 4025870827 ps
CPU time 32.07 seconds
Started May 05 02:58:24 PM PDT 24
Finished May 05 02:58:56 PM PDT 24
Peak memory 245240 kb
Host smart-4582e6b0-f39c-4bb8-bbe1-0d01ae157336
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1028294595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1028294595
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2317634564
Short name T190
Test name
Test status
Simulation time 143100017 ps
CPU time 7.14 seconds
Started May 05 02:58:32 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 237264 kb
Host smart-9c85ab2c-f321-413a-b99f-e7413d3bd013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2317634564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2317634564
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.304564721
Short name T189
Test name
Test status
Simulation time 177969925 ps
CPU time 22.01 seconds
Started May 05 02:58:36 PM PDT 24
Finished May 05 02:58:59 PM PDT 24
Peak memory 237140 kb
Host smart-ea6e31c4-8b53-46f1-914f-937601a28602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=304564721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.304564721
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1682190521
Short name T196
Test name
Test status
Simulation time 7370467746 ps
CPU time 79.31 seconds
Started May 05 02:57:56 PM PDT 24
Finished May 05 02:59:16 PM PDT 24
Peak memory 237436 kb
Host smart-2dc2d0e2-e20e-449d-9831-9b3948bcb330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1682190521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1682190521
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2979947070
Short name T155
Test name
Test status
Simulation time 3241624087 ps
CPU time 91.44 seconds
Started May 05 02:57:58 PM PDT 24
Finished May 05 02:59:29 PM PDT 24
Peak memory 265420 kb
Host smart-61f2b5fd-5597-472a-9d9a-b88989a786a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2979947070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2979947070
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.453804654
Short name T186
Test name
Test status
Simulation time 112546152 ps
CPU time 5.8 seconds
Started May 05 02:58:09 PM PDT 24
Finished May 05 02:58:15 PM PDT 24
Peak memory 236880 kb
Host smart-7186a00a-cac8-44a8-b1d7-b563fe56a6b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=453804654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.453804654
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1858051507
Short name T2
Test name
Test status
Simulation time 1302538800 ps
CPU time 27.09 seconds
Started May 05 02:18:34 PM PDT 24
Finished May 05 02:19:02 PM PDT 24
Peak memory 256028 kb
Host smart-866f23d4-f4eb-41d2-a127-2541c9e86707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18580
51507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1858051507
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.343391792
Short name T191
Test name
Test status
Simulation time 1856122350 ps
CPU time 27.57 seconds
Started May 05 02:58:22 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 239732 kb
Host smart-0e8582a9-dcc9-4a27-97b4-0dc1b03634b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=343391792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.343391792
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2621517702
Short name T201
Test name
Test status
Simulation time 21473553 ps
CPU time 2.27 seconds
Started May 05 02:58:26 PM PDT 24
Finished May 05 02:58:28 PM PDT 24
Peak memory 235968 kb
Host smart-89dc00dd-e4d2-403a-8c5d-20661326fe08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2621517702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2621517702
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1945859713
Short name T194
Test name
Test status
Simulation time 1388756443 ps
CPU time 41.02 seconds
Started May 05 02:58:31 PM PDT 24
Finished May 05 02:59:13 PM PDT 24
Peak memory 245228 kb
Host smart-d94f9378-dbe4-455d-9fae-3b77c5fa3c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1945859713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1945859713
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1970959252
Short name T193
Test name
Test status
Simulation time 4913377410 ps
CPU time 81.78 seconds
Started May 05 02:58:44 PM PDT 24
Finished May 05 03:00:07 PM PDT 24
Peak memory 238180 kb
Host smart-e54ce6e2-04d2-4743-afae-45d11292c077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1970959252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1970959252
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.854751801
Short name T27
Test name
Test status
Simulation time 1446591486 ps
CPU time 27.96 seconds
Started May 05 02:19:00 PM PDT 24
Finished May 05 02:19:28 PM PDT 24
Peak memory 256144 kb
Host smart-7b53099e-1010-4420-b05c-10c40927b623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85475
1801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.854751801
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1789900621
Short name T809
Test name
Test status
Simulation time 1191164591 ps
CPU time 72.2 seconds
Started May 05 02:57:44 PM PDT 24
Finished May 05 02:58:57 PM PDT 24
Peak memory 236848 kb
Host smart-80271949-5e8d-43b6-8dc2-b3697f062ce9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1789900621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1789900621
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3951970916
Short name T804
Test name
Test status
Simulation time 30490657746 ps
CPU time 510.29 seconds
Started May 05 02:57:47 PM PDT 24
Finished May 05 03:06:17 PM PDT 24
Peak memory 236872 kb
Host smart-8d0f53b6-c3d2-4d4a-962d-b947dba3787f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3951970916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3951970916
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4059526400
Short name T788
Test name
Test status
Simulation time 75899213 ps
CPU time 5.78 seconds
Started May 05 02:57:45 PM PDT 24
Finished May 05 02:57:51 PM PDT 24
Peak memory 240328 kb
Host smart-cfcde022-ec3b-49d6-bf54-e7e254c6f066
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4059526400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4059526400
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2499510776
Short name T785
Test name
Test status
Simulation time 69762958 ps
CPU time 5.71 seconds
Started May 05 02:57:45 PM PDT 24
Finished May 05 02:57:51 PM PDT 24
Peak memory 238992 kb
Host smart-b0fd535a-92b2-444a-aaff-9d1fc3f5de85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499510776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2499510776
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4226483325
Short name T792
Test name
Test status
Simulation time 79326226 ps
CPU time 2.86 seconds
Started May 05 02:57:44 PM PDT 24
Finished May 05 02:57:47 PM PDT 24
Peak memory 235920 kb
Host smart-2050abea-947c-4d7b-b982-94ac4dd1c177
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4226483325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4226483325
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.42996002
Short name T793
Test name
Test status
Simulation time 8673975 ps
CPU time 1.25 seconds
Started May 05 02:57:44 PM PDT 24
Finished May 05 02:57:46 PM PDT 24
Peak memory 236928 kb
Host smart-24392196-52b0-4f71-8788-e4def353897a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=42996002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.42996002
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1261157784
Short name T827
Test name
Test status
Simulation time 657476452 ps
CPU time 18.41 seconds
Started May 05 02:57:46 PM PDT 24
Finished May 05 02:58:05 PM PDT 24
Peak memory 248648 kb
Host smart-713c4acf-6a78-4a23-863c-24c41b2d7ac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1261157784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1261157784
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1446183582
Short name T342
Test name
Test status
Simulation time 29652711622 ps
CPU time 489.29 seconds
Started May 05 02:57:45 PM PDT 24
Finished May 05 03:05:55 PM PDT 24
Peak memory 265352 kb
Host smart-2e9c3bbc-8e34-403c-82ad-b8c367625c3f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446183582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1446183582
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1783765217
Short name T724
Test name
Test status
Simulation time 41275805 ps
CPU time 5.41 seconds
Started May 05 02:57:47 PM PDT 24
Finished May 05 02:57:52 PM PDT 24
Peak memory 249716 kb
Host smart-e38c9016-19f9-426a-a522-f10e06d3f642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1783765217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1783765217
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.407944774
Short name T188
Test name
Test status
Simulation time 641602554 ps
CPU time 19.63 seconds
Started May 05 02:57:47 PM PDT 24
Finished May 05 02:58:06 PM PDT 24
Peak memory 245100 kb
Host smart-11450f7f-8767-42a8-a901-940e992ab49a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=407944774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.407944774
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2764115141
Short name T213
Test name
Test status
Simulation time 3370651601 ps
CPU time 240.91 seconds
Started May 05 02:57:48 PM PDT 24
Finished May 05 03:01:49 PM PDT 24
Peak memory 240772 kb
Host smart-602806d8-2563-4f00-9178-da405df41e04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2764115141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2764115141
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3820893457
Short name T816
Test name
Test status
Simulation time 15440889262 ps
CPU time 201.62 seconds
Started May 05 02:57:48 PM PDT 24
Finished May 05 03:01:10 PM PDT 24
Peak memory 235944 kb
Host smart-5f222c44-1bcf-461f-a8be-51a6b76044c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3820893457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3820893457
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.574901842
Short name T789
Test name
Test status
Simulation time 37530331 ps
CPU time 5.56 seconds
Started May 05 02:57:45 PM PDT 24
Finished May 05 02:57:51 PM PDT 24
Peak memory 240376 kb
Host smart-6b846abc-2b89-498c-9fde-9e42fafccef0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=574901842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.574901842
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1041196361
Short name T726
Test name
Test status
Simulation time 33995119 ps
CPU time 5.03 seconds
Started May 05 02:57:48 PM PDT 24
Finished May 05 02:57:53 PM PDT 24
Peak memory 241752 kb
Host smart-32f83435-b40f-4779-bfb6-fd4cf3605cd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041196361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1041196361
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4013247536
Short name T826
Test name
Test status
Simulation time 111350588 ps
CPU time 7.77 seconds
Started May 05 02:57:48 PM PDT 24
Finished May 05 02:57:56 PM PDT 24
Peak memory 240308 kb
Host smart-2222fba2-4723-4ee2-b4a0-9f311bed1ccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4013247536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4013247536
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.810766480
Short name T244
Test name
Test status
Simulation time 14620074 ps
CPU time 1.4 seconds
Started May 05 02:57:44 PM PDT 24
Finished May 05 02:57:46 PM PDT 24
Peak memory 236912 kb
Host smart-2e5b7365-7372-4cbe-9ba7-25a027fd4ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=810766480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.810766480
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3557094128
Short name T807
Test name
Test status
Simulation time 85230366 ps
CPU time 11.35 seconds
Started May 05 02:57:47 PM PDT 24
Finished May 05 02:57:59 PM PDT 24
Peak memory 245128 kb
Host smart-8c317513-469b-4eef-b886-4151de8cfbfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3557094128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3557094128
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1926776529
Short name T168
Test name
Test status
Simulation time 4028009167 ps
CPU time 142.19 seconds
Started May 05 02:57:46 PM PDT 24
Finished May 05 03:00:08 PM PDT 24
Peak memory 265416 kb
Host smart-4692d5de-89f2-4532-88e5-277d73edc1ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1926776529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1926776529
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4097617437
Short name T767
Test name
Test status
Simulation time 47719536 ps
CPU time 5.99 seconds
Started May 05 02:57:46 PM PDT 24
Finished May 05 02:57:52 PM PDT 24
Peak memory 251732 kb
Host smart-a7c3e393-e8a4-47de-8242-dc204905fc3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097617437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4097617437
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.628701091
Short name T794
Test name
Test status
Simulation time 38470116 ps
CPU time 5.66 seconds
Started May 05 02:58:22 PM PDT 24
Finished May 05 02:58:28 PM PDT 24
Peak memory 241720 kb
Host smart-65c58dcb-e71c-462d-8110-b23303051e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628701091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.628701091
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3775981853
Short name T778
Test name
Test status
Simulation time 170243311 ps
CPU time 7.56 seconds
Started May 05 02:58:25 PM PDT 24
Finished May 05 02:58:33 PM PDT 24
Peak memory 236840 kb
Host smart-c0ad3696-230c-4084-8952-5f59ac80773a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3775981853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3775981853
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1006415330
Short name T775
Test name
Test status
Simulation time 15874940 ps
CPU time 1.46 seconds
Started May 05 02:58:24 PM PDT 24
Finished May 05 02:58:25 PM PDT 24
Peak memory 236920 kb
Host smart-c54ebd18-be40-436c-b063-b8cf27a18319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006415330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1006415330
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1262149790
Short name T215
Test name
Test status
Simulation time 2111073097 ps
CPU time 35.04 seconds
Started May 05 02:58:25 PM PDT 24
Finished May 05 02:59:01 PM PDT 24
Peak memory 244184 kb
Host smart-ffe19574-0476-4362-ae60-b6607624cd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1262149790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1262149790
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3453618999
Short name T173
Test name
Test status
Simulation time 772884488 ps
CPU time 91.12 seconds
Started May 05 02:58:22 PM PDT 24
Finished May 05 02:59:54 PM PDT 24
Peak memory 257164 kb
Host smart-d54baee3-f5dd-4ebd-8a1e-f5ca0cd9601d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3453618999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3453618999
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2081553755
Short name T753
Test name
Test status
Simulation time 100738777 ps
CPU time 6.81 seconds
Started May 05 02:58:23 PM PDT 24
Finished May 05 02:58:31 PM PDT 24
Peak memory 248356 kb
Host smart-2f72a339-c90c-4d24-82f4-09660be37256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2081553755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2081553755
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1758678780
Short name T829
Test name
Test status
Simulation time 1469336366 ps
CPU time 10.15 seconds
Started May 05 02:58:26 PM PDT 24
Finished May 05 02:58:36 PM PDT 24
Peak memory 250900 kb
Host smart-4dcfd5ab-0b66-43b3-b3c5-842c27af7da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758678780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1758678780
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2912097266
Short name T338
Test name
Test status
Simulation time 120065715 ps
CPU time 4.97 seconds
Started May 05 02:58:27 PM PDT 24
Finished May 05 02:58:32 PM PDT 24
Peak memory 236812 kb
Host smart-f4028291-caa9-48eb-ad3a-c8a2234e41d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2912097266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2912097266
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2346452905
Short name T814
Test name
Test status
Simulation time 15325940 ps
CPU time 1.24 seconds
Started May 05 02:58:23 PM PDT 24
Finished May 05 02:58:25 PM PDT 24
Peak memory 236912 kb
Host smart-9ef1edbc-fd44-48d4-a2a4-93042e049ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2346452905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2346452905
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2373105351
Short name T770
Test name
Test status
Simulation time 678741036 ps
CPU time 46.16 seconds
Started May 05 02:58:29 PM PDT 24
Finished May 05 02:59:15 PM PDT 24
Peak memory 245084 kb
Host smart-426fa04d-034e-4472-a267-e6f31da02bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2373105351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2373105351
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4086961029
Short name T740
Test name
Test status
Simulation time 485910155 ps
CPU time 8.09 seconds
Started May 05 02:58:23 PM PDT 24
Finished May 05 02:58:31 PM PDT 24
Peak memory 248644 kb
Host smart-5ed44a43-221d-4d6f-860c-7b18229a5a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4086961029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4086961029
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3693344492
Short name T752
Test name
Test status
Simulation time 304314776 ps
CPU time 6.91 seconds
Started May 05 02:58:31 PM PDT 24
Finished May 05 02:58:38 PM PDT 24
Peak memory 240544 kb
Host smart-b46aa87e-e570-4b7f-8a41-e4643a966613
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693344492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3693344492
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.478884813
Short name T248
Test name
Test status
Simulation time 123121282 ps
CPU time 8.33 seconds
Started May 05 02:58:26 PM PDT 24
Finished May 05 02:58:35 PM PDT 24
Peak memory 236796 kb
Host smart-fe4a214f-7bd1-41ee-8143-a6cd357cfc6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=478884813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.478884813
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.167786275
Short name T746
Test name
Test status
Simulation time 9976788 ps
CPU time 1.48 seconds
Started May 05 02:58:27 PM PDT 24
Finished May 05 02:58:28 PM PDT 24
Peak memory 236920 kb
Host smart-3b180634-5da4-4451-a957-2543021306d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=167786275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.167786275
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.206510393
Short name T772
Test name
Test status
Simulation time 347278964 ps
CPU time 20.88 seconds
Started May 05 02:58:28 PM PDT 24
Finished May 05 02:58:49 PM PDT 24
Peak memory 244156 kb
Host smart-cb7080af-50cb-4ef2-ab90-b29fd72a791b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=206510393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.206510393
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1348423884
Short name T160
Test name
Test status
Simulation time 10201556893 ps
CPU time 149.44 seconds
Started May 05 02:58:25 PM PDT 24
Finished May 05 03:00:55 PM PDT 24
Peak memory 265400 kb
Host smart-5d608143-e6e5-47ec-9393-267be6822c94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1348423884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1348423884
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.334483560
Short name T166
Test name
Test status
Simulation time 22038313329 ps
CPU time 326.3 seconds
Started May 05 02:58:26 PM PDT 24
Finished May 05 03:03:53 PM PDT 24
Peak memory 265408 kb
Host smart-871839ec-4e70-43ad-bac2-57ded571265f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334483560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.334483560
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4132787898
Short name T717
Test name
Test status
Simulation time 129376913 ps
CPU time 9.09 seconds
Started May 05 02:58:27 PM PDT 24
Finished May 05 02:58:37 PM PDT 24
Peak memory 248732 kb
Host smart-9604d115-0a84-4631-a5b5-e85d3dcecfd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4132787898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4132787898
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.758479391
Short name T751
Test name
Test status
Simulation time 32587353 ps
CPU time 4.86 seconds
Started May 05 02:58:32 PM PDT 24
Finished May 05 02:58:37 PM PDT 24
Peak memory 248728 kb
Host smart-8ec43ee8-7eec-4047-8cd4-2fc42d10ebea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758479391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.758479391
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1198238242
Short name T218
Test name
Test status
Simulation time 68100291 ps
CPU time 5.14 seconds
Started May 05 02:58:34 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 237004 kb
Host smart-1fddf28d-5bc6-42b4-995b-0f32191dac31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1198238242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1198238242
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.506646218
Short name T821
Test name
Test status
Simulation time 3446415519 ps
CPU time 39.26 seconds
Started May 05 02:58:37 PM PDT 24
Finished May 05 02:59:16 PM PDT 24
Peak memory 245152 kb
Host smart-81c71763-4d7b-421f-9767-d929a21c1ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=506646218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.506646218
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1753571501
Short name T147
Test name
Test status
Simulation time 3378089662 ps
CPU time 104.09 seconds
Started May 05 02:58:33 PM PDT 24
Finished May 05 03:00:17 PM PDT 24
Peak memory 257216 kb
Host smart-a5109b06-6ed8-4732-9e60-51a91697c3b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1753571501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1753571501
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.564400952
Short name T714
Test name
Test status
Simulation time 216360534 ps
CPU time 14.24 seconds
Started May 05 02:58:30 PM PDT 24
Finished May 05 02:58:45 PM PDT 24
Peak memory 248688 kb
Host smart-ce9cbdc1-f01b-47d1-8112-1e40d25e1e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=564400952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.564400952
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2263172080
Short name T742
Test name
Test status
Simulation time 134768935 ps
CPU time 8.46 seconds
Started May 05 02:58:36 PM PDT 24
Finished May 05 02:58:44 PM PDT 24
Peak memory 239720 kb
Host smart-957ed5e3-3982-49cc-8efe-216b42eaa1b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263172080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2263172080
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1019922371
Short name T806
Test name
Test status
Simulation time 67488134 ps
CPU time 5.34 seconds
Started May 05 02:58:38 PM PDT 24
Finished May 05 02:58:44 PM PDT 24
Peak memory 237004 kb
Host smart-4a72502c-a9de-4499-926a-a42ead49abce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1019922371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1019922371
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.578036550
Short name T747
Test name
Test status
Simulation time 11437224 ps
CPU time 1.5 seconds
Started May 05 02:58:37 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 236912 kb
Host smart-fde2e0cd-4482-4b09-87c3-d38724d6ac39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=578036550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.578036550
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.990652769
Short name T790
Test name
Test status
Simulation time 1243060585 ps
CPU time 37.17 seconds
Started May 05 02:58:35 PM PDT 24
Finished May 05 02:59:13 PM PDT 24
Peak memory 244208 kb
Host smart-65ea7ae2-f183-4294-b30e-71257c3e95a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=990652769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.990652769
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2847616535
Short name T715
Test name
Test status
Simulation time 208298514 ps
CPU time 7.34 seconds
Started May 05 02:58:34 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 248640 kb
Host smart-59aedc38-65f9-4275-8bb3-0bd9e0399d06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2847616535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2847616535
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3734721030
Short name T766
Test name
Test status
Simulation time 201559473 ps
CPU time 8.71 seconds
Started May 05 02:58:37 PM PDT 24
Finished May 05 02:58:46 PM PDT 24
Peak memory 238612 kb
Host smart-fe606cfa-adc1-46fc-8137-094b14943718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734721030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3734721030
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4230464017
Short name T729
Test name
Test status
Simulation time 366160258 ps
CPU time 7.5 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:51 PM PDT 24
Peak memory 236856 kb
Host smart-c64bbf9d-705f-401a-af6e-92f001e96c4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4230464017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4230464017
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3074213940
Short name T741
Test name
Test status
Simulation time 319231259 ps
CPU time 12.81 seconds
Started May 05 02:58:38 PM PDT 24
Finished May 05 02:58:51 PM PDT 24
Peak memory 245120 kb
Host smart-dc65a0bb-25a9-42f2-92f1-ba9524d94211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3074213940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3074213940
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.182514727
Short name T162
Test name
Test status
Simulation time 7694167552 ps
CPU time 261.61 seconds
Started May 05 02:58:35 PM PDT 24
Finished May 05 03:02:57 PM PDT 24
Peak memory 265448 kb
Host smart-e829bf00-81d2-4747-9435-52eee2f889b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=182514727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.182514727
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.883315311
Short name T343
Test name
Test status
Simulation time 25666501999 ps
CPU time 513.39 seconds
Started May 05 02:58:36 PM PDT 24
Finished May 05 03:07:10 PM PDT 24
Peak memory 268848 kb
Host smart-55eb5f31-9995-4e27-b08f-62ea36ed83a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883315311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.883315311
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.4066267145
Short name T748
Test name
Test status
Simulation time 63061627 ps
CPU time 7.99 seconds
Started May 05 02:58:35 PM PDT 24
Finished May 05 02:58:43 PM PDT 24
Peak memory 248692 kb
Host smart-decefc3e-9f6e-4d2c-a921-2345db1ecf31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4066267145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.4066267145
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1989130201
Short name T181
Test name
Test status
Simulation time 639592630 ps
CPU time 21.67 seconds
Started May 05 02:58:34 PM PDT 24
Finished May 05 02:58:56 PM PDT 24
Peak memory 240424 kb
Host smart-001e2d09-f204-4397-82ad-8405fbcf9e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1989130201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1989130201
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3357207625
Short name T224
Test name
Test status
Simulation time 285986327 ps
CPU time 5.53 seconds
Started May 05 02:58:36 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 239124 kb
Host smart-f27c67ef-0da4-4a62-837a-817b2115ff41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357207625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3357207625
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2139171954
Short name T736
Test name
Test status
Simulation time 126586379 ps
CPU time 5.17 seconds
Started May 05 02:58:37 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 240440 kb
Host smart-2329f418-4a1a-4523-938d-229096970951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2139171954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2139171954
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3341887886
Short name T332
Test name
Test status
Simulation time 6483060 ps
CPU time 1.4 seconds
Started May 05 02:58:38 PM PDT 24
Finished May 05 02:58:40 PM PDT 24
Peak memory 235996 kb
Host smart-0d622660-267d-4f94-9200-530e672c5e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3341887886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3341887886
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.4009769707
Short name T782
Test name
Test status
Simulation time 1445693053 ps
CPU time 46.41 seconds
Started May 05 02:58:37 PM PDT 24
Finished May 05 02:59:24 PM PDT 24
Peak memory 245084 kb
Host smart-a6c99125-cd18-4daa-b243-1abd721cb552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4009769707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.4009769707
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4225031728
Short name T172
Test name
Test status
Simulation time 28921428535 ps
CPU time 520.63 seconds
Started May 05 02:58:34 PM PDT 24
Finished May 05 03:07:15 PM PDT 24
Peak memory 269688 kb
Host smart-b1bdeee0-eb73-4780-a19b-626cdd910692
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225031728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4225031728
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1229404253
Short name T820
Test name
Test status
Simulation time 122321301 ps
CPU time 9.53 seconds
Started May 05 02:58:38 PM PDT 24
Finished May 05 02:58:48 PM PDT 24
Peak memory 248256 kb
Host smart-bd25264b-d586-4995-b1e4-9a226f558a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1229404253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1229404253
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2103681535
Short name T200
Test name
Test status
Simulation time 59585363 ps
CPU time 3.57 seconds
Started May 05 02:58:35 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 236896 kb
Host smart-b17797fb-c2de-4cd4-bf64-d743579af8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2103681535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2103681535
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1913655241
Short name T197
Test name
Test status
Simulation time 121559220 ps
CPU time 4 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 02:58:46 PM PDT 24
Peak memory 240728 kb
Host smart-85cba3d8-b543-4721-ba20-c257fe60b9e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913655241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1913655241
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3960407314
Short name T728
Test name
Test status
Simulation time 34727878 ps
CPU time 3.12 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:47 PM PDT 24
Peak memory 235928 kb
Host smart-e42e5f5f-005a-41f9-b74b-04629fe84e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3960407314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3960407314
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3035060695
Short name T183
Test name
Test status
Simulation time 10095967 ps
CPU time 1.34 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 02:58:44 PM PDT 24
Peak memory 235008 kb
Host smart-02f9033a-9e0b-4fda-99ef-8187e83bf1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3035060695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3035060695
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.449722403
Short name T786
Test name
Test status
Simulation time 364604647 ps
CPU time 22.37 seconds
Started May 05 02:58:44 PM PDT 24
Finished May 05 02:59:07 PM PDT 24
Peak memory 245140 kb
Host smart-2896b0ef-4d52-4093-a0bc-db10f4108fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=449722403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.449722403
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1635064893
Short name T158
Test name
Test status
Simulation time 45882383644 ps
CPU time 150.42 seconds
Started May 05 02:58:36 PM PDT 24
Finished May 05 03:01:07 PM PDT 24
Peak memory 265444 kb
Host smart-d49ca065-1edd-43fd-b21c-c94e70f640c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1635064893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1635064893
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3021345386
Short name T780
Test name
Test status
Simulation time 345238093 ps
CPU time 20.99 seconds
Started May 05 02:58:37 PM PDT 24
Finished May 05 02:58:58 PM PDT 24
Peak memory 254288 kb
Host smart-7d019586-8b85-4575-811d-6d94bc17e93a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3021345386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3021345386
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1247784242
Short name T824
Test name
Test status
Simulation time 273740257 ps
CPU time 5.45 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:49 PM PDT 24
Peak memory 238004 kb
Host smart-af686902-259b-4c1d-bd4a-4207634b4f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247784242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1247784242
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1318679979
Short name T768
Test name
Test status
Simulation time 33128768 ps
CPU time 4.47 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 02:58:47 PM PDT 24
Peak memory 235884 kb
Host smart-58d4e726-2e6f-4b08-ac64-cc8edc6bb43d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1318679979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1318679979
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3070027119
Short name T810
Test name
Test status
Simulation time 9540692 ps
CPU time 1.24 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 02:58:44 PM PDT 24
Peak memory 236912 kb
Host smart-21094d41-6f25-4c97-9d0b-73cc625db72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3070027119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3070027119
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3802488762
Short name T812
Test name
Test status
Simulation time 1362705622 ps
CPU time 43.74 seconds
Started May 05 02:58:42 PM PDT 24
Finished May 05 02:59:27 PM PDT 24
Peak memory 245068 kb
Host smart-a2af9240-44a1-41a2-8802-5ae32c3c98ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3802488762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3802488762
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.641514908
Short name T178
Test name
Test status
Simulation time 6375643334 ps
CPU time 190.98 seconds
Started May 05 02:58:41 PM PDT 24
Finished May 05 03:01:52 PM PDT 24
Peak memory 265428 kb
Host smart-a33dd819-b902-44bc-bc7b-ed2bafcb4e8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=641514908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.641514908
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.792006665
Short name T713
Test name
Test status
Simulation time 143972945 ps
CPU time 10.52 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:55 PM PDT 24
Peak memory 248732 kb
Host smart-425cb55f-a9b0-46de-b4b4-654f6965c9cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=792006665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.792006665
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.4046231542
Short name T784
Test name
Test status
Simulation time 114797534 ps
CPU time 5.56 seconds
Started May 05 02:58:45 PM PDT 24
Finished May 05 02:58:51 PM PDT 24
Peak memory 240424 kb
Host smart-c61521fc-b25c-42c4-8e34-18892a180ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046231542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.4046231542
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2478125195
Short name T769
Test name
Test status
Simulation time 19995041 ps
CPU time 3.19 seconds
Started May 05 02:58:44 PM PDT 24
Finished May 05 02:58:48 PM PDT 24
Peak memory 235768 kb
Host smart-b86027c8-83a9-463c-b960-9ac24bcd7ae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2478125195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2478125195
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2849799121
Short name T830
Test name
Test status
Simulation time 8483965 ps
CPU time 1.49 seconds
Started May 05 02:58:47 PM PDT 24
Finished May 05 02:58:49 PM PDT 24
Peak memory 236900 kb
Host smart-3a786f26-215a-469c-8c54-ec5aae15a901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849799121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2849799121
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1130646836
Short name T247
Test name
Test status
Simulation time 1197965118 ps
CPU time 40.3 seconds
Started May 05 02:58:45 PM PDT 24
Finished May 05 02:59:26 PM PDT 24
Peak memory 244192 kb
Host smart-78a16a64-510a-4cf7-a549-980fae0cb6a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1130646836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1130646836
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3052765325
Short name T164
Test name
Test status
Simulation time 5794197806 ps
CPU time 128.44 seconds
Started May 05 02:58:40 PM PDT 24
Finished May 05 03:00:49 PM PDT 24
Peak memory 256860 kb
Host smart-96bb8c91-4dac-4744-aa80-e244449293bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3052765325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3052765325
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2592466310
Short name T735
Test name
Test status
Simulation time 339915915 ps
CPU time 11.74 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:55 PM PDT 24
Peak memory 248712 kb
Host smart-594a79a5-a8b1-46dc-99b0-0bf328a1d9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2592466310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2592466310
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3566468179
Short name T732
Test name
Test status
Simulation time 1173924862 ps
CPU time 130.16 seconds
Started May 05 02:57:56 PM PDT 24
Finished May 05 03:00:06 PM PDT 24
Peak memory 240408 kb
Host smart-6d8d897d-79c9-40cd-8a01-df4229de40d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3566468179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3566468179
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4186569919
Short name T777
Test name
Test status
Simulation time 9076153931 ps
CPU time 102.07 seconds
Started May 05 02:57:51 PM PDT 24
Finished May 05 02:59:34 PM PDT 24
Peak memory 236876 kb
Host smart-49f58bad-7015-4690-91b6-cc83fa751c1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4186569919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4186569919
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2940111127
Short name T779
Test name
Test status
Simulation time 501136623 ps
CPU time 9.73 seconds
Started May 05 02:57:54 PM PDT 24
Finished May 05 02:58:04 PM PDT 24
Peak memory 240572 kb
Host smart-ba32744a-1bc1-4210-b72a-07db13fc1d5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2940111127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2940111127
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2630577595
Short name T745
Test name
Test status
Simulation time 80524204 ps
CPU time 5.19 seconds
Started May 05 02:57:53 PM PDT 24
Finished May 05 02:57:59 PM PDT 24
Peak memory 244456 kb
Host smart-726c99b8-c6c3-4a2e-b177-e662c3b5f2bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630577595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2630577595
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.349883677
Short name T757
Test name
Test status
Simulation time 51219510 ps
CPU time 4.33 seconds
Started May 05 02:57:54 PM PDT 24
Finished May 05 02:57:59 PM PDT 24
Peak memory 236868 kb
Host smart-6603068a-d97a-4500-98e9-1a9b57834fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=349883677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.349883677
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.914768925
Short name T759
Test name
Test status
Simulation time 10704371 ps
CPU time 1.33 seconds
Started May 05 02:57:55 PM PDT 24
Finished May 05 02:57:57 PM PDT 24
Peak memory 236940 kb
Host smart-a10046df-581f-41b2-aa93-067558adfa03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914768925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.914768925
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4266539745
Short name T214
Test name
Test status
Simulation time 2790323732 ps
CPU time 34.98 seconds
Started May 05 02:57:54 PM PDT 24
Finished May 05 02:58:29 PM PDT 24
Peak memory 245176 kb
Host smart-851e2226-6f96-43f5-b022-f08d95299829
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4266539745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4266539745
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2514856635
Short name T179
Test name
Test status
Simulation time 30431379277 ps
CPU time 543.26 seconds
Started May 05 02:57:48 PM PDT 24
Finished May 05 03:06:52 PM PDT 24
Peak memory 265388 kb
Host smart-1bd2e16c-777a-4f62-a0da-a541f50e4ee7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514856635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2514856635
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.46528023
Short name T711
Test name
Test status
Simulation time 629654540 ps
CPU time 12.58 seconds
Started May 05 02:57:49 PM PDT 24
Finished May 05 02:58:02 PM PDT 24
Peak memory 256304 kb
Host smart-f07e8f5c-6041-441f-9834-670821be0adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=46528023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.46528023
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2298931293
Short name T791
Test name
Test status
Simulation time 12000963 ps
CPU time 1.61 seconds
Started May 05 02:58:44 PM PDT 24
Finished May 05 02:58:46 PM PDT 24
Peak memory 236884 kb
Host smart-d2f785eb-9576-4c41-8102-9e7797034726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2298931293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2298931293
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2566413262
Short name T719
Test name
Test status
Simulation time 8988607 ps
CPU time 1.24 seconds
Started May 05 02:58:45 PM PDT 24
Finished May 05 02:58:47 PM PDT 24
Peak memory 235996 kb
Host smart-550831f8-5f1a-4b07-aa19-51623be77499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2566413262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2566413262
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1589190127
Short name T762
Test name
Test status
Simulation time 6591037 ps
CPU time 1.32 seconds
Started May 05 02:58:45 PM PDT 24
Finished May 05 02:58:47 PM PDT 24
Peak memory 234940 kb
Host smart-8ca24c3d-6981-41a7-a956-ae2af7b6f22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1589190127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1589190127
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.164332224
Short name T743
Test name
Test status
Simulation time 43885210 ps
CPU time 1.34 seconds
Started May 05 02:58:43 PM PDT 24
Finished May 05 02:58:45 PM PDT 24
Peak memory 236828 kb
Host smart-7fba1d43-30f6-4a46-bc4b-031642a6c118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=164332224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.164332224
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3974281887
Short name T333
Test name
Test status
Simulation time 21500019 ps
CPU time 1.33 seconds
Started May 05 02:58:44 PM PDT 24
Finished May 05 02:58:46 PM PDT 24
Peak memory 235952 kb
Host smart-797b2833-c03e-4ca8-a966-fefe464708e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3974281887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3974281887
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3143739108
Short name T776
Test name
Test status
Simulation time 12727323 ps
CPU time 1.65 seconds
Started May 05 02:58:54 PM PDT 24
Finished May 05 02:58:56 PM PDT 24
Peak memory 235976 kb
Host smart-6e337e3d-ea38-40bd-92fa-63a1bbcd1dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3143739108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3143739108
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1967878975
Short name T817
Test name
Test status
Simulation time 6500045 ps
CPU time 1.43 seconds
Started May 05 02:58:50 PM PDT 24
Finished May 05 02:58:52 PM PDT 24
Peak memory 236940 kb
Host smart-310aa3f1-b3c5-4d8c-8c8d-df64f13865dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1967878975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1967878975
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1747079959
Short name T337
Test name
Test status
Simulation time 19734744 ps
CPU time 1.29 seconds
Started May 05 02:58:49 PM PDT 24
Finished May 05 02:58:51 PM PDT 24
Peak memory 236884 kb
Host smart-3d708ead-bedd-493a-ba8e-f7858dd4bd62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1747079959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1747079959
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.413577222
Short name T755
Test name
Test status
Simulation time 11987525 ps
CPU time 1.22 seconds
Started May 05 02:58:49 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 235016 kb
Host smart-a6723e16-055f-43ae-8364-1197157f114b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=413577222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.413577222
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2250601218
Short name T738
Test name
Test status
Simulation time 11738938 ps
CPU time 1.38 seconds
Started May 05 02:58:51 PM PDT 24
Finished May 05 02:58:53 PM PDT 24
Peak memory 235992 kb
Host smart-fce7bf10-b9b9-4c0f-9624-2e69aa63acaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2250601218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2250601218
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3726561911
Short name T758
Test name
Test status
Simulation time 3837431712 ps
CPU time 241.22 seconds
Started May 05 02:57:56 PM PDT 24
Finished May 05 03:01:57 PM PDT 24
Peak memory 240528 kb
Host smart-037d17a0-50f5-46a4-b1b5-a33281dd3ccf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3726561911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3726561911
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.104937520
Short name T773
Test name
Test status
Simulation time 3269706320 ps
CPU time 83.4 seconds
Started May 05 02:57:58 PM PDT 24
Finished May 05 02:59:22 PM PDT 24
Peak memory 240468 kb
Host smart-a9528b9b-2d79-4b43-b162-62bffe8f9134
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=104937520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.104937520
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3589202747
Short name T220
Test name
Test status
Simulation time 205467908 ps
CPU time 4.87 seconds
Started May 05 02:57:57 PM PDT 24
Finished May 05 02:58:02 PM PDT 24
Peak memory 240572 kb
Host smart-5598a3a8-e153-4df7-8737-4bb4f3b9df0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3589202747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3589202747
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.594488391
Short name T811
Test name
Test status
Simulation time 294264806 ps
CPU time 12.04 seconds
Started May 05 02:57:58 PM PDT 24
Finished May 05 02:58:11 PM PDT 24
Peak memory 242752 kb
Host smart-03f7315d-a806-48d1-80ca-103711d332cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594488391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.594488391
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.90759315
Short name T805
Test name
Test status
Simulation time 136708833 ps
CPU time 5.05 seconds
Started May 05 02:57:56 PM PDT 24
Finished May 05 02:58:01 PM PDT 24
Peak memory 240368 kb
Host smart-e90252bf-3f0d-4ad0-9683-dadc1bd09e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=90759315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.90759315
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2980725433
Short name T734
Test name
Test status
Simulation time 8489104 ps
CPU time 1.33 seconds
Started May 05 02:57:57 PM PDT 24
Finished May 05 02:57:59 PM PDT 24
Peak memory 236924 kb
Host smart-8b692006-81f3-434c-bb14-88918347a409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2980725433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2980725433
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2210860168
Short name T819
Test name
Test status
Simulation time 1292116137 ps
CPU time 18.32 seconds
Started May 05 02:57:56 PM PDT 24
Finished May 05 02:58:15 PM PDT 24
Peak memory 244176 kb
Host smart-45a51f24-e702-468e-9ac8-9c9267ec0b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2210860168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2210860168
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2635714550
Short name T175
Test name
Test status
Simulation time 16682660340 ps
CPU time 596.25 seconds
Started May 05 02:57:54 PM PDT 24
Finished May 05 03:07:51 PM PDT 24
Peak memory 265464 kb
Host smart-91c206a6-96e2-4eb9-b741-eb7f501f8801
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635714550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2635714550
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3786505301
Short name T802
Test name
Test status
Simulation time 59965798 ps
CPU time 6.41 seconds
Started May 05 02:57:55 PM PDT 24
Finished May 05 02:58:01 PM PDT 24
Peak memory 252340 kb
Host smart-74fed5c7-fbd0-4d09-8e33-65179f0d496f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3786505301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3786505301
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3729725843
Short name T731
Test name
Test status
Simulation time 8265699 ps
CPU time 1.45 seconds
Started May 05 02:58:53 PM PDT 24
Finished May 05 02:58:55 PM PDT 24
Peak memory 235012 kb
Host smart-2bbeebb6-b599-4204-a8d3-d58798a04abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3729725843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3729725843
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4007990161
Short name T335
Test name
Test status
Simulation time 9104905 ps
CPU time 1.5 seconds
Started May 05 02:58:48 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 236040 kb
Host smart-78686354-5b09-47e7-b6b7-06ddc544dca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4007990161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4007990161
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3163411707
Short name T756
Test name
Test status
Simulation time 7590769 ps
CPU time 1.41 seconds
Started May 05 02:58:48 PM PDT 24
Finished May 05 02:58:49 PM PDT 24
Peak memory 236936 kb
Host smart-19510cc2-1785-4873-af28-747509f31825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3163411707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3163411707
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1060727072
Short name T739
Test name
Test status
Simulation time 12896899 ps
CPU time 1.35 seconds
Started May 05 02:58:49 PM PDT 24
Finished May 05 02:58:51 PM PDT 24
Peak memory 235904 kb
Host smart-a1520007-a44c-4ff9-a0f5-d921426d574f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1060727072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1060727072
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.284492516
Short name T771
Test name
Test status
Simulation time 11051045 ps
CPU time 1.37 seconds
Started May 05 02:58:48 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 234948 kb
Host smart-d54a3f68-4844-45fb-b84d-0a65f52d3d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=284492516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.284492516
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3658865182
Short name T749
Test name
Test status
Simulation time 11743485 ps
CPU time 1.36 seconds
Started May 05 02:58:47 PM PDT 24
Finished May 05 02:58:49 PM PDT 24
Peak memory 236932 kb
Host smart-7c1ac801-7261-4d27-8dd3-f16229aa0c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3658865182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3658865182
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2575461451
Short name T825
Test name
Test status
Simulation time 6244351 ps
CPU time 1.28 seconds
Started May 05 02:58:48 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 235972 kb
Host smart-dbe8d657-6623-4395-90b9-b87e4fb19553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2575461451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2575461451
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3407912454
Short name T781
Test name
Test status
Simulation time 8118891 ps
CPU time 1.49 seconds
Started May 05 02:58:49 PM PDT 24
Finished May 05 02:58:51 PM PDT 24
Peak memory 236912 kb
Host smart-26d470b6-f122-4d78-924d-6f750ae5d101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3407912454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3407912454
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3655243557
Short name T787
Test name
Test status
Simulation time 9859140 ps
CPU time 1.58 seconds
Started May 05 02:58:50 PM PDT 24
Finished May 05 02:58:52 PM PDT 24
Peak memory 236900 kb
Host smart-799dbb29-44f3-4b4a-9863-554a87c571cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3655243557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3655243557
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3324187541
Short name T822
Test name
Test status
Simulation time 20897998 ps
CPU time 1.33 seconds
Started May 05 02:58:50 PM PDT 24
Finished May 05 02:58:52 PM PDT 24
Peak memory 236004 kb
Host smart-78f47a30-0deb-462b-b87d-d86f7247e87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324187541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3324187541
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2386945130
Short name T199
Test name
Test status
Simulation time 1673788405 ps
CPU time 115.13 seconds
Started May 05 02:58:01 PM PDT 24
Finished May 05 02:59:56 PM PDT 24
Peak memory 236820 kb
Host smart-e82f1f62-23ab-4673-9622-a8bc9c79fd0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2386945130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2386945130
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4045720427
Short name T765
Test name
Test status
Simulation time 13257340369 ps
CPU time 206.69 seconds
Started May 05 02:58:02 PM PDT 24
Finished May 05 03:01:29 PM PDT 24
Peak memory 235992 kb
Host smart-a6b6a248-08a9-4333-bbf6-1f8f5963ae54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4045720427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4045720427
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.329119190
Short name T828
Test name
Test status
Simulation time 365193581 ps
CPU time 8.25 seconds
Started May 05 02:58:03 PM PDT 24
Finished May 05 02:58:12 PM PDT 24
Peak memory 240376 kb
Host smart-8343181d-1098-4df4-ad38-ea532ed7f19e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=329119190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.329119190
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3823759080
Short name T722
Test name
Test status
Simulation time 33913329 ps
CPU time 4.62 seconds
Started May 05 02:58:02 PM PDT 24
Finished May 05 02:58:08 PM PDT 24
Peak memory 240140 kb
Host smart-e4acba78-fe1b-40c0-8173-bdfb31dace28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823759080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3823759080
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.773485097
Short name T198
Test name
Test status
Simulation time 74748992 ps
CPU time 4.5 seconds
Started May 05 02:58:02 PM PDT 24
Finished May 05 02:58:07 PM PDT 24
Peak memory 235868 kb
Host smart-30befb59-7a2d-4406-8b50-f2e8dbd69cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=773485097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.773485097
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1141034865
Short name T797
Test name
Test status
Simulation time 12866616 ps
CPU time 1.35 seconds
Started May 05 02:58:03 PM PDT 24
Finished May 05 02:58:05 PM PDT 24
Peak memory 235972 kb
Host smart-abd83b11-1fa2-4449-8a4f-8a5e79a5c553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1141034865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1141034865
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.63262424
Short name T733
Test name
Test status
Simulation time 2466058184 ps
CPU time 19.62 seconds
Started May 05 02:58:02 PM PDT 24
Finished May 05 02:58:22 PM PDT 24
Peak memory 248712 kb
Host smart-8402cb4b-5272-4f47-8288-0b903e12fe05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=63262424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outst
anding.63262424
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1379585859
Short name T174
Test name
Test status
Simulation time 2367596485 ps
CPU time 303.6 seconds
Started May 05 02:57:57 PM PDT 24
Finished May 05 03:03:01 PM PDT 24
Peak memory 265384 kb
Host smart-306fe7bf-1883-463c-8574-15434e578d6e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379585859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1379585859
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.787549907
Short name T815
Test name
Test status
Simulation time 92928766 ps
CPU time 10.53 seconds
Started May 05 02:57:57 PM PDT 24
Finished May 05 02:58:08 PM PDT 24
Peak memory 247888 kb
Host smart-d1cd31ba-3d35-475f-b70a-bee8676e49a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=787549907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.787549907
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2429972258
Short name T727
Test name
Test status
Simulation time 10710923 ps
CPU time 1.51 seconds
Started May 05 02:58:50 PM PDT 24
Finished May 05 02:58:52 PM PDT 24
Peak memory 235972 kb
Host smart-e3b3ce47-412e-43e1-a0af-cc7ebd16d7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2429972258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2429972258
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.898217899
Short name T336
Test name
Test status
Simulation time 22221804 ps
CPU time 1.41 seconds
Started May 05 02:58:55 PM PDT 24
Finished May 05 02:58:57 PM PDT 24
Peak memory 236912 kb
Host smart-6cfabd06-b213-436c-8e8e-b692d2f69278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=898217899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.898217899
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3785390749
Short name T761
Test name
Test status
Simulation time 12471828 ps
CPU time 1.44 seconds
Started May 05 02:58:51 PM PDT 24
Finished May 05 02:58:53 PM PDT 24
Peak memory 236908 kb
Host smart-839ec774-baf2-43e9-95a9-44353dde8fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3785390749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3785390749
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1699428682
Short name T808
Test name
Test status
Simulation time 13805629 ps
CPU time 1.63 seconds
Started May 05 02:58:53 PM PDT 24
Finished May 05 02:58:55 PM PDT 24
Peak memory 235916 kb
Host smart-1bf46472-aa70-46e0-b40b-0c1578688725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1699428682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1699428682
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4280580422
Short name T184
Test name
Test status
Simulation time 15277660 ps
CPU time 1.28 seconds
Started May 05 02:58:53 PM PDT 24
Finished May 05 02:58:54 PM PDT 24
Peak memory 234952 kb
Host smart-7838bb47-cc46-44b8-9dfc-4675e04aa842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4280580422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4280580422
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2483679294
Short name T754
Test name
Test status
Simulation time 8962187 ps
CPU time 1.55 seconds
Started May 05 02:58:52 PM PDT 24
Finished May 05 02:58:54 PM PDT 24
Peak memory 236780 kb
Host smart-45916958-26f6-4fab-b1f4-06509d36d7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2483679294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2483679294
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2951350927
Short name T801
Test name
Test status
Simulation time 16382584 ps
CPU time 1.3 seconds
Started May 05 02:58:53 PM PDT 24
Finished May 05 02:58:55 PM PDT 24
Peak memory 236916 kb
Host smart-1f6fadd7-0180-4937-bc35-b43c27e168d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2951350927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2951350927
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3257065717
Short name T723
Test name
Test status
Simulation time 6937723 ps
CPU time 1.34 seconds
Started May 05 02:58:52 PM PDT 24
Finished May 05 02:58:54 PM PDT 24
Peak memory 236912 kb
Host smart-e012c48a-af9b-4103-a4a5-171e7ad12f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3257065717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3257065717
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1401771524
Short name T185
Test name
Test status
Simulation time 7966688 ps
CPU time 1.46 seconds
Started May 05 02:58:52 PM PDT 24
Finished May 05 02:58:54 PM PDT 24
Peak memory 236928 kb
Host smart-02ac6d2f-0039-482b-a4ea-7e3d6cf056fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1401771524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1401771524
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3007728366
Short name T796
Test name
Test status
Simulation time 36046783 ps
CPU time 4.89 seconds
Started May 05 02:58:13 PM PDT 24
Finished May 05 02:58:18 PM PDT 24
Peak memory 240512 kb
Host smart-6491ba12-c393-4fc1-a92c-07aa759cbbd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007728366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3007728366
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1158445054
Short name T823
Test name
Test status
Simulation time 96394995 ps
CPU time 7.71 seconds
Started May 05 02:58:06 PM PDT 24
Finished May 05 02:58:15 PM PDT 24
Peak memory 237008 kb
Host smart-afefa2a0-2412-4914-aaa9-2af4ed3051da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1158445054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1158445054
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2478750634
Short name T763
Test name
Test status
Simulation time 14701593 ps
CPU time 1.45 seconds
Started May 05 02:58:05 PM PDT 24
Finished May 05 02:58:07 PM PDT 24
Peak memory 236928 kb
Host smart-1addb39d-7a35-473c-ab28-b15c4cb18bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2478750634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2478750634
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.375258226
Short name T216
Test name
Test status
Simulation time 1992915089 ps
CPU time 36.53 seconds
Started May 05 02:58:08 PM PDT 24
Finished May 05 02:58:45 PM PDT 24
Peak memory 244160 kb
Host smart-c4e1b604-9446-4f1b-b879-645227fbecc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=375258226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.375258226
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2529327833
Short name T167
Test name
Test status
Simulation time 2084546928 ps
CPU time 130.27 seconds
Started May 05 02:58:06 PM PDT 24
Finished May 05 03:00:17 PM PDT 24
Peak memory 266340 kb
Host smart-76943c62-b84a-4883-9518-0b8bb3138e95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2529327833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2529327833
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.859252249
Short name T177
Test name
Test status
Simulation time 24064917847 ps
CPU time 994.38 seconds
Started May 05 02:58:06 PM PDT 24
Finished May 05 03:14:41 PM PDT 24
Peak memory 273628 kb
Host smart-4a2ce28c-b0b8-4124-ba3a-ac8c1a105f3c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859252249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.859252249
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3696319620
Short name T712
Test name
Test status
Simulation time 624282008 ps
CPU time 11.51 seconds
Started May 05 02:58:06 PM PDT 24
Finished May 05 02:58:18 PM PDT 24
Peak memory 252640 kb
Host smart-1a9cbb2f-1c67-42db-a8a4-26539ff8eb1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696319620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3696319620
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3284010769
Short name T221
Test name
Test status
Simulation time 89907058 ps
CPU time 5.21 seconds
Started May 05 02:58:06 PM PDT 24
Finished May 05 02:58:12 PM PDT 24
Peak memory 236876 kb
Host smart-fa4cf4be-7864-4d4e-849c-466c1305189f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3284010769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3284010769
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4087875118
Short name T716
Test name
Test status
Simulation time 346665165 ps
CPU time 4.24 seconds
Started May 05 02:58:12 PM PDT 24
Finished May 05 02:58:16 PM PDT 24
Peak memory 239272 kb
Host smart-0fffa04e-ac75-440e-86d8-db71e0ad5ea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087875118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4087875118
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2367859216
Short name T798
Test name
Test status
Simulation time 129434680 ps
CPU time 7.41 seconds
Started May 05 02:58:10 PM PDT 24
Finished May 05 02:58:17 PM PDT 24
Peak memory 235768 kb
Host smart-867499c5-9165-406a-95b3-da8e069185db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2367859216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2367859216
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.101909649
Short name T750
Test name
Test status
Simulation time 17990120 ps
CPU time 1.32 seconds
Started May 05 02:58:12 PM PDT 24
Finished May 05 02:58:14 PM PDT 24
Peak memory 236884 kb
Host smart-08190766-f16c-4419-849a-bdb17aed2ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=101909649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.101909649
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2045588885
Short name T725
Test name
Test status
Simulation time 500119596 ps
CPU time 18.21 seconds
Started May 05 02:58:13 PM PDT 24
Finished May 05 02:58:31 PM PDT 24
Peak memory 245084 kb
Host smart-1fd0e236-93a3-4155-84ae-540aade8b1ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2045588885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2045588885
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1623353334
Short name T340
Test name
Test status
Simulation time 4640651680 ps
CPU time 288.37 seconds
Started May 05 02:58:10 PM PDT 24
Finished May 05 03:02:59 PM PDT 24
Peak memory 269540 kb
Host smart-554a19c0-30e9-4462-abad-6d2bb54196d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623353334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1623353334
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2970722165
Short name T799
Test name
Test status
Simulation time 2036828395 ps
CPU time 8.81 seconds
Started May 05 02:58:11 PM PDT 24
Finished May 05 02:58:20 PM PDT 24
Peak memory 248680 kb
Host smart-d6450f04-dfa6-4fea-a289-3fd89c5756b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2970722165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2970722165
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2768623584
Short name T795
Test name
Test status
Simulation time 240294670 ps
CPU time 4.82 seconds
Started May 05 02:58:14 PM PDT 24
Finished May 05 02:58:19 PM PDT 24
Peak memory 237392 kb
Host smart-faa2b20f-ea95-44b6-baa0-51fe2ebc74a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768623584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2768623584
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3507858836
Short name T217
Test name
Test status
Simulation time 62161031 ps
CPU time 5.11 seconds
Started May 05 02:58:16 PM PDT 24
Finished May 05 02:58:21 PM PDT 24
Peak memory 240352 kb
Host smart-9fe19bf3-2387-4492-8528-ffb7bf7e9eec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3507858836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3507858836
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4135781869
Short name T774
Test name
Test status
Simulation time 26472800 ps
CPU time 1.42 seconds
Started May 05 02:58:15 PM PDT 24
Finished May 05 02:58:17 PM PDT 24
Peak memory 235992 kb
Host smart-9a62fc9c-67a6-42a8-96d2-65cddfc324f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4135781869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4135781869
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3059840293
Short name T219
Test name
Test status
Simulation time 3935460493 ps
CPU time 41.9 seconds
Started May 05 02:58:17 PM PDT 24
Finished May 05 02:58:59 PM PDT 24
Peak memory 245148 kb
Host smart-1bec4038-16c1-40ca-8e39-17c1f5b97986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3059840293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3059840293
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3457128432
Short name T163
Test name
Test status
Simulation time 31379113338 ps
CPU time 1134.48 seconds
Started May 05 02:58:10 PM PDT 24
Finished May 05 03:17:05 PM PDT 24
Peak memory 266404 kb
Host smart-fc31bad8-5f28-4d0f-aa84-971d815729aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457128432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3457128432
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1765823026
Short name T720
Test name
Test status
Simulation time 536965679 ps
CPU time 11.58 seconds
Started May 05 02:58:16 PM PDT 24
Finished May 05 02:58:28 PM PDT 24
Peak memory 248724 kb
Host smart-75fc023b-4670-4822-900b-5c34c0aa719b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1765823026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1765823026
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1034097635
Short name T813
Test name
Test status
Simulation time 172648105 ps
CPU time 3.52 seconds
Started May 05 02:58:17 PM PDT 24
Finished May 05 02:58:20 PM PDT 24
Peak memory 236884 kb
Host smart-f3bd0c75-d55e-4eda-ac78-38519a06625b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1034097635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1034097635
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3370544300
Short name T764
Test name
Test status
Simulation time 154603101 ps
CPU time 10.99 seconds
Started May 05 02:58:21 PM PDT 24
Finished May 05 02:58:33 PM PDT 24
Peak memory 239816 kb
Host smart-3142bd70-a5c8-4198-a353-409060fa5d96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370544300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3370544300
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2936124420
Short name T339
Test name
Test status
Simulation time 1443463239 ps
CPU time 6.82 seconds
Started May 05 02:58:19 PM PDT 24
Finished May 05 02:58:26 PM PDT 24
Peak memory 235744 kb
Host smart-095c1fb1-fd8c-4deb-b237-fdb2b2bdf0f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2936124420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2936124420
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1838444406
Short name T800
Test name
Test status
Simulation time 14358804 ps
CPU time 1.3 seconds
Started May 05 02:58:19 PM PDT 24
Finished May 05 02:58:21 PM PDT 24
Peak memory 236008 kb
Host smart-cf49af30-9995-484a-8916-68b575ee6895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1838444406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1838444406
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3103172092
Short name T737
Test name
Test status
Simulation time 1261167581 ps
CPU time 17.32 seconds
Started May 05 02:58:18 PM PDT 24
Finished May 05 02:58:36 PM PDT 24
Peak memory 244172 kb
Host smart-a10149db-1ef1-4068-b304-3626ec3619f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3103172092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3103172092
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3491644954
Short name T803
Test name
Test status
Simulation time 19233516701 ps
CPU time 173.72 seconds
Started May 05 02:58:18 PM PDT 24
Finished May 05 03:01:12 PM PDT 24
Peak memory 265424 kb
Host smart-81b82cc4-8aea-4e42-bc8e-b0783c0dc0ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3491644954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3491644954
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4260190874
Short name T249
Test name
Test status
Simulation time 586285134 ps
CPU time 17.73 seconds
Started May 05 02:58:19 PM PDT 24
Finished May 05 02:58:37 PM PDT 24
Peak memory 250064 kb
Host smart-7ca4d78c-b4d1-4c1e-9f5b-28774d47c2b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4260190874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4260190874
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2101769213
Short name T744
Test name
Test status
Simulation time 106380737 ps
CPU time 4.28 seconds
Started May 05 02:58:21 PM PDT 24
Finished May 05 02:58:25 PM PDT 24
Peak memory 237204 kb
Host smart-1b153517-704a-4f0c-9564-bd9d1c61546c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2101769213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2101769213
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1959725500
Short name T344
Test name
Test status
Simulation time 583321160 ps
CPU time 11.1 seconds
Started May 05 02:58:24 PM PDT 24
Finished May 05 02:58:35 PM PDT 24
Peak memory 250832 kb
Host smart-8c992b92-eea8-4290-b57f-24be88e46141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959725500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1959725500
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4068974708
Short name T718
Test name
Test status
Simulation time 188481796 ps
CPU time 4.71 seconds
Started May 05 02:58:21 PM PDT 24
Finished May 05 02:58:27 PM PDT 24
Peak memory 236852 kb
Host smart-b232b278-2293-4e6b-bdbe-67aa78f8f407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4068974708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4068974708
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2991157946
Short name T783
Test name
Test status
Simulation time 9065079 ps
CPU time 1.45 seconds
Started May 05 02:58:22 PM PDT 24
Finished May 05 02:58:24 PM PDT 24
Peak memory 236008 kb
Host smart-001a53fa-be6a-404a-b9f4-05c1cf1018d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2991157946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2991157946
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1310061345
Short name T760
Test name
Test status
Simulation time 164933305 ps
CPU time 21.04 seconds
Started May 05 02:58:21 PM PDT 24
Finished May 05 02:58:42 PM PDT 24
Peak memory 245132 kb
Host smart-b2590810-4896-40ae-ad35-0011b650d77b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1310061345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1310061345
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4174453363
Short name T721
Test name
Test status
Simulation time 343393189 ps
CPU time 6.77 seconds
Started May 05 02:58:19 PM PDT 24
Finished May 05 02:58:26 PM PDT 24
Peak memory 246652 kb
Host smart-d72c4159-076a-4c25-8ac7-787b90151337
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4174453363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4174453363
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4020070777
Short name T818
Test name
Test status
Simulation time 2180973812 ps
CPU time 31.46 seconds
Started May 05 02:58:18 PM PDT 24
Finished May 05 02:58:50 PM PDT 24
Peak memory 240524 kb
Host smart-7fc1471c-a964-4f71-8a26-3bdad51c80bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4020070777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4020070777
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2079054137
Short name T516
Test name
Test status
Simulation time 7192273055 ps
CPU time 785.33 seconds
Started May 05 02:18:31 PM PDT 24
Finished May 05 02:31:38 PM PDT 24
Peak memory 273360 kb
Host smart-ac15f172-a206-4b3e-be14-1c1a0155612f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079054137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2079054137
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1113034049
Short name T404
Test name
Test status
Simulation time 42679686191 ps
CPU time 140.59 seconds
Started May 05 02:18:31 PM PDT 24
Finished May 05 02:20:52 PM PDT 24
Peak memory 256936 kb
Host smart-518bd6ac-15de-4f53-8c04-c1c7c86c11eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130
34049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1113034049
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2313186764
Short name T627
Test name
Test status
Simulation time 127647291 ps
CPU time 5.38 seconds
Started May 05 02:18:34 PM PDT 24
Finished May 05 02:18:40 PM PDT 24
Peak memory 250792 kb
Host smart-f9e8b3c7-ca99-4109-a5a4-91fae2b35627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23131
86764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2313186764
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1333345569
Short name T633
Test name
Test status
Simulation time 89066872659 ps
CPU time 1162.7 seconds
Started May 05 02:18:36 PM PDT 24
Finished May 05 02:37:59 PM PDT 24
Peak memory 283196 kb
Host smart-26765a21-cd0b-40b8-baea-251a6b1c455f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333345569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1333345569
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3878975849
Short name T614
Test name
Test status
Simulation time 28359287740 ps
CPU time 1119.4 seconds
Started May 05 02:18:31 PM PDT 24
Finished May 05 02:37:12 PM PDT 24
Peak memory 288792 kb
Host smart-30f97e5b-db72-41bd-897c-ddc2827d6f15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878975849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3878975849
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1893422668
Short name T304
Test name
Test status
Simulation time 9589359767 ps
CPU time 401.52 seconds
Started May 05 02:18:33 PM PDT 24
Finished May 05 02:25:15 PM PDT 24
Peak memory 248312 kb
Host smart-b11a8513-459b-4f45-ba04-735887b44b15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893422668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1893422668
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.605284469
Short name T488
Test name
Test status
Simulation time 15826169670 ps
CPU time 67.96 seconds
Started May 05 02:18:31 PM PDT 24
Finished May 05 02:19:39 PM PDT 24
Peak memory 248796 kb
Host smart-53b19631-6b93-4426-af81-514287d35c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60528
4469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.605284469
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2853184217
Short name T278
Test name
Test status
Simulation time 2447256742 ps
CPU time 62.71 seconds
Started May 05 02:18:35 PM PDT 24
Finished May 05 02:19:38 PM PDT 24
Peak memory 248796 kb
Host smart-a421a302-6334-47c8-8c37-68c5b97462c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28531
84217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2853184217
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2552535281
Short name T35
Test name
Test status
Simulation time 407150700 ps
CPU time 21.08 seconds
Started May 05 02:18:34 PM PDT 24
Finished May 05 02:18:55 PM PDT 24
Peak memory 277516 kb
Host smart-dedd9715-f21c-4932-9443-1d948eab0623
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2552535281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2552535281
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.767833638
Short name T101
Test name
Test status
Simulation time 964145725 ps
CPU time 57.53 seconds
Started May 05 02:18:34 PM PDT 24
Finished May 05 02:19:32 PM PDT 24
Peak memory 248740 kb
Host smart-d2cbe2a7-7839-42f9-b55e-c4351cb666b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76783
3638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.767833638
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2185755478
Short name T623
Test name
Test status
Simulation time 501421704 ps
CPU time 30.45 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:19:09 PM PDT 24
Peak memory 248824 kb
Host smart-cc203fb3-81d6-43eb-8973-2b6555799b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21857
55478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2185755478
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4228872522
Short name T112
Test name
Test status
Simulation time 15264639439 ps
CPU time 661.05 seconds
Started May 05 02:18:32 PM PDT 24
Finished May 05 02:29:33 PM PDT 24
Peak memory 273348 kb
Host smart-2a7f7dd3-d591-47a4-8f82-dd9bd36597da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228872522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4228872522
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.4217289792
Short name T229
Test name
Test status
Simulation time 653997418 ps
CPU time 3.31 seconds
Started May 05 02:18:36 PM PDT 24
Finished May 05 02:18:40 PM PDT 24
Peak memory 248868 kb
Host smart-8632bf80-ead5-4386-ba82-465acea6cb48
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4217289792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.4217289792
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1630045115
Short name T373
Test name
Test status
Simulation time 38654587251 ps
CPU time 994.61 seconds
Started May 05 02:18:35 PM PDT 24
Finished May 05 02:35:10 PM PDT 24
Peak memory 265140 kb
Host smart-1e00bb34-ef7a-4010-a757-ac3200eb2816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630045115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1630045115
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1049407538
Short name T384
Test name
Test status
Simulation time 1188737702 ps
CPU time 27.02 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:19:04 PM PDT 24
Peak memory 248756 kb
Host smart-40dccb24-d6b3-446a-9feb-a3f1c5a4ca71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1049407538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1049407538
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2312238629
Short name T252
Test name
Test status
Simulation time 984748620 ps
CPU time 83.7 seconds
Started May 05 02:18:34 PM PDT 24
Finished May 05 02:19:58 PM PDT 24
Peak memory 256916 kb
Host smart-fd37287c-23c4-44ff-8c1e-f353b96c0b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23122
38629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2312238629
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1184953038
Short name T581
Test name
Test status
Simulation time 379753719 ps
CPU time 30.89 seconds
Started May 05 02:18:34 PM PDT 24
Finished May 05 02:19:05 PM PDT 24
Peak memory 255940 kb
Host smart-921f4078-b07e-4582-89fd-69186324c968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11849
53038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1184953038
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.804447941
Short name T543
Test name
Test status
Simulation time 47620399783 ps
CPU time 1087.44 seconds
Started May 05 02:18:33 PM PDT 24
Finished May 05 02:36:41 PM PDT 24
Peak memory 282528 kb
Host smart-a7ef3868-7f03-4739-a44f-070cfcc2b736
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804447941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.804447941
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1465531955
Short name T643
Test name
Test status
Simulation time 4316989018 ps
CPU time 80.26 seconds
Started May 05 02:18:33 PM PDT 24
Finished May 05 02:19:54 PM PDT 24
Peak memory 248240 kb
Host smart-f9a12f16-7555-40d8-8284-f12af7c97a1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465531955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1465531955
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1804730972
Short name T43
Test name
Test status
Simulation time 764480155 ps
CPU time 15.03 seconds
Started May 05 02:18:35 PM PDT 24
Finished May 05 02:18:51 PM PDT 24
Peak memory 248752 kb
Host smart-8d0df22e-b3e4-429d-97cb-704ac5414fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18047
30972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1804730972
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4239008968
Short name T56
Test name
Test status
Simulation time 694146883 ps
CPU time 44.44 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:19:23 PM PDT 24
Peak memory 256076 kb
Host smart-f58ced18-e20c-4399-b2d3-db1f144208a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42390
08968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4239008968
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3831966244
Short name T13
Test name
Test status
Simulation time 329112938 ps
CPU time 10.88 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:18:55 PM PDT 24
Peak memory 277416 kb
Host smart-9dc58090-c86c-4ab7-b398-8c5fc33f2656
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3831966244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3831966244
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.278424882
Short name T654
Test name
Test status
Simulation time 268863840 ps
CPU time 4.77 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:18:43 PM PDT 24
Peak memory 240596 kb
Host smart-2e08272a-29e6-46c1-bbdb-ca43284fad58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27842
4882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.278424882
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3031468472
Short name T144
Test name
Test status
Simulation time 35951202260 ps
CPU time 1278.54 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:40:04 PM PDT 24
Peak memory 289700 kb
Host smart-d3849518-d911-42e6-aa28-6670d1cc9335
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031468472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3031468472
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4251792677
Short name T134
Test name
Test status
Simulation time 98371256386 ps
CPU time 9308.79 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 04:53:50 PM PDT 24
Peak memory 347164 kb
Host smart-3585c5af-77d1-49f6-bfb3-66b97bcef1df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251792677 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4251792677
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1689966067
Short name T133
Test name
Test status
Simulation time 6837268098 ps
CPU time 865.05 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:33:35 PM PDT 24
Peak memory 273332 kb
Host smart-e6e506a3-3c3c-4131-84a5-3a0e07bb78a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689966067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1689966067
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.754294880
Short name T363
Test name
Test status
Simulation time 2308487547 ps
CPU time 87.28 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:20:37 PM PDT 24
Peak memory 248800 kb
Host smart-333a21c4-7a53-4da8-93f1-90fb4d1b8a11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=754294880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.754294880
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.534743334
Short name T457
Test name
Test status
Simulation time 7390317574 ps
CPU time 133.59 seconds
Started May 05 02:19:02 PM PDT 24
Finished May 05 02:21:16 PM PDT 24
Peak memory 250944 kb
Host smart-11d102c9-a206-4016-932f-8192348a692a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53474
3334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.534743334
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2877394433
Short name T450
Test name
Test status
Simulation time 710923149 ps
CPU time 42.34 seconds
Started May 05 02:19:00 PM PDT 24
Finished May 05 02:19:43 PM PDT 24
Peak memory 255540 kb
Host smart-de1c4b67-46b5-4039-8b46-345886c40d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28773
94433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2877394433
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2340937469
Short name T644
Test name
Test status
Simulation time 596821399637 ps
CPU time 1486.12 seconds
Started May 05 02:19:14 PM PDT 24
Finished May 05 02:44:01 PM PDT 24
Peak memory 272772 kb
Host smart-f80dd1e3-bec3-40ad-ac34-fb212237a950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340937469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2340937469
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2478653656
Short name T531
Test name
Test status
Simulation time 4648507039 ps
CPU time 73.08 seconds
Started May 05 02:19:01 PM PDT 24
Finished May 05 02:20:15 PM PDT 24
Peak memory 248808 kb
Host smart-e091eecc-63c6-458d-9adf-eefb2feb58e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
53656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2478653656
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3166887846
Short name T458
Test name
Test status
Simulation time 991727318 ps
CPU time 67.73 seconds
Started May 05 02:19:01 PM PDT 24
Finished May 05 02:20:09 PM PDT 24
Peak memory 249096 kb
Host smart-ff845542-7163-45fd-817b-cfe6c904c7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
87846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3166887846
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.59446086
Short name T686
Test name
Test status
Simulation time 119052580 ps
CPU time 8.44 seconds
Started May 05 02:19:00 PM PDT 24
Finished May 05 02:19:09 PM PDT 24
Peak memory 248716 kb
Host smart-d24aa916-0e94-4420-9011-72fefa421f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59446
086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.59446086
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2741499462
Short name T586
Test name
Test status
Simulation time 1198849254 ps
CPU time 90.92 seconds
Started May 05 02:19:08 PM PDT 24
Finished May 05 02:20:40 PM PDT 24
Peak memory 250108 kb
Host smart-a7941816-ec9f-4582-b770-8e4108a198fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741499462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2741499462
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4117112106
Short name T411
Test name
Test status
Simulation time 157410751378 ps
CPU time 1526.33 seconds
Started May 05 02:19:08 PM PDT 24
Finished May 05 02:44:35 PM PDT 24
Peak memory 273344 kb
Host smart-b15a3db4-83ef-42cf-a570-340dcd3f7b92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117112106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4117112106
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4102816898
Short name T389
Test name
Test status
Simulation time 527509344 ps
CPU time 22.31 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:19:33 PM PDT 24
Peak memory 248756 kb
Host smart-30cfb081-cb93-4a5f-8b37-5afa3f8b6acc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4102816898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4102816898
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.4270321796
Short name T407
Test name
Test status
Simulation time 731376097 ps
CPU time 41.78 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:19:51 PM PDT 24
Peak memory 255348 kb
Host smart-c7e5f147-dacb-4ff6-84eb-1a3256b44629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42703
21796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.4270321796
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2752168007
Short name T559
Test name
Test status
Simulation time 1231585800 ps
CPU time 17.99 seconds
Started May 05 02:19:11 PM PDT 24
Finished May 05 02:19:30 PM PDT 24
Peak memory 255536 kb
Host smart-2faed449-360a-49cb-af64-8861143e389e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27521
68007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2752168007
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1778107728
Short name T318
Test name
Test status
Simulation time 694563571184 ps
CPU time 2395.22 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:59:05 PM PDT 24
Peak memory 281600 kb
Host smart-18848a47-c82b-4e20-9027-c8f23b9bbc7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778107728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1778107728
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.843568746
Short name T537
Test name
Test status
Simulation time 23836207764 ps
CPU time 1470.73 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:43:41 PM PDT 24
Peak memory 273076 kb
Host smart-106213f7-d76a-4958-93d7-2953dfb6f208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843568746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.843568746
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2682114004
Short name T606
Test name
Test status
Simulation time 307533822 ps
CPU time 19.46 seconds
Started May 05 02:19:08 PM PDT 24
Finished May 05 02:19:29 PM PDT 24
Peak memory 256920 kb
Host smart-919c3117-8bf3-41e7-b89d-9e69b0c9c6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821
14004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2682114004
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.759628745
Short name T20
Test name
Test status
Simulation time 457798598 ps
CPU time 18.67 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:19:28 PM PDT 24
Peak memory 249140 kb
Host smart-2182ed8c-015a-4f6c-b955-cf23b48b278c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75962
8745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.759628745
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.573762538
Short name T470
Test name
Test status
Simulation time 40451437 ps
CPU time 4.99 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:19:16 PM PDT 24
Peak memory 248744 kb
Host smart-99abd4e4-f858-4319-9c98-73a89d154a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57376
2538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.573762538
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2599874198
Short name T652
Test name
Test status
Simulation time 71157195415 ps
CPU time 1690.51 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:47:21 PM PDT 24
Peak memory 298640 kb
Host smart-d7aafb5f-f712-4443-a6be-d6efe7cf6a2d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599874198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2599874198
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1823303925
Short name T203
Test name
Test status
Simulation time 211984983070 ps
CPU time 4787.11 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 03:38:57 PM PDT 24
Peak memory 346908 kb
Host smart-fd49c1c9-8f30-4e39-b297-02e5f60d460a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823303925 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1823303925
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2202126201
Short name T232
Test name
Test status
Simulation time 37386525 ps
CPU time 2.21 seconds
Started May 05 02:19:11 PM PDT 24
Finished May 05 02:19:14 PM PDT 24
Peak memory 248900 kb
Host smart-2aa8c2fd-e3e3-4a6a-9396-ecacc9cfbbf2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2202126201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2202126201
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4026210423
Short name T589
Test name
Test status
Simulation time 24817401846 ps
CPU time 1281.4 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:40:32 PM PDT 24
Peak memory 273332 kb
Host smart-50785cb6-4766-4d15-8273-a578e4a96994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026210423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4026210423
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3605103771
Short name T378
Test name
Test status
Simulation time 581809647 ps
CPU time 9.57 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:19:20 PM PDT 24
Peak memory 248716 kb
Host smart-aaf3aeb5-a29e-4870-b7af-d254a6eea0ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3605103771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3605103771
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1543683032
Short name T362
Test name
Test status
Simulation time 1212140867 ps
CPU time 44.44 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:19:56 PM PDT 24
Peak memory 248752 kb
Host smart-98e28eb5-d8c3-48b2-969c-43264dea050a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
83032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1543683032
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2023718474
Short name T356
Test name
Test status
Simulation time 1719023942 ps
CPU time 46.57 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:19:57 PM PDT 24
Peak memory 255540 kb
Host smart-416ad9a7-bb79-4030-9ee0-41dc3bcbf393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
18474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2023718474
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.832339239
Short name T66
Test name
Test status
Simulation time 23802291120 ps
CPU time 1262.81 seconds
Started May 05 02:19:14 PM PDT 24
Finished May 05 02:40:18 PM PDT 24
Peak memory 272684 kb
Host smart-356569ce-2f1a-4f30-a9ce-56653c1807a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832339239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.832339239
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1342398605
Short name T274
Test name
Test status
Simulation time 108498283982 ps
CPU time 1517.9 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:44:28 PM PDT 24
Peak memory 272788 kb
Host smart-6c14097f-7123-447e-a738-2ca01ddfe785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342398605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1342398605
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2458244470
Short name T295
Test name
Test status
Simulation time 6004508362 ps
CPU time 236.24 seconds
Started May 05 02:19:14 PM PDT 24
Finished May 05 02:23:11 PM PDT 24
Peak memory 247944 kb
Host smart-1a6f5c48-691b-4f29-bff0-ca6079d0ab61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458244470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2458244470
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1122880609
Short name T681
Test name
Test status
Simulation time 2852883280 ps
CPU time 43.09 seconds
Started May 05 02:19:09 PM PDT 24
Finished May 05 02:19:52 PM PDT 24
Peak memory 248756 kb
Host smart-7e56c0e4-bc80-48f4-a292-19389e1e532f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11228
80609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1122880609
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3005048060
Short name T514
Test name
Test status
Simulation time 423777441 ps
CPU time 32.93 seconds
Started May 05 02:19:10 PM PDT 24
Finished May 05 02:19:44 PM PDT 24
Peak memory 255456 kb
Host smart-15f36a55-b2b2-45ea-8b9e-577fedd95596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30050
48060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3005048060
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3359108112
Short name T266
Test name
Test status
Simulation time 4929872599 ps
CPU time 23.48 seconds
Started May 05 02:19:11 PM PDT 24
Finished May 05 02:19:35 PM PDT 24
Peak memory 254680 kb
Host smart-ee228701-ec39-4929-813e-228e73ae23b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
08112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3359108112
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1925927319
Short name T117
Test name
Test status
Simulation time 801105217 ps
CPU time 28.13 seconds
Started May 05 02:19:08 PM PDT 24
Finished May 05 02:19:36 PM PDT 24
Peak memory 248700 kb
Host smart-43aa82de-643b-49e0-ad76-89378ee5d431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19259
27319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1925927319
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2129624730
Short name T439
Test name
Test status
Simulation time 21773546957 ps
CPU time 278.38 seconds
Started May 05 02:19:08 PM PDT 24
Finished May 05 02:23:46 PM PDT 24
Peak memory 256952 kb
Host smart-5cfcbfd8-8f8f-4121-9ae7-e1b9385f27d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129624730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2129624730
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2719353592
Short name T240
Test name
Test status
Simulation time 37256099 ps
CPU time 3.12 seconds
Started May 05 02:19:18 PM PDT 24
Finished May 05 02:19:21 PM PDT 24
Peak memory 248880 kb
Host smart-dee3d9f6-89c0-4d58-a90a-ee8b23ba2ad8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2719353592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2719353592
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.4208294179
Short name T540
Test name
Test status
Simulation time 12116369681 ps
CPU time 941.49 seconds
Started May 05 02:19:17 PM PDT 24
Finished May 05 02:34:59 PM PDT 24
Peak memory 281544 kb
Host smart-6a132fdc-e5d9-442b-93b3-d14fa1f4ce5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208294179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.4208294179
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.4027892179
Short name T246
Test name
Test status
Simulation time 5577382600 ps
CPU time 44.16 seconds
Started May 05 02:19:17 PM PDT 24
Finished May 05 02:20:02 PM PDT 24
Peak memory 248860 kb
Host smart-f6f92498-ec02-4e64-a559-9915505a874f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4027892179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4027892179
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4178174000
Short name T365
Test name
Test status
Simulation time 483954709 ps
CPU time 13.39 seconds
Started May 05 02:19:17 PM PDT 24
Finished May 05 02:19:30 PM PDT 24
Peak memory 249036 kb
Host smart-ce8a0a23-9122-4304-b028-fd356ba03ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41781
74000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4178174000
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4166192011
Short name T624
Test name
Test status
Simulation time 552558962 ps
CPU time 28.52 seconds
Started May 05 02:19:13 PM PDT 24
Finished May 05 02:19:42 PM PDT 24
Peak memory 255436 kb
Host smart-d9465380-3aba-4f98-aa79-23d409c248c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
92011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4166192011
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.4170038869
Short name T71
Test name
Test status
Simulation time 26770656936 ps
CPU time 1645.03 seconds
Started May 05 02:19:18 PM PDT 24
Finished May 05 02:46:44 PM PDT 24
Peak memory 269384 kb
Host smart-9e4bbaba-1a6d-46cc-88af-fecf7ec8e9b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170038869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.4170038869
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2245643285
Short name T70
Test name
Test status
Simulation time 24093242060 ps
CPU time 1434.28 seconds
Started May 05 02:19:19 PM PDT 24
Finished May 05 02:43:13 PM PDT 24
Peak memory 272644 kb
Host smart-da5c6aad-efca-45e1-8d19-7577a2d2d78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245643285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2245643285
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1685846329
Short name T638
Test name
Test status
Simulation time 41823322580 ps
CPU time 172.49 seconds
Started May 05 02:19:18 PM PDT 24
Finished May 05 02:22:11 PM PDT 24
Peak memory 247808 kb
Host smart-b388fb0b-ac99-41a0-ae04-8848ca67347d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685846329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1685846329
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.164596454
Short name T609
Test name
Test status
Simulation time 906924614 ps
CPU time 28.83 seconds
Started May 05 02:19:15 PM PDT 24
Finished May 05 02:19:45 PM PDT 24
Peak memory 248760 kb
Host smart-6eb106c0-78db-49ce-943d-ab5708c100ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16459
6454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.164596454
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2496261010
Short name T632
Test name
Test status
Simulation time 876330356 ps
CPU time 52.5 seconds
Started May 05 02:19:15 PM PDT 24
Finished May 05 02:20:08 PM PDT 24
Peak memory 249152 kb
Host smart-92d88fca-65e5-4b06-82f9-d23a47a05448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
61010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2496261010
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.647096971
Short name T69
Test name
Test status
Simulation time 293921206 ps
CPU time 17.66 seconds
Started May 05 02:19:19 PM PDT 24
Finished May 05 02:19:37 PM PDT 24
Peak memory 247796 kb
Host smart-58336b1c-d0a9-4ec3-b88d-0886c09b2c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64709
6971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.647096971
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3844096151
Short name T669
Test name
Test status
Simulation time 314241512 ps
CPU time 30.93 seconds
Started May 05 02:19:14 PM PDT 24
Finished May 05 02:19:46 PM PDT 24
Peak memory 248736 kb
Host smart-ee045ed7-55b4-41d1-b12a-d4f910735805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38440
96151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3844096151
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.885471421
Short name T52
Test name
Test status
Simulation time 57922458767 ps
CPU time 2895.77 seconds
Started May 05 02:19:18 PM PDT 24
Finished May 05 03:07:35 PM PDT 24
Peak memory 299616 kb
Host smart-4e1bf478-617b-4108-9a04-8a91c5c8309a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885471421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.885471421
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1786651443
Short name T464
Test name
Test status
Simulation time 60307273148 ps
CPU time 991.93 seconds
Started May 05 02:19:22 PM PDT 24
Finished May 05 02:35:54 PM PDT 24
Peak memory 273256 kb
Host smart-3360c184-8c44-4975-ab0d-d7c82514de98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786651443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1786651443
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4059225567
Short name T236
Test name
Test status
Simulation time 32759155 ps
CPU time 2.99 seconds
Started May 05 02:19:26 PM PDT 24
Finished May 05 02:19:30 PM PDT 24
Peak memory 248932 kb
Host smart-fbf14819-c313-4965-8401-607556132ce1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4059225567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4059225567
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2394487108
Short name T286
Test name
Test status
Simulation time 42521175617 ps
CPU time 1012.28 seconds
Started May 05 02:19:26 PM PDT 24
Finished May 05 02:36:19 PM PDT 24
Peak memory 272852 kb
Host smart-915c2cf0-0db7-4fd3-847f-4b99acb69d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394487108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2394487108
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1767385425
Short name T463
Test name
Test status
Simulation time 1340388013 ps
CPU time 29.12 seconds
Started May 05 02:19:27 PM PDT 24
Finished May 05 02:19:56 PM PDT 24
Peak memory 248776 kb
Host smart-84d86f6d-2777-43e7-803a-7aa6e3778dd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1767385425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1767385425
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2558700471
Short name T379
Test name
Test status
Simulation time 23526692344 ps
CPU time 173.45 seconds
Started May 05 02:19:23 PM PDT 24
Finished May 05 02:22:16 PM PDT 24
Peak memory 249952 kb
Host smart-aa84ac5f-fa30-4c31-9ce7-ba90bfa1143f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25587
00471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2558700471
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.136012430
Short name T650
Test name
Test status
Simulation time 3069887697 ps
CPU time 18.57 seconds
Started May 05 02:19:22 PM PDT 24
Finished May 05 02:19:41 PM PDT 24
Peak memory 256328 kb
Host smart-b0042805-5232-4ac7-9cc1-db41c601be43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
2430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.136012430
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1037441144
Short name T331
Test name
Test status
Simulation time 79455317985 ps
CPU time 2154.94 seconds
Started May 05 02:19:25 PM PDT 24
Finished May 05 02:55:21 PM PDT 24
Peak memory 281592 kb
Host smart-6bbd2c28-9487-4d62-8f22-4644c5ceca06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037441144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1037441144
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1661326602
Short name T456
Test name
Test status
Simulation time 384242580559 ps
CPU time 2991.22 seconds
Started May 05 02:19:27 PM PDT 24
Finished May 05 03:09:19 PM PDT 24
Peak memory 289120 kb
Host smart-4eb51b68-fc4a-4e6b-92f9-d9a0add5b8bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661326602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1661326602
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2242003808
Short name T301
Test name
Test status
Simulation time 77130452056 ps
CPU time 477.25 seconds
Started May 05 02:19:27 PM PDT 24
Finished May 05 02:27:25 PM PDT 24
Peak memory 247796 kb
Host smart-ac9a0f7d-e7ae-402e-b901-d2ef718c148d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242003808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2242003808
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.557966714
Short name T528
Test name
Test status
Simulation time 392110349 ps
CPU time 28.6 seconds
Started May 05 02:19:22 PM PDT 24
Finished May 05 02:19:51 PM PDT 24
Peak memory 248764 kb
Host smart-cdb79ed4-2874-4f07-9f66-452adba05a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55796
6714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.557966714
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1954170442
Short name T695
Test name
Test status
Simulation time 180586511 ps
CPU time 16.24 seconds
Started May 05 02:19:24 PM PDT 24
Finished May 05 02:19:41 PM PDT 24
Peak memory 248748 kb
Host smart-507fd982-bd70-4c44-bace-faa83d0008c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19541
70442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1954170442
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1051545403
Short name T262
Test name
Test status
Simulation time 2037683991 ps
CPU time 33.21 seconds
Started May 05 02:19:23 PM PDT 24
Finished May 05 02:19:56 PM PDT 24
Peak memory 255476 kb
Host smart-3f6b34c7-b882-4bc7-8a31-0c061a68f22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
45403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1051545403
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1217468675
Short name T466
Test name
Test status
Simulation time 441225711 ps
CPU time 12.99 seconds
Started May 05 02:19:20 PM PDT 24
Finished May 05 02:19:34 PM PDT 24
Peak memory 254088 kb
Host smart-ad89e382-12d2-461e-84c0-4ee2397437c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12174
68675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1217468675
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4179497170
Short name T210
Test name
Test status
Simulation time 31770535250 ps
CPU time 817.72 seconds
Started May 05 02:19:26 PM PDT 24
Finished May 05 02:33:04 PM PDT 24
Peak memory 266576 kb
Host smart-b8bea79b-0e20-497b-9835-1e4f3a01bade
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179497170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4179497170
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.962087259
Short name T225
Test name
Test status
Simulation time 169922585 ps
CPU time 3.58 seconds
Started May 05 02:19:32 PM PDT 24
Finished May 05 02:19:36 PM PDT 24
Peak memory 248924 kb
Host smart-a56a727c-7bb0-4979-9605-5a0ebe050d7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=962087259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.962087259
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3737078450
Short name T497
Test name
Test status
Simulation time 1210165568 ps
CPU time 15.57 seconds
Started May 05 02:19:31 PM PDT 24
Finished May 05 02:19:47 PM PDT 24
Peak memory 248712 kb
Host smart-a3c85074-4363-42e8-85d5-fd66df8cb3a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3737078450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3737078450
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1048465582
Short name T613
Test name
Test status
Simulation time 3832083506 ps
CPU time 207.09 seconds
Started May 05 02:19:26 PM PDT 24
Finished May 05 02:22:54 PM PDT 24
Peak memory 256868 kb
Host smart-af36a426-34d3-472f-8446-66c026b0678a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
65582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1048465582
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.566560055
Short name T588
Test name
Test status
Simulation time 406323215 ps
CPU time 5.17 seconds
Started May 05 02:19:27 PM PDT 24
Finished May 05 02:19:32 PM PDT 24
Peak memory 240516 kb
Host smart-20ea6fa2-3a0b-4cbf-b8e1-a2a8209f0612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56656
0055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.566560055
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.406166036
Short name T206
Test name
Test status
Simulation time 220008892268 ps
CPU time 1631.82 seconds
Started May 05 02:19:31 PM PDT 24
Finished May 05 02:46:43 PM PDT 24
Peak memory 282140 kb
Host smart-7606ff7f-b336-492f-93cb-8abc91e76b61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406166036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.406166036
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3927213325
Short name T480
Test name
Test status
Simulation time 198787812 ps
CPU time 8.51 seconds
Started May 05 02:19:28 PM PDT 24
Finished May 05 02:19:37 PM PDT 24
Peak memory 248696 kb
Host smart-c85ec5dc-15ef-4f26-a821-fd7f1ab5f929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39272
13325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3927213325
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.204258214
Short name T108
Test name
Test status
Simulation time 8715244943 ps
CPU time 54.24 seconds
Started May 05 02:19:28 PM PDT 24
Finished May 05 02:20:23 PM PDT 24
Peak memory 249036 kb
Host smart-c1933b36-6466-4594-81f5-b8b4e5112f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425
8214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.204258214
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3217289032
Short name T454
Test name
Test status
Simulation time 280491497 ps
CPU time 16.47 seconds
Started May 05 02:19:30 PM PDT 24
Finished May 05 02:19:47 PM PDT 24
Peak memory 248740 kb
Host smart-a34ee0bb-2d9c-45bf-a439-5807003dd5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32172
89032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3217289032
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2891867124
Short name T591
Test name
Test status
Simulation time 138874163527 ps
CPU time 1974.99 seconds
Started May 05 02:19:33 PM PDT 24
Finished May 05 02:52:28 PM PDT 24
Peak memory 289672 kb
Host smart-62aed65b-6cd8-4c90-bbfa-570cbaec5738
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891867124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2891867124
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2942524308
Short name T484
Test name
Test status
Simulation time 39985965133 ps
CPU time 2589.89 seconds
Started May 05 02:19:31 PM PDT 24
Finished May 05 03:02:42 PM PDT 24
Peak memory 305324 kb
Host smart-adef729f-6517-459e-90fc-a0bbd2e59cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942524308 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2942524308
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3602290744
Short name T109
Test name
Test status
Simulation time 59060767689 ps
CPU time 1702.81 seconds
Started May 05 02:19:36 PM PDT 24
Finished May 05 02:47:59 PM PDT 24
Peak memory 269224 kb
Host smart-4e68a813-4b5b-4a8a-8a8c-c8964b1ac019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602290744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3602290744
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3173610119
Short name T473
Test name
Test status
Simulation time 338763145 ps
CPU time 6.69 seconds
Started May 05 02:19:40 PM PDT 24
Finished May 05 02:19:47 PM PDT 24
Peak memory 248756 kb
Host smart-7eb64968-a833-4ba4-9077-ca07e354ee44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3173610119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3173610119
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2137388577
Short name T425
Test name
Test status
Simulation time 1028375284 ps
CPU time 59.36 seconds
Started May 05 02:19:37 PM PDT 24
Finished May 05 02:20:37 PM PDT 24
Peak memory 256740 kb
Host smart-5a9ddeed-92b7-42af-92fc-2e8d15f71dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
88577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2137388577
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1909271156
Short name T398
Test name
Test status
Simulation time 821219247 ps
CPU time 40.43 seconds
Started May 05 02:19:35 PM PDT 24
Finished May 05 02:20:16 PM PDT 24
Peak memory 248764 kb
Host smart-228b7566-bc79-44d2-bb54-d70e1bf3387a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19092
71156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1909271156
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.19131970
Short name T323
Test name
Test status
Simulation time 181434386148 ps
CPU time 2335.21 seconds
Started May 05 02:19:43 PM PDT 24
Finished May 05 02:58:39 PM PDT 24
Peak memory 281520 kb
Host smart-51e71f07-1482-4966-9732-9d3e427332ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19131970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.19131970
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1150257775
Short name T369
Test name
Test status
Simulation time 117366535501 ps
CPU time 1747.77 seconds
Started May 05 02:19:39 PM PDT 24
Finished May 05 02:48:48 PM PDT 24
Peak memory 285752 kb
Host smart-8d412986-d9d6-45c9-84bb-746e536c91eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150257775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1150257775
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2380262975
Short name T245
Test name
Test status
Simulation time 22746134757 ps
CPU time 467.75 seconds
Started May 05 02:19:37 PM PDT 24
Finished May 05 02:27:25 PM PDT 24
Peak memory 247092 kb
Host smart-bf461055-e4de-41ba-bb89-706293daaa5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380262975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2380262975
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.970566133
Short name T513
Test name
Test status
Simulation time 352233749 ps
CPU time 22.07 seconds
Started May 05 02:19:35 PM PDT 24
Finished May 05 02:19:58 PM PDT 24
Peak memory 248756 kb
Host smart-6d645738-01d4-4170-985f-905150678569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97056
6133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.970566133
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.434545885
Short name T397
Test name
Test status
Simulation time 279562787 ps
CPU time 16.65 seconds
Started May 05 02:19:34 PM PDT 24
Finished May 05 02:19:51 PM PDT 24
Peak memory 254012 kb
Host smart-5b163a3f-7865-4a3b-86b4-d751f3e73c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43454
5885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.434545885
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.854333997
Short name T487
Test name
Test status
Simulation time 1150842156 ps
CPU time 22.79 seconds
Started May 05 02:19:35 PM PDT 24
Finished May 05 02:19:58 PM PDT 24
Peak memory 248716 kb
Host smart-2a2663a5-f19c-4c53-8592-0184e09bf952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85433
3997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.854333997
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2736742652
Short name T444
Test name
Test status
Simulation time 18531315492 ps
CPU time 2040.16 seconds
Started May 05 02:19:41 PM PDT 24
Finished May 05 02:53:42 PM PDT 24
Peak memory 304936 kb
Host smart-f1938a35-af58-4daa-8afe-e806ed45ff2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736742652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2736742652
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.427821085
Short name T230
Test name
Test status
Simulation time 44720858 ps
CPU time 2.65 seconds
Started May 05 02:19:51 PM PDT 24
Finished May 05 02:19:54 PM PDT 24
Peak memory 248892 kb
Host smart-d188b967-c802-4a30-a0c5-cc54b6020ba4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427821085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.427821085
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4114540024
Short name T666
Test name
Test status
Simulation time 21118630760 ps
CPU time 1177.9 seconds
Started May 05 02:19:45 PM PDT 24
Finished May 05 02:39:23 PM PDT 24
Peak memory 273400 kb
Host smart-877bd181-ec9b-4a65-a9e2-555375ae69b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114540024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4114540024
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.593324807
Short name T502
Test name
Test status
Simulation time 830580237 ps
CPU time 20.24 seconds
Started May 05 02:19:45 PM PDT 24
Finished May 05 02:20:06 PM PDT 24
Peak memory 240548 kb
Host smart-ef182f0c-499c-42f7-bddd-7a33441d1242
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=593324807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.593324807
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.583057876
Short name T381
Test name
Test status
Simulation time 167906015 ps
CPU time 7.22 seconds
Started May 05 02:19:46 PM PDT 24
Finished May 05 02:19:54 PM PDT 24
Peak memory 254128 kb
Host smart-b2ae9c96-526b-4fd1-a67e-3744eac5a74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58305
7876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.583057876
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.290219749
Short name T467
Test name
Test status
Simulation time 785212463 ps
CPU time 47.5 seconds
Started May 05 02:19:49 PM PDT 24
Finished May 05 02:20:36 PM PDT 24
Peak memory 256872 kb
Host smart-07abd363-62b7-4aad-8814-7148eaa7e13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
9749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.290219749
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3097668886
Short name T491
Test name
Test status
Simulation time 13799379002 ps
CPU time 1149.13 seconds
Started May 05 02:19:46 PM PDT 24
Finished May 05 02:38:55 PM PDT 24
Peak memory 281608 kb
Host smart-4abd707a-2ba9-456c-9b8d-3d14bbe7db3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097668886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3097668886
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1510333405
Short name T208
Test name
Test status
Simulation time 16914472227 ps
CPU time 1166.95 seconds
Started May 05 02:19:46 PM PDT 24
Finished May 05 02:39:13 PM PDT 24
Peak memory 281164 kb
Host smart-f53c446a-16bd-44c0-8f27-4ce7032d1266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510333405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1510333405
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2054120782
Short name T610
Test name
Test status
Simulation time 14411267460 ps
CPU time 272.28 seconds
Started May 05 02:19:46 PM PDT 24
Finished May 05 02:24:18 PM PDT 24
Peak memory 247828 kb
Host smart-8ec50357-cc2e-48e9-9ead-0e662df5657d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054120782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2054120782
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2928679767
Short name T507
Test name
Test status
Simulation time 125859786 ps
CPU time 4.3 seconds
Started May 05 02:19:45 PM PDT 24
Finished May 05 02:19:50 PM PDT 24
Peak memory 250916 kb
Host smart-1564ebd0-4033-45a5-b4d2-bd8976bc7b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
79767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2928679767
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4146339511
Short name T106
Test name
Test status
Simulation time 834088041 ps
CPU time 23.18 seconds
Started May 05 02:19:45 PM PDT 24
Finished May 05 02:20:09 PM PDT 24
Peak memory 255528 kb
Host smart-c786db1c-0864-4792-91d3-8ac29d5782e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
39511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4146339511
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3180532069
Short name T449
Test name
Test status
Simulation time 789039617 ps
CPU time 22.61 seconds
Started May 05 02:19:48 PM PDT 24
Finished May 05 02:20:11 PM PDT 24
Peak memory 249072 kb
Host smart-3ea03194-dc9a-4c36-a140-a398aeec54a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805
32069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3180532069
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2454784869
Short name T445
Test name
Test status
Simulation time 712701414 ps
CPU time 36.36 seconds
Started May 05 02:19:40 PM PDT 24
Finished May 05 02:20:16 PM PDT 24
Peak memory 248732 kb
Host smart-8fa97434-e0a7-48f6-9013-ebbe17828af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24547
84869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2454784869
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2662889029
Short name T409
Test name
Test status
Simulation time 1134287967 ps
CPU time 90.45 seconds
Started May 05 02:19:51 PM PDT 24
Finished May 05 02:21:22 PM PDT 24
Peak memory 256232 kb
Host smart-64e5c0f7-ee51-4e9e-bc3b-0e091009d8cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662889029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2662889029
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2968338070
Short name T243
Test name
Test status
Simulation time 29865696 ps
CPU time 2.57 seconds
Started May 05 02:19:55 PM PDT 24
Finished May 05 02:19:57 PM PDT 24
Peak memory 248892 kb
Host smart-5ceb41fd-7bc4-4127-b89e-4e4de437590f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2968338070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2968338070
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3769355399
Short name T59
Test name
Test status
Simulation time 219858663226 ps
CPU time 3020.24 seconds
Started May 05 02:19:55 PM PDT 24
Finished May 05 03:10:16 PM PDT 24
Peak memory 289156 kb
Host smart-88e52356-dbb1-465b-a164-426c141b205e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769355399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3769355399
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2858518612
Short name T90
Test name
Test status
Simulation time 2483562891 ps
CPU time 10.89 seconds
Started May 05 02:19:55 PM PDT 24
Finished May 05 02:20:06 PM PDT 24
Peak memory 252824 kb
Host smart-c1628fb0-e324-4ea5-9eed-0b9f3c316e9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2858518612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2858518612
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.336734580
Short name T659
Test name
Test status
Simulation time 18142797600 ps
CPU time 217.9 seconds
Started May 05 02:19:52 PM PDT 24
Finished May 05 02:23:30 PM PDT 24
Peak memory 256888 kb
Host smart-bd73d6e3-27f0-426b-b9a0-d756998d88b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
4580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.336734580
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1222818451
Short name T3
Test name
Test status
Simulation time 241676440 ps
CPU time 4.28 seconds
Started May 05 02:19:50 PM PDT 24
Finished May 05 02:19:55 PM PDT 24
Peak memory 240552 kb
Host smart-619774fa-7c3b-4a42-a02f-4bd7503b4bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12228
18451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1222818451
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1779791121
Short name T326
Test name
Test status
Simulation time 33526951805 ps
CPU time 2007.11 seconds
Started May 05 02:19:56 PM PDT 24
Finished May 05 02:53:23 PM PDT 24
Peak memory 289732 kb
Host smart-7deff42d-0b96-4b62-bdbd-d6cd50d3267e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779791121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1779791121
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.4252354045
Short name T427
Test name
Test status
Simulation time 795301532582 ps
CPU time 2747.02 seconds
Started May 05 02:19:55 PM PDT 24
Finished May 05 03:05:42 PM PDT 24
Peak memory 289044 kb
Host smart-d4db052c-fbe3-45a9-8cc2-ddaacf7c2fcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252354045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.4252354045
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3972655010
Short name T317
Test name
Test status
Simulation time 4204921615 ps
CPU time 155.89 seconds
Started May 05 02:19:54 PM PDT 24
Finished May 05 02:22:30 PM PDT 24
Peak memory 248160 kb
Host smart-f8930c8d-fb7e-4455-88ac-6654c70f8464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972655010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3972655010
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3823930146
Short name T387
Test name
Test status
Simulation time 5117492177 ps
CPU time 36.69 seconds
Started May 05 02:19:51 PM PDT 24
Finished May 05 02:20:28 PM PDT 24
Peak memory 248784 kb
Host smart-6ccd1580-7579-49bb-b663-bdaed01e0ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38239
30146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3823930146
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1258627850
Short name T692
Test name
Test status
Simulation time 537665418 ps
CPU time 8.1 seconds
Started May 05 02:19:50 PM PDT 24
Finished May 05 02:19:59 PM PDT 24
Peak memory 250640 kb
Host smart-978b1c5b-500e-4c5a-a790-0482e13f7028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12586
27850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1258627850
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.893390054
Short name T285
Test name
Test status
Simulation time 599523265 ps
CPU time 9.48 seconds
Started May 05 02:19:50 PM PDT 24
Finished May 05 02:20:00 PM PDT 24
Peak memory 247596 kb
Host smart-cb8a7dcb-6786-4b3b-bb10-011e8f7c1ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89339
0054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.893390054
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2313245608
Short name T459
Test name
Test status
Simulation time 545082683 ps
CPU time 30.28 seconds
Started May 05 02:19:51 PM PDT 24
Finished May 05 02:20:21 PM PDT 24
Peak memory 248712 kb
Host smart-f4569669-45f3-4e32-8595-590c78d8fc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23132
45608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2313245608
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2900587928
Short name T580
Test name
Test status
Simulation time 59072196354 ps
CPU time 1863.4 seconds
Started May 05 02:19:55 PM PDT 24
Finished May 05 02:50:59 PM PDT 24
Peak memory 288592 kb
Host smart-aa6ab1c5-0c26-47c2-95ee-0dc0806b7bd8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900587928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2900587928
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.4227285893
Short name T125
Test name
Test status
Simulation time 223988611902 ps
CPU time 4530.11 seconds
Started May 05 02:19:53 PM PDT 24
Finished May 05 03:35:24 PM PDT 24
Peak memory 322216 kb
Host smart-f1674d32-06eb-4c26-9e45-3d2301fe6698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227285893 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.4227285893
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3600952518
Short name T19
Test name
Test status
Simulation time 125013261 ps
CPU time 2.46 seconds
Started May 05 02:20:03 PM PDT 24
Finished May 05 02:20:06 PM PDT 24
Peak memory 248944 kb
Host smart-6bd3a606-3cf2-4ba4-b15b-e87403615953
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3600952518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3600952518
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1637042886
Short name T618
Test name
Test status
Simulation time 42275004533 ps
CPU time 2214.09 seconds
Started May 05 02:20:00 PM PDT 24
Finished May 05 02:56:54 PM PDT 24
Peak memory 289752 kb
Host smart-9d8535e2-ed0f-4442-a40e-351c2c3cfdff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637042886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1637042886
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3026639457
Short name T461
Test name
Test status
Simulation time 1097415702 ps
CPU time 46.11 seconds
Started May 05 02:20:04 PM PDT 24
Finished May 05 02:20:50 PM PDT 24
Peak memory 248740 kb
Host smart-a72a2c92-0297-4293-a97c-ce7292ae4f0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3026639457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3026639457
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.338531292
Short name T79
Test name
Test status
Simulation time 780801430 ps
CPU time 74.07 seconds
Started May 05 02:20:04 PM PDT 24
Finished May 05 02:21:18 PM PDT 24
Peak memory 256716 kb
Host smart-80b3ec2b-9bcc-4a64-9b59-3505799e9608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
1292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.338531292
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2576393948
Short name T434
Test name
Test status
Simulation time 303449254 ps
CPU time 23.13 seconds
Started May 05 02:19:58 PM PDT 24
Finished May 05 02:20:22 PM PDT 24
Peak memory 255436 kb
Host smart-01cb0775-c3c4-45db-95a1-5021a313fd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25763
93948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2576393948
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2226045670
Short name T313
Test name
Test status
Simulation time 21279190881 ps
CPU time 1515.25 seconds
Started May 05 02:20:00 PM PDT 24
Finished May 05 02:45:15 PM PDT 24
Peak memory 288840 kb
Host smart-2f84ce75-b414-4d6f-9a61-8db2af33b1c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226045670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2226045670
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1192363891
Short name T493
Test name
Test status
Simulation time 11243032902 ps
CPU time 1088.11 seconds
Started May 05 02:20:00 PM PDT 24
Finished May 05 02:38:08 PM PDT 24
Peak memory 281552 kb
Host smart-70ff46a1-3d87-42db-8742-27db9f2b2456
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192363891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1192363891
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2222102009
Short name T311
Test name
Test status
Simulation time 6833747113 ps
CPU time 266.83 seconds
Started May 05 02:20:01 PM PDT 24
Finished May 05 02:24:28 PM PDT 24
Peak memory 247004 kb
Host smart-d1de2719-dfed-4855-a2c0-02d50cf4a557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222102009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2222102009
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2788395616
Short name T564
Test name
Test status
Simulation time 96305095 ps
CPU time 8.4 seconds
Started May 05 02:20:05 PM PDT 24
Finished May 05 02:20:13 PM PDT 24
Peak memory 248700 kb
Host smart-b2d67be7-63ec-4498-826e-2a0530e38df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883
95616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2788395616
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3144370148
Short name T51
Test name
Test status
Simulation time 284011130 ps
CPU time 9.32 seconds
Started May 05 02:19:58 PM PDT 24
Finished May 05 02:20:08 PM PDT 24
Peak memory 248716 kb
Host smart-1edec395-ef1b-40b2-a622-eca6eed7b519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31443
70148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3144370148
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2017815749
Short name T619
Test name
Test status
Simulation time 2366934256 ps
CPU time 13.23 seconds
Started May 05 02:19:55 PM PDT 24
Finished May 05 02:20:08 PM PDT 24
Peak memory 248796 kb
Host smart-9e7f2fd5-5df4-4903-a73c-9e0e12b62220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20178
15749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2017815749
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3837862896
Short name T631
Test name
Test status
Simulation time 830178572374 ps
CPU time 3318.26 seconds
Started May 05 02:20:03 PM PDT 24
Finished May 05 03:15:22 PM PDT 24
Peak memory 289784 kb
Host smart-9188635a-e3dd-4316-bba0-e05ab301d32a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837862896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3837862896
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1036156173
Short name T239
Test name
Test status
Simulation time 146520521 ps
CPU time 3.27 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 02:18:43 PM PDT 24
Peak memory 248856 kb
Host smart-aae2eddc-8caa-4e20-84e0-5688a458a3d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1036156173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1036156173
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2345326796
Short name T656
Test name
Test status
Simulation time 59508567107 ps
CPU time 1742.12 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:47:39 PM PDT 24
Peak memory 273356 kb
Host smart-d80eee55-5d2e-446a-baaf-8d8c5e600eb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345326796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2345326796
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2299305080
Short name T380
Test name
Test status
Simulation time 3500100979 ps
CPU time 28.73 seconds
Started May 05 02:18:40 PM PDT 24
Finished May 05 02:19:10 PM PDT 24
Peak memory 248760 kb
Host smart-18596038-2b1e-43f0-a539-25af4d0b38d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2299305080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2299305080
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.972182527
Short name T521
Test name
Test status
Simulation time 679470426 ps
CPU time 48.42 seconds
Started May 05 02:18:40 PM PDT 24
Finished May 05 02:19:29 PM PDT 24
Peak memory 249116 kb
Host smart-c941a71b-9235-429d-9e58-589da3f2c4f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97218
2527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.972182527
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3945913227
Short name T483
Test name
Test status
Simulation time 1713273799 ps
CPU time 46.52 seconds
Started May 05 02:18:48 PM PDT 24
Finished May 05 02:19:35 PM PDT 24
Peak memory 248748 kb
Host smart-3dbca5d9-70af-4178-9eae-f3c423d69ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39459
13227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3945913227
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3597100182
Short name T683
Test name
Test status
Simulation time 16872442914 ps
CPU time 1280.82 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:39:58 PM PDT 24
Peak memory 288736 kb
Host smart-a5fcba3f-70a4-4e73-8c2c-6a8fb4e266fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597100182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3597100182
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1484750935
Short name T273
Test name
Test status
Simulation time 22827189428 ps
CPU time 1332.38 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:40:50 PM PDT 24
Peak memory 273352 kb
Host smart-4a76de47-88f3-4b0c-9769-f6716325981b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484750935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1484750935
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1864803442
Short name T11
Test name
Test status
Simulation time 18872578166 ps
CPU time 356.66 seconds
Started May 05 02:18:48 PM PDT 24
Finished May 05 02:24:45 PM PDT 24
Peak memory 248220 kb
Host smart-c7976648-174f-46d8-a43b-4f739565c509
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864803442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1864803442
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.175116665
Short name T49
Test name
Test status
Simulation time 686398121 ps
CPU time 37.58 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:19:15 PM PDT 24
Peak memory 248968 kb
Host smart-7b563a2b-b925-4c63-bc76-70905c5b163c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17511
6665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.175116665
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3960583844
Short name T512
Test name
Test status
Simulation time 315534057 ps
CPU time 8.82 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:18:54 PM PDT 24
Peak memory 255012 kb
Host smart-7db7bf6e-3c17-4a13-84eb-e83220e2b68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39605
83844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3960583844
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3420061546
Short name T376
Test name
Test status
Simulation time 948724774 ps
CPU time 58.28 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:19:36 PM PDT 24
Peak memory 255564 kb
Host smart-aba64699-4da7-4e71-9e51-c7df22a9888a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
61546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3420061546
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.278713608
Short name T455
Test name
Test status
Simulation time 1631738397 ps
CPU time 34.61 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 02:19:14 PM PDT 24
Peak memory 255856 kb
Host smart-3aef0c65-4e3c-4123-926d-fc385f032c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27871
3608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.278713608
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3415560243
Short name T48
Test name
Test status
Simulation time 377203781885 ps
CPU time 2944.64 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 03:07:43 PM PDT 24
Peak memory 297928 kb
Host smart-d87cb52b-37a9-461d-ba79-3fd8c211daf7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415560243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3415560243
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4061796148
Short name T97
Test name
Test status
Simulation time 39576350257 ps
CPU time 1133.13 seconds
Started May 05 02:20:03 PM PDT 24
Finished May 05 02:38:57 PM PDT 24
Peak memory 272908 kb
Host smart-f00f34b6-6705-4ffb-b1ab-b401828a2d9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061796148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4061796148
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4037286625
Short name T436
Test name
Test status
Simulation time 5615860483 ps
CPU time 287.29 seconds
Started May 05 02:20:02 PM PDT 24
Finished May 05 02:24:50 PM PDT 24
Peak memory 256896 kb
Host smart-655ef3af-71e9-455e-a405-638e365974fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40372
86625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4037286625
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.651284056
Short name T509
Test name
Test status
Simulation time 290757991 ps
CPU time 22.64 seconds
Started May 05 02:20:02 PM PDT 24
Finished May 05 02:20:25 PM PDT 24
Peak memory 255348 kb
Host smart-b0076378-232c-4941-a95a-663ad813e62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65128
4056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.651284056
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2367701410
Short name T612
Test name
Test status
Simulation time 153350005862 ps
CPU time 1728.32 seconds
Started May 05 02:20:09 PM PDT 24
Finished May 05 02:48:58 PM PDT 24
Peak memory 273376 kb
Host smart-c782d997-20de-495f-bd3b-729b6f740d8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367701410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2367701410
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2334921739
Short name T699
Test name
Test status
Simulation time 4419468677 ps
CPU time 182.45 seconds
Started May 05 02:20:08 PM PDT 24
Finished May 05 02:23:11 PM PDT 24
Peak memory 247864 kb
Host smart-d3ff5834-4b67-4487-9f81-9e9d23d2e7df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334921739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2334921739
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3592488312
Short name T701
Test name
Test status
Simulation time 82738458 ps
CPU time 6.56 seconds
Started May 05 02:20:06 PM PDT 24
Finished May 05 02:20:13 PM PDT 24
Peak memory 252040 kb
Host smart-86b2aa5b-d0c4-4897-a5e8-e40590719e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35924
88312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3592488312
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3701997387
Short name T460
Test name
Test status
Simulation time 2637140625 ps
CPU time 38.12 seconds
Started May 05 02:20:03 PM PDT 24
Finished May 05 02:20:41 PM PDT 24
Peak memory 256112 kb
Host smart-ad11d8bc-e9ce-4a31-94e6-b2345e988bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
97387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3701997387
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2386179973
Short name T429
Test name
Test status
Simulation time 139092303 ps
CPU time 14.24 seconds
Started May 05 02:20:04 PM PDT 24
Finished May 05 02:20:19 PM PDT 24
Peak memory 248728 kb
Host smart-317a3459-cc63-40c3-ab9a-67fed37bab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
79973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2386179973
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.186585871
Short name T222
Test name
Test status
Simulation time 1482985884 ps
CPU time 47.03 seconds
Started May 05 02:20:06 PM PDT 24
Finished May 05 02:20:53 PM PDT 24
Peak memory 248764 kb
Host smart-9887e4c3-e308-47f2-8bd4-949c03bce56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18658
5871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.186585871
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2295954331
Short name T405
Test name
Test status
Simulation time 114555239005 ps
CPU time 1911.87 seconds
Started May 05 02:20:13 PM PDT 24
Finished May 05 02:52:05 PM PDT 24
Peak memory 281560 kb
Host smart-5f349184-970f-467d-bfaf-4a518cc46635
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295954331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2295954331
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1006092728
Short name T386
Test name
Test status
Simulation time 437560508 ps
CPU time 24.88 seconds
Started May 05 02:20:12 PM PDT 24
Finished May 05 02:20:38 PM PDT 24
Peak memory 248740 kb
Host smart-efd57fe0-4b1f-4d91-858e-465af1b66938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10060
92728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1006092728
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3461206108
Short name T506
Test name
Test status
Simulation time 721221877 ps
CPU time 11.62 seconds
Started May 05 02:20:14 PM PDT 24
Finished May 05 02:20:26 PM PDT 24
Peak memory 253192 kb
Host smart-0be33097-a602-4417-8b1e-dbdae211b1bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34612
06108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3461206108
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2899023840
Short name T102
Test name
Test status
Simulation time 27294548813 ps
CPU time 1387.33 seconds
Started May 05 02:20:12 PM PDT 24
Finished May 05 02:43:20 PM PDT 24
Peak memory 265196 kb
Host smart-850bdf25-649b-41b7-88ad-2dcc49acee49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899023840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2899023840
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4000256312
Short name T29
Test name
Test status
Simulation time 40420907929 ps
CPU time 1049.23 seconds
Started May 05 02:20:13 PM PDT 24
Finished May 05 02:37:43 PM PDT 24
Peak memory 289752 kb
Host smart-71a1accc-cd60-4fa0-ac0e-67ce93276019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000256312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4000256312
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2576796077
Short name T68
Test name
Test status
Simulation time 18789873109 ps
CPU time 297.52 seconds
Started May 05 02:20:14 PM PDT 24
Finished May 05 02:25:12 PM PDT 24
Peak memory 248088 kb
Host smart-2451b0ca-9c0e-4eb1-8a77-bbd9ad80bd53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576796077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2576796077
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2575765166
Short name T672
Test name
Test status
Simulation time 218180670 ps
CPU time 21.32 seconds
Started May 05 02:20:11 PM PDT 24
Finished May 05 02:20:33 PM PDT 24
Peak memory 255532 kb
Host smart-f0f297a6-5096-4774-ab0b-fde36d83f624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25757
65166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2575765166
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4096455991
Short name T40
Test name
Test status
Simulation time 230094835 ps
CPU time 4.75 seconds
Started May 05 02:20:10 PM PDT 24
Finished May 05 02:20:15 PM PDT 24
Peak memory 240544 kb
Host smart-de952ab8-0329-496a-b12b-3960f03a99be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40964
55991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4096455991
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2989217223
Short name T571
Test name
Test status
Simulation time 237878675 ps
CPU time 5.95 seconds
Started May 05 02:20:13 PM PDT 24
Finished May 05 02:20:19 PM PDT 24
Peak memory 247392 kb
Host smart-c84f19c3-6a20-4dd0-86ac-ae9f6670325e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
17223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2989217223
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4177414552
Short name T430
Test name
Test status
Simulation time 725212988 ps
CPU time 43.94 seconds
Started May 05 02:20:08 PM PDT 24
Finished May 05 02:20:53 PM PDT 24
Peak memory 248796 kb
Host smart-156eb844-6813-4bb6-a3dc-c04974686611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41774
14552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4177414552
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2251655607
Short name T691
Test name
Test status
Simulation time 13112204171 ps
CPU time 339.42 seconds
Started May 05 02:20:13 PM PDT 24
Finished May 05 02:25:53 PM PDT 24
Peak memory 256980 kb
Host smart-42cfd1c8-eb38-4043-9188-38fe4c1ea25b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251655607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2251655607
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.441696250
Short name T675
Test name
Test status
Simulation time 25837158266 ps
CPU time 1369.98 seconds
Started May 05 02:20:17 PM PDT 24
Finished May 05 02:43:08 PM PDT 24
Peak memory 273372 kb
Host smart-9e5341f8-68a2-4cfb-b490-f1f31030e27c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441696250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.441696250
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.4098978461
Short name T561
Test name
Test status
Simulation time 4034378666 ps
CPU time 78.54 seconds
Started May 05 02:20:19 PM PDT 24
Finished May 05 02:21:38 PM PDT 24
Peak memory 249960 kb
Host smart-cbfd881c-fdb3-4cd3-b55f-3461a0295213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40989
78461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4098978461
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1363434184
Short name T395
Test name
Test status
Simulation time 638854512 ps
CPU time 40.79 seconds
Started May 05 02:20:19 PM PDT 24
Finished May 05 02:21:00 PM PDT 24
Peak memory 255924 kb
Host smart-8d8db58b-e6a2-4b2a-8c34-3250ed603238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13634
34184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1363434184
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3663252019
Short name T622
Test name
Test status
Simulation time 79267679801 ps
CPU time 1842.46 seconds
Started May 05 02:20:19 PM PDT 24
Finished May 05 02:51:02 PM PDT 24
Peak memory 269992 kb
Host smart-80970279-aaee-4004-b833-0c2d2ee6fcd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663252019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3663252019
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4093154465
Short name T9
Test name
Test status
Simulation time 3240942302 ps
CPU time 104.52 seconds
Started May 05 02:20:18 PM PDT 24
Finished May 05 02:22:03 PM PDT 24
Peak memory 253640 kb
Host smart-e4aa2374-dfd9-4d77-945f-9e3380569f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093154465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4093154465
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2771832323
Short name T204
Test name
Test status
Simulation time 5631767526 ps
CPU time 18.38 seconds
Started May 05 02:20:17 PM PDT 24
Finished May 05 02:20:36 PM PDT 24
Peak memory 248772 kb
Host smart-f2619e90-4293-4fd8-a225-68446d07d273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27718
32323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2771832323
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2682818365
Short name T548
Test name
Test status
Simulation time 2255815783 ps
CPU time 29.92 seconds
Started May 05 02:20:18 PM PDT 24
Finished May 05 02:20:48 PM PDT 24
Peak memory 255920 kb
Host smart-cd5f5b23-7c03-4dda-92b0-ce99b669e873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26828
18365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2682818365
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.944109442
Short name T272
Test name
Test status
Simulation time 586352995 ps
CPU time 22.11 seconds
Started May 05 02:20:21 PM PDT 24
Finished May 05 02:20:44 PM PDT 24
Peak memory 247432 kb
Host smart-bbeb3e3c-d723-43e8-8cb1-2608ac067c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94410
9442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.944109442
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1136786326
Short name T567
Test name
Test status
Simulation time 979079312 ps
CPU time 38.99 seconds
Started May 05 02:20:21 PM PDT 24
Finished May 05 02:21:00 PM PDT 24
Peak memory 255768 kb
Host smart-da3d4503-ecf3-4ea2-b447-217909d6ee20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11367
86326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1136786326
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.71187353
Short name T645
Test name
Test status
Simulation time 139662856397 ps
CPU time 1403.73 seconds
Started May 05 02:20:18 PM PDT 24
Finished May 05 02:43:42 PM PDT 24
Peak memory 288568 kb
Host smart-d1bcd07e-3a64-48d3-9d4d-51c58e5ed76b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71187353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_hand
ler_stress_all.71187353
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1347335077
Short name T648
Test name
Test status
Simulation time 26078336107 ps
CPU time 1460.68 seconds
Started May 05 02:20:26 PM PDT 24
Finished May 05 02:44:47 PM PDT 24
Peak memory 272772 kb
Host smart-659b2368-2ec1-4315-aa03-a6dce2f8ae03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347335077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1347335077
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2861362237
Short name T677
Test name
Test status
Simulation time 2412373644 ps
CPU time 143.74 seconds
Started May 05 02:20:23 PM PDT 24
Finished May 05 02:22:47 PM PDT 24
Peak memory 257000 kb
Host smart-53518657-f8db-43a0-a8aa-4c01e83325e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28613
62237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2861362237
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.978499249
Short name T553
Test name
Test status
Simulation time 1183507802 ps
CPU time 18.58 seconds
Started May 05 02:20:21 PM PDT 24
Finished May 05 02:20:40 PM PDT 24
Peak memory 254936 kb
Host smart-a5b3f28b-602d-4aa1-a1be-3a251daf5aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97849
9249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.978499249
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.432568562
Short name T584
Test name
Test status
Simulation time 60750253805 ps
CPU time 1701.6 seconds
Started May 05 02:20:26 PM PDT 24
Finished May 05 02:48:49 PM PDT 24
Peak memory 268272 kb
Host smart-85dc4c4e-3dce-461b-9d5f-276e7776a0b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432568562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.432568562
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4167445995
Short name T371
Test name
Test status
Simulation time 67818795793 ps
CPU time 1615.42 seconds
Started May 05 02:20:28 PM PDT 24
Finished May 05 02:47:24 PM PDT 24
Peak memory 289064 kb
Host smart-4c115aec-9a8e-4c58-8bb6-a606266e2720
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167445995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4167445995
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3064608947
Short name T305
Test name
Test status
Simulation time 10381506566 ps
CPU time 110.7 seconds
Started May 05 02:20:26 PM PDT 24
Finished May 05 02:22:17 PM PDT 24
Peak memory 248232 kb
Host smart-74a4ce7e-06de-4632-9cac-8e9ca75ec342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064608947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3064608947
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3892217847
Short name T496
Test name
Test status
Simulation time 647850898 ps
CPU time 40.94 seconds
Started May 05 02:20:22 PM PDT 24
Finished May 05 02:21:03 PM PDT 24
Peak memory 248736 kb
Host smart-62233578-df35-459e-b33d-7982720c1564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
17847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3892217847
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4034567695
Short name T700
Test name
Test status
Simulation time 166652139 ps
CPU time 9.53 seconds
Started May 05 02:20:23 PM PDT 24
Finished May 05 02:20:33 PM PDT 24
Peak memory 254116 kb
Host smart-6f5fa8e3-1b13-441b-bb4c-a38fb24bc470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
67695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4034567695
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2108738494
Short name T111
Test name
Test status
Simulation time 712581902 ps
CPU time 22.34 seconds
Started May 05 02:20:24 PM PDT 24
Finished May 05 02:20:47 PM PDT 24
Peak memory 248736 kb
Host smart-98cc410e-9a3d-4572-8102-dc7a34059053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21087
38494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2108738494
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3495948970
Short name T375
Test name
Test status
Simulation time 667216943 ps
CPU time 9.22 seconds
Started May 05 02:20:24 PM PDT 24
Finished May 05 02:20:34 PM PDT 24
Peak memory 248864 kb
Host smart-617ebbdb-0494-4110-8b9f-61c90a86588c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34959
48970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3495948970
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1799905307
Short name T611
Test name
Test status
Simulation time 65474595558 ps
CPU time 1603.12 seconds
Started May 05 02:20:27 PM PDT 24
Finished May 05 02:47:11 PM PDT 24
Peak memory 289204 kb
Host smart-670b158c-2575-4354-bb7c-72635a52ddc8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799905307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1799905307
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3923677621
Short name T16
Test name
Test status
Simulation time 30444311129 ps
CPU time 1743.93 seconds
Started May 05 02:20:33 PM PDT 24
Finished May 05 02:49:37 PM PDT 24
Peak memory 273420 kb
Host smart-21e2fe7d-e425-4e82-a201-b8a1a8bcedaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923677621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3923677621
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2666320667
Short name T518
Test name
Test status
Simulation time 207239284 ps
CPU time 16.76 seconds
Started May 05 02:20:34 PM PDT 24
Finished May 05 02:20:51 PM PDT 24
Peak memory 248636 kb
Host smart-0a26f92f-b33e-46cd-9e89-1bc3c4fff7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26663
20667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2666320667
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2067888680
Short name T269
Test name
Test status
Simulation time 488950259 ps
CPU time 28.89 seconds
Started May 05 02:20:33 PM PDT 24
Finished May 05 02:21:02 PM PDT 24
Peak memory 255924 kb
Host smart-5b85111b-d5e2-4544-ace0-62efcb6b5bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20678
88680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2067888680
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1911987357
Short name T415
Test name
Test status
Simulation time 33062305207 ps
CPU time 2058.27 seconds
Started May 05 02:20:31 PM PDT 24
Finished May 05 02:54:50 PM PDT 24
Peak memory 270272 kb
Host smart-31d73e64-655e-4573-817f-3e7ef63f3cec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911987357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1911987357
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3176901131
Short name T300
Test name
Test status
Simulation time 13810322295 ps
CPU time 517.95 seconds
Started May 05 02:20:32 PM PDT 24
Finished May 05 02:29:10 PM PDT 24
Peak memory 248140 kb
Host smart-84b48eb8-e73e-4b14-9087-b1f86d512bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176901131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3176901131
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2762636812
Short name T400
Test name
Test status
Simulation time 3484757429 ps
CPU time 47.82 seconds
Started May 05 02:20:28 PM PDT 24
Finished May 05 02:21:16 PM PDT 24
Peak memory 248896 kb
Host smart-ddc8dfc6-84f9-40b2-a8c5-03da68614fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27626
36812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2762636812
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.82448228
Short name T205
Test name
Test status
Simulation time 2359464583 ps
CPU time 67.52 seconds
Started May 05 02:20:31 PM PDT 24
Finished May 05 02:21:39 PM PDT 24
Peak memory 256116 kb
Host smart-11813853-2997-48d3-b386-b82a89c1de45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82448
228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.82448228
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.895932921
Short name T84
Test name
Test status
Simulation time 174435851 ps
CPU time 21.98 seconds
Started May 05 02:20:32 PM PDT 24
Finished May 05 02:20:54 PM PDT 24
Peak memory 255600 kb
Host smart-40ae0a03-00d5-43e6-b00f-b287f09db4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89593
2921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.895932921
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1822932704
Short name T519
Test name
Test status
Simulation time 406117359 ps
CPU time 19.09 seconds
Started May 05 02:20:31 PM PDT 24
Finished May 05 02:20:50 PM PDT 24
Peak memory 248752 kb
Host smart-d67f835f-33f2-4590-b210-311d4b13736b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18229
32704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1822932704
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3647303693
Short name T87
Test name
Test status
Simulation time 372914106240 ps
CPU time 2085.79 seconds
Started May 05 02:20:31 PM PDT 24
Finished May 05 02:55:18 PM PDT 24
Peak memory 272648 kb
Host smart-9f651387-077d-4c8f-86a9-87d3fc458143
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647303693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3647303693
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3134528855
Short name T641
Test name
Test status
Simulation time 89574628105 ps
CPU time 1373.83 seconds
Started May 05 02:20:41 PM PDT 24
Finished May 05 02:43:35 PM PDT 24
Peak memory 281612 kb
Host smart-8fd31aa8-99ed-4f93-983d-2c52333566de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134528855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3134528855
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4265439912
Short name T416
Test name
Test status
Simulation time 1754240296 ps
CPU time 156.33 seconds
Started May 05 02:20:38 PM PDT 24
Finished May 05 02:23:15 PM PDT 24
Peak memory 250852 kb
Host smart-d7970677-c6f8-495b-bfc4-cd7466efd1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
39912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4265439912
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.314856425
Short name T1
Test name
Test status
Simulation time 264134450 ps
CPU time 15.79 seconds
Started May 05 02:20:40 PM PDT 24
Finished May 05 02:20:56 PM PDT 24
Peak memory 255056 kb
Host smart-5668e7de-74c2-4eef-b1ed-4080f4bf745d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31485
6425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.314856425
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2289406227
Short name T136
Test name
Test status
Simulation time 158840565613 ps
CPU time 2015.06 seconds
Started May 05 02:20:45 PM PDT 24
Finished May 05 02:54:21 PM PDT 24
Peak memory 270444 kb
Host smart-bcd70205-6c40-402f-a30b-4361e53a72a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289406227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2289406227
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1119090889
Short name T490
Test name
Test status
Simulation time 68757565736 ps
CPU time 1861.68 seconds
Started May 05 02:20:45 PM PDT 24
Finished May 05 02:51:48 PM PDT 24
Peak memory 269536 kb
Host smart-937966de-a4ad-4031-8880-3f005fb5ecf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119090889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1119090889
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1964207933
Short name T676
Test name
Test status
Simulation time 50510564995 ps
CPU time 502.73 seconds
Started May 05 02:20:40 PM PDT 24
Finished May 05 02:29:03 PM PDT 24
Peak memory 247116 kb
Host smart-78d49cff-aa3e-41e9-a984-8055a33261fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964207933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1964207933
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2138321388
Short name T349
Test name
Test status
Simulation time 744922115 ps
CPU time 47.65 seconds
Started May 05 02:20:30 PM PDT 24
Finished May 05 02:21:18 PM PDT 24
Peak memory 248760 kb
Host smart-996bfcec-2e5c-4703-a895-dd2cd81dc856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21383
21388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2138321388
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2222051850
Short name T91
Test name
Test status
Simulation time 1613268342 ps
CPU time 30.94 seconds
Started May 05 02:20:34 PM PDT 24
Finished May 05 02:21:05 PM PDT 24
Peak memory 248720 kb
Host smart-b68997be-be5b-4d62-8088-5aa0d93863ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
51850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2222051850
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1030148975
Short name T685
Test name
Test status
Simulation time 284342968 ps
CPU time 20.13 seconds
Started May 05 02:20:40 PM PDT 24
Finished May 05 02:21:01 PM PDT 24
Peak memory 254912 kb
Host smart-e5a2bb17-59ea-4918-818b-42222ea8cffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
48975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1030148975
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2534471521
Short name T505
Test name
Test status
Simulation time 1145989211 ps
CPU time 32.4 seconds
Started May 05 02:20:31 PM PDT 24
Finished May 05 02:21:04 PM PDT 24
Peak memory 248712 kb
Host smart-159e3722-e667-4033-af02-a393c668367a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
71521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2534471521
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1430777173
Short name T24
Test name
Test status
Simulation time 37652475225 ps
CPU time 2232.75 seconds
Started May 05 02:20:43 PM PDT 24
Finished May 05 02:57:56 PM PDT 24
Peak memory 289736 kb
Host smart-16e383c4-01b0-41d4-858f-5b911ea35885
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430777173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1430777173
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3126779606
Short name T110
Test name
Test status
Simulation time 110792642517 ps
CPU time 2552.53 seconds
Started May 05 02:20:45 PM PDT 24
Finished May 05 03:03:18 PM PDT 24
Peak memory 299216 kb
Host smart-0a3582af-25b8-4efa-a925-253094be2174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126779606 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3126779606
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.807392077
Short name T585
Test name
Test status
Simulation time 109739895604 ps
CPU time 1329.35 seconds
Started May 05 02:20:50 PM PDT 24
Finished May 05 02:43:00 PM PDT 24
Peak memory 273368 kb
Host smart-ed616d89-e364-42ef-b86b-7b1f39b37783
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807392077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.807392077
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3803428922
Short name T658
Test name
Test status
Simulation time 3455436893 ps
CPU time 102.35 seconds
Started May 05 02:20:50 PM PDT 24
Finished May 05 02:22:33 PM PDT 24
Peak memory 256960 kb
Host smart-aa9d50df-9805-4e1e-8f86-5ae462c133ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38034
28922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3803428922
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3401395528
Short name T532
Test name
Test status
Simulation time 343927547 ps
CPU time 12.44 seconds
Started May 05 02:20:48 PM PDT 24
Finished May 05 02:21:01 PM PDT 24
Peak memory 248744 kb
Host smart-d0f62664-dce2-4460-b383-182f9f808ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
95528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3401395528
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3935747805
Short name T661
Test name
Test status
Simulation time 11724070743 ps
CPU time 1048.05 seconds
Started May 05 02:20:48 PM PDT 24
Finished May 05 02:38:17 PM PDT 24
Peak memory 273212 kb
Host smart-cd4acc82-39a0-4646-b150-213dd7da9fe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935747805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3935747805
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.98480691
Short name T76
Test name
Test status
Simulation time 12029975120 ps
CPU time 590.38 seconds
Started May 05 02:20:49 PM PDT 24
Finished May 05 02:30:40 PM PDT 24
Peak memory 265188 kb
Host smart-fe8757c0-7e3d-4c10-a74f-57ea4a56daa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98480691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.98480691
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1839518076
Short name T551
Test name
Test status
Simulation time 10449029823 ps
CPU time 402.36 seconds
Started May 05 02:20:50 PM PDT 24
Finished May 05 02:27:33 PM PDT 24
Peak memory 248084 kb
Host smart-c323c4f2-4852-49c8-94fe-316c82537e56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839518076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1839518076
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1398449033
Short name T372
Test name
Test status
Simulation time 122815811 ps
CPU time 8.82 seconds
Started May 05 02:20:49 PM PDT 24
Finished May 05 02:20:58 PM PDT 24
Peak memory 248776 kb
Host smart-3e07fd28-f0fa-4b41-9e41-a957525a6376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13984
49033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1398449033
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2233882747
Short name T706
Test name
Test status
Simulation time 231640816 ps
CPU time 13.91 seconds
Started May 05 02:20:48 PM PDT 24
Finished May 05 02:21:02 PM PDT 24
Peak memory 248748 kb
Host smart-45c3ed9d-6164-45d8-9b63-881a07b93c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22338
82747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2233882747
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.552914784
Short name T640
Test name
Test status
Simulation time 280078972 ps
CPU time 27.39 seconds
Started May 05 02:20:49 PM PDT 24
Finished May 05 02:21:18 PM PDT 24
Peak memory 248828 kb
Host smart-bce74af7-d7c5-42a1-ae17-92e02ae74781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55291
4784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.552914784
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.621213175
Short name T703
Test name
Test status
Simulation time 27877298 ps
CPU time 2.56 seconds
Started May 05 02:20:43 PM PDT 24
Finished May 05 02:20:46 PM PDT 24
Peak memory 240732 kb
Host smart-1a1600c7-09ec-4187-ac8d-e3e0646f8a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62121
3175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.621213175
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1841155880
Short name T263
Test name
Test status
Simulation time 274949119135 ps
CPU time 3850.78 seconds
Started May 05 02:20:59 PM PDT 24
Finished May 05 03:25:10 PM PDT 24
Peak memory 302312 kb
Host smart-15798ca5-f42b-47a1-aafc-3f63aaa42877
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841155880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1841155880
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2092366499
Short name T630
Test name
Test status
Simulation time 7054397180 ps
CPU time 76.74 seconds
Started May 05 02:20:57 PM PDT 24
Finished May 05 02:22:14 PM PDT 24
Peak memory 249044 kb
Host smart-d3f52894-862b-4062-8135-fc31192f9245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20923
66499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2092366499
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.980207553
Short name T479
Test name
Test status
Simulation time 843308572 ps
CPU time 30.11 seconds
Started May 05 02:20:57 PM PDT 24
Finished May 05 02:21:28 PM PDT 24
Peak memory 255936 kb
Host smart-164b625f-85bf-4a33-82c5-f086d7e90b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98020
7553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.980207553
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3034994719
Short name T61
Test name
Test status
Simulation time 190689985865 ps
CPU time 2535.18 seconds
Started May 05 02:21:02 PM PDT 24
Finished May 05 03:03:18 PM PDT 24
Peak memory 289084 kb
Host smart-ab0cbe41-3014-4ae7-9431-be3db9056426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034994719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3034994719
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2474657608
Short name T307
Test name
Test status
Simulation time 8412783717 ps
CPU time 337.81 seconds
Started May 05 02:21:03 PM PDT 24
Finished May 05 02:26:41 PM PDT 24
Peak memory 255236 kb
Host smart-a53101e6-59d5-42c0-92c2-f40b8a6a4a79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474657608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2474657608
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3086040715
Short name T73
Test name
Test status
Simulation time 823109022 ps
CPU time 43.21 seconds
Started May 05 02:20:54 PM PDT 24
Finished May 05 02:21:37 PM PDT 24
Peak memory 255608 kb
Host smart-45f3914a-0c58-4b24-a1de-9d38fb531fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30860
40715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3086040715
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3465702532
Short name T21
Test name
Test status
Simulation time 850501846 ps
CPU time 32.92 seconds
Started May 05 02:20:52 PM PDT 24
Finished May 05 02:21:26 PM PDT 24
Peak memory 248716 kb
Host smart-38bf0815-cf81-4e8e-be64-dc1888a5c0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34657
02532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3465702532
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.638392382
Short name T140
Test name
Test status
Simulation time 445134968 ps
CPU time 8.57 seconds
Started May 05 02:20:58 PM PDT 24
Finished May 05 02:21:07 PM PDT 24
Peak memory 251608 kb
Host smart-bdbacbf4-6c02-4073-8796-f290528a1bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63839
2382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.638392382
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3017709767
Short name T573
Test name
Test status
Simulation time 104444908 ps
CPU time 7.82 seconds
Started May 05 02:20:52 PM PDT 24
Finished May 05 02:21:00 PM PDT 24
Peak memory 248784 kb
Host smart-b45873f7-ea7c-404e-83ff-05af9bf70ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30177
09767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3017709767
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1060957773
Short name T141
Test name
Test status
Simulation time 20243586281 ps
CPU time 1631.53 seconds
Started May 05 02:21:11 PM PDT 24
Finished May 05 02:48:23 PM PDT 24
Peak memory 305464 kb
Host smart-2ac2191d-08da-4128-a278-2049a19988ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060957773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1060957773
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.928419206
Short name T280
Test name
Test status
Simulation time 55007837162 ps
CPU time 973.32 seconds
Started May 05 02:21:10 PM PDT 24
Finished May 05 02:37:24 PM PDT 24
Peak memory 288728 kb
Host smart-aa5909de-de6c-4fd5-89cd-59f5761112cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928419206 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.928419206
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2085619993
Short name T653
Test name
Test status
Simulation time 62483288907 ps
CPU time 1909.83 seconds
Started May 05 02:21:10 PM PDT 24
Finished May 05 02:53:01 PM PDT 24
Peak memory 289324 kb
Host smart-b7c84c5f-1c81-49ae-ba06-1dd9a92041d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085619993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2085619993
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.668294946
Short name T359
Test name
Test status
Simulation time 3758711709 ps
CPU time 212.78 seconds
Started May 05 02:21:12 PM PDT 24
Finished May 05 02:24:45 PM PDT 24
Peak memory 257012 kb
Host smart-8679892b-c772-4786-a7c9-bfcff7041f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66829
4946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.668294946
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2551222825
Short name T474
Test name
Test status
Simulation time 533582811 ps
CPU time 34.2 seconds
Started May 05 02:21:12 PM PDT 24
Finished May 05 02:21:46 PM PDT 24
Peak memory 256412 kb
Host smart-e967588d-eced-4e30-a6f3-a6fda577c8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512
22825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2551222825
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3774728352
Short name T393
Test name
Test status
Simulation time 10630625266 ps
CPU time 983.3 seconds
Started May 05 02:21:11 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 265176 kb
Host smart-d7ce7b66-8db2-43cc-92a9-3e0ae8eefc07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774728352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3774728352
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3850608682
Short name T495
Test name
Test status
Simulation time 55253834648 ps
CPU time 1811.25 seconds
Started May 05 02:21:17 PM PDT 24
Finished May 05 02:51:29 PM PDT 24
Peak memory 281272 kb
Host smart-8537fb16-3031-4fe5-aecc-5835a0e12176
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850608682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3850608682
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2688781036
Short name T621
Test name
Test status
Simulation time 49329352470 ps
CPU time 557 seconds
Started May 05 02:21:10 PM PDT 24
Finished May 05 02:30:27 PM PDT 24
Peak memory 247804 kb
Host smart-6e4c8341-b1dd-4853-a8ae-11aaf71c04c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688781036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2688781036
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.4129671306
Short name T568
Test name
Test status
Simulation time 134721118 ps
CPU time 14.26 seconds
Started May 05 02:21:07 PM PDT 24
Finished May 05 02:21:22 PM PDT 24
Peak memory 248756 kb
Host smart-8114e25c-3c9d-4543-8d84-c2f2a53f6741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41296
71306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.4129671306
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1046991460
Short name T348
Test name
Test status
Simulation time 723063338 ps
CPU time 22.93 seconds
Started May 05 02:21:12 PM PDT 24
Finished May 05 02:21:35 PM PDT 24
Peak memory 248776 kb
Host smart-0afcdd37-dff0-4e4b-977b-37eede809152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10469
91460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1046991460
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.928480328
Short name T258
Test name
Test status
Simulation time 128052347 ps
CPU time 3.97 seconds
Started May 05 02:21:11 PM PDT 24
Finished May 05 02:21:16 PM PDT 24
Peak memory 250804 kb
Host smart-65e26411-c092-4d5b-b5ac-91a80e746041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92848
0328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.928480328
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1532272815
Short name T574
Test name
Test status
Simulation time 942809574 ps
CPU time 28.04 seconds
Started May 05 02:21:06 PM PDT 24
Finished May 05 02:21:35 PM PDT 24
Peak memory 248744 kb
Host smart-8d2d43aa-29ae-4d69-9f98-b52951b89c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
72815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1532272815
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.291520666
Short name T46
Test name
Test status
Simulation time 66335658187 ps
CPU time 1252.3 seconds
Started May 05 02:21:17 PM PDT 24
Finished May 05 02:42:10 PM PDT 24
Peak memory 288972 kb
Host smart-68aa1866-8142-4e0c-86ee-f348b660437c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291520666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.291520666
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3798357173
Short name T582
Test name
Test status
Simulation time 295430133048 ps
CPU time 4633.48 seconds
Started May 05 02:21:15 PM PDT 24
Finished May 05 03:38:30 PM PDT 24
Peak memory 298300 kb
Host smart-62695649-c098-4e7e-9c22-254c7d266c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798357173 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3798357173
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1298685268
Short name T694
Test name
Test status
Simulation time 17380593129 ps
CPU time 557.53 seconds
Started May 05 02:21:25 PM PDT 24
Finished May 05 02:30:43 PM PDT 24
Peak memory 272148 kb
Host smart-acc8c4ec-e2a6-40ff-93f7-95f54fbeaf38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298685268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1298685268
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1937114519
Short name T377
Test name
Test status
Simulation time 26470457133 ps
CPU time 282.43 seconds
Started May 05 02:21:20 PM PDT 24
Finished May 05 02:26:03 PM PDT 24
Peak memory 256256 kb
Host smart-ed0c5875-c02b-4cbb-beb8-cc04b5606a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19371
14519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1937114519
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2977472301
Short name T626
Test name
Test status
Simulation time 90130046 ps
CPU time 9.91 seconds
Started May 05 02:21:22 PM PDT 24
Finished May 05 02:21:32 PM PDT 24
Peak memory 249160 kb
Host smart-af13067b-a517-4531-a267-feab9401a5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29774
72301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2977472301
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1590647427
Short name T126
Test name
Test status
Simulation time 36053809395 ps
CPU time 738.65 seconds
Started May 05 02:21:26 PM PDT 24
Finished May 05 02:33:45 PM PDT 24
Peak memory 267228 kb
Host smart-d0a985f2-7335-4fd5-b27e-84794a36d5e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590647427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1590647427
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2090201730
Short name T98
Test name
Test status
Simulation time 110801834994 ps
CPU time 1911.12 seconds
Started May 05 02:21:26 PM PDT 24
Finished May 05 02:53:18 PM PDT 24
Peak memory 281588 kb
Host smart-c1036493-2e90-4d0c-94ad-7377cb2f90e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090201730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2090201730
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1364034876
Short name T499
Test name
Test status
Simulation time 554080921 ps
CPU time 33.36 seconds
Started May 05 02:21:19 PM PDT 24
Finished May 05 02:21:53 PM PDT 24
Peak memory 248936 kb
Host smart-fbc7adfb-53d1-4e35-9cb3-ca1ea1ea3454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13640
34876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1364034876
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2088943974
Short name T605
Test name
Test status
Simulation time 230245196 ps
CPU time 14.65 seconds
Started May 05 02:21:20 PM PDT 24
Finished May 05 02:21:35 PM PDT 24
Peak memory 255504 kb
Host smart-7790eca1-9caa-48a0-b3f9-af30f01f7e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20889
43974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2088943974
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.258632980
Short name T441
Test name
Test status
Simulation time 294266817 ps
CPU time 18.56 seconds
Started May 05 02:21:21 PM PDT 24
Finished May 05 02:21:40 PM PDT 24
Peak memory 248692 kb
Host smart-88477267-0c40-427f-a680-b89722254f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25863
2980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.258632980
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3353710366
Short name T472
Test name
Test status
Simulation time 415254606 ps
CPU time 23.68 seconds
Started May 05 02:21:21 PM PDT 24
Finished May 05 02:21:45 PM PDT 24
Peak memory 248736 kb
Host smart-2db6e835-9a3a-4e0d-bfaa-03580786ca66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33537
10366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3353710366
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3258258588
Short name T228
Test name
Test status
Simulation time 137635859 ps
CPU time 3.38 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:18:49 PM PDT 24
Peak memory 248876 kb
Host smart-c4ef17c2-20c2-432c-99ec-730a3066af4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3258258588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3258258588
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.29053555
Short name T673
Test name
Test status
Simulation time 25699651539 ps
CPU time 1147.51 seconds
Started May 05 02:18:47 PM PDT 24
Finished May 05 02:37:55 PM PDT 24
Peak memory 281604 kb
Host smart-8495e44d-cd2a-47dd-ae12-0e575792300b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29053555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.29053555
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1122989025
Short name T437
Test name
Test status
Simulation time 930637994 ps
CPU time 22.9 seconds
Started May 05 02:18:40 PM PDT 24
Finished May 05 02:19:03 PM PDT 24
Peak memory 248760 kb
Host smart-e3dde430-72fa-41ac-acb2-fd443beb3bd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1122989025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1122989025
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2426695135
Short name T557
Test name
Test status
Simulation time 6596874961 ps
CPU time 216.03 seconds
Started May 05 02:18:38 PM PDT 24
Finished May 05 02:22:15 PM PDT 24
Peak memory 250544 kb
Host smart-b5a31b75-e889-410b-a325-2b2e06a7e0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
95135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2426695135
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3922807219
Short name T662
Test name
Test status
Simulation time 2613381753 ps
CPU time 40.89 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 02:19:21 PM PDT 24
Peak memory 256788 kb
Host smart-49adc0ba-b008-46f3-b1bb-d3692d7a7dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39228
07219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3922807219
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.679166949
Short name T138
Test name
Test status
Simulation time 300735718042 ps
CPU time 3132.9 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 03:10:53 PM PDT 24
Peak memory 281528 kb
Host smart-c362da12-a4a1-4e7e-9ebe-4a19abad8a73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679166949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.679166949
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.4168756520
Short name T520
Test name
Test status
Simulation time 41387029895 ps
CPU time 111.56 seconds
Started May 05 02:18:39 PM PDT 24
Finished May 05 02:20:32 PM PDT 24
Peak memory 253332 kb
Host smart-e42637b3-b0c3-421c-adac-663487c31959
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168756520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.4168756520
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2534482695
Short name T634
Test name
Test status
Simulation time 1324909743 ps
CPU time 20.29 seconds
Started May 05 02:18:49 PM PDT 24
Finished May 05 02:19:09 PM PDT 24
Peak memory 248744 kb
Host smart-b791c654-7633-41ad-be1e-140666bcf6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
82695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2534482695
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2790990629
Short name T360
Test name
Test status
Simulation time 231965135 ps
CPU time 14.91 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:18:52 PM PDT 24
Peak memory 255916 kb
Host smart-f9082df2-07d5-4a4a-b587-fb50e60caec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27909
90629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2790990629
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3608714263
Short name T36
Test name
Test status
Simulation time 882427394 ps
CPU time 12.79 seconds
Started May 05 02:18:38 PM PDT 24
Finished May 05 02:18:52 PM PDT 24
Peak memory 266312 kb
Host smart-2e5e4a7c-c4cb-4227-a6fc-a6dc1d207a49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3608714263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3608714263
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2237872116
Short name T253
Test name
Test status
Simulation time 194392677 ps
CPU time 14.99 seconds
Started May 05 02:18:37 PM PDT 24
Finished May 05 02:18:52 PM PDT 24
Peak memory 252936 kb
Host smart-97e013ca-1a8c-4514-bf4f-f7c7d5d8a3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22378
72116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2237872116
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1152412162
Short name T500
Test name
Test status
Simulation time 480160178 ps
CPU time 16.31 seconds
Started May 05 02:18:35 PM PDT 24
Finished May 05 02:18:52 PM PDT 24
Peak memory 248708 kb
Host smart-b397b5db-9d0d-421c-9e14-ecebbb918af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11524
12162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1152412162
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3935341170
Short name T67
Test name
Test status
Simulation time 3409681732 ps
CPU time 40.67 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:19:26 PM PDT 24
Peak memory 255344 kb
Host smart-584462db-714c-43ce-9663-a428f08827e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935341170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3935341170
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.383715773
Short name T345
Test name
Test status
Simulation time 28025065411 ps
CPU time 1469.12 seconds
Started May 05 02:21:28 PM PDT 24
Finished May 05 02:45:57 PM PDT 24
Peak memory 267280 kb
Host smart-ff3f3074-c50c-4f04-a730-b648eed07ff2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383715773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.383715773
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4108205693
Short name T655
Test name
Test status
Simulation time 1257359980 ps
CPU time 102.01 seconds
Started May 05 02:21:29 PM PDT 24
Finished May 05 02:23:11 PM PDT 24
Peak memory 256944 kb
Host smart-812703f6-31a3-43f3-bd64-b8641403068f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41082
05693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4108205693
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3641665271
Short name T494
Test name
Test status
Simulation time 3196078610 ps
CPU time 45.96 seconds
Started May 05 02:21:28 PM PDT 24
Finished May 05 02:22:15 PM PDT 24
Peak memory 256920 kb
Host smart-f3fcadaf-0eb3-4f78-89bf-34fcc5a4e20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36416
65271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3641665271
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.251589111
Short name T486
Test name
Test status
Simulation time 11164425974 ps
CPU time 918.89 seconds
Started May 05 02:21:32 PM PDT 24
Finished May 05 02:36:51 PM PDT 24
Peak memory 273408 kb
Host smart-19f52f74-6e45-428b-8109-f3161373ed7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251589111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.251589111
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1113020137
Short name T114
Test name
Test status
Simulation time 35931897459 ps
CPU time 1213.87 seconds
Started May 05 02:21:34 PM PDT 24
Finished May 05 02:41:49 PM PDT 24
Peak memory 272516 kb
Host smart-c63d07ac-97ca-45c1-94f9-42436efb85ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113020137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1113020137
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3844152283
Short name T72
Test name
Test status
Simulation time 24989607989 ps
CPU time 225.75 seconds
Started May 05 02:21:34 PM PDT 24
Finished May 05 02:25:20 PM PDT 24
Peak memory 255028 kb
Host smart-b7501d95-2407-42f9-a763-710cbc65320a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844152283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3844152283
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3729086676
Short name T527
Test name
Test status
Simulation time 144253580 ps
CPU time 17.34 seconds
Started May 05 02:21:23 PM PDT 24
Finished May 05 02:21:40 PM PDT 24
Peak memory 255984 kb
Host smart-5c83d2f5-3953-4507-8cc9-bf8914fa69f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37290
86676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3729086676
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1527246898
Short name T256
Test name
Test status
Simulation time 1989501535 ps
CPU time 35.39 seconds
Started May 05 02:21:30 PM PDT 24
Finished May 05 02:22:06 PM PDT 24
Peak memory 249216 kb
Host smart-333858df-e093-4e57-9fb9-756ed897da15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15272
46898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1527246898
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2595043274
Short name T426
Test name
Test status
Simulation time 747695738 ps
CPU time 12.14 seconds
Started May 05 02:21:23 PM PDT 24
Finished May 05 02:21:35 PM PDT 24
Peak memory 248736 kb
Host smart-d0ed05d5-b79a-49d3-9d18-91dc2e21187d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25950
43274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2595043274
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1489499372
Short name T270
Test name
Test status
Simulation time 43312424511 ps
CPU time 1436.09 seconds
Started May 05 02:21:33 PM PDT 24
Finished May 05 02:45:30 PM PDT 24
Peak memory 286324 kb
Host smart-92ae173a-1e9d-4ffc-a071-a2c9dc0257dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489499372 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1489499372
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2855896655
Short name T465
Test name
Test status
Simulation time 86534951288 ps
CPU time 3153.49 seconds
Started May 05 02:21:39 PM PDT 24
Finished May 05 03:14:13 PM PDT 24
Peak memory 289332 kb
Host smart-26ad8d72-b5fd-43d0-bdfb-8adde972aed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855896655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2855896655
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.124820769
Short name T209
Test name
Test status
Simulation time 7612879143 ps
CPU time 126.95 seconds
Started May 05 02:21:41 PM PDT 24
Finished May 05 02:23:48 PM PDT 24
Peak memory 248916 kb
Host smart-37700abd-c96d-441c-90c3-b184dfe4d130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
0769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.124820769
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3621328764
Short name T660
Test name
Test status
Simulation time 426940954 ps
CPU time 26.66 seconds
Started May 05 02:21:39 PM PDT 24
Finished May 05 02:22:06 PM PDT 24
Peak memory 256936 kb
Host smart-e4823eec-1a32-43b0-a82b-b0596d2696c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36213
28764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3621328764
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.704533556
Short name T321
Test name
Test status
Simulation time 22860738217 ps
CPU time 1189.05 seconds
Started May 05 02:21:42 PM PDT 24
Finished May 05 02:41:32 PM PDT 24
Peak memory 271044 kb
Host smart-a35edcbe-ca5e-4579-9b60-af4883a7eb6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704533556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.704533556
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3025852676
Short name T374
Test name
Test status
Simulation time 47301181742 ps
CPU time 1337.04 seconds
Started May 05 02:21:43 PM PDT 24
Finished May 05 02:44:00 PM PDT 24
Peak memory 272680 kb
Host smart-2638a106-16e4-436e-a9e5-30b913d7aa84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025852676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3025852676
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1154047565
Short name T137
Test name
Test status
Simulation time 141244733622 ps
CPU time 460.02 seconds
Started May 05 02:21:38 PM PDT 24
Finished May 05 02:29:19 PM PDT 24
Peak memory 247668 kb
Host smart-b9df2f92-5151-4bb8-ba57-d6fe13f780bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154047565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1154047565
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3593377947
Short name T399
Test name
Test status
Simulation time 894850671 ps
CPU time 45.17 seconds
Started May 05 02:21:33 PM PDT 24
Finished May 05 02:22:18 PM PDT 24
Peak memory 248712 kb
Host smart-ea98d5d3-2519-4543-ab75-b1b6c3806ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35933
77947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3593377947
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.322006378
Short name T396
Test name
Test status
Simulation time 1887995808 ps
CPU time 54.65 seconds
Started May 05 02:21:35 PM PDT 24
Finished May 05 02:22:30 PM PDT 24
Peak memory 255940 kb
Host smart-ec8fc778-a5ce-41fe-8a2f-69361b17443a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32200
6378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.322006378
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3533542773
Short name T616
Test name
Test status
Simulation time 1512544365 ps
CPU time 60.99 seconds
Started May 05 02:21:39 PM PDT 24
Finished May 05 02:22:40 PM PDT 24
Peak memory 248728 kb
Host smart-beed1e3f-9447-4321-b71d-546bcf27df23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35335
42773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3533542773
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1226093010
Short name T481
Test name
Test status
Simulation time 16182235851 ps
CPU time 52 seconds
Started May 05 02:21:35 PM PDT 24
Finished May 05 02:22:27 PM PDT 24
Peak memory 256988 kb
Host smart-68a5ba02-3c85-4539-b166-247d6e84ac3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12260
93010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1226093010
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4168757192
Short name T23
Test name
Test status
Simulation time 12229259397 ps
CPU time 1361.96 seconds
Started May 05 02:21:43 PM PDT 24
Finished May 05 02:44:26 PM PDT 24
Peak memory 289604 kb
Host smart-b4417a4e-8350-45a0-b377-ef22832093d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168757192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4168757192
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4011595835
Short name T33
Test name
Test status
Simulation time 33738780063 ps
CPU time 2034.79 seconds
Started May 05 02:21:52 PM PDT 24
Finished May 05 02:55:48 PM PDT 24
Peak memory 289532 kb
Host smart-bdf62013-8335-4c7b-965e-9915378ec0a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011595835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4011595835
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1638482131
Short name T448
Test name
Test status
Simulation time 332219753 ps
CPU time 7.17 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:22:05 PM PDT 24
Peak memory 248744 kb
Host smart-85ae1d0c-1bd4-4464-bad7-5592b8efe0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16384
82131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1638482131
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2794815676
Short name T492
Test name
Test status
Simulation time 206863193 ps
CPU time 12.79 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:22:10 PM PDT 24
Peak memory 248760 kb
Host smart-bff27df0-adad-4ef8-b0a7-53a9e6c5b450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27948
15676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2794815676
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.801147487
Short name T421
Test name
Test status
Simulation time 25326460713 ps
CPU time 1234.25 seconds
Started May 05 02:21:51 PM PDT 24
Finished May 05 02:42:25 PM PDT 24
Peak memory 265156 kb
Host smart-732bc00a-fb04-4557-aa18-8ef95491d4ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801147487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.801147487
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2541848015
Short name T42
Test name
Test status
Simulation time 18200048200 ps
CPU time 1262.92 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:43:01 PM PDT 24
Peak memory 288600 kb
Host smart-ba0485be-dc32-480c-9bc5-da62b0b1b0cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541848015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2541848015
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.271497281
Short name T670
Test name
Test status
Simulation time 17227902640 ps
CPU time 174.45 seconds
Started May 05 02:21:51 PM PDT 24
Finished May 05 02:24:46 PM PDT 24
Peak memory 248320 kb
Host smart-0d5714f4-6d01-4c6d-ad02-1cd5acf4bfa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271497281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.271497281
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3535580166
Short name T469
Test name
Test status
Simulation time 47837839 ps
CPU time 5.68 seconds
Started May 05 02:21:49 PM PDT 24
Finished May 05 02:21:55 PM PDT 24
Peak memory 248692 kb
Host smart-17bc94b1-f1d5-476f-a0f3-b6ffec5138a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35355
80166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3535580166
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2214352305
Short name T32
Test name
Test status
Simulation time 238435583 ps
CPU time 5.25 seconds
Started May 05 02:21:48 PM PDT 24
Finished May 05 02:21:54 PM PDT 24
Peak memory 240480 kb
Host smart-35222c2c-69a5-412b-8522-a8397d5bc3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22143
52305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2214352305
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.482784995
Short name T364
Test name
Test status
Simulation time 153412491 ps
CPU time 17.34 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:22:14 PM PDT 24
Peak memory 255584 kb
Host smart-f3973775-ac06-4fdd-b147-1296221d1d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48278
4995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.482784995
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1261049630
Short name T394
Test name
Test status
Simulation time 227440679 ps
CPU time 15.13 seconds
Started May 05 02:21:48 PM PDT 24
Finished May 05 02:22:03 PM PDT 24
Peak memory 254676 kb
Host smart-26215099-3238-475f-8784-0309165c20de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12610
49630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1261049630
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1998661591
Short name T597
Test name
Test status
Simulation time 4801764770 ps
CPU time 84.75 seconds
Started May 05 02:21:53 PM PDT 24
Finished May 05 02:23:18 PM PDT 24
Peak memory 249804 kb
Host smart-6b172cca-bdab-4f1f-ac95-9ddf60268ea2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998661591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1998661591
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.64346943
Short name T116
Test name
Test status
Simulation time 113684939207 ps
CPU time 1437.55 seconds
Started May 05 02:22:06 PM PDT 24
Finished May 05 02:46:04 PM PDT 24
Peak memory 273028 kb
Host smart-45a51d39-17fe-4546-a6f6-10caf31a47fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64346943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.64346943
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3513199165
Short name T414
Test name
Test status
Simulation time 12577512720 ps
CPU time 190.46 seconds
Started May 05 02:22:01 PM PDT 24
Finished May 05 02:25:12 PM PDT 24
Peak memory 250164 kb
Host smart-8c2d068a-1f94-4d42-8cd5-e31c5809c041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35131
99165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3513199165
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1218638298
Short name T211
Test name
Test status
Simulation time 378258440 ps
CPU time 12.55 seconds
Started May 05 02:21:56 PM PDT 24
Finished May 05 02:22:09 PM PDT 24
Peak memory 248700 kb
Host smart-1e5c2291-dce3-441b-be6d-0de81a9157f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12186
38298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1218638298
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3786185689
Short name T563
Test name
Test status
Simulation time 42862329216 ps
CPU time 2510.06 seconds
Started May 05 02:22:08 PM PDT 24
Finished May 05 03:03:58 PM PDT 24
Peak memory 288948 kb
Host smart-4e278ceb-78b6-4b84-a8b2-da566320ff4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786185689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3786185689
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.661060930
Short name T428
Test name
Test status
Simulation time 69312898802 ps
CPU time 2244.35 seconds
Started May 05 02:22:07 PM PDT 24
Finished May 05 02:59:32 PM PDT 24
Peak memory 281260 kb
Host smart-eeff5b6d-8835-4caf-ac43-a9af5101d2d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661060930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.661060930
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3525086811
Short name T316
Test name
Test status
Simulation time 9024626953 ps
CPU time 344.31 seconds
Started May 05 02:22:06 PM PDT 24
Finished May 05 02:27:50 PM PDT 24
Peak memory 248148 kb
Host smart-f9a826a8-c6cb-434a-b208-85624cc3f551
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525086811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3525086811
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2172594915
Short name T601
Test name
Test status
Simulation time 393166180 ps
CPU time 4.99 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:22:03 PM PDT 24
Peak memory 240504 kb
Host smart-f708808c-c545-48b2-8bd9-cf5767ec54d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21725
94915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2172594915
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.19190480
Short name T508
Test name
Test status
Simulation time 3502983868 ps
CPU time 51.63 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:22:49 PM PDT 24
Peak memory 256300 kb
Host smart-5443e0b6-ac5d-4877-8622-56a7898717ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19190
480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.19190480
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2406008925
Short name T58
Test name
Test status
Simulation time 1181854791 ps
CPU time 34.15 seconds
Started May 05 02:22:02 PM PDT 24
Finished May 05 02:22:37 PM PDT 24
Peak memory 255488 kb
Host smart-876ea344-3a67-43c6-bfbf-afcd9fa3eacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24060
08925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2406008925
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.698703259
Short name T482
Test name
Test status
Simulation time 1451368031 ps
CPU time 7.83 seconds
Started May 05 02:21:57 PM PDT 24
Finished May 05 02:22:06 PM PDT 24
Peak memory 248748 kb
Host smart-f06b680b-4975-4bd7-9e89-882a275c9d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69870
3259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.698703259
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2876193802
Short name T75
Test name
Test status
Simulation time 55656756143 ps
CPU time 3130.47 seconds
Started May 05 02:22:12 PM PDT 24
Finished May 05 03:14:23 PM PDT 24
Peak memory 289624 kb
Host smart-375046f4-ed2d-41ba-a2fa-36b0b7229c50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876193802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2876193802
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.762820163
Short name T420
Test name
Test status
Simulation time 83511493695 ps
CPU time 2154.49 seconds
Started May 05 02:22:12 PM PDT 24
Finished May 05 02:58:07 PM PDT 24
Peak memory 306228 kb
Host smart-1a8a292c-f197-4b46-8019-af5de5b562ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762820163 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.762820163
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2440142630
Short name T96
Test name
Test status
Simulation time 78403853436 ps
CPU time 1463.85 seconds
Started May 05 02:22:15 PM PDT 24
Finished May 05 02:46:40 PM PDT 24
Peak memory 289396 kb
Host smart-ba4f789b-36bf-4334-95d1-36e2cb393195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440142630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2440142630
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.4071930802
Short name T350
Test name
Test status
Simulation time 969802622 ps
CPU time 15.16 seconds
Started May 05 02:22:12 PM PDT 24
Finished May 05 02:22:28 PM PDT 24
Peak memory 255476 kb
Host smart-f257da7e-11cb-464c-a178-ae3c20db224d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
30802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4071930802
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.4100579952
Short name T257
Test name
Test status
Simulation time 3389946319 ps
CPU time 58.75 seconds
Started May 05 02:22:12 PM PDT 24
Finished May 05 02:23:11 PM PDT 24
Peak memory 248736 kb
Host smart-780ffc54-ef16-47af-9e9c-a845ca6c414a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41005
79952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4100579952
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3608425980
Short name T664
Test name
Test status
Simulation time 68057017443 ps
CPU time 1442.05 seconds
Started May 05 02:22:21 PM PDT 24
Finished May 05 02:46:24 PM PDT 24
Peak memory 288776 kb
Host smart-1919fe11-94a8-4f7a-b9d1-6c1cc16dbfae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608425980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3608425980
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4007819169
Short name T549
Test name
Test status
Simulation time 22740368252 ps
CPU time 1398.67 seconds
Started May 05 02:22:25 PM PDT 24
Finished May 05 02:45:45 PM PDT 24
Peak memory 289732 kb
Host smart-10646e45-2848-4510-b63d-a4783638e00b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007819169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4007819169
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2208441607
Short name T93
Test name
Test status
Simulation time 4213628583 ps
CPU time 175.32 seconds
Started May 05 02:22:21 PM PDT 24
Finished May 05 02:25:16 PM PDT 24
Peak memory 248188 kb
Host smart-f51f99bc-34d9-41c8-a0b9-6f8360bce7b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208441607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2208441607
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2565844374
Short name T476
Test name
Test status
Simulation time 1350014668 ps
CPU time 19.08 seconds
Started May 05 02:22:11 PM PDT 24
Finished May 05 02:22:31 PM PDT 24
Peak memory 256936 kb
Host smart-a9487d59-1026-4d48-a13c-8b6aab34939a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
44374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2565844374
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.680398805
Short name T390
Test name
Test status
Simulation time 230277758 ps
CPU time 13.77 seconds
Started May 05 02:22:11 PM PDT 24
Finished May 05 02:22:25 PM PDT 24
Peak memory 248848 kb
Host smart-4ffd5e29-1213-4eca-a8fe-569af6d04f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68039
8805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.680398805
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1223224643
Short name T646
Test name
Test status
Simulation time 994167348 ps
CPU time 24.3 seconds
Started May 05 02:22:15 PM PDT 24
Finished May 05 02:22:40 PM PDT 24
Peak memory 255632 kb
Host smart-4f1c7967-fae2-4c86-9f87-0b6add932c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
24643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1223224643
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3745417380
Short name T489
Test name
Test status
Simulation time 493496041 ps
CPU time 12.78 seconds
Started May 05 02:22:11 PM PDT 24
Finished May 05 02:22:25 PM PDT 24
Peak memory 248752 kb
Host smart-f67c7102-ff3b-4932-a437-f2a0e5f39b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
17380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3745417380
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1290479154
Short name T347
Test name
Test status
Simulation time 33101103811 ps
CPU time 1217.2 seconds
Started May 05 02:22:39 PM PDT 24
Finished May 05 02:42:57 PM PDT 24
Peak memory 265260 kb
Host smart-1823b609-c830-42d5-9b95-8752138777b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290479154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1290479154
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3577209812
Short name T603
Test name
Test status
Simulation time 599396270 ps
CPU time 55.54 seconds
Started May 05 02:22:41 PM PDT 24
Finished May 05 02:23:37 PM PDT 24
Peak memory 249200 kb
Host smart-96d05201-a682-48c9-8fb6-b2ea3d20de92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
09812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3577209812
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3045538017
Short name T408
Test name
Test status
Simulation time 262157316 ps
CPU time 25.8 seconds
Started May 05 02:22:36 PM PDT 24
Finished May 05 02:23:02 PM PDT 24
Peak memory 255264 kb
Host smart-06677de3-0f13-4f76-bbf8-347cebefbff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30455
38017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3045538017
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1414307824
Short name T65
Test name
Test status
Simulation time 42673846698 ps
CPU time 1449.28 seconds
Started May 05 02:22:41 PM PDT 24
Finished May 05 02:46:51 PM PDT 24
Peak memory 288996 kb
Host smart-c81cba22-9625-445f-a4d8-f939494f01da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414307824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1414307824
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1556795445
Short name T598
Test name
Test status
Simulation time 50959143775 ps
CPU time 2650.02 seconds
Started May 05 02:22:39 PM PDT 24
Finished May 05 03:06:49 PM PDT 24
Peak memory 289144 kb
Host smart-88270d98-a4bf-4766-afb5-f25131e09813
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556795445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1556795445
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.227871425
Short name T550
Test name
Test status
Simulation time 7613358322 ps
CPU time 156.5 seconds
Started May 05 02:22:39 PM PDT 24
Finished May 05 02:25:16 PM PDT 24
Peak memory 254756 kb
Host smart-3ef30419-c80d-4b8b-aa4d-11f8639c8ffd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227871425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.227871425
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.435475312
Short name T77
Test name
Test status
Simulation time 680984158 ps
CPU time 14.98 seconds
Started May 05 02:22:35 PM PDT 24
Finished May 05 02:22:51 PM PDT 24
Peak memory 256000 kb
Host smart-87ba7e74-de9f-47ff-920f-6c448545f4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43547
5312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.435475312
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2317932284
Short name T283
Test name
Test status
Simulation time 232142929 ps
CPU time 22.48 seconds
Started May 05 02:22:37 PM PDT 24
Finished May 05 02:23:00 PM PDT 24
Peak memory 248704 kb
Host smart-13a6cd72-6d08-4f3e-982d-8ab3ac89fab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23179
32284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2317932284
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3345868318
Short name T261
Test name
Test status
Simulation time 2064628637 ps
CPU time 37.26 seconds
Started May 05 02:22:41 PM PDT 24
Finished May 05 02:23:19 PM PDT 24
Peak memory 256880 kb
Host smart-eaf5da15-0a8c-410a-adea-05777024c75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
68318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3345868318
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.694262007
Short name T223
Test name
Test status
Simulation time 2065309905 ps
CPU time 56.31 seconds
Started May 05 02:22:30 PM PDT 24
Finished May 05 02:23:27 PM PDT 24
Peak memory 255996 kb
Host smart-f171b733-bec1-4983-b2e6-c20e3ee1bbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69426
2007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.694262007
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1949083389
Short name T569
Test name
Test status
Simulation time 62960426889 ps
CPU time 3360.31 seconds
Started May 05 02:22:39 PM PDT 24
Finished May 05 03:18:40 PM PDT 24
Peak memory 297948 kb
Host smart-55c7338a-f31f-4ecb-a7f4-fe6d9980e947
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949083389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1949083389
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.312452243
Short name T403
Test name
Test status
Simulation time 53900883640 ps
CPU time 3011.82 seconds
Started May 05 02:22:48 PM PDT 24
Finished May 05 03:13:01 PM PDT 24
Peak memory 289400 kb
Host smart-4fa457ae-ef8d-488d-ad6c-a15ec290c30a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312452243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.312452243
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.341727714
Short name T78
Test name
Test status
Simulation time 5664301973 ps
CPU time 96.95 seconds
Started May 05 02:22:46 PM PDT 24
Finished May 05 02:24:24 PM PDT 24
Peak memory 248720 kb
Host smart-f84bd4f4-5b02-415e-9f5d-5b691209c772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
7714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.341727714
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1903650691
Short name T524
Test name
Test status
Simulation time 91225818 ps
CPU time 4.1 seconds
Started May 05 02:22:42 PM PDT 24
Finished May 05 02:22:47 PM PDT 24
Peak memory 240736 kb
Host smart-feb456e6-bdca-46b5-ba6b-49f99fb8a2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036
50691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1903650691
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2543839123
Short name T693
Test name
Test status
Simulation time 8233033503 ps
CPU time 841.05 seconds
Started May 05 02:22:49 PM PDT 24
Finished May 05 02:36:50 PM PDT 24
Peak memory 273328 kb
Host smart-7f141af2-7355-4b66-ae84-24ac47dfc4d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543839123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2543839123
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2468396142
Short name T498
Test name
Test status
Simulation time 20086645074 ps
CPU time 1163.41 seconds
Started May 05 02:22:49 PM PDT 24
Finished May 05 02:42:13 PM PDT 24
Peak memory 273432 kb
Host smart-1bb5d782-9e5d-4199-a6ad-c9c5bfbde773
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468396142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2468396142
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4038750128
Short name T708
Test name
Test status
Simulation time 18905194018 ps
CPU time 366.55 seconds
Started May 05 02:22:49 PM PDT 24
Finished May 05 02:28:56 PM PDT 24
Peak memory 248036 kb
Host smart-6a84fd74-2998-4761-b8a8-4011bb364dc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038750128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4038750128
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2826670394
Short name T501
Test name
Test status
Simulation time 2934001841 ps
CPU time 40.48 seconds
Started May 05 02:22:43 PM PDT 24
Finished May 05 02:23:24 PM PDT 24
Peak memory 248764 kb
Host smart-6c77c578-8cf5-4d77-b084-bb7794e30158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
70394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2826670394
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1749211370
Short name T123
Test name
Test status
Simulation time 261308052 ps
CPU time 31.08 seconds
Started May 05 02:22:42 PM PDT 24
Finished May 05 02:23:14 PM PDT 24
Peak memory 248720 kb
Host smart-04deefa9-09ad-4bec-8722-b5175d19964d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17492
11370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1749211370
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1915284004
Short name T697
Test name
Test status
Simulation time 119272191 ps
CPU time 14.18 seconds
Started May 05 02:22:47 PM PDT 24
Finished May 05 02:23:02 PM PDT 24
Peak memory 248712 kb
Host smart-0842023e-a875-43c5-909c-bf8df0da9bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19152
84004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1915284004
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1300813919
Short name T533
Test name
Test status
Simulation time 665865809 ps
CPU time 37.86 seconds
Started May 05 02:22:43 PM PDT 24
Finished May 05 02:23:22 PM PDT 24
Peak memory 248840 kb
Host smart-f380ebcb-1af2-4d2a-a6aa-21c4a78f8ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13008
13919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1300813919
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.941628655
Short name T710
Test name
Test status
Simulation time 58845650289 ps
CPU time 5156.61 seconds
Started May 05 02:22:51 PM PDT 24
Finished May 05 03:48:48 PM PDT 24
Peak memory 321888 kb
Host smart-18aef8ca-f99c-48ab-8508-fb3b4013d808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941628655 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.941628655
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1478366310
Short name T696
Test name
Test status
Simulation time 11199321490 ps
CPU time 1361.11 seconds
Started May 05 02:22:57 PM PDT 24
Finished May 05 02:45:39 PM PDT 24
Peak memory 284860 kb
Host smart-f3972f35-7645-4683-9b66-8e515d7ad5f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478366310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1478366310
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2117134494
Short name T446
Test name
Test status
Simulation time 2264335546 ps
CPU time 20.26 seconds
Started May 05 02:22:58 PM PDT 24
Finished May 05 02:23:19 PM PDT 24
Peak memory 248832 kb
Host smart-6333d383-47cf-4f29-8256-c882456ea34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21171
34494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2117134494
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1292861349
Short name T657
Test name
Test status
Simulation time 790557953 ps
CPU time 44.5 seconds
Started May 05 02:22:56 PM PDT 24
Finished May 05 02:23:40 PM PDT 24
Peak memory 256900 kb
Host smart-22c0f5a6-0273-43ba-9c99-8ed6dae88eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
61349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1292861349
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.209701988
Short name T328
Test name
Test status
Simulation time 39416401258 ps
CPU time 2199.24 seconds
Started May 05 02:23:09 PM PDT 24
Finished May 05 02:59:49 PM PDT 24
Peak memory 288188 kb
Host smart-bfeecd75-f019-4327-9168-e56e62e8b4f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209701988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.209701988
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3862172666
Short name T515
Test name
Test status
Simulation time 99514897588 ps
CPU time 1675.91 seconds
Started May 05 02:23:10 PM PDT 24
Finished May 05 02:51:06 PM PDT 24
Peak memory 281572 kb
Host smart-5e67e1ba-7d13-4898-bbfe-bed289a6cc8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862172666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3862172666
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.152792921
Short name T282
Test name
Test status
Simulation time 7564732237 ps
CPU time 296.74 seconds
Started May 05 02:23:10 PM PDT 24
Finished May 05 02:28:08 PM PDT 24
Peak memory 248208 kb
Host smart-81351742-26db-457d-af8b-35994cdf20a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152792921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.152792921
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.719268151
Short name T462
Test name
Test status
Simulation time 350936154 ps
CPU time 34.65 seconds
Started May 05 02:22:51 PM PDT 24
Finished May 05 02:23:26 PM PDT 24
Peak memory 255996 kb
Host smart-35f17568-6729-49c1-8713-c94f579b376c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71926
8151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.719268151
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1169717471
Short name T30
Test name
Test status
Simulation time 981884377 ps
CPU time 27.35 seconds
Started May 05 02:22:52 PM PDT 24
Finished May 05 02:23:19 PM PDT 24
Peak memory 255892 kb
Host smart-ad399785-c16a-4cc9-8bce-85c86f79e17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
17471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1169717471
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4069847648
Short name T402
Test name
Test status
Simulation time 732851514 ps
CPU time 27.36 seconds
Started May 05 02:22:57 PM PDT 24
Finished May 05 02:23:24 PM PDT 24
Peak memory 248716 kb
Host smart-3c08a75a-6ed5-43f5-a0a6-17081fbf6f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40698
47648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4069847648
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2676879718
Short name T38
Test name
Test status
Simulation time 163737293 ps
CPU time 12.73 seconds
Started May 05 02:22:51 PM PDT 24
Finished May 05 02:23:04 PM PDT 24
Peak memory 255908 kb
Host smart-aa9b03f0-5d36-48ca-a6d2-c341a83b10f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26768
79718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2676879718
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1756575493
Short name T629
Test name
Test status
Simulation time 34887413696 ps
CPU time 1912.97 seconds
Started May 05 02:23:09 PM PDT 24
Finished May 05 02:55:03 PM PDT 24
Peak memory 289132 kb
Host smart-610804d8-a16c-422c-818c-2620ba0634e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756575493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1756575493
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3222882937
Short name T34
Test name
Test status
Simulation time 52823704650 ps
CPU time 1587.42 seconds
Started May 05 02:23:09 PM PDT 24
Finished May 05 02:49:38 PM PDT 24
Peak memory 281704 kb
Host smart-e6862659-5521-48ed-8f77-413230feddcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222882937 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3222882937
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2605213104
Short name T452
Test name
Test status
Simulation time 26341493066 ps
CPU time 1508.35 seconds
Started May 05 02:23:18 PM PDT 24
Finished May 05 02:48:27 PM PDT 24
Peak memory 273276 kb
Host smart-02f6fd5a-a792-4dfe-aa88-24ab4f316f63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605213104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2605213104
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2057787327
Short name T628
Test name
Test status
Simulation time 3052659910 ps
CPU time 60.51 seconds
Started May 05 02:23:14 PM PDT 24
Finished May 05 02:24:15 PM PDT 24
Peak memory 256952 kb
Host smart-45f28b97-e98b-45a2-a01f-5acf917bb0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20577
87327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2057787327
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3456353483
Short name T289
Test name
Test status
Simulation time 5315415208 ps
CPU time 53.33 seconds
Started May 05 02:23:09 PM PDT 24
Finished May 05 02:24:03 PM PDT 24
Peak memory 248752 kb
Host smart-83ce747b-c0d1-4600-955d-95d3ceef56d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34563
53483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3456353483
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2003900297
Short name T60
Test name
Test status
Simulation time 182194672555 ps
CPU time 1307.74 seconds
Started May 05 02:23:22 PM PDT 24
Finished May 05 02:45:11 PM PDT 24
Peak memory 285240 kb
Host smart-3fae3e63-f302-40a6-8c5d-fb41f35137ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003900297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2003900297
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1100557414
Short name T63
Test name
Test status
Simulation time 203872389563 ps
CPU time 2232.22 seconds
Started May 05 02:23:23 PM PDT 24
Finished May 05 03:00:36 PM PDT 24
Peak memory 288920 kb
Host smart-4b5c5dcd-4547-4458-a962-75b959a7c1fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100557414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1100557414
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.288420186
Short name T129
Test name
Test status
Simulation time 11016408286 ps
CPU time 114.44 seconds
Started May 05 02:23:18 PM PDT 24
Finished May 05 02:25:13 PM PDT 24
Peak memory 247996 kb
Host smart-0335bdfd-88e9-42be-93c7-0fe53493f5fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288420186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.288420186
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3238044992
Short name T687
Test name
Test status
Simulation time 133155209 ps
CPU time 13.57 seconds
Started May 05 02:23:09 PM PDT 24
Finished May 05 02:23:23 PM PDT 24
Peak memory 255996 kb
Host smart-880c02bb-1e59-4aab-af39-d28b05fcdbc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
44992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3238044992
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2355812252
Short name T354
Test name
Test status
Simulation time 565929303 ps
CPU time 32.13 seconds
Started May 05 02:23:09 PM PDT 24
Finished May 05 02:23:42 PM PDT 24
Peak memory 255224 kb
Host smart-50a8c0fb-29d2-483c-a9b3-270936f4c83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
12252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2355812252
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.542350081
Short name T679
Test name
Test status
Simulation time 861104758 ps
CPU time 28.62 seconds
Started May 05 02:23:08 PM PDT 24
Finished May 05 02:23:37 PM PDT 24
Peak memory 248832 kb
Host smart-f8294106-9e03-44fc-a31a-fb690318cf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54235
0081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.542350081
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.892036525
Short name T80
Test name
Test status
Simulation time 35781565974 ps
CPU time 1767.02 seconds
Started May 05 02:23:23 PM PDT 24
Finished May 05 02:52:51 PM PDT 24
Peak memory 269916 kb
Host smart-37937b95-2f64-419f-8a7f-bd43632d4cb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892036525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.892036525
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3769221706
Short name T95
Test name
Test status
Simulation time 93553547810 ps
CPU time 2601.09 seconds
Started May 05 02:23:28 PM PDT 24
Finished May 05 03:06:50 PM PDT 24
Peak memory 320576 kb
Host smart-5343d7da-8b1f-4ea5-8505-5d0d9476340b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769221706 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3769221706
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1736636082
Short name T383
Test name
Test status
Simulation time 111997554073 ps
CPU time 1580.3 seconds
Started May 05 02:23:41 PM PDT 24
Finished May 05 02:50:02 PM PDT 24
Peak memory 281612 kb
Host smart-89f47645-5275-48e6-a411-806c4cbc25cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736636082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1736636082
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3062065490
Short name T447
Test name
Test status
Simulation time 26846434551 ps
CPU time 85.03 seconds
Started May 05 02:23:37 PM PDT 24
Finished May 05 02:25:02 PM PDT 24
Peak memory 256988 kb
Host smart-3649dd39-b285-430f-ab80-0e009794b38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
65490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3062065490
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1604482320
Short name T595
Test name
Test status
Simulation time 392655859 ps
CPU time 18.14 seconds
Started May 05 02:23:37 PM PDT 24
Finished May 05 02:23:56 PM PDT 24
Peak memory 248700 kb
Host smart-e68eaca8-1bdc-47ef-8f9b-ab3f7f9b3c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16044
82320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1604482320
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1425645761
Short name T579
Test name
Test status
Simulation time 47552797503 ps
CPU time 2621.51 seconds
Started May 05 02:23:45 PM PDT 24
Finished May 05 03:07:27 PM PDT 24
Peak memory 289096 kb
Host smart-67cb8cd9-5657-4c2c-addc-04587f263076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425645761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1425645761
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2900126251
Short name T592
Test name
Test status
Simulation time 2987572340 ps
CPU time 26.45 seconds
Started May 05 02:23:31 PM PDT 24
Finished May 05 02:23:57 PM PDT 24
Peak memory 256028 kb
Host smart-46d15365-0b6b-4d33-bb88-561b4b4d6e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29001
26251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2900126251
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1355675709
Short name T539
Test name
Test status
Simulation time 577577719 ps
CPU time 31.62 seconds
Started May 05 02:23:31 PM PDT 24
Finished May 05 02:24:03 PM PDT 24
Peak memory 249112 kb
Host smart-33733100-d18e-4625-8773-01e554c71e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
75709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1355675709
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2511410039
Short name T130
Test name
Test status
Simulation time 212661911 ps
CPU time 23.34 seconds
Started May 05 02:23:36 PM PDT 24
Finished May 05 02:23:59 PM PDT 24
Peak memory 247620 kb
Host smart-cebff0c4-5681-4c83-ad20-1aca281264fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
10039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2511410039
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.518617706
Short name T562
Test name
Test status
Simulation time 4453286083 ps
CPU time 66.56 seconds
Started May 05 02:23:32 PM PDT 24
Finished May 05 02:24:39 PM PDT 24
Peak memory 248788 kb
Host smart-f6ad3acf-3b0d-48e6-9fb4-76f70bd646a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51861
7706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.518617706
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.736187198
Short name T281
Test name
Test status
Simulation time 244523795762 ps
CPU time 3256.31 seconds
Started May 05 02:23:45 PM PDT 24
Finished May 05 03:18:02 PM PDT 24
Peak memory 306120 kb
Host smart-08a1f7ea-6f9d-4d9d-8129-318133fe5ab1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736187198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.736187198
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2306125278
Short name T235
Test name
Test status
Simulation time 16999689 ps
CPU time 2.58 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:18:46 PM PDT 24
Peak memory 248920 kb
Host smart-eb05a8ee-091e-4686-ac3d-cbd332224228
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2306125278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2306125278
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2444095933
Short name T440
Test name
Test status
Simulation time 60681305735 ps
CPU time 1342.5 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:41:07 PM PDT 24
Peak memory 281604 kb
Host smart-03d56fb3-c73d-4330-bdd9-c8abb47040dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444095933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2444095933
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3550547375
Short name T587
Test name
Test status
Simulation time 218890508 ps
CPU time 11.16 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:18:53 PM PDT 24
Peak memory 248748 kb
Host smart-238ed542-273c-4e73-b144-14a1c12e56c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3550547375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3550547375
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2405892146
Short name T351
Test name
Test status
Simulation time 11836663109 ps
CPU time 122.32 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:20:48 PM PDT 24
Peak memory 256936 kb
Host smart-a73bdb46-d8b1-460a-8323-c890b89825cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24058
92146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2405892146
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.618812501
Short name T688
Test name
Test status
Simulation time 1531952197 ps
CPU time 17.14 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:19:00 PM PDT 24
Peak memory 248796 kb
Host smart-7428452b-8f36-4db6-b2da-74eef0a34712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61881
2501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.618812501
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.652003301
Short name T535
Test name
Test status
Simulation time 64595508064 ps
CPU time 1155.15 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:37:59 PM PDT 24
Peak memory 273376 kb
Host smart-8068316a-2bd3-4c8a-8091-9b8a8ac80731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652003301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.652003301
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.71275363
Short name T312
Test name
Test status
Simulation time 19660016786 ps
CPU time 378.66 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:25:01 PM PDT 24
Peak memory 248176 kb
Host smart-e5b705ae-1165-4f04-bbcd-d02e3aeb60c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71275363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.71275363
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1544897271
Short name T607
Test name
Test status
Simulation time 51394482 ps
CPU time 3.21 seconds
Started May 05 02:18:40 PM PDT 24
Finished May 05 02:18:44 PM PDT 24
Peak memory 240536 kb
Host smart-cd5cbbb9-e9d4-4719-ae57-6c505e9f2b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15448
97271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1544897271
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1979722296
Short name T128
Test name
Test status
Simulation time 256388696 ps
CPU time 17.18 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:19:02 PM PDT 24
Peak memory 248692 kb
Host smart-f879c77d-bd72-4de3-a9eb-070fb502d323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19797
22296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1979722296
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3733049257
Short name T689
Test name
Test status
Simulation time 184272269 ps
CPU time 5.9 seconds
Started May 05 02:18:44 PM PDT 24
Finished May 05 02:18:51 PM PDT 24
Peak memory 251832 kb
Host smart-cca2c321-94e6-4627-ba93-7bd348dc7ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
49257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3733049257
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2167306893
Short name T663
Test name
Test status
Simulation time 1795580498 ps
CPU time 27.8 seconds
Started May 05 02:18:38 PM PDT 24
Finished May 05 02:19:07 PM PDT 24
Peak memory 248756 kb
Host smart-2aa457f0-09c1-4823-84db-bef50c69c045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673
06893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2167306893
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.673421045
Short name T406
Test name
Test status
Simulation time 2037821103 ps
CPU time 60.18 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:19:42 PM PDT 24
Peak memory 255248 kb
Host smart-35e78b56-0314-4763-8ef0-4aecf43185a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673421045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.673421045
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1895010569
Short name T412
Test name
Test status
Simulation time 124707826210 ps
CPU time 2486.58 seconds
Started May 05 02:18:41 PM PDT 24
Finished May 05 03:00:08 PM PDT 24
Peak memory 305776 kb
Host smart-392217ea-e7ad-45dc-ae8f-8899b48ec339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895010569 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1895010569
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3968708344
Short name T55
Test name
Test status
Simulation time 8121465320 ps
CPU time 964.89 seconds
Started May 05 02:23:52 PM PDT 24
Finished May 05 02:39:57 PM PDT 24
Peak memory 289176 kb
Host smart-a98c7f34-da7f-404c-bb64-db75069fda9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968708344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3968708344
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1940021174
Short name T608
Test name
Test status
Simulation time 3717068384 ps
CPU time 206.6 seconds
Started May 05 02:23:53 PM PDT 24
Finished May 05 02:27:19 PM PDT 24
Peak memory 250252 kb
Host smart-6fe1776f-43b3-4521-a23f-0cc838dde366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400
21174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1940021174
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2834964142
Short name T308
Test name
Test status
Simulation time 100998402110 ps
CPU time 1271.72 seconds
Started May 05 02:23:53 PM PDT 24
Finished May 05 02:45:05 PM PDT 24
Peak memory 288996 kb
Host smart-3ab5198a-445f-464e-8215-c461a091245e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834964142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2834964142
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3708557834
Short name T297
Test name
Test status
Simulation time 36848018681 ps
CPU time 364.61 seconds
Started May 05 02:23:54 PM PDT 24
Finished May 05 02:29:59 PM PDT 24
Peak memory 248168 kb
Host smart-82dba268-5bcc-4b61-8948-4967c1fdccfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708557834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3708557834
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.504546500
Short name T529
Test name
Test status
Simulation time 1772489567 ps
CPU time 22.76 seconds
Started May 05 02:23:45 PM PDT 24
Finished May 05 02:24:09 PM PDT 24
Peak memory 248748 kb
Host smart-d5ed33ae-a3e5-4500-9a87-86d113b2f628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50454
6500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.504546500
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1042859054
Short name T511
Test name
Test status
Simulation time 3149813159 ps
CPU time 35.6 seconds
Started May 05 02:23:48 PM PDT 24
Finished May 05 02:24:24 PM PDT 24
Peak memory 248816 kb
Host smart-1f62d360-aa35-494e-92e1-41c9ee17f900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10428
59054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1042859054
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.443851437
Short name T74
Test name
Test status
Simulation time 728982496 ps
CPU time 12.71 seconds
Started May 05 02:23:53 PM PDT 24
Finished May 05 02:24:07 PM PDT 24
Peak memory 255864 kb
Host smart-efcc8f63-8201-436f-b565-b930cff7b36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44385
1437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.443851437
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.405059182
Short name T575
Test name
Test status
Simulation time 4396499231 ps
CPU time 29.39 seconds
Started May 05 02:23:47 PM PDT 24
Finished May 05 02:24:16 PM PDT 24
Peak memory 248764 kb
Host smart-8f6f95dd-edb7-451c-ada0-ee8fb239824b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40505
9182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.405059182
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3585109765
Short name T293
Test name
Test status
Simulation time 52486195725 ps
CPU time 2953.02 seconds
Started May 05 02:23:56 PM PDT 24
Finished May 05 03:13:10 PM PDT 24
Peak memory 289288 kb
Host smart-a44e34a6-93dc-4586-bd98-a0ed349343ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585109765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3585109765
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2739548601
Short name T92
Test name
Test status
Simulation time 24778399363 ps
CPU time 2626.47 seconds
Started May 05 02:23:56 PM PDT 24
Finished May 05 03:07:43 PM PDT 24
Peak memory 315944 kb
Host smart-4e7ff5b8-96de-4295-a3d8-e4cced7842bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739548601 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2739548601
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1194799529
Short name T556
Test name
Test status
Simulation time 766166221 ps
CPU time 68.6 seconds
Started May 05 02:24:10 PM PDT 24
Finished May 05 02:25:19 PM PDT 24
Peak memory 248752 kb
Host smart-06964e7d-ee69-4663-8d47-03a2cd558b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
99529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1194799529
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2256882719
Short name T635
Test name
Test status
Simulation time 398538460 ps
CPU time 38.78 seconds
Started May 05 02:24:05 PM PDT 24
Finished May 05 02:24:44 PM PDT 24
Peak memory 248772 kb
Host smart-870ed503-dc63-448b-8dee-6dab7df6685e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22568
82719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2256882719
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.941166525
Short name T707
Test name
Test status
Simulation time 124315201193 ps
CPU time 1162.55 seconds
Started May 05 02:24:19 PM PDT 24
Finished May 05 02:43:42 PM PDT 24
Peak memory 289060 kb
Host smart-174484ac-9abf-4d25-9441-5cc2c630608e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941166525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.941166525
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.656064487
Short name T346
Test name
Test status
Simulation time 17444585240 ps
CPU time 1210.99 seconds
Started May 05 02:24:19 PM PDT 24
Finished May 05 02:44:30 PM PDT 24
Peak memory 281624 kb
Host smart-868623af-d0c5-42e2-9625-43c565c266d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656064487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.656064487
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3248526334
Short name T296
Test name
Test status
Simulation time 18850667770 ps
CPU time 383.97 seconds
Started May 05 02:24:17 PM PDT 24
Finished May 05 02:30:41 PM PDT 24
Peak memory 248196 kb
Host smart-d9943b01-0c75-462f-80c5-7d0e3af2901c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248526334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3248526334
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.4284009999
Short name T288
Test name
Test status
Simulation time 333105353 ps
CPU time 9.82 seconds
Started May 05 02:24:03 PM PDT 24
Finished May 05 02:24:13 PM PDT 24
Peak memory 248760 kb
Host smart-af1c1df6-8c84-4f18-a5e1-c8425002aa9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42840
09999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4284009999
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2113815906
Short name T422
Test name
Test status
Simulation time 254869806 ps
CPU time 5.48 seconds
Started May 05 02:24:00 PM PDT 24
Finished May 05 02:24:06 PM PDT 24
Peak memory 240512 kb
Host smart-7c6115df-cd94-4412-9359-c337bdb24b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21138
15906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2113815906
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1511282301
Short name T265
Test name
Test status
Simulation time 3278417106 ps
CPU time 49.58 seconds
Started May 05 02:24:12 PM PDT 24
Finished May 05 02:25:02 PM PDT 24
Peak memory 248764 kb
Host smart-3a4038a5-da7d-4e1d-a7e3-a7dac21f1087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15112
82301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1511282301
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2082281621
Short name T290
Test name
Test status
Simulation time 1761366440 ps
CPU time 53.02 seconds
Started May 05 02:24:00 PM PDT 24
Finished May 05 02:24:53 PM PDT 24
Peak memory 256228 kb
Host smart-b961e70b-aed3-4c99-a550-dc95136ac28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
81621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2082281621
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1613760852
Short name T636
Test name
Test status
Simulation time 15397180583 ps
CPU time 1050.53 seconds
Started May 05 02:24:28 PM PDT 24
Finished May 05 02:41:59 PM PDT 24
Peak memory 272128 kb
Host smart-8f7d04ee-3d29-4a7a-bdda-cd97c646ae82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613760852 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1613760852
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3256947616
Short name T678
Test name
Test status
Simulation time 50301548121 ps
CPU time 1383.25 seconds
Started May 05 02:24:36 PM PDT 24
Finished May 05 02:47:39 PM PDT 24
Peak memory 271328 kb
Host smart-a75b447d-2ad0-4fcb-9b14-e22178b116e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256947616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3256947616
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4027522322
Short name T419
Test name
Test status
Simulation time 6152107569 ps
CPU time 137.85 seconds
Started May 05 02:24:39 PM PDT 24
Finished May 05 02:26:57 PM PDT 24
Peak memory 250948 kb
Host smart-24323348-b7c6-4c6e-bb6e-3980dbddc593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40275
22322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4027522322
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1723019072
Short name T433
Test name
Test status
Simulation time 1626472026 ps
CPU time 22.91 seconds
Started May 05 02:24:32 PM PDT 24
Finished May 05 02:24:56 PM PDT 24
Peak memory 254920 kb
Host smart-74c8ea6b-ec47-4087-9fd3-5709e7c53561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17230
19072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1723019072
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.13406114
Short name T327
Test name
Test status
Simulation time 29204988846 ps
CPU time 1706.87 seconds
Started May 05 02:24:37 PM PDT 24
Finished May 05 02:53:05 PM PDT 24
Peak memory 289412 kb
Host smart-bb20f231-1a70-4db9-8fb6-ed911aa66999
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13406114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.13406114
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.261578791
Short name T118
Test name
Test status
Simulation time 65349818806 ps
CPU time 142.09 seconds
Started May 05 02:24:37 PM PDT 24
Finished May 05 02:26:59 PM PDT 24
Peak memory 248764 kb
Host smart-7d3c3ad9-f7d8-4024-ab0d-ff560d48fa68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261578791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.261578791
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.973040410
Short name T26
Test name
Test status
Simulation time 239158088 ps
CPU time 15.44 seconds
Started May 05 02:24:28 PM PDT 24
Finished May 05 02:24:44 PM PDT 24
Peak memory 248720 kb
Host smart-67a81105-d787-4566-9555-ddafa64668aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97304
0410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.973040410
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3812333251
Short name T577
Test name
Test status
Simulation time 1347026935 ps
CPU time 22.58 seconds
Started May 05 02:24:29 PM PDT 24
Finished May 05 02:24:52 PM PDT 24
Peak memory 248680 kb
Host smart-4cf90a37-0968-4741-8789-0663da3b3b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38123
33251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3812333251
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.153650685
Short name T54
Test name
Test status
Simulation time 1699082609 ps
CPU time 29.97 seconds
Started May 05 02:24:39 PM PDT 24
Finished May 05 02:25:09 PM PDT 24
Peak memory 254608 kb
Host smart-4be273db-1aa8-4010-b8c1-615e3590b27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15365
0685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.153650685
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3756316788
Short name T212
Test name
Test status
Simulation time 224243339 ps
CPU time 21.04 seconds
Started May 05 02:24:28 PM PDT 24
Finished May 05 02:24:50 PM PDT 24
Peak memory 248676 kb
Host smart-3e2846ff-fac3-45c6-8f61-2c4518b045a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37563
16788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3756316788
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.260965940
Short name T391
Test name
Test status
Simulation time 26703270846 ps
CPU time 1024.86 seconds
Started May 05 02:24:37 PM PDT 24
Finished May 05 02:41:42 PM PDT 24
Peak memory 284388 kb
Host smart-c3e29cdc-0c3e-4c96-958a-0a9227f372c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260965940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.260965940
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1288416906
Short name T417
Test name
Test status
Simulation time 198515819758 ps
CPU time 2949.86 seconds
Started May 05 02:24:48 PM PDT 24
Finished May 05 03:13:59 PM PDT 24
Peak memory 281532 kb
Host smart-af97f46a-96ad-4175-977d-fe88aadb88d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288416906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1288416906
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1706443081
Short name T639
Test name
Test status
Simulation time 17467721848 ps
CPU time 178.94 seconds
Started May 05 02:24:46 PM PDT 24
Finished May 05 02:27:45 PM PDT 24
Peak memory 249832 kb
Host smart-5d82adb0-129e-4578-81ce-1feec56eeb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
43081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1706443081
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2494231384
Short name T570
Test name
Test status
Simulation time 1124083768 ps
CPU time 62.25 seconds
Started May 05 02:24:46 PM PDT 24
Finished May 05 02:25:49 PM PDT 24
Peak memory 255964 kb
Host smart-b3f42e3f-cf0b-4581-9702-2cad03f30cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24942
31384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2494231384
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1381900589
Short name T115
Test name
Test status
Simulation time 62933586129 ps
CPU time 1214.93 seconds
Started May 05 02:24:51 PM PDT 24
Finished May 05 02:45:07 PM PDT 24
Peak memory 288972 kb
Host smart-6ea19dad-7e12-4c6e-81d7-cb085d334273
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381900589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1381900589
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2781683585
Short name T684
Test name
Test status
Simulation time 14499721239 ps
CPU time 1195.93 seconds
Started May 05 02:24:59 PM PDT 24
Finished May 05 02:44:55 PM PDT 24
Peak memory 283252 kb
Host smart-6319c10c-5ee9-48e6-bdfd-ed4b66cabcd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781683585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2781683585
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2523913819
Short name T121
Test name
Test status
Simulation time 40659065177 ps
CPU time 458.26 seconds
Started May 05 02:24:52 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 248292 kb
Host smart-bcee3d11-fcba-4b43-9430-6b5dd4f1c548
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523913819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2523913819
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.397087350
Short name T477
Test name
Test status
Simulation time 301644601 ps
CPU time 22.88 seconds
Started May 05 02:24:44 PM PDT 24
Finished May 05 02:25:07 PM PDT 24
Peak memory 248756 kb
Host smart-98a6cc3e-2371-4f7e-ab34-65fc7a5ee8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39708
7350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.397087350
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3607280150
Short name T599
Test name
Test status
Simulation time 3728439920 ps
CPU time 18.38 seconds
Started May 05 02:24:48 PM PDT 24
Finished May 05 02:25:07 PM PDT 24
Peak memory 247188 kb
Host smart-bb29f261-9b20-4ecb-b92e-d77b89c506af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
80150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3607280150
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.563739284
Short name T284
Test name
Test status
Simulation time 486849184 ps
CPU time 9.06 seconds
Started May 05 02:24:47 PM PDT 24
Finished May 05 02:24:57 PM PDT 24
Peak memory 253008 kb
Host smart-aadbaca5-4c2b-43cf-b464-04c51b798be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56373
9284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.563739284
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3396374115
Short name T442
Test name
Test status
Simulation time 260462015 ps
CPU time 20.19 seconds
Started May 05 02:24:42 PM PDT 24
Finished May 05 02:25:02 PM PDT 24
Peak memory 248832 kb
Host smart-4a883842-1a72-46c7-a62b-1794223c933e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33963
74115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3396374115
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.61332230
Short name T85
Test name
Test status
Simulation time 46563521044 ps
CPU time 2677.3 seconds
Started May 05 02:24:59 PM PDT 24
Finished May 05 03:09:37 PM PDT 24
Peak memory 305584 kb
Host smart-ca262c6c-0016-40e5-9b4c-6c30ba89c30c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61332230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_hand
ler_stress_all.61332230
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.542810852
Short name T202
Test name
Test status
Simulation time 41974116541 ps
CPU time 1999.2 seconds
Started May 05 02:25:01 PM PDT 24
Finished May 05 02:58:21 PM PDT 24
Peak memory 298100 kb
Host smart-9fe5eeb6-040a-4ebf-9465-ce7a1a0fde5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542810852 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.542810852
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2854395760
Short name T674
Test name
Test status
Simulation time 66685285889 ps
CPU time 2103.26 seconds
Started May 05 02:25:14 PM PDT 24
Finished May 05 03:00:18 PM PDT 24
Peak memory 289204 kb
Host smart-1f473e4e-fb0e-451e-b97a-a6718fbc1739
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854395760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2854395760
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3619259609
Short name T668
Test name
Test status
Simulation time 3086204339 ps
CPU time 116.1 seconds
Started May 05 02:25:10 PM PDT 24
Finished May 05 02:27:06 PM PDT 24
Peak memory 256960 kb
Host smart-0ab24459-6a77-4b55-b962-e0a255b6be15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36192
59609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3619259609
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.317341961
Short name T353
Test name
Test status
Simulation time 650002111 ps
CPU time 32.95 seconds
Started May 05 02:25:11 PM PDT 24
Finished May 05 02:25:44 PM PDT 24
Peak memory 248724 kb
Host smart-8856d92a-6346-4f30-a2d6-076dc2066669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734
1961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.317341961
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.295652535
Short name T324
Test name
Test status
Simulation time 140489875030 ps
CPU time 2106.86 seconds
Started May 05 02:25:16 PM PDT 24
Finished May 05 03:00:24 PM PDT 24
Peak memory 280828 kb
Host smart-276a7052-b597-49b5-8e05-0ea84614c6f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295652535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.295652535
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.545168574
Short name T637
Test name
Test status
Simulation time 31255432353 ps
CPU time 739.07 seconds
Started May 05 02:25:18 PM PDT 24
Finished May 05 02:37:38 PM PDT 24
Peak memory 266208 kb
Host smart-d7a443b0-796b-436e-972d-64400472563a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545168574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.545168574
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3125163475
Short name T382
Test name
Test status
Simulation time 197943104 ps
CPU time 18.38 seconds
Started May 05 02:25:06 PM PDT 24
Finished May 05 02:25:25 PM PDT 24
Peak memory 248712 kb
Host smart-e3ce112b-308b-4a1b-8544-4d5f26df78fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31251
63475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3125163475
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2443603608
Short name T81
Test name
Test status
Simulation time 4631415690 ps
CPU time 46.29 seconds
Started May 05 02:25:10 PM PDT 24
Finished May 05 02:25:56 PM PDT 24
Peak memory 256016 kb
Host smart-efc346fe-a3f6-44bd-83be-3f860684792f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24436
03608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2443603608
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3152653620
Short name T565
Test name
Test status
Simulation time 470012782 ps
CPU time 11.79 seconds
Started May 05 02:25:16 PM PDT 24
Finished May 05 02:25:28 PM PDT 24
Peak memory 255932 kb
Host smart-a3a80c06-e342-4a8e-a219-a3a3085c09d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31526
53620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3152653620
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1434937319
Short name T651
Test name
Test status
Simulation time 403296001 ps
CPU time 28.79 seconds
Started May 05 02:25:01 PM PDT 24
Finished May 05 02:25:30 PM PDT 24
Peak memory 255892 kb
Host smart-cb4e1648-4780-43ec-86f3-746423272de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
37319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1434937319
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2273975718
Short name T401
Test name
Test status
Simulation time 19970925855 ps
CPU time 1569.72 seconds
Started May 05 02:25:18 PM PDT 24
Finished May 05 02:51:28 PM PDT 24
Peak memory 289216 kb
Host smart-5d742292-7dd9-4dfa-a288-769a24613857
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273975718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2273975718
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1672401599
Short name T451
Test name
Test status
Simulation time 501742703414 ps
CPU time 2022.01 seconds
Started May 05 02:25:23 PM PDT 24
Finished May 05 02:59:05 PM PDT 24
Peak memory 288252 kb
Host smart-0cfedcd1-7b71-4de0-a82e-c166988131bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672401599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1672401599
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3828630679
Short name T552
Test name
Test status
Simulation time 5878379320 ps
CPU time 66.96 seconds
Started May 05 02:25:23 PM PDT 24
Finished May 05 02:26:30 PM PDT 24
Peak memory 256932 kb
Host smart-11811f48-c67a-46f1-ad69-03dd94df7627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38286
30679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3828630679
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1815098289
Short name T388
Test name
Test status
Simulation time 3223456561 ps
CPU time 44.33 seconds
Started May 05 02:25:24 PM PDT 24
Finished May 05 02:26:09 PM PDT 24
Peak memory 256012 kb
Host smart-63be6bfa-48a2-458b-b047-fc3d8b88a11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18150
98289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1815098289
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2312627048
Short name T319
Test name
Test status
Simulation time 699440654806 ps
CPU time 2012.55 seconds
Started May 05 02:25:28 PM PDT 24
Finished May 05 02:59:01 PM PDT 24
Peak memory 270356 kb
Host smart-b925ade6-8ee1-442c-a7ee-58aa36fcb66c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312627048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2312627048
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3074448556
Short name T578
Test name
Test status
Simulation time 188732843144 ps
CPU time 2813.66 seconds
Started May 05 02:25:29 PM PDT 24
Finished May 05 03:12:23 PM PDT 24
Peak memory 281268 kb
Host smart-eeafd0bb-2d86-436f-bbe1-f3ed85822b4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074448556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3074448556
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2588219406
Short name T315
Test name
Test status
Simulation time 70717466826 ps
CPU time 557.63 seconds
Started May 05 02:25:23 PM PDT 24
Finished May 05 02:34:41 PM PDT 24
Peak memory 248172 kb
Host smart-d55eb809-db7e-4d4a-b6cf-a32543d35181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588219406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2588219406
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2146256766
Short name T667
Test name
Test status
Simulation time 604883428 ps
CPU time 7.49 seconds
Started May 05 02:25:18 PM PDT 24
Finished May 05 02:25:26 PM PDT 24
Peak memory 248696 kb
Host smart-7a8c7cbe-d201-4604-bbd8-f26cf0a22116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
56766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2146256766
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.535000156
Short name T279
Test name
Test status
Simulation time 2370153095 ps
CPU time 35.62 seconds
Started May 05 02:25:22 PM PDT 24
Finished May 05 02:25:58 PM PDT 24
Peak memory 256004 kb
Host smart-68b97cae-a47d-413e-9999-b49cba6a6181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53500
0156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.535000156
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.413642939
Short name T541
Test name
Test status
Simulation time 7168404143 ps
CPU time 56.58 seconds
Started May 05 02:25:24 PM PDT 24
Finished May 05 02:26:21 PM PDT 24
Peak memory 247836 kb
Host smart-6fd9de04-b176-4d3e-ac96-ac5900a98651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41364
2939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.413642939
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3966244311
Short name T705
Test name
Test status
Simulation time 372995385 ps
CPU time 21.84 seconds
Started May 05 02:25:20 PM PDT 24
Finished May 05 02:25:42 PM PDT 24
Peak memory 248780 kb
Host smart-faa3c4e7-cdd3-437f-86f4-87a8fdd31791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39662
44311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3966244311
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.52695741
Short name T602
Test name
Test status
Simulation time 46388129420 ps
CPU time 1445.58 seconds
Started May 05 02:25:28 PM PDT 24
Finished May 05 02:49:34 PM PDT 24
Peak memory 270608 kb
Host smart-4cf9ffa1-9d02-4db5-a3f0-6f92b79389dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52695741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_hand
ler_stress_all.52695741
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3475586552
Short name T542
Test name
Test status
Simulation time 108972496013 ps
CPU time 1330.45 seconds
Started May 05 02:25:38 PM PDT 24
Finished May 05 02:47:49 PM PDT 24
Peak memory 281560 kb
Host smart-be22d7c3-93c4-4eb8-afa7-4400147a29c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475586552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3475586552
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2758440198
Short name T361
Test name
Test status
Simulation time 1561147320 ps
CPU time 129.44 seconds
Started May 05 02:25:37 PM PDT 24
Finished May 05 02:27:47 PM PDT 24
Peak memory 251968 kb
Host smart-a3de289d-79e6-48d0-a869-b30e396b34a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27584
40198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2758440198
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1229827550
Short name T510
Test name
Test status
Simulation time 655504175 ps
CPU time 29.47 seconds
Started May 05 02:25:38 PM PDT 24
Finished May 05 02:26:08 PM PDT 24
Peak memory 256904 kb
Host smart-78cadfc4-7dd7-4f72-8b7c-fc05fa60c80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12298
27550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1229827550
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1624468295
Short name T329
Test name
Test status
Simulation time 13121323711 ps
CPU time 1099.37 seconds
Started May 05 02:25:42 PM PDT 24
Finished May 05 02:44:01 PM PDT 24
Peak memory 281524 kb
Host smart-27d9e608-c8c7-4e26-80a3-9d2b5f622129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624468295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1624468295
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4279627307
Short name T615
Test name
Test status
Simulation time 182994341221 ps
CPU time 2129.94 seconds
Started May 05 02:25:42 PM PDT 24
Finished May 05 03:01:13 PM PDT 24
Peak memory 273388 kb
Host smart-5adb1714-9b19-49ec-acab-40fd6c5eb1bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279627307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4279627307
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2804279742
Short name T617
Test name
Test status
Simulation time 31317854618 ps
CPU time 321.43 seconds
Started May 05 02:25:43 PM PDT 24
Finished May 05 02:31:05 PM PDT 24
Peak memory 248080 kb
Host smart-f3f9511b-8ff2-4e07-abde-db8837ea878d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804279742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2804279742
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1899330619
Short name T367
Test name
Test status
Simulation time 368197212 ps
CPU time 30.9 seconds
Started May 05 02:25:38 PM PDT 24
Finished May 05 02:26:09 PM PDT 24
Peak memory 248756 kb
Host smart-1267f6b6-7061-4a3b-86db-7ed5d436d4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18993
30619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1899330619
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3738740660
Short name T526
Test name
Test status
Simulation time 265065840 ps
CPU time 15.23 seconds
Started May 05 02:25:39 PM PDT 24
Finished May 05 02:25:55 PM PDT 24
Peak memory 248704 kb
Host smart-07e202b3-d072-4885-aad8-c5dbb26dae84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37387
40660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3738740660
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.613548882
Short name T366
Test name
Test status
Simulation time 116683358 ps
CPU time 4.14 seconds
Started May 05 02:25:38 PM PDT 24
Finished May 05 02:25:43 PM PDT 24
Peak memory 239128 kb
Host smart-a01e3d81-bf9c-4841-bb2d-f63fcf8e4cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61354
8882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.613548882
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3256086077
Short name T385
Test name
Test status
Simulation time 560890760 ps
CPU time 32.14 seconds
Started May 05 02:25:32 PM PDT 24
Finished May 05 02:26:05 PM PDT 24
Peak memory 256152 kb
Host smart-3ae81738-dfad-42fa-94c5-6699a4327eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32560
86077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3256086077
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2717138942
Short name T536
Test name
Test status
Simulation time 30437393299 ps
CPU time 1190.04 seconds
Started May 05 02:25:46 PM PDT 24
Finished May 05 02:45:36 PM PDT 24
Peak memory 285916 kb
Host smart-5ebe25bc-aef1-47fe-8218-7f53c214bbe4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717138942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2717138942
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3815291779
Short name T625
Test name
Test status
Simulation time 95774195356 ps
CPU time 2257.43 seconds
Started May 05 02:25:46 PM PDT 24
Finished May 05 03:03:24 PM PDT 24
Peak memory 305224 kb
Host smart-6863d5b6-8ce2-43f6-8b36-301f5d6101ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815291779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3815291779
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1050176125
Short name T50
Test name
Test status
Simulation time 11534385993 ps
CPU time 1014.73 seconds
Started May 05 02:25:59 PM PDT 24
Finished May 05 02:42:54 PM PDT 24
Peak memory 287396 kb
Host smart-428c51c7-07cd-4001-bec3-42b02ebfa31a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050176125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1050176125
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3554954959
Short name T392
Test name
Test status
Simulation time 2147081117 ps
CPU time 148.69 seconds
Started May 05 02:25:49 PM PDT 24
Finished May 05 02:28:18 PM PDT 24
Peak memory 256888 kb
Host smart-29d6fe7e-4f87-43b5-8d35-ccd63de73844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35549
54959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3554954959
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1688927570
Short name T642
Test name
Test status
Simulation time 125207050 ps
CPU time 11.83 seconds
Started May 05 02:25:49 PM PDT 24
Finished May 05 02:26:01 PM PDT 24
Peak memory 248692 kb
Host smart-befec538-468d-4887-a0bf-62ea140b941a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16889
27570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1688927570
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3756355556
Short name T702
Test name
Test status
Simulation time 26130502385 ps
CPU time 1139.46 seconds
Started May 05 02:26:04 PM PDT 24
Finished May 05 02:45:04 PM PDT 24
Peak memory 273368 kb
Host smart-a129ba95-61ca-4805-bf58-5501d3dda254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756355556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3756355556
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2080488093
Short name T298
Test name
Test status
Simulation time 14689614882 ps
CPU time 300.68 seconds
Started May 05 02:26:01 PM PDT 24
Finished May 05 02:31:02 PM PDT 24
Peak memory 247804 kb
Host smart-ee1660cb-0060-4db9-bc79-2688d64029b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080488093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2080488093
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3771365915
Short name T485
Test name
Test status
Simulation time 4404062362 ps
CPU time 71.8 seconds
Started May 05 02:25:47 PM PDT 24
Finished May 05 02:26:59 PM PDT 24
Peak memory 255852 kb
Host smart-b0b4a86a-5ddd-4dfe-a5b4-6991357084d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
65915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3771365915
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1586506822
Short name T107
Test name
Test status
Simulation time 225551974 ps
CPU time 15.82 seconds
Started May 05 02:25:50 PM PDT 24
Finished May 05 02:26:06 PM PDT 24
Peak memory 255860 kb
Host smart-6918dd87-c600-45be-99ea-c2af6a3b31db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
06822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1586506822
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2490623074
Short name T478
Test name
Test status
Simulation time 185221204 ps
CPU time 11.69 seconds
Started May 05 02:25:55 PM PDT 24
Finished May 05 02:26:08 PM PDT 24
Peak memory 248696 kb
Host smart-b28966e6-466f-438e-8118-c11a7064138e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24906
23074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2490623074
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.446464191
Short name T600
Test name
Test status
Simulation time 762830205 ps
CPU time 38.87 seconds
Started May 05 02:25:46 PM PDT 24
Finished May 05 02:26:26 PM PDT 24
Peak memory 255520 kb
Host smart-74d57ac3-3007-47d9-be03-0fedf18a6ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44646
4191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.446464191
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3797842185
Short name T604
Test name
Test status
Simulation time 20076997116 ps
CPU time 1641.13 seconds
Started May 05 02:26:04 PM PDT 24
Finished May 05 02:53:25 PM PDT 24
Peak memory 289080 kb
Host smart-b4cd255d-5995-4a92-8161-f9e45540f2b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797842185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3797842185
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.65220259
Short name T594
Test name
Test status
Simulation time 9330233733 ps
CPU time 540.47 seconds
Started May 05 02:26:24 PM PDT 24
Finished May 05 02:35:25 PM PDT 24
Peak memory 272324 kb
Host smart-ca794a57-86d3-4f51-ab69-f1904ae52ea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65220259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.65220259
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1281584188
Short name T523
Test name
Test status
Simulation time 32589949744 ps
CPU time 190.06 seconds
Started May 05 02:26:27 PM PDT 24
Finished May 05 02:29:38 PM PDT 24
Peak memory 250224 kb
Host smart-ea0832ba-9e98-41fd-89dc-6da4e2388f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
84188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1281584188
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.831896574
Short name T522
Test name
Test status
Simulation time 237553560 ps
CPU time 19.69 seconds
Started May 05 02:26:18 PM PDT 24
Finished May 05 02:26:38 PM PDT 24
Peak memory 255696 kb
Host smart-6a3e8af1-fd7d-4343-8e0d-463bd8dd534d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83189
6574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.831896574
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1178294868
Short name T322
Test name
Test status
Simulation time 26517437760 ps
CPU time 1626.74 seconds
Started May 05 02:26:29 PM PDT 24
Finished May 05 02:53:36 PM PDT 24
Peak memory 282088 kb
Host smart-80b76bfc-e5a4-4525-afd5-afb5b10bf687
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178294868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1178294868
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4031183918
Short name T291
Test name
Test status
Simulation time 171621955615 ps
CPU time 2753.42 seconds
Started May 05 02:26:30 PM PDT 24
Finished May 05 03:12:24 PM PDT 24
Peak memory 289448 kb
Host smart-e001817b-9e00-479f-a900-7ec747362fd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031183918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4031183918
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.657476007
Short name T545
Test name
Test status
Simulation time 554643314 ps
CPU time 10.52 seconds
Started May 05 02:26:18 PM PDT 24
Finished May 05 02:26:29 PM PDT 24
Peak memory 248816 kb
Host smart-fb3476cd-1346-44ee-828d-060d319ccc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65747
6007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.657476007
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1415381239
Short name T39
Test name
Test status
Simulation time 4628329131 ps
CPU time 38.01 seconds
Started May 05 02:26:17 PM PDT 24
Finished May 05 02:26:56 PM PDT 24
Peak memory 248792 kb
Host smart-6263fe19-d9af-4606-8082-f6ee197dbf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
81239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1415381239
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3080842767
Short name T124
Test name
Test status
Simulation time 245585324 ps
CPU time 23.91 seconds
Started May 05 02:26:27 PM PDT 24
Finished May 05 02:26:52 PM PDT 24
Peak memory 248736 kb
Host smart-b139f42d-a49f-423c-aecf-cd4e1b0f0c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30808
42767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3080842767
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4227655253
Short name T62
Test name
Test status
Simulation time 133958943 ps
CPU time 8.7 seconds
Started May 05 02:26:11 PM PDT 24
Finished May 05 02:26:20 PM PDT 24
Peak memory 248700 kb
Host smart-b2dfb322-d320-40b7-9294-6d9b86101a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
55253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4227655253
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2578969242
Short name T53
Test name
Test status
Simulation time 42180235449 ps
CPU time 2275.94 seconds
Started May 05 02:26:30 PM PDT 24
Finished May 05 03:04:27 PM PDT 24
Peak memory 284780 kb
Host smart-90056d5c-2037-4d1f-9492-915aad89f5c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578969242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2578969242
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2356133261
Short name T132
Test name
Test status
Simulation time 196732922892 ps
CPU time 2650.58 seconds
Started May 05 02:26:39 PM PDT 24
Finished May 05 03:10:50 PM PDT 24
Peak memory 281540 kb
Host smart-d8cd915d-778d-4cb6-a622-26d394daa095
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356133261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2356133261
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2265765482
Short name T649
Test name
Test status
Simulation time 348540337 ps
CPU time 29.29 seconds
Started May 05 02:26:42 PM PDT 24
Finished May 05 02:27:12 PM PDT 24
Peak memory 255948 kb
Host smart-d1008da8-e1d7-4b15-a8d4-11c4721d0f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22657
65482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2265765482
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.595818623
Short name T418
Test name
Test status
Simulation time 1835294926 ps
CPU time 24.99 seconds
Started May 05 02:26:39 PM PDT 24
Finished May 05 02:27:05 PM PDT 24
Peak memory 248748 kb
Host smart-b332582b-666b-4002-9d84-b657e543b8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59581
8623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.595818623
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2644601414
Short name T7
Test name
Test status
Simulation time 9707527852 ps
CPU time 937.71 seconds
Started May 05 02:26:44 PM PDT 24
Finished May 05 02:42:22 PM PDT 24
Peak memory 268252 kb
Host smart-36b7bdc5-2d16-4cf1-bc91-d258a6a986de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644601414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2644601414
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3546083612
Short name T709
Test name
Test status
Simulation time 12848884932 ps
CPU time 1267.34 seconds
Started May 05 02:26:45 PM PDT 24
Finished May 05 02:47:53 PM PDT 24
Peak memory 281576 kb
Host smart-b02261e8-cf43-43ad-a99a-b6ada5e5ea2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546083612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3546083612
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2798662544
Short name T555
Test name
Test status
Simulation time 15817427807 ps
CPU time 654.95 seconds
Started May 05 02:26:42 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 247868 kb
Host smart-7c7c39e9-a0b7-40d2-a49e-02855c4a8bcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798662544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2798662544
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1826956500
Short name T431
Test name
Test status
Simulation time 53945742 ps
CPU time 4.56 seconds
Started May 05 02:26:41 PM PDT 24
Finished May 05 02:26:46 PM PDT 24
Peak memory 240544 kb
Host smart-a9521bf2-26ef-4605-bb65-20238e53f6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18269
56500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1826956500
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3645463955
Short name T453
Test name
Test status
Simulation time 1601023633 ps
CPU time 33.41 seconds
Started May 05 02:26:39 PM PDT 24
Finished May 05 02:27:13 PM PDT 24
Peak memory 248692 kb
Host smart-cb3c4ee6-693a-4385-ad47-6004e53dad19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
63955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3645463955
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3875631643
Short name T560
Test name
Test status
Simulation time 881664293 ps
CPU time 26.02 seconds
Started May 05 02:26:42 PM PDT 24
Finished May 05 02:27:08 PM PDT 24
Peak memory 248736 kb
Host smart-b3d6d94b-8383-41cd-bfe8-fafd138d1e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756
31643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3875631643
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.399192463
Short name T352
Test name
Test status
Simulation time 952545447 ps
CPU time 56.02 seconds
Started May 05 02:26:36 PM PDT 24
Finished May 05 02:27:32 PM PDT 24
Peak memory 248680 kb
Host smart-393a61d7-0163-40a2-b944-7ea7e343bfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39919
2463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.399192463
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1653456658
Short name T572
Test name
Test status
Simulation time 103388242011 ps
CPU time 1674.08 seconds
Started May 05 02:26:44 PM PDT 24
Finished May 05 02:54:39 PM PDT 24
Peak memory 282576 kb
Host smart-a6474888-931b-464b-be33-d381895013fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653456658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1653456658
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.810753198
Short name T596
Test name
Test status
Simulation time 53700336177 ps
CPU time 3507.66 seconds
Started May 05 02:26:52 PM PDT 24
Finished May 05 03:25:21 PM PDT 24
Peak memory 306208 kb
Host smart-7b5088ff-0066-4b23-addd-8e91c6e402de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810753198 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.810753198
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1833634781
Short name T237
Test name
Test status
Simulation time 212590424 ps
CPU time 3.95 seconds
Started May 05 02:18:45 PM PDT 24
Finished May 05 02:18:50 PM PDT 24
Peak memory 248916 kb
Host smart-e2dfce8b-039e-4150-a3e4-3b7f4df99a22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1833634781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1833634781
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2503539442
Short name T534
Test name
Test status
Simulation time 45858938429 ps
CPU time 653.7 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:29:38 PM PDT 24
Peak memory 273096 kb
Host smart-162f30df-3151-4556-8c90-aff6cdc11b22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503539442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2503539442
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1652841286
Short name T413
Test name
Test status
Simulation time 208419910 ps
CPU time 10.78 seconds
Started May 05 02:18:47 PM PDT 24
Finished May 05 02:18:59 PM PDT 24
Peak memory 240532 kb
Host smart-56b59759-94b6-4ddd-9212-639d0e71a6ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1652841286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1652841286
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1761147870
Short name T64
Test name
Test status
Simulation time 12591111442 ps
CPU time 157.25 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:21:20 PM PDT 24
Peak memory 250432 kb
Host smart-48281b74-1476-4178-be17-ea64a22d1515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17611
47870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1761147870
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3937592250
Short name T89
Test name
Test status
Simulation time 4361074819 ps
CPU time 59.49 seconds
Started May 05 02:18:45 PM PDT 24
Finished May 05 02:19:45 PM PDT 24
Peak memory 249076 kb
Host smart-25bf1dc1-ce52-4290-95df-f5a32dde998a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375
92250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3937592250
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.324743829
Short name T538
Test name
Test status
Simulation time 116268748954 ps
CPU time 3250.76 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 03:12:55 PM PDT 24
Peak memory 288024 kb
Host smart-27d8850a-12e4-4193-89cb-4621dca9aa24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324743829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.324743829
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.711541912
Short name T665
Test name
Test status
Simulation time 20644435131 ps
CPU time 1124.42 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:37:29 PM PDT 24
Peak memory 288808 kb
Host smart-ebc17892-df37-40c4-8283-82052a5c80a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711541912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.711541912
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3861831292
Short name T704
Test name
Test status
Simulation time 8677809045 ps
CPU time 95.88 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:20:19 PM PDT 24
Peak memory 247956 kb
Host smart-e5de4804-0759-40cd-8ca8-27e51f1ab1c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861831292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3861831292
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2238047123
Short name T131
Test name
Test status
Simulation time 2814251569 ps
CPU time 27.74 seconds
Started May 05 02:18:41 PM PDT 24
Finished May 05 02:19:09 PM PDT 24
Peak memory 248816 kb
Host smart-a57dbbd5-1a1e-483d-a108-40a1689b864a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
47123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2238047123
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3193516465
Short name T45
Test name
Test status
Simulation time 1416619705 ps
CPU time 44.37 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:19:29 PM PDT 24
Peak memory 248780 kb
Host smart-864147e8-04f8-4186-b681-407251efe45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
16465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3193516465
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1721252145
Short name T593
Test name
Test status
Simulation time 48863756 ps
CPU time 6.76 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:18:51 PM PDT 24
Peak memory 251888 kb
Host smart-91d83c8f-51dd-48b1-9738-dc6f1a346577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17212
52145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1721252145
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3255884858
Short name T438
Test name
Test status
Simulation time 3369115458 ps
CPU time 45.14 seconds
Started May 05 02:18:41 PM PDT 24
Finished May 05 02:19:27 PM PDT 24
Peak memory 248796 kb
Host smart-ea305fa8-286c-41cc-8644-470e53b6057c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32558
84858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3255884858
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2644966606
Short name T475
Test name
Test status
Simulation time 65529070296 ps
CPU time 1858.83 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:49:43 PM PDT 24
Peak memory 286204 kb
Host smart-e4244367-c410-46b0-8a72-f5d226d98bff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644966606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2644966606
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.736946826
Short name T227
Test name
Test status
Simulation time 34508272 ps
CPU time 2.62 seconds
Started May 05 02:18:49 PM PDT 24
Finished May 05 02:18:52 PM PDT 24
Peak memory 248984 kb
Host smart-ce0f1963-615c-4971-8eb1-45586b06aab1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=736946826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.736946826
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1602383051
Short name T546
Test name
Test status
Simulation time 164647670030 ps
CPU time 2338.66 seconds
Started May 05 02:18:51 PM PDT 24
Finished May 05 02:57:51 PM PDT 24
Peak memory 286024 kb
Host smart-25cc7817-01b4-47e1-88d7-ef14e03a43aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602383051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1602383051
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2037390144
Short name T14
Test name
Test status
Simulation time 994385833 ps
CPU time 14.01 seconds
Started May 05 02:18:49 PM PDT 24
Finished May 05 02:19:03 PM PDT 24
Peak memory 240532 kb
Host smart-1e3feeb7-6798-46a6-82bc-93dd71031276
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2037390144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2037390144
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2829604638
Short name T251
Test name
Test status
Simulation time 7822407289 ps
CPU time 169.44 seconds
Started May 05 02:18:46 PM PDT 24
Finished May 05 02:21:36 PM PDT 24
Peak memory 250852 kb
Host smart-2bc5af88-cf36-4aa1-9876-c6b6c282e724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28296
04638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2829604638
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.740363989
Short name T503
Test name
Test status
Simulation time 107233713 ps
CPU time 9.23 seconds
Started May 05 02:18:46 PM PDT 24
Finished May 05 02:18:55 PM PDT 24
Peak memory 248736 kb
Host smart-37f17b85-22d7-4700-bbd4-4620065e1d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74036
3989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.740363989
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.555943678
Short name T432
Test name
Test status
Simulation time 35652494682 ps
CPU time 2131.71 seconds
Started May 05 02:18:47 PM PDT 24
Finished May 05 02:54:20 PM PDT 24
Peak memory 288288 kb
Host smart-ae189e1d-e5ed-48b6-8274-ef4acfc2c71b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555943678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.555943678
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2553775017
Short name T671
Test name
Test status
Simulation time 101984767 ps
CPU time 7.28 seconds
Started May 05 02:18:43 PM PDT 24
Finished May 05 02:18:51 PM PDT 24
Peak memory 248716 kb
Host smart-89f8b5c0-96c5-4934-b337-2bae97ba0dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25537
75017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2553775017
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1911316727
Short name T544
Test name
Test status
Simulation time 642651361 ps
CPU time 13.8 seconds
Started May 05 02:18:42 PM PDT 24
Finished May 05 02:18:57 PM PDT 24
Peak memory 248836 kb
Host smart-b71ee407-1c86-4fae-ab3a-5111f945de56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19113
16727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1911316727
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.318196235
Short name T410
Test name
Test status
Simulation time 74554636 ps
CPU time 6.43 seconds
Started May 05 02:18:50 PM PDT 24
Finished May 05 02:18:56 PM PDT 24
Peak memory 247376 kb
Host smart-603cae15-2f8c-4b8a-bb4e-0e2e47725e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819
6235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.318196235
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2642705496
Short name T517
Test name
Test status
Simulation time 2637151507 ps
CPU time 24.7 seconds
Started May 05 02:18:47 PM PDT 24
Finished May 05 02:19:13 PM PDT 24
Peak memory 256312 kb
Host smart-e63b4480-5313-4177-9d95-39c4f87fc558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26427
05496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2642705496
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2988302816
Short name T242
Test name
Test status
Simulation time 23801945 ps
CPU time 2.67 seconds
Started May 05 02:18:53 PM PDT 24
Finished May 05 02:18:56 PM PDT 24
Peak memory 248924 kb
Host smart-8ed9f50b-1e93-4310-9b7e-60d3fffd0e6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2988302816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2988302816
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3955701701
Short name T558
Test name
Test status
Simulation time 32604237065 ps
CPU time 1715.79 seconds
Started May 05 02:18:46 PM PDT 24
Finished May 05 02:47:23 PM PDT 24
Peak memory 283132 kb
Host smart-269c7dc3-4c1c-4252-ab2d-c4cfa10b5789
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955701701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3955701701
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.131655824
Short name T120
Test name
Test status
Simulation time 1499769087 ps
CPU time 17.9 seconds
Started May 05 02:18:52 PM PDT 24
Finished May 05 02:19:10 PM PDT 24
Peak memory 248704 kb
Host smart-1d361e06-28dc-4cdf-b1f4-1c92a2e67c0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=131655824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.131655824
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3678728613
Short name T443
Test name
Test status
Simulation time 26899930089 ps
CPU time 210.97 seconds
Started May 05 02:18:45 PM PDT 24
Finished May 05 02:22:17 PM PDT 24
Peak memory 251832 kb
Host smart-14f7bd33-18d7-469b-b810-118ec5988ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
28613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3678728613
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2132133929
Short name T504
Test name
Test status
Simulation time 2159234849 ps
CPU time 29.69 seconds
Started May 05 02:18:49 PM PDT 24
Finished May 05 02:19:19 PM PDT 24
Peak memory 254908 kb
Host smart-f100de7e-cd50-4bcb-bb36-8a9808ac3256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21321
33929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2132133929
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3409448798
Short name T547
Test name
Test status
Simulation time 35673553570 ps
CPU time 713.53 seconds
Started May 05 02:18:51 PM PDT 24
Finished May 05 02:30:45 PM PDT 24
Peak memory 265312 kb
Host smart-de4815b7-1715-46d5-a479-dd88e31e6776
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409448798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3409448798
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3754158587
Short name T435
Test name
Test status
Simulation time 167715919882 ps
CPU time 2108.25 seconds
Started May 05 02:18:53 PM PDT 24
Finished May 05 02:54:02 PM PDT 24
Peak memory 273356 kb
Host smart-feacd881-c03e-4ad3-9a56-1cf65655faea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754158587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3754158587
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3242519962
Short name T525
Test name
Test status
Simulation time 61730117224 ps
CPU time 584.76 seconds
Started May 05 02:18:53 PM PDT 24
Finished May 05 02:28:38 PM PDT 24
Peak memory 247040 kb
Host smart-e6820d84-021a-43d3-a2a5-1be3bbb5fd36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242519962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3242519962
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3104582446
Short name T357
Test name
Test status
Simulation time 667678259 ps
CPU time 32.7 seconds
Started May 05 02:18:46 PM PDT 24
Finished May 05 02:19:20 PM PDT 24
Peak memory 255932 kb
Host smart-8f8c6bfb-907d-49e0-a1b6-224cd6ea8010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31045
82446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3104582446
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3825148433
Short name T583
Test name
Test status
Simulation time 55044083 ps
CPU time 5.26 seconds
Started May 05 02:18:47 PM PDT 24
Finished May 05 02:18:53 PM PDT 24
Peak memory 240644 kb
Host smart-3ec1d9e7-7248-412f-ae30-edf3b18049fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38251
48433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3825148433
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1383005856
Short name T259
Test name
Test status
Simulation time 2910622067 ps
CPU time 48.47 seconds
Started May 05 02:18:48 PM PDT 24
Finished May 05 02:19:37 PM PDT 24
Peak memory 256288 kb
Host smart-effeb79e-5cd8-4b56-a56f-72a0a919922b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13830
05856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1383005856
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.4109502033
Short name T680
Test name
Test status
Simulation time 679833172 ps
CPU time 18.31 seconds
Started May 05 02:18:51 PM PDT 24
Finished May 05 02:19:10 PM PDT 24
Peak memory 248732 kb
Host smart-b00396bd-3e12-46e4-824b-645182afe7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095
02033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.4109502033
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.955807943
Short name T226
Test name
Test status
Simulation time 75594462 ps
CPU time 3.11 seconds
Started May 05 02:18:57 PM PDT 24
Finished May 05 02:19:01 PM PDT 24
Peak memory 248888 kb
Host smart-ffe6e91f-bc94-4df2-9d75-89596fe49540
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=955807943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.955807943
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.4140815395
Short name T554
Test name
Test status
Simulation time 47374857475 ps
CPU time 1511.98 seconds
Started May 05 02:18:58 PM PDT 24
Finished May 05 02:44:11 PM PDT 24
Peak memory 273388 kb
Host smart-707cac25-d1f5-46a9-ad2e-cefec7df6de1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140815395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4140815395
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.648060160
Short name T368
Test name
Test status
Simulation time 706002336 ps
CPU time 9.81 seconds
Started May 05 02:18:55 PM PDT 24
Finished May 05 02:19:06 PM PDT 24
Peak memory 248144 kb
Host smart-bd9dc545-c154-4473-b4a4-0d49dacfb05c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=648060160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.648060160
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2080029779
Short name T647
Test name
Test status
Simulation time 13783610915 ps
CPU time 64.18 seconds
Started May 05 02:18:54 PM PDT 24
Finished May 05 02:19:58 PM PDT 24
Peak memory 256064 kb
Host smart-7a87cbcc-ec52-46d5-9ac7-d78062a6f97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
29779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2080029779
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2781568476
Short name T698
Test name
Test status
Simulation time 848063988 ps
CPU time 33.75 seconds
Started May 05 02:18:52 PM PDT 24
Finished May 05 02:19:26 PM PDT 24
Peak memory 256024 kb
Host smart-77c68269-b1b9-4fda-b2dc-8fad93a2f062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27815
68476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2781568476
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.976193313
Short name T330
Test name
Test status
Simulation time 139096902529 ps
CPU time 1777.19 seconds
Started May 05 02:18:57 PM PDT 24
Finished May 05 02:48:35 PM PDT 24
Peak memory 272940 kb
Host smart-7803b884-97cd-4cd5-943b-a8614e5d64b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976193313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.976193313
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.451914225
Short name T370
Test name
Test status
Simulation time 71241856758 ps
CPU time 2061.74 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:53:18 PM PDT 24
Peak memory 284628 kb
Host smart-60fd9015-d06a-4c39-9147-de9f236f3d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451914225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.451914225
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1179745633
Short name T590
Test name
Test status
Simulation time 5450096544 ps
CPU time 131.8 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:21:08 PM PDT 24
Peak memory 253656 kb
Host smart-a158b1bc-fd1f-40ef-baf6-18fc8a9b8ec7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179745633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1179745633
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3259390711
Short name T424
Test name
Test status
Simulation time 726944437 ps
CPU time 32.03 seconds
Started May 05 02:18:50 PM PDT 24
Finished May 05 02:19:22 PM PDT 24
Peak memory 248704 kb
Host smart-7aa5d249-17f4-46fc-a774-2c7dffb4e494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
90711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3259390711
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.939402859
Short name T271
Test name
Test status
Simulation time 1093980144 ps
CPU time 57.12 seconds
Started May 05 02:18:50 PM PDT 24
Finished May 05 02:19:48 PM PDT 24
Peak memory 248760 kb
Host smart-bd37b080-cc22-4f47-87c6-d7dda840cf74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93940
2859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.939402859
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3578764388
Short name T468
Test name
Test status
Simulation time 486870902 ps
CPU time 29.62 seconds
Started May 05 02:18:57 PM PDT 24
Finished May 05 02:19:26 PM PDT 24
Peak memory 248952 kb
Host smart-200cb312-c285-4e25-bf8a-2806c54d3281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35787
64388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3578764388
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.615942477
Short name T355
Test name
Test status
Simulation time 1134977254 ps
CPU time 21.29 seconds
Started May 05 02:18:53 PM PDT 24
Finished May 05 02:19:14 PM PDT 24
Peak memory 255964 kb
Host smart-41544e9c-274b-4d09-beb0-a97dcace69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61594
2477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.615942477
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3090130481
Short name T83
Test name
Test status
Simulation time 38291433626 ps
CPU time 2044.22 seconds
Started May 05 02:18:54 PM PDT 24
Finished May 05 02:52:59 PM PDT 24
Peak memory 283604 kb
Host smart-ff78c936-d949-40b6-96ed-34a92b19e5c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090130481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3090130481
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3997882495
Short name T241
Test name
Test status
Simulation time 74246866 ps
CPU time 2.41 seconds
Started May 05 02:18:55 PM PDT 24
Finished May 05 02:18:58 PM PDT 24
Peak memory 248944 kb
Host smart-28539936-9a0a-48ea-8cb6-94b8f4ead4ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3997882495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3997882495
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1206109097
Short name T207
Test name
Test status
Simulation time 22080253844 ps
CPU time 1393.96 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:42:10 PM PDT 24
Peak memory 271420 kb
Host smart-975a556a-d60c-43c7-bf89-5e3b1ed04c7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206109097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1206109097
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2572965135
Short name T576
Test name
Test status
Simulation time 499338939 ps
CPU time 22.74 seconds
Started May 05 02:18:55 PM PDT 24
Finished May 05 02:19:19 PM PDT 24
Peak memory 248760 kb
Host smart-a0c147a6-1a10-4c96-aec4-3496a416251d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2572965135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2572965135
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4164505140
Short name T122
Test name
Test status
Simulation time 8711575776 ps
CPU time 119.69 seconds
Started May 05 02:19:00 PM PDT 24
Finished May 05 02:21:00 PM PDT 24
Peak memory 256896 kb
Host smart-967c9909-e6ad-4193-b2c1-875d7ce78238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41645
05140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4164505140
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3159795294
Short name T423
Test name
Test status
Simulation time 1199891136 ps
CPU time 14.05 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:19:11 PM PDT 24
Peak memory 253092 kb
Host smart-14ff200a-95d5-4228-8324-2a932d1092b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597
95294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3159795294
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3928496835
Short name T314
Test name
Test status
Simulation time 58132352513 ps
CPU time 968.79 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:35:05 PM PDT 24
Peak memory 282764 kb
Host smart-6226ee42-6ecd-428a-b113-be6792fdb816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928496835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3928496835
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2737382738
Short name T620
Test name
Test status
Simulation time 99453115023 ps
CPU time 1616.95 seconds
Started May 05 02:18:57 PM PDT 24
Finished May 05 02:45:55 PM PDT 24
Peak memory 273372 kb
Host smart-ee3416b7-5f75-4131-86be-088351a5d79d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737382738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2737382738
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1377398622
Short name T303
Test name
Test status
Simulation time 30578757547 ps
CPU time 255.91 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:23:12 PM PDT 24
Peak memory 248104 kb
Host smart-d03b167b-a4a8-4b54-b440-37a3a925d1d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377398622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1377398622
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2297251038
Short name T119
Test name
Test status
Simulation time 251338156 ps
CPU time 18.44 seconds
Started May 05 02:19:00 PM PDT 24
Finished May 05 02:19:19 PM PDT 24
Peak memory 248676 kb
Host smart-725b2c35-2710-4b30-baf9-af9f82999417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22972
51038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2297251038
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1260882650
Short name T292
Test name
Test status
Simulation time 2014281871 ps
CPU time 21.78 seconds
Started May 05 02:18:59 PM PDT 24
Finished May 05 02:19:21 PM PDT 24
Peak memory 248680 kb
Host smart-1163a291-13c8-49af-9713-0d2a194a6441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12608
82650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1260882650
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.694137400
Short name T135
Test name
Test status
Simulation time 1941383418 ps
CPU time 35.8 seconds
Started May 05 02:18:55 PM PDT 24
Finished May 05 02:19:32 PM PDT 24
Peak memory 254936 kb
Host smart-b740af70-9cd8-4015-b5ff-50e20069b09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69413
7400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.694137400
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2188861000
Short name T530
Test name
Test status
Simulation time 281955922 ps
CPU time 19.89 seconds
Started May 05 02:18:56 PM PDT 24
Finished May 05 02:19:16 PM PDT 24
Peak memory 248752 kb
Host smart-667467f7-9186-4eee-a0d8-d7aa912ae1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21888
61000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2188861000
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.960853691
Short name T358
Test name
Test status
Simulation time 298387235 ps
CPU time 29.21 seconds
Started May 05 02:18:57 PM PDT 24
Finished May 05 02:19:27 PM PDT 24
Peak memory 256920 kb
Host smart-31b5ad7b-ae77-43c2-adc8-89b7500b6a79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960853691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.960853691
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1705997994
Short name T566
Test name
Test status
Simulation time 187790189206 ps
CPU time 2723.65 seconds
Started May 05 02:19:00 PM PDT 24
Finished May 05 03:04:25 PM PDT 24
Peak memory 285976 kb
Host smart-ca19ff23-4300-41a5-9ee3-5ce845f8eb89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705997994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1705997994
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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