Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	88838	1			T1	34		T4	5		T5	8
class_i[0x1]	56735	1			T4	2		T19	5		T7	294
class_i[0x2]	75692	1			T1	42		T19	10		T7	1
class_i[0x3]	69170	1			T2	5		T4	1		T18	88

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	70570	1			T1	4		T2	2		T4	3
alert[0x1]	70533	1			T1	14		T2	1		T18	29
alert[0x2]	73064	1			T1	11		T2	1		T4	3
alert[0x3]	76268	1			T1	47		T2	1		T4	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

290199

1

T1

76

T4

5

T18

88

esc_ping_fail

236

1

T2

5

T4

3

T5

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	70493	1			T1	4		T4	2		T18	29
esc_integrity_fail	alert[0x1]	70477	1			T1	14		T18	29		T5	2
esc_integrity_fail	alert[0x2]	73011	1			T1	11		T4	2		T18	22
esc_integrity_fail	alert[0x3]	76218	1			T1	47		T4	1		T18	8
esc_ping_fail	alert[0x0]	77	1			T2	2		T4	1		T5	3
esc_ping_fail	alert[0x1]	56	1			T2	1		T5	1		T118	1
esc_ping_fail	alert[0x2]	53	1			T2	1		T4	1		T5	1
esc_ping_fail	alert[0x3]	50	1			T2	1		T4	1		T5	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	88772	1			T1	34		T4	5		T19	7
esc_integrity_fail	class_i[0x1]	56686	1			T19	5		T7	294		T23	247
esc_integrity_fail	class_i[0x2]	75653	1			T1	42		T19	10		T7	1
esc_integrity_fail	class_i[0x3]	69088	1			T18	88		T5	16		T19	17
esc_ping_fail	class_i[0x0]	66	1			T5	8		T118	4		T129	4
esc_ping_fail	class_i[0x1]	49	1			T4	2		T321	4		T34	1
esc_ping_fail	class_i[0x2]	39	1			T129	3		T37	2		T40	5
esc_ping_fail	class_i[0x3]	82	1			T2	5		T4	1		T318	10