Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	72	1			T1	2		T79	1		T24	2
class_index[0x1]	63	1			T24	1		T20	3		T27	2
class_index[0x2]	75	1			T18	1		T24	2		T20	6
class_index[0x3]	68	1			T1	1		T19	1		T7	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	106	1			T7	1		T23	4		T79	1
intr_timeout_cnt[1]	59	1			T18	1		T7	2		T82	1
intr_timeout_cnt[2]	32	1			T67	2		T24	3		T20	2
intr_timeout_cnt[3]	26	1			T1	3		T24	1		T27	2
intr_timeout_cnt[4]	17	1			T19	1		T20	1		T39	1
intr_timeout_cnt[5]	17	1			T27	1		T102	1		T279	1
intr_timeout_cnt[6]	9	1			T280	1		T59	1		T281	1
intr_timeout_cnt[7]	4	1			T89	1		T281	1		T213	1
intr_timeout_cnt[8]	5	1			T109	1		T219	1		T282	1
intr_timeout_cnt[9]	3	1			T102	1		T109	1		T283	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	28	1			T79	1		T24	1		T48	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T20	1		T39	1		T88	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T24	1		T93	1		T261	1
class_index[0x0]	intr_timeout_cnt[3]	9	1			T1	2		T27	1		T284	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T283	1		T285	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	10	1			T27	1		T102	1		T279	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T59	1		T286	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T89	1		T213	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T109	1		T287	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	25	1			T20	1		T27	1		T85	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T53	1		T87	1		T93	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T20	2		T114	1		T221	1
class_index[0x1]	intr_timeout_cnt[3]	8	1			T24	1		T27	1		T89	2
class_index[0x1]	intr_timeout_cnt[4]	1	1			T288	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	4	1			T289	1		T290	1		T291	2
class_index[0x1]	intr_timeout_cnt[6]	4	1			T281	1		T63	1		T292	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T283	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	26	1			T48	1		T27	1		T84	1
class_index[0x2]	intr_timeout_cnt[1]	18	1			T18	1		T20	5		T91	2
class_index[0x2]	intr_timeout_cnt[2]	13	1			T24	2		T86	1		T280	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T288	1		T293	1		T294	1
class_index[0x2]	intr_timeout_cnt[4]	8	1			T20	1		T39	1		T109	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T196	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T280	1		T62	1		T295	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T281	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T219	1		T282	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	27	1			T7	1		T23	4		T84	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T7	2		T82	1		T21	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T67	2		T27	1		T296	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T1	1		T92	1		T59	1
class_index[0x3]	intr_timeout_cnt[4]	6	1			T19	1		T297	1		T114	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T298	1		T283	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T299	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T300	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T102	1		T109	1		-	-