Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	393346	1			T1	99		T2	21		T3	953
all_values[1]	393346	1			T1	99		T2	21		T3	953
all_values[2]	393346	1			T1	99		T2	21		T3	953
all_values[3]	393346	1			T1	99		T2	21		T3	953

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

781654

1

T1

182

T3

1871

T15

364

auto[1]

791730

1

T1

214

T2

84

T3

1941

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

932721

1

T1

239

T2

74

T3

3349

auto[1]

640663

1

T1

157

T2

10

T3

463

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	111269	1			T1	28		T3	454		T15	49
all_values[0]	auto[0]	auto[1]	84209	1			T1	19		T3	2		T15	49
all_values[0]	auto[1]	auto[0]	112964	1			T1	27		T2	16		T3	497
all_values[0]	auto[1]	auto[1]	84904	1			T1	25		T2	5		T15	45
all_values[1]	auto[0]	auto[0]	117913	1			T1	28		T3	373		T15	47
all_values[1]	auto[0]	auto[1]	77764	1			T1	12		T3	104		T15	44
all_values[1]	auto[1]	auto[0]	119537	1			T1	35		T2	21		T3	349
all_values[1]	auto[1]	auto[1]	78132	1			T1	24		T3	127		T15	49
all_values[2]	auto[0]	auto[0]	116624	1			T1	32		T3	475		T15	47
all_values[2]	auto[0]	auto[1]	78823	1			T1	15		T3	1		T15	46
all_values[2]	auto[1]	auto[0]	118624	1			T1	29		T2	21		T3	477
all_values[2]	auto[1]	auto[1]	79275	1			T1	23		T15	48		T16	22
all_values[3]	auto[0]	auto[0]	116636	1			T1	29		T3	350		T15	41
all_values[3]	auto[0]	auto[1]	78416	1			T1	19		T3	112		T15	41
all_values[3]	auto[1]	auto[0]	119154	1			T1	31		T2	16		T3	374
all_values[3]	auto[1]	auto[1]	79140	1			T1	20		T2	5		T3	117