Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	393346	1			T1	99		T2	21		T3	953
all_pins[1]	393346	1			T1	99		T2	21		T3	953
all_pins[2]	393346	1			T1	99		T2	21		T3	953
all_pins[3]	393346	1			T1	99		T2	21		T3	953

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1251933	1			T1	304		T2	74		T3	3568
values[0x1]	321451	1			T1	92		T2	10		T3	244
transitions[0x0=>0x1]	213058	1			T1	56		T2	9		T3	244
transitions[0x1=>0x0]	213325	1			T1	57		T2	10		T3	244

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	308442	1			T1	74		T2	16		T3	953
all_pins[0]	values[0x1]	84904	1			T1	25		T2	5		T15	45
all_pins[0]	transitions[0x0=>0x1]	84140	1			T1	23		T2	4		T15	44
all_pins[0]	transitions[0x1=>0x0]	78643	1			T1	19		T2	5		T3	117
all_pins[1]	values[0x0]	315214	1			T1	75		T2	21		T3	826
all_pins[1]	values[0x1]	78132	1			T1	24		T3	127		T15	49
all_pins[1]	transitions[0x0=>0x1]	42303	1			T1	13		T3	127		T15	25
all_pins[1]	transitions[0x1=>0x0]	49075	1			T1	14		T2	5		T15	21
all_pins[2]	values[0x0]	314071	1			T1	76		T2	21		T3	953
all_pins[2]	values[0x1]	79275	1			T1	23		T15	48		T16	22
all_pins[2]	transitions[0x0=>0x1]	43691	1			T1	11		T15	21		T16	12
all_pins[2]	transitions[0x1=>0x0]	42548	1			T1	12		T3	127		T15	22
all_pins[3]	values[0x0]	314206	1			T1	79		T2	16		T3	836
all_pins[3]	values[0x1]	79140	1			T1	20		T2	5		T3	117
all_pins[3]	transitions[0x0=>0x1]	42924	1			T1	9		T2	5		T3	117
all_pins[3]	transitions[0x1=>0x0]	43059	1			T1	12		T15	20		T16	12