Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T174	7		T175	7		T176	4
all_values[1]	272	1			T174	7		T175	7		T176	4
all_values[2]	272	1			T174	7		T175	7		T176	4
all_values[3]	272	1			T174	7		T175	7		T176	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T174

16

T175

19

T176

9

auto[1]

458

1

T174

12

T175

9

T176

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

393

1

T174

9

T175

13

T176

7

auto[1]

695

1

T174

19

T175

15

T176

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T174

13

T175

17

T176

10

auto[1]

468

1

T174

15

T175

11

T176

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

56

1

T175

1

T276

3

T364

2

all_values[0]

auto[0]

auto[0]

auto[1]

33

1

T174

1

T176

1

T365

2

all_values[0]

auto[0]

auto[1]

auto[0]

38

1

T174

3

T175

1

T276

1

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T174

1

T176

1

T366

2

all_values[0]

auto[1]

auto[0]

auto[1]

76

1

T174

1

T175

4

T176

2

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T174

1

T175

1

T367

1

all_values[1]

auto[0]

auto[0]

auto[0]

55

1

T174

3

T175

2

T176

1

all_values[1]

auto[0]

auto[0]

auto[1]

43

1

T175

2

T365

1

T368

1

all_values[1]

auto[0]

auto[1]

auto[0]

33

1

T365

1

T367

1

T369

1

all_values[1]

auto[0]

auto[1]

auto[1]

25

1

T175

1

T176

1

T276

2

all_values[1]

auto[1]

auto[0]

auto[1]

76

1

T174

4

T175

1

T176

1

all_values[1]

auto[1]

auto[1]

auto[1]

40

1

T175

1

T176

1

T276

1

all_values[2]

auto[0]

auto[0]

auto[0]

63

1

T174

1

T175

6

T176

1

all_values[2]

auto[0]

auto[0]

auto[1]

22

1

T276

1

T365

1

T370

1

all_values[2]

auto[0]

auto[1]

auto[0]

45

1

T174

1

T176

2

T365

1

all_values[2]

auto[0]

auto[1]

auto[1]

22

1

T174

1

T365

1

T368

2

all_values[2]

auto[1]

auto[0]

auto[1]

65

1

T174

1

T176

1

T276

2

all_values[2]

auto[1]

auto[1]

auto[1]

55

1

T174

3

T175

1

T365

1

all_values[3]

auto[0]

auto[0]

auto[0]

55

1

T174

1

T175

1

T176

1

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T174

1

T175

1

T365

2

all_values[3]

auto[0]

auto[1]

auto[0]

48

1

T175

2

T176

2

T276

1

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T371

1

T372

1

T369

1

all_values[3]

auto[1]

auto[0]

auto[1]

57

1

T174

3

T175

1

T176

1

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T174

2

T175

2

T365

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal