Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	92252	1			T7	103		T12	612		T13	1347
accum_cnt_1000	248457	1			T15	155		T6	1159		T19	70
accum_cnt_100	29780	1			T15	54		T6	171		T19	52
accum_cnt_50	78608	1			T1	77		T15	138		T18	8
accum_cnt_10	205572	1			T1	84		T2	15		T3	2
accum_cnt_0	452486	1			T1	179		T2	45		T3	2870

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	290441	1			T1	85		T2	15		T3	718
class_index[0x1]	290441	1			T1	85		T2	15		T3	718
class_index[0x2]	290441	1			T1	85		T2	15		T3	718
class_index[0x3]	290441	1			T1	85		T2	15		T3	718

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25721	1			T13	663		T42	539		T74	686
class_index[0x0]	accum_cnt_1000	65973	1			T15	63		T19	34		T7	325
class_index[0x0]	accum_cnt_100	8364	1			T15	14		T19	29		T7	59
class_index[0x0]	accum_cnt_50	23551	1			T15	12		T5	24		T19	60
class_index[0x0]	accum_cnt_10	59275	1			T1	20		T2	15		T3	2
class_index[0x0]	accum_cnt_0	89094	1			T1	65		T3	716		T16	65
class_index[0x1]	accum_cnt_2000	24197	1			T12	612		T14	540		T23	172
class_index[0x1]	accum_cnt_1000	61292	1			T7	170		T11	773		T12	546
class_index[0x1]	accum_cnt_100	8823	1			T7	39		T11	130		T12	33
class_index[0x1]	accum_cnt_50	12805	1			T1	38		T15	87		T19	52
class_index[0x1]	accum_cnt_10	48435	1			T1	23		T15	7		T16	63
class_index[0x1]	accum_cnt_0	124636	1			T1	24		T2	15		T3	718
class_index[0x2]	accum_cnt_2000	21810	1			T23	441		T43	304		T24	1
class_index[0x2]	accum_cnt_1000	60182	1			T15	53		T6	1159		T7	295
class_index[0x2]	accum_cnt_100	6098	1			T15	15		T6	171		T19	2
class_index[0x2]	accum_cnt_50	19814	1			T1	22		T15	17		T18	8
class_index[0x2]	accum_cnt_10	46192	1			T1	22		T15	6		T18	16
class_index[0x2]	accum_cnt_0	122873	1			T1	41		T2	15		T3	718
class_index[0x3]	accum_cnt_2000	20524	1			T7	103		T13	684		T42	125
class_index[0x3]	accum_cnt_1000	61010	1			T15	39		T19	36		T7	204
class_index[0x3]	accum_cnt_100	6495	1			T15	25		T19	21		T7	21
class_index[0x3]	accum_cnt_50	22438	1			T1	17		T15	22		T19	63
class_index[0x3]	accum_cnt_10	51670	1			T1	19		T15	7		T19	30
class_index[0x3]	accum_cnt_0	115883	1			T1	49		T2	15		T3	718