Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3531	1			T118	1		T24	23		T28	46
alert[0x1]	3560	1			T5	1		T25	21		T78	220
alert[0x2]	15650	1			T2	1		T7	5		T43	3947
alert[0x3]	6437	1			T7	10		T43	12		T21	6
alert[0x4]	4894	1			T43	14		T24	921		T21	459
alert[0x5]	5219	1			T4	1		T43	33		T118	1
alert[0x6]	6619	1			T43	56		T20	12		T25	223
alert[0x7]	8335	1			T7	17		T23	32		T131	2
alert[0x8]	2823	1			T7	402		T23	202		T24	15
alert[0x9]	8828	1			T118	1		T24	213		T21	36
alert[0xa]	5220	1			T5	1		T7	17		T46	1
alert[0xb]	9930	1			T7	16		T23	22		T74	5
alert[0xc]	13187	1			T5	2		T20	114		T25	1224
alert[0xd]	11042	1			T5	1		T43	319		T20	29
alert[0xe]	9257	1			T24	3		T20	38		T21	144
alert[0xf]	11077	1			T5	2		T7	5		T43	27
alert[0x10]	4603	1			T23	5		T43	31		T24	41
alert[0x11]	5126	1			T18	1		T5	1		T19	3
alert[0x12]	3155	1			T20	35		T25	125		T78	470
alert[0x13]	10174	1			T7	3		T23	19		T43	289
alert[0x14]	5312	1			T7	16		T46	1		T74	8
alert[0x15]	4037	1			T7	87		T11	1		T23	129
alert[0x16]	14405	1			T7	21		T11	1		T24	26
alert[0x17]	8106	1			T7	44		T23	1526		T24	30
alert[0x18]	4170	1			T19	5		T20	137		T48	3
alert[0x19]	13262	1			T2	1		T7	999		T24	26
alert[0x1a]	6640	1			T5	1		T23	19		T43	414
alert[0x1b]	5522	1			T7	15		T43	129		T24	85
alert[0x1c]	2597	1			T4	1		T5	1		T118	1
alert[0x1d]	7165	1			T23	14		T43	52		T20	249
alert[0x1e]	5284	1			T5	1		T7	48		T23	36
alert[0x1f]	12626	1			T4	1		T43	8		T20	1851
alert[0x20]	4090	1			T23	59		T25	157		T52	174
alert[0x21]	2855	1			T23	845		T43	50		T27	223
alert[0x22]	6693	1			T7	9		T43	164		T118	1
alert[0x23]	9504	1			T2	1		T7	39		T43	29
alert[0x24]	12121	1			T7	7		T23	30		T43	132
alert[0x25]	5413	1			T7	129		T23	29		T43	10
alert[0x26]	10650	1			T23	81		T24	178		T318	1
alert[0x27]	4970	1			T19	1		T23	89		T21	2
alert[0x28]	6382	1			T4	1		T18	1		T7	1
alert[0x29]	4454	1			T4	1		T118	1		T20	7
alert[0x2a]	7795	1			T5	2		T7	3		T23	23
alert[0x2b]	8772	1			T45	1		T24	134		T21	174
alert[0x2c]	5728	1			T6	1		T23	71		T21	29
alert[0x2d]	6811	1			T24	68		T21	67		T48	242
alert[0x2e]	4270	1			T7	3		T23	257		T130	1
alert[0x2f]	5589	1			T7	684		T43	63		T24	23
alert[0x30]	6169	1			T21	209		T48	38		T318	1
alert[0x31]	5707	1			T5	2		T23	40		T43	178
alert[0x32]	12295	1			T20	101		T21	1		T120	11
alert[0x33]	4616	1			T43	9		T21	24		T78	242
alert[0x34]	8349	1			T7	94		T43	26		T24	34
alert[0x35]	7259	1			T23	91		T20	91		T48	39
alert[0x36]	14110	1			T5	2		T23	143		T43	27
alert[0x37]	6860	1			T24	1		T21	222		T25	868
alert[0x38]	5322	1			T5	2		T74	4		T20	8
alert[0x39]	7536	1			T19	1		T7	12		T43	303
alert[0x3a]	7124	1			T23	484		T44	1		T24	7
alert[0x3b]	8080	1			T2	1		T4	1		T7	10
alert[0x3c]	4364	1			T43	19		T24	2		T21	312
alert[0x3d]	9536	1			T2	1		T7	3		T23	144
alert[0x3e]	7631	1			T5	1		T20	25		T77	1
alert[0x3f]	2604	1			T43	375		T24	5		T21	6
alert[0x40]	4352	1			T4	1		T7	147		T23	110

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	132623	1			T2	5		T5	19		T7	6
class_i[0x1]	118976	1			T4	7		T18	1		T5	1
class_i[0x2]	105483	1			T19	5		T11	2		T23	5
class_i[0x3]	108722	1			T18	1		T7	2820		T23	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

465153

1

T18

2

T19

10

T7

2877

alert_ping_fail

651

1

T2

5

T4

7

T5

20

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3524	1			T24	23		T28	46		T99	2
alert_integrity_fail	alert[0x1]	3553	1			T25	21		T78	220		T28	260
alert_integrity_fail	alert[0x2]	15642	1			T7	5		T43	3947		T24	1
alert_integrity_fail	alert[0x3]	6431	1			T7	10		T43	12		T21	6
alert_integrity_fail	alert[0x4]	4889	1			T43	14		T24	921		T21	459
alert_integrity_fail	alert[0x5]	5199	1			T43	33		T24	7		T20	882
alert_integrity_fail	alert[0x6]	6604	1			T43	56		T20	12		T25	223
alert_integrity_fail	alert[0x7]	8323	1			T7	17		T23	32		T43	42
alert_integrity_fail	alert[0x8]	2817	1			T7	402		T23	202		T24	15
alert_integrity_fail	alert[0x9]	8819	1			T24	213		T21	36		T78	913
alert_integrity_fail	alert[0xa]	5207	1			T7	17		T24	7		T20	987
alert_integrity_fail	alert[0xb]	9924	1			T7	16		T23	22		T74	5
alert_integrity_fail	alert[0xc]	13177	1			T20	114		T25	1224		T48	5
alert_integrity_fail	alert[0xd]	11035	1			T43	319		T20	29		T25	961
alert_integrity_fail	alert[0xe]	9249	1			T24	3		T20	38		T21	144
alert_integrity_fail	alert[0xf]	11067	1			T7	5		T43	27		T25	40
alert_integrity_fail	alert[0x10]	4591	1			T23	5		T43	31		T24	41
alert_integrity_fail	alert[0x11]	5118	1			T18	1		T19	3		T7	31
alert_integrity_fail	alert[0x12]	3145	1			T20	35		T25	125		T78	470
alert_integrity_fail	alert[0x13]	10164	1			T7	3		T23	19		T43	289
alert_integrity_fail	alert[0x14]	5297	1			T7	16		T74	8		T24	43
alert_integrity_fail	alert[0x15]	4020	1			T7	87		T23	129		T24	1591
alert_integrity_fail	alert[0x16]	14386	1			T7	21		T24	26		T21	16
alert_integrity_fail	alert[0x17]	8098	1			T7	44		T23	1526		T24	30
alert_integrity_fail	alert[0x18]	4162	1			T19	5		T20	137		T48	3
alert_integrity_fail	alert[0x19]	13248	1			T7	999		T24	26		T28	232
alert_integrity_fail	alert[0x1a]	6631	1			T23	19		T43	414		T74	1
alert_integrity_fail	alert[0x1b]	5505	1			T7	15		T43	129		T24	85
alert_integrity_fail	alert[0x1c]	2587	1			T78	9		T51	37		T86	4
alert_integrity_fail	alert[0x1d]	7158	1			T23	14		T43	52		T20	249
alert_integrity_fail	alert[0x1e]	5272	1			T7	48		T23	36		T43	24
alert_integrity_fail	alert[0x1f]	12616	1			T43	8		T20	1851		T78	104
alert_integrity_fail	alert[0x20]	4083	1			T23	59		T25	157		T52	174
alert_integrity_fail	alert[0x21]	2843	1			T23	845		T43	50		T27	223
alert_integrity_fail	alert[0x22]	6680	1			T7	9		T43	164		T20	8
alert_integrity_fail	alert[0x23]	9493	1			T7	39		T43	29		T24	2
alert_integrity_fail	alert[0x24]	12115	1			T7	7		T23	30		T43	132
alert_integrity_fail	alert[0x25]	5408	1			T7	129		T23	29		T43	10
alert_integrity_fail	alert[0x26]	10643	1			T23	81		T24	178		T28	2392
alert_integrity_fail	alert[0x27]	4962	1			T19	1		T23	89		T21	2
alert_integrity_fail	alert[0x28]	6361	1			T18	1		T7	1		T23	1838
alert_integrity_fail	alert[0x29]	4445	1			T20	7		T21	266		T78	11
alert_integrity_fail	alert[0x2a]	7777	1			T7	3		T23	23		T24	70
alert_integrity_fail	alert[0x2b]	8759	1			T24	134		T21	174		T25	663
alert_integrity_fail	alert[0x2c]	5717	1			T23	71		T21	29		T53	504
alert_integrity_fail	alert[0x2d]	6801	1			T24	68		T21	67		T48	242
alert_integrity_fail	alert[0x2e]	4258	1			T7	3		T23	257		T52	5
alert_integrity_fail	alert[0x2f]	5574	1			T7	684		T43	63		T24	23
alert_integrity_fail	alert[0x30]	6159	1			T21	209		T48	38		T27	1
alert_integrity_fail	alert[0x31]	5701	1			T23	40		T43	178		T24	309
alert_integrity_fail	alert[0x32]	12286	1			T20	101		T21	1		T120	11
alert_integrity_fail	alert[0x33]	4614	1			T43	9		T21	24		T78	242
alert_integrity_fail	alert[0x34]	8338	1			T7	94		T43	26		T24	34
alert_integrity_fail	alert[0x35]	7251	1			T23	91		T20	91		T48	39
alert_integrity_fail	alert[0x36]	14099	1			T23	143		T43	27		T20	17
alert_integrity_fail	alert[0x37]	6853	1			T24	1		T21	222		T25	868
alert_integrity_fail	alert[0x38]	5314	1			T74	4		T20	8		T25	32
alert_integrity_fail	alert[0x39]	7526	1			T19	1		T7	12		T43	303
alert_integrity_fail	alert[0x3a]	7116	1			T23	484		T44	1		T24	7
alert_integrity_fail	alert[0x3b]	8069	1			T7	10		T23	3		T24	5
alert_integrity_fail	alert[0x3c]	4358	1			T43	19		T24	2		T21	312
alert_integrity_fail	alert[0x3d]	9526	1			T7	3		T23	144		T43	417
alert_integrity_fail	alert[0x3e]	7620	1			T20	25		T77	1		T27	196
alert_integrity_fail	alert[0x3f]	2596	1			T43	375		T24	5		T21	6
alert_integrity_fail	alert[0x40]	4350	1			T7	147		T23	110		T43	108
alert_ping_fail	alert[0x0]	7	1			T118	1		T34	1		T320	1
alert_ping_fail	alert[0x1]	7	1			T5	1		T320	1		T304	1
alert_ping_fail	alert[0x2]	8	1			T2	1		T129	1		T321	1
alert_ping_fail	alert[0x3]	6	1			T318	1		T322	1		T323	1
alert_ping_fail	alert[0x4]	5	1			T318	1		T324	1		T325	1
alert_ping_fail	alert[0x5]	20	1			T4	1		T118	1		T40	2
alert_ping_fail	alert[0x6]	15	1			T117	1		T326	2		T247	1
alert_ping_fail	alert[0x7]	12	1			T131	2		T118	1		T94	1
alert_ping_fail	alert[0x8]	6	1			T321	1		T320	1		T327	1
alert_ping_fail	alert[0x9]	9	1			T118	1		T40	1		T326	1
alert_ping_fail	alert[0xa]	13	1			T5	1		T46	1		T328	1
alert_ping_fail	alert[0xb]	6	1			T214	1		T329	2		T330	1
alert_ping_fail	alert[0xc]	10	1			T5	2		T318	1		T40	1
alert_ping_fail	alert[0xd]	7	1			T5	1		T37	1		T331	1
alert_ping_fail	alert[0xe]	8	1			T332	2		T320	2		T322	3
alert_ping_fail	alert[0xf]	10	1			T5	2		T333	1		T334	3
alert_ping_fail	alert[0x10]	12	1			T318	2		T129	1		T326	1
alert_ping_fail	alert[0x11]	8	1			T5	1		T333	1		T335	1
alert_ping_fail	alert[0x12]	10	1			T336	1		T214	1		T337	1
alert_ping_fail	alert[0x13]	10	1			T319	2		T338	1		T214	1
alert_ping_fail	alert[0x14]	15	1			T46	1		T117	1		T40	1
alert_ping_fail	alert[0x15]	17	1			T11	1		T321	1		T333	1
alert_ping_fail	alert[0x16]	19	1			T11	1		T318	1		T129	1
alert_ping_fail	alert[0x17]	8	1			T326	1		T338	1		T334	1
alert_ping_fail	alert[0x18]	8	1			T129	1		T320	1		T214	1
alert_ping_fail	alert[0x19]	14	1			T2	1		T321	1		T40	1
alert_ping_fail	alert[0x1a]	9	1			T5	1		T37	1		T326	1
alert_ping_fail	alert[0x1b]	17	1			T129	1		T37	1		T40	1
alert_ping_fail	alert[0x1c]	10	1			T4	1		T5	1		T118	1
alert_ping_fail	alert[0x1d]	7	1			T326	1		T339	1		T340	2
alert_ping_fail	alert[0x1e]	12	1			T5	1		T318	2		T129	1
alert_ping_fail	alert[0x1f]	10	1			T4	1		T318	1		T321	1
alert_ping_fail	alert[0x20]	7	1			T326	1		T214	1		T331	1
alert_ping_fail	alert[0x21]	12	1			T326	1		T320	1		T214	1
alert_ping_fail	alert[0x22]	13	1			T118	1		T94	1		T34	1
alert_ping_fail	alert[0x23]	11	1			T2	1		T321	1		T322	1
alert_ping_fail	alert[0x24]	6	1			T40	1		T336	1		T214	1
alert_ping_fail	alert[0x25]	5	1			T326	1		T251	1		T320	2
alert_ping_fail	alert[0x26]	7	1			T318	1		T37	1		T331	1
alert_ping_fail	alert[0x27]	8	1			T129	1		T332	1		T341	1
alert_ping_fail	alert[0x28]	21	1			T4	1		T46	1		T130	1
alert_ping_fail	alert[0x29]	9	1			T4	1		T118	1		T318	1
alert_ping_fail	alert[0x2a]	18	1			T5	2		T318	1		T34	4
alert_ping_fail	alert[0x2b]	13	1			T45	1		T129	1		T319	1
alert_ping_fail	alert[0x2c]	11	1			T6	1		T130	1		T336	1
alert_ping_fail	alert[0x2d]	10	1			T129	1		T321	1		T326	1
alert_ping_fail	alert[0x2e]	12	1			T130	1		T332	1		T342	2
alert_ping_fail	alert[0x2f]	15	1			T129	1		T250	1		T337	1
alert_ping_fail	alert[0x30]	10	1			T318	1		T37	1		T326	1
alert_ping_fail	alert[0x31]	6	1			T5	2		T331	1		T339	1
alert_ping_fail	alert[0x32]	9	1			T321	2		T40	1		T332	1
alert_ping_fail	alert[0x33]	2	1			T318	1		T327	1		-	-
alert_ping_fail	alert[0x34]	11	1			T318	1		T129	1		T321	1
alert_ping_fail	alert[0x35]	8	1			T321	1		T251	1		T214	1
alert_ping_fail	alert[0x36]	11	1			T5	2		T318	1		T251	1
alert_ping_fail	alert[0x37]	7	1			T129	1		T40	1		T251	1
alert_ping_fail	alert[0x38]	8	1			T5	2		T40	1		T214	1
alert_ping_fail	alert[0x39]	10	1			T118	2		T40	1		T338	1
alert_ping_fail	alert[0x3a]	8	1			T321	1		T343	1		T331	1
alert_ping_fail	alert[0x3b]	11	1			T2	1		T4	1		T37	1
alert_ping_fail	alert[0x3c]	6	1			T37	1		T344	1		T325	1
alert_ping_fail	alert[0x3d]	10	1			T2	1		T318	1		T326	1
alert_ping_fail	alert[0x3e]	11	1			T5	1		T318	1		T40	1
alert_ping_fail	alert[0x3f]	8	1			T336	1		T343	1		T330	1
alert_ping_fail	alert[0x40]	2	1			T4	1		T322	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	132444	1			T7	6		T23	3		T43	15
alert_integrity_fail	class_i[0x1]	118854	1			T18	1		T19	5		T7	51
alert_integrity_fail	class_i[0x2]	105283	1			T19	5		T23	5		T74	5
alert_integrity_fail	class_i[0x3]	108572	1			T18	1		T7	2820		T23	6
alert_ping_fail	class_i[0x0]	179	1			T2	5		T5	19		T94	2
alert_ping_fail	class_i[0x1]	122	1			T4	7		T5	1		T6	1
alert_ping_fail	class_i[0x2]	200	1			T11	2		T131	2		T117	2
alert_ping_fail	class_i[0x3]	150	1			T118	9		T46	3		T318	18