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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.69 100.00 100.00 100.00 99.38 99.52


Total test records in report: 840
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T776 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4009788448 May 07 03:15:38 PM PDT 24 May 07 03:15:47 PM PDT 24 529226398 ps
T777 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4140139193 May 07 03:16:08 PM PDT 24 May 07 03:16:10 PM PDT 24 6343937 ps
T778 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.7547878 May 07 03:16:09 PM PDT 24 May 07 03:16:12 PM PDT 24 11453794 ps
T178 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.249683573 May 07 03:15:50 PM PDT 24 May 07 03:16:50 PM PDT 24 1987310307 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3970737967 May 07 03:15:43 PM PDT 24 May 07 03:15:48 PM PDT 24 22455803 ps
T192 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.962905700 May 07 03:16:02 PM PDT 24 May 07 03:16:21 PM PDT 24 998935946 ps
T191 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.517313349 May 07 03:15:46 PM PDT 24 May 07 03:15:49 PM PDT 24 105337550 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.113177008 May 07 03:15:36 PM PDT 24 May 07 03:16:02 PM PDT 24 1444145077 ps
T781 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.422235848 May 07 03:16:11 PM PDT 24 May 07 03:16:14 PM PDT 24 7720424 ps
T154 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2738968665 May 07 03:15:56 PM PDT 24 May 07 03:18:23 PM PDT 24 4845571049 ps
T157 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.729180941 May 07 03:16:02 PM PDT 24 May 07 03:25:56 PM PDT 24 37240325326 ps
T167 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.788481078 May 07 03:15:32 PM PDT 24 May 07 03:23:37 PM PDT 24 34571762367 ps
T782 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1898169746 May 07 03:15:37 PM PDT 24 May 07 03:15:42 PM PDT 24 20547061 ps
T783 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3666340423 May 07 03:16:05 PM PDT 24 May 07 03:16:41 PM PDT 24 937424759 ps
T784 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.686811480 May 07 03:16:11 PM PDT 24 May 07 03:16:14 PM PDT 24 9825669 ps
T162 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.28938931 May 07 03:15:57 PM PDT 24 May 07 03:17:26 PM PDT 24 5093577133 ps
T785 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4283003977 May 07 03:16:04 PM PDT 24 May 07 03:16:11 PM PDT 24 32985101 ps
T182 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.173214665 May 07 03:15:56 PM PDT 24 May 07 03:16:00 PM PDT 24 106590079 ps
T155 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.336787719 May 07 03:16:02 PM PDT 24 May 07 03:23:46 PM PDT 24 7051185676 ps
T786 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.142831947 May 07 03:15:46 PM PDT 24 May 07 03:15:54 PM PDT 24 54231355 ps
T160 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1008414440 May 07 03:16:00 PM PDT 24 May 07 03:17:30 PM PDT 24 767462514 ps
T787 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3407690156 May 07 03:16:01 PM PDT 24 May 07 03:16:22 PM PDT 24 1367136881 ps
T788 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.659553953 May 07 03:15:48 PM PDT 24 May 07 03:15:54 PM PDT 24 119495816 ps
T789 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.363338560 May 07 03:16:03 PM PDT 24 May 07 03:16:11 PM PDT 24 206677843 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.409270295 May 07 03:15:55 PM PDT 24 May 07 03:16:01 PM PDT 24 128646020 ps
T791 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2222222777 May 07 03:16:10 PM PDT 24 May 07 03:16:13 PM PDT 24 25372356 ps
T156 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3173037649 May 07 03:15:48 PM PDT 24 May 07 03:18:59 PM PDT 24 7832032055 ps
T142 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.846310595 May 07 03:16:04 PM PDT 24 May 07 03:18:40 PM PDT 24 2311542035 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.19561190 May 07 03:15:34 PM PDT 24 May 07 03:15:40 PM PDT 24 317755877 ps
T793 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2400300445 May 07 03:16:04 PM PDT 24 May 07 03:16:13 PM PDT 24 94636975 ps
T794 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3136244594 May 07 03:16:09 PM PDT 24 May 07 03:16:12 PM PDT 24 9934043 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.233752240 May 07 03:15:40 PM PDT 24 May 07 03:16:06 PM PDT 24 1525221272 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1930485738 May 07 03:15:41 PM PDT 24 May 07 03:17:23 PM PDT 24 1636991595 ps
T797 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3122672545 May 07 03:15:54 PM PDT 24 May 07 03:15:58 PM PDT 24 19740702 ps
T798 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4003881455 May 07 03:16:15 PM PDT 24 May 07 03:16:19 PM PDT 24 13401000 ps
T799 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3982255616 May 07 03:15:35 PM PDT 24 May 07 03:15:43 PM PDT 24 198265320 ps
T177 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2221903747 May 07 03:15:46 PM PDT 24 May 07 03:17:13 PM PDT 24 5177681709 ps
T800 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.269059980 May 07 03:16:12 PM PDT 24 May 07 03:16:14 PM PDT 24 7763427 ps
T143 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4061849870 May 07 03:15:32 PM PDT 24 May 07 03:17:20 PM PDT 24 1089424037 ps
T801 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4037376580 May 07 03:15:40 PM PDT 24 May 07 03:15:52 PM PDT 24 123941964 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3471003427 May 07 03:15:52 PM PDT 24 May 07 03:16:02 PM PDT 24 515012057 ps
T803 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2454642819 May 07 03:15:51 PM PDT 24 May 07 03:15:54 PM PDT 24 27203515 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.216506880 May 07 03:15:34 PM PDT 24 May 07 03:15:38 PM PDT 24 63155805 ps
T159 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2482914173 May 07 03:15:56 PM PDT 24 May 07 03:24:01 PM PDT 24 49448539081 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.557531336 May 07 03:15:40 PM PDT 24 May 07 03:15:43 PM PDT 24 16081582 ps
T185 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.860971428 May 07 03:15:58 PM PDT 24 May 07 03:17:07 PM PDT 24 1843091415 ps
T806 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3536578834 May 07 03:16:09 PM PDT 24 May 07 03:16:12 PM PDT 24 7048421 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3508719015 May 07 03:15:33 PM PDT 24 May 07 03:15:42 PM PDT 24 870634905 ps
T168 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3721835247 May 07 03:16:02 PM PDT 24 May 07 03:20:28 PM PDT 24 9058623736 ps
T808 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2762422617 May 07 03:15:49 PM PDT 24 May 07 03:15:59 PM PDT 24 199099318 ps
T809 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3407499717 May 07 03:16:10 PM PDT 24 May 07 03:16:13 PM PDT 24 14998833 ps
T810 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1201772843 May 07 03:15:56 PM PDT 24 May 07 03:16:04 PM PDT 24 363217520 ps
T811 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2353492051 May 07 03:16:10 PM PDT 24 May 07 03:16:13 PM PDT 24 8892042 ps
T181 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3872502294 May 07 03:15:39 PM PDT 24 May 07 03:16:21 PM PDT 24 361545704 ps
T812 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2249419347 May 07 03:16:00 PM PDT 24 May 07 03:16:20 PM PDT 24 603696729 ps
T813 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2933899025 May 07 03:16:00 PM PDT 24 May 07 03:16:04 PM PDT 24 33878751 ps
T814 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2540427316 May 07 03:16:08 PM PDT 24 May 07 03:16:11 PM PDT 24 25957065 ps
T166 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2360660114 May 07 03:15:55 PM PDT 24 May 07 03:26:49 PM PDT 24 15396222702 ps
T815 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3248044311 May 07 03:16:10 PM PDT 24 May 07 03:16:13 PM PDT 24 6699750 ps
T816 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1414417543 May 07 03:16:08 PM PDT 24 May 07 03:16:11 PM PDT 24 7060623 ps
T164 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1870865732 May 07 03:15:55 PM PDT 24 May 07 03:18:43 PM PDT 24 10299555318 ps
T817 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1100189683 May 07 03:16:11 PM PDT 24 May 07 03:16:14 PM PDT 24 11938186 ps
T818 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.623478158 May 07 03:15:57 PM PDT 24 May 07 03:16:07 PM PDT 24 529392998 ps
T819 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2706631360 May 07 03:15:46 PM PDT 24 May 07 03:16:05 PM PDT 24 1112450286 ps
T820 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3301206542 May 07 03:16:09 PM PDT 24 May 07 03:16:12 PM PDT 24 32519572 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4145253325 May 07 03:15:46 PM PDT 24 May 07 03:15:48 PM PDT 24 22434299 ps
T822 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.344910033 May 07 03:15:59 PM PDT 24 May 07 03:16:14 PM PDT 24 210583363 ps
T823 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.80194532 May 07 03:16:09 PM PDT 24 May 07 03:16:12 PM PDT 24 12011098 ps
T824 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1111722614 May 07 03:15:52 PM PDT 24 May 07 03:15:58 PM PDT 24 98720120 ps
T161 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1703784116 May 07 03:15:45 PM PDT 24 May 07 03:19:21 PM PDT 24 7368759164 ps
T825 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3443969637 May 07 03:15:40 PM PDT 24 May 07 03:17:38 PM PDT 24 1631243484 ps
T170 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3693456163 May 07 03:15:41 PM PDT 24 May 07 03:31:05 PM PDT 24 28269712164 ps
T826 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3394557474 May 07 03:16:11 PM PDT 24 May 07 03:16:14 PM PDT 24 7545137 ps
T827 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3933897761 May 07 03:16:10 PM PDT 24 May 07 03:16:13 PM PDT 24 8294186 ps
T828 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.914314417 May 07 03:15:52 PM PDT 24 May 07 03:16:35 PM PDT 24 729890218 ps
T829 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4117210541 May 07 03:16:03 PM PDT 24 May 07 03:16:06 PM PDT 24 10087559 ps
T165 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4197100025 May 07 03:15:36 PM PDT 24 May 07 03:21:11 PM PDT 24 23492413479 ps
T830 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1452749233 May 07 03:15:52 PM PDT 24 May 07 03:20:12 PM PDT 24 2366403991 ps
T831 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2728014471 May 07 03:15:58 PM PDT 24 May 07 03:16:01 PM PDT 24 9879012 ps
T832 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2853030152 May 07 03:15:45 PM PDT 24 May 07 03:15:47 PM PDT 24 8777470 ps
T169 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2692292668 May 07 03:15:36 PM PDT 24 May 07 03:20:07 PM PDT 24 8691141949 ps
T833 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2717010885 May 07 03:16:02 PM PDT 24 May 07 03:17:44 PM PDT 24 1008114976 ps
T183 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.63133378 May 07 03:15:57 PM PDT 24 May 07 03:16:00 PM PDT 24 115201620 ps
T834 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3131568083 May 07 03:15:50 PM PDT 24 May 07 03:15:59 PM PDT 24 329463485 ps
T835 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3615209905 May 07 03:15:36 PM PDT 24 May 07 03:15:41 PM PDT 24 49268697 ps
T836 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1965623884 May 07 03:16:02 PM PDT 24 May 07 03:16:20 PM PDT 24 484424441 ps
T837 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3275506865 May 07 03:16:06 PM PDT 24 May 07 03:16:21 PM PDT 24 2589916844 ps
T838 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2055517069 May 07 03:16:03 PM PDT 24 May 07 03:16:33 PM PDT 24 9496767999 ps
T839 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2149784725 May 07 03:15:56 PM PDT 24 May 07 03:15:58 PM PDT 24 18073510 ps
T840 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1137492933 May 07 03:16:03 PM PDT 24 May 07 03:16:09 PM PDT 24 35895806 ps

Test location /workspace/coverage/default/30.alert_handler_stress_all.849048696
Short name T1
Test name
Test status
Simulation time 1776921867 ps
CPU time 81.22 seconds
Started May 07 02:10:55 PM PDT 24
Finished May 07 02:12:17 PM PDT 24
Peak memory 257012 kb
Host smart-d7991377-d0e8-4114-9a86-4aa7f6320368
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849048696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.849048696
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1310681442
Short name T7
Test name
Test status
Simulation time 86231513606 ps
CPU time 2036.4 seconds
Started May 07 02:08:20 PM PDT 24
Finished May 07 02:42:18 PM PDT 24
Peak memory 298124 kb
Host smart-09c743c9-8bc7-4e15-9cb0-857b544d03d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310681442 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1310681442
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4134019997
Short name T9
Test name
Test status
Simulation time 1610858185 ps
CPU time 22.21 seconds
Started May 07 02:08:20 PM PDT 24
Finished May 07 02:08:43 PM PDT 24
Peak memory 265244 kb
Host smart-0219d75f-a25e-4fae-87d1-43d7f269ac73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4134019997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4134019997
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.4275028032
Short name T20
Test name
Test status
Simulation time 44301082026 ps
CPU time 2478.14 seconds
Started May 07 02:11:46 PM PDT 24
Finished May 07 02:53:06 PM PDT 24
Peak memory 284824 kb
Host smart-f7ac0bcf-0405-488e-9778-025bedb2cc6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275028032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.4275028032
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.706054717
Short name T224
Test name
Test status
Simulation time 131987145 ps
CPU time 9.08 seconds
Started May 07 03:16:06 PM PDT 24
Finished May 07 03:16:16 PM PDT 24
Peak memory 238080 kb
Host smart-de56357d-921a-4ff9-b8b1-9f9d095f5d70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706054717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.706054717
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3788780937
Short name T27
Test name
Test status
Simulation time 87876100684 ps
CPU time 6936.17 seconds
Started May 07 02:10:21 PM PDT 24
Finished May 07 04:05:58 PM PDT 24
Peak memory 371180 kb
Host smart-8fcbb8cf-1610-456e-94d5-408c02800896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788780937 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3788780937
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3904091955
Short name T6
Test name
Test status
Simulation time 189854641449 ps
CPU time 2683.87 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:54:17 PM PDT 24
Peak memory 288312 kb
Host smart-f4367a16-ac15-4d64-81e7-6c41a9981b5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904091955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3904091955
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2533730631
Short name T21
Test name
Test status
Simulation time 61676738409 ps
CPU time 4026.17 seconds
Started May 07 02:08:38 PM PDT 24
Finished May 07 03:15:46 PM PDT 24
Peak memory 306308 kb
Host smart-a33a90e0-fd09-4dd6-a492-8f13cedeef27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533730631 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2533730631
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.341403551
Short name T101
Test name
Test status
Simulation time 85593793131 ps
CPU time 2513.93 seconds
Started May 07 02:11:02 PM PDT 24
Finished May 07 02:52:57 PM PDT 24
Peak memory 288744 kb
Host smart-42aabeb8-0d2b-4395-bb68-255eb02b5ad6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341403551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.341403551
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2585754482
Short name T144
Test name
Test status
Simulation time 24228300746 ps
CPU time 910.06 seconds
Started May 07 03:15:51 PM PDT 24
Finished May 07 03:31:02 PM PDT 24
Peak memory 272196 kb
Host smart-c92a8b38-5388-4f2c-8796-733fb0f2dad7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585754482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2585754482
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3987340170
Short name T140
Test name
Test status
Simulation time 8788746666 ps
CPU time 188.21 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:19:01 PM PDT 24
Peak memory 265460 kb
Host smart-a14f3050-e77e-4a2a-ae03-208b4cc7a5a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3987340170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3987340170
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2405810297
Short name T25
Test name
Test status
Simulation time 53800580262 ps
CPU time 3231.07 seconds
Started May 07 02:09:56 PM PDT 24
Finished May 07 03:03:48 PM PDT 24
Peak memory 289944 kb
Host smart-6fae7841-1fd6-494e-bb0b-910a1e1e807c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405810297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2405810297
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3908004500
Short name T305
Test name
Test status
Simulation time 102088140551 ps
CPU time 1585.82 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:36:14 PM PDT 24
Peak memory 265512 kb
Host smart-b3fbcc08-8687-4810-8b46-a69f4131d935
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908004500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3908004500
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2028057175
Short name T225
Test name
Test status
Simulation time 6531537032 ps
CPU time 209.11 seconds
Started May 07 03:15:36 PM PDT 24
Finished May 07 03:19:06 PM PDT 24
Peak memory 240488 kb
Host smart-ba8f26eb-5122-4827-9127-e81ba9b90875
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2028057175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2028057175
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2488297165
Short name T23
Test name
Test status
Simulation time 16100685949 ps
CPU time 1569.35 seconds
Started May 07 02:11:19 PM PDT 24
Finished May 07 02:37:29 PM PDT 24
Peak memory 289468 kb
Host smart-40ecc55d-1017-43bf-a201-c6196f448226
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488297165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2488297165
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1703784116
Short name T161
Test name
Test status
Simulation time 7368759164 ps
CPU time 215 seconds
Started May 07 03:15:45 PM PDT 24
Finished May 07 03:19:21 PM PDT 24
Peak memory 265444 kb
Host smart-04b11fde-8773-4720-9b7b-71cdac972a58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1703784116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1703784116
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.316184109
Short name T139
Test name
Test status
Simulation time 3096246012 ps
CPU time 173.88 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:18:57 PM PDT 24
Peak memory 271060 kb
Host smart-645163a6-198f-462a-95da-4b2d01d66403
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=316184109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.316184109
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.734709532
Short name T126
Test name
Test status
Simulation time 235403625036 ps
CPU time 3074.02 seconds
Started May 07 02:08:18 PM PDT 24
Finished May 07 02:59:33 PM PDT 24
Peak memory 288964 kb
Host smart-5db2eea1-d815-44cd-a258-0b0482fc5d05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734709532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.734709532
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3022061779
Short name T365
Test name
Test status
Simulation time 6898670 ps
CPU time 1.43 seconds
Started May 07 03:15:50 PM PDT 24
Finished May 07 03:15:52 PM PDT 24
Peak memory 236952 kb
Host smart-23473bfd-8003-44bd-93ba-8847c5de06f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3022061779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3022061779
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1916942552
Short name T150
Test name
Test status
Simulation time 12680512889 ps
CPU time 952.3 seconds
Started May 07 03:15:53 PM PDT 24
Finished May 07 03:31:46 PM PDT 24
Peak memory 265428 kb
Host smart-3e77cc35-3ce0-472a-9c87-475d55f29515
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916942552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1916942552
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.481690405
Short name T326
Test name
Test status
Simulation time 40167725658 ps
CPU time 405.78 seconds
Started May 07 02:09:57 PM PDT 24
Finished May 07 02:16:43 PM PDT 24
Peak memory 248208 kb
Host smart-0a831d39-9269-44b8-9d6e-d3aa7a836fe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481690405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.481690405
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4110573999
Short name T130
Test name
Test status
Simulation time 221299784276 ps
CPU time 3276.46 seconds
Started May 07 02:11:53 PM PDT 24
Finished May 07 03:06:31 PM PDT 24
Peak memory 288704 kb
Host smart-14ca7f31-a4d6-4548-94b3-c68f49aa4928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110573999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4110573999
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1225219832
Short name T135
Test name
Test status
Simulation time 8498205003 ps
CPU time 119.39 seconds
Started May 07 03:15:38 PM PDT 24
Finished May 07 03:17:39 PM PDT 24
Peak memory 265440 kb
Host smart-41d5a59c-e0ac-48f0-a3b3-178daf910197
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1225219832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1225219832
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1459724201
Short name T318
Test name
Test status
Simulation time 28041884134 ps
CPU time 574.93 seconds
Started May 07 02:10:59 PM PDT 24
Finished May 07 02:20:35 PM PDT 24
Peak memory 248236 kb
Host smart-05977d18-241f-48ce-8f6a-6f8f593b8c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459724201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1459724201
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1172301643
Short name T39
Test name
Test status
Simulation time 69428542285 ps
CPU time 3717.81 seconds
Started May 07 02:11:37 PM PDT 24
Finished May 07 03:13:36 PM PDT 24
Peak memory 305308 kb
Host smart-9814a4d9-8041-46cd-9e16-5f094b15034f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172301643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1172301643
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1397368269
Short name T134
Test name
Test status
Simulation time 33758101916 ps
CPU time 298.69 seconds
Started May 07 03:15:47 PM PDT 24
Finished May 07 03:20:46 PM PDT 24
Peak memory 265432 kb
Host smart-0b29314b-5bd8-4212-9e0f-a5ece9894601
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397368269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1397368269
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.616209159
Short name T345
Test name
Test status
Simulation time 65973552745 ps
CPU time 2737.8 seconds
Started May 07 02:12:41 PM PDT 24
Finished May 07 02:58:21 PM PDT 24
Peak memory 289020 kb
Host smart-f0183b72-d015-460f-8b88-6be4bbb30b01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616209159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.616209159
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.669792617
Short name T146
Test name
Test status
Simulation time 1915905909 ps
CPU time 216.37 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:19:43 PM PDT 24
Peak memory 265432 kb
Host smart-6abdb001-2cb8-4d22-81f4-bfeea9b03c3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=669792617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.669792617
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2111819580
Short name T214
Test name
Test status
Simulation time 39785145916 ps
CPU time 468.6 seconds
Started May 07 02:09:33 PM PDT 24
Finished May 07 02:17:22 PM PDT 24
Peak memory 247892 kb
Host smart-18dfa4ac-3015-443f-8d56-9857987f9a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111819580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2111819580
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.394090622
Short name T184
Test name
Test status
Simulation time 782387734 ps
CPU time 3.58 seconds
Started May 07 03:15:33 PM PDT 24
Finished May 07 03:15:37 PM PDT 24
Peak memory 235876 kb
Host smart-32e8e74e-0737-4f95-8954-b235d848744d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=394090622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.394090622
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2594292057
Short name T102
Test name
Test status
Simulation time 51057729680 ps
CPU time 3330.78 seconds
Started May 07 02:09:09 PM PDT 24
Finished May 07 03:04:41 PM PDT 24
Peak memory 305216 kb
Host smart-a06da986-ee03-4828-9453-01fb1ce1f800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594292057 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2594292057
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1517479512
Short name T137
Test name
Test status
Simulation time 2411756002 ps
CPU time 304.89 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:21:11 PM PDT 24
Peak memory 267928 kb
Host smart-a29f8ee3-65ed-4382-a1c8-1333e61cc500
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517479512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1517479512
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2351096700
Short name T5
Test name
Test status
Simulation time 26424779127 ps
CPU time 486.44 seconds
Started May 07 02:13:50 PM PDT 24
Finished May 07 02:21:57 PM PDT 24
Peak memory 248252 kb
Host smart-7cb46158-9282-47c4-ae3b-93f92be6cbb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351096700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2351096700
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1777037983
Short name T250
Test name
Test status
Simulation time 120095342524 ps
CPU time 3554.37 seconds
Started May 07 02:09:17 PM PDT 24
Finished May 07 03:08:32 PM PDT 24
Peak memory 289324 kb
Host smart-cdd63731-ef60-466b-b29a-fa6d287ee041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777037983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1777037983
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4197100025
Short name T165
Test name
Test status
Simulation time 23492413479 ps
CPU time 334.07 seconds
Started May 07 03:15:36 PM PDT 24
Finished May 07 03:21:11 PM PDT 24
Peak memory 265444 kb
Host smart-cc78b093-4c31-4ece-80db-da6dc9cccd67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197100025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4197100025
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1863367999
Short name T219
Test name
Test status
Simulation time 45257133771 ps
CPU time 1760.54 seconds
Started May 07 02:10:27 PM PDT 24
Finished May 07 02:39:49 PM PDT 24
Peak memory 289660 kb
Host smart-b64403cd-4a7c-43d5-be51-ad4d4eb7bfda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863367999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1863367999
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4001346822
Short name T670
Test name
Test status
Simulation time 6475048234 ps
CPU time 265.09 seconds
Started May 07 02:12:41 PM PDT 24
Finished May 07 02:17:08 PM PDT 24
Peak memory 248368 kb
Host smart-636782f2-6fa7-4ea4-81b4-f127cfde7210
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001346822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4001346822
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2933760855
Short name T196
Test name
Test status
Simulation time 182371991122 ps
CPU time 4305.61 seconds
Started May 07 02:10:04 PM PDT 24
Finished May 07 03:21:51 PM PDT 24
Peak memory 305632 kb
Host smart-356b3a46-f0ef-4c2e-9cf0-9177c767ebb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933760855 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2933760855
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1765970734
Short name T136
Test name
Test status
Simulation time 6207570368 ps
CPU time 180.96 seconds
Started May 07 03:15:50 PM PDT 24
Finished May 07 03:18:52 PM PDT 24
Peak memory 257228 kb
Host smart-c47a8d66-8961-49e8-b213-4d03263304ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1765970734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1765970734
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3721835247
Short name T168
Test name
Test status
Simulation time 9058623736 ps
CPU time 264.52 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:20:28 PM PDT 24
Peak memory 265412 kb
Host smart-4445bd74-751f-482d-82fe-7e2837024c47
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721835247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3721835247
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.789708737
Short name T371
Test name
Test status
Simulation time 36921372 ps
CPU time 1.34 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 236908 kb
Host smart-8e43de0a-1686-4d4d-9944-ba85fd65119d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=789708737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.789708737
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1014183299
Short name T281
Test name
Test status
Simulation time 741823953 ps
CPU time 44.14 seconds
Started May 07 02:09:33 PM PDT 24
Finished May 07 02:10:18 PM PDT 24
Peak memory 255388 kb
Host smart-361d347b-e938-45a4-8b12-d7ce6fde8dba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014183299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1014183299
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3263691951
Short name T352
Test name
Test status
Simulation time 212713804703 ps
CPU time 3082.38 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 03:01:01 PM PDT 24
Peak memory 289136 kb
Host smart-d21ac0ab-6021-42ce-b1db-a43d46d6efb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263691951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3263691951
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.780808579
Short name T138
Test name
Test status
Simulation time 9372772512 ps
CPU time 466.16 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:23:42 PM PDT 24
Peak memory 269132 kb
Host smart-1127272f-089c-45d8-8c7b-83e205e7a219
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780808579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.780808579
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3909720764
Short name T350
Test name
Test status
Simulation time 49222488486 ps
CPU time 2815.46 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:55:29 PM PDT 24
Peak memory 289300 kb
Host smart-822c907c-fc54-4dac-8c1d-61c22c12770d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909720764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3909720764
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3792704982
Short name T356
Test name
Test status
Simulation time 43236005121 ps
CPU time 816.69 seconds
Started May 07 02:08:15 PM PDT 24
Finished May 07 02:21:53 PM PDT 24
Peak memory 267236 kb
Host smart-fe5a5b2d-c06f-42b0-8bc1-ed4b9c434f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792704982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3792704982
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1615443349
Short name T334
Test name
Test status
Simulation time 11737633410 ps
CPU time 472.17 seconds
Started May 07 02:09:21 PM PDT 24
Finished May 07 02:17:14 PM PDT 24
Peak memory 247100 kb
Host smart-f43e45fc-664c-4b3d-9839-8e234564c10c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615443349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1615443349
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.848427521
Short name T283
Test name
Test status
Simulation time 60223649812 ps
CPU time 6360.58 seconds
Started May 07 02:14:05 PM PDT 24
Finished May 07 04:00:07 PM PDT 24
Peak memory 354764 kb
Host smart-1282fcea-f58b-497b-aafa-31d3185cc3cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848427521 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.848427521
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1584199298
Short name T241
Test name
Test status
Simulation time 45588334 ps
CPU time 3.64 seconds
Started May 07 02:08:15 PM PDT 24
Finished May 07 02:08:20 PM PDT 24
Peak memory 248948 kb
Host smart-6b19e31b-f965-49d0-a22e-bfcc4d2279f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1584199298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1584199298
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2150667731
Short name T231
Test name
Test status
Simulation time 133687584 ps
CPU time 2.17 seconds
Started May 07 02:08:23 PM PDT 24
Finished May 07 02:08:26 PM PDT 24
Peak memory 248936 kb
Host smart-57c2dfc3-a782-458c-a98f-5a4ee967f019
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2150667731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2150667731
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3969767941
Short name T232
Test name
Test status
Simulation time 28499286 ps
CPU time 2.22 seconds
Started May 07 02:09:09 PM PDT 24
Finished May 07 02:09:12 PM PDT 24
Peak memory 248912 kb
Host smart-31b7e643-3068-49ff-972f-7631464f11a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3969767941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3969767941
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3270490121
Short name T234
Test name
Test status
Simulation time 32707116 ps
CPU time 3.09 seconds
Started May 07 02:09:21 PM PDT 24
Finished May 07 02:09:25 PM PDT 24
Peak memory 248856 kb
Host smart-6bce6b15-bc24-48f5-85ff-ba8eb4e8d716
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3270490121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3270490121
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.846310595
Short name T142
Test name
Test status
Simulation time 2311542035 ps
CPU time 155.37 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:18:40 PM PDT 24
Peak memory 265452 kb
Host smart-1dba6ec5-7a57-452e-b3e1-1f4ccc427308
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=846310595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.846310595
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.627104400
Short name T372
Test name
Test status
Simulation time 9914835 ps
CPU time 1.43 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:01 PM PDT 24
Peak memory 236980 kb
Host smart-d1e23301-926a-426c-9393-5be4a5393a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=627104400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.627104400
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2486853348
Short name T213
Test name
Test status
Simulation time 77736335047 ps
CPU time 6717.73 seconds
Started May 07 02:09:55 PM PDT 24
Finished May 07 04:01:54 PM PDT 24
Peak memory 322360 kb
Host smart-26289637-c4e1-4eb9-ad79-2e4434a97c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486853348 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2486853348
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.835668402
Short name T292
Test name
Test status
Simulation time 12566481963 ps
CPU time 726.34 seconds
Started May 07 02:10:37 PM PDT 24
Finished May 07 02:22:44 PM PDT 24
Peak memory 269860 kb
Host smart-f1ab559c-5162-412c-ae97-7b1cc7943f4b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835668402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.835668402
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.998122181
Short name T293
Test name
Test status
Simulation time 80221304711 ps
CPU time 5158.45 seconds
Started May 07 02:10:42 PM PDT 24
Finished May 07 03:36:42 PM PDT 24
Peak memory 322648 kb
Host smart-70ca9479-8301-4dad-b4c7-9932bdee9a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998122181 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.998122181
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1559964894
Short name T304
Test name
Test status
Simulation time 4176012330 ps
CPU time 163.88 seconds
Started May 07 02:11:12 PM PDT 24
Finished May 07 02:13:57 PM PDT 24
Peak memory 254496 kb
Host smart-b2772973-fad4-4fe4-8404-e182fe568fe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559964894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1559964894
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2481044105
Short name T286
Test name
Test status
Simulation time 103694619450 ps
CPU time 3120.86 seconds
Started May 07 02:13:52 PM PDT 24
Finished May 07 03:05:53 PM PDT 24
Peak memory 297996 kb
Host smart-dc852e2e-5a10-450d-978a-dc3464d8fc80
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481044105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2481044105
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3852520625
Short name T322
Test name
Test status
Simulation time 63489652262 ps
CPU time 526.13 seconds
Started May 07 02:14:16 PM PDT 24
Finished May 07 02:23:03 PM PDT 24
Peak memory 248208 kb
Host smart-b31ab2b7-b050-447e-a1ff-8fbf0ec258a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852520625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3852520625
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.959005970
Short name T702
Test name
Test status
Simulation time 15382598692 ps
CPU time 592.54 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:18:24 PM PDT 24
Peak memory 248100 kb
Host smart-0fb3fb32-f14f-402e-a31f-c7d3a4b95d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959005970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.959005970
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.249683573
Short name T178
Test name
Test status
Simulation time 1987310307 ps
CPU time 59.7 seconds
Started May 07 03:15:50 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 248656 kb
Host smart-95659ccc-0d90-4cfa-a72d-b7febaf21839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=249683573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.249683573
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3835011361
Short name T145
Test name
Test status
Simulation time 16625096753 ps
CPU time 1035.81 seconds
Started May 07 03:15:32 PM PDT 24
Finished May 07 03:32:49 PM PDT 24
Peak memory 265540 kb
Host smart-9cf86ac1-c671-4893-ab93-e2d46e03c39f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835011361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3835011361
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3402591932
Short name T301
Test name
Test status
Simulation time 1469656009 ps
CPU time 43.38 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:16:49 PM PDT 24
Peak memory 239932 kb
Host smart-053720db-227b-4c88-b5a2-fceb5f4e75c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3402591932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3402591932
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.729180941
Short name T157
Test name
Test status
Simulation time 37240325326 ps
CPU time 592.91 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:25:56 PM PDT 24
Peak memory 265400 kb
Host smart-182a7d57-15be-4fcb-8a00-dc3d3dbc8984
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729180941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.729180941
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3826112867
Short name T303
Test name
Test status
Simulation time 49865821762 ps
CPU time 3042.86 seconds
Started May 07 02:08:53 PM PDT 24
Finished May 07 02:59:37 PM PDT 24
Peak memory 289348 kb
Host smart-e2781b01-a1b1-4559-ba3b-27ed36241361
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826112867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3826112867
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3540186095
Short name T342
Test name
Test status
Simulation time 105857558346 ps
CPU time 1628.08 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:36:25 PM PDT 24
Peak memory 268492 kb
Host smart-9d0476aa-dca2-4c74-b5ae-a928f997b657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540186095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3540186095
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2660915456
Short name T358
Test name
Test status
Simulation time 44151882530 ps
CPU time 859.15 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:24:08 PM PDT 24
Peak memory 283520 kb
Host smart-10b1977a-d9a7-4d36-a884-4d771a01d6f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660915456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2660915456
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.1917050205
Short name T300
Test name
Test status
Simulation time 27069897300 ps
CPU time 1510.2 seconds
Started May 07 02:09:51 PM PDT 24
Finished May 07 02:35:02 PM PDT 24
Peak memory 281704 kb
Host smart-381c9049-53ac-4783-b948-b27cdf688362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917050205 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.1917050205
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3747351763
Short name T291
Test name
Test status
Simulation time 3185466271 ps
CPU time 17.66 seconds
Started May 07 02:09:49 PM PDT 24
Finished May 07 02:10:07 PM PDT 24
Peak memory 255488 kb
Host smart-070aa798-93eb-46c2-96fd-c213f00f056c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37473
51763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3747351763
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.93064642
Short name T280
Test name
Test status
Simulation time 71039168169 ps
CPU time 2248.25 seconds
Started May 07 02:09:55 PM PDT 24
Finished May 07 02:47:24 PM PDT 24
Peak memory 289060 kb
Host smart-95b546ca-ec37-4088-a37e-8849d6ad02df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93064642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_hand
ler_stress_all.93064642
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.340696293
Short name T258
Test name
Test status
Simulation time 4829564196 ps
CPU time 86.09 seconds
Started May 07 02:10:41 PM PDT 24
Finished May 07 02:12:08 PM PDT 24
Peak memory 256940 kb
Host smart-a498de8e-5551-431e-ba4a-c28711f028f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
6293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.340696293
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4290028166
Short name T223
Test name
Test status
Simulation time 522627849009 ps
CPU time 5913.37 seconds
Started May 07 02:10:50 PM PDT 24
Finished May 07 03:49:24 PM PDT 24
Peak memory 363292 kb
Host smart-dd4e0fc8-a8b2-4c47-9cc8-6b76bf380035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290028166 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4290028166
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.963569361
Short name T71
Test name
Test status
Simulation time 19935720194 ps
CPU time 1634.62 seconds
Started May 07 02:10:54 PM PDT 24
Finished May 07 02:38:10 PM PDT 24
Peak memory 289800 kb
Host smart-589af458-b62f-4387-b293-3a50cb50bab9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963569361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.963569361
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.880464056
Short name T604
Test name
Test status
Simulation time 155721012 ps
CPU time 16.19 seconds
Started May 07 02:11:02 PM PDT 24
Finished May 07 02:11:19 PM PDT 24
Peak memory 248776 kb
Host smart-40690ae6-0bdf-401b-bc1b-563fabc1bdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88046
4056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.880464056
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2439969227
Short name T106
Test name
Test status
Simulation time 4476592680 ps
CPU time 723.87 seconds
Started May 07 02:11:14 PM PDT 24
Finished May 07 02:23:18 PM PDT 24
Peak memory 272328 kb
Host smart-cc9f1f5d-3151-448e-94b9-f6d7e42d7b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439969227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2439969227
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3357121044
Short name T109
Test name
Test status
Simulation time 240282063926 ps
CPU time 7601.98 seconds
Started May 07 02:12:30 PM PDT 24
Finished May 07 04:19:14 PM PDT 24
Peak memory 321948 kb
Host smart-0c749d59-4e40-41a0-95ad-1a5e4c7ffb03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357121044 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3357121044
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3351937634
Short name T299
Test name
Test status
Simulation time 50380304041 ps
CPU time 2871.37 seconds
Started May 07 02:13:24 PM PDT 24
Finished May 07 03:01:16 PM PDT 24
Peak memory 289756 kb
Host smart-be8cc688-e5fb-43c3-934d-7c55a062a233
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351937634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3351937634
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.396343560
Short name T288
Test name
Test status
Simulation time 12232753308 ps
CPU time 613.32 seconds
Started May 07 02:14:16 PM PDT 24
Finished May 07 02:24:30 PM PDT 24
Peak memory 269968 kb
Host smart-9f8c59a8-6670-4459-a3c9-5199692c9aa1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396343560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.396343560
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1755504269
Short name T42
Test name
Test status
Simulation time 59225322020 ps
CPU time 2945.87 seconds
Started May 07 02:08:15 PM PDT 24
Finished May 07 02:57:23 PM PDT 24
Peak memory 289092 kb
Host smart-cb62aec0-c560-40c9-bf8f-a70474bfa55f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755504269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1755504269
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3872502294
Short name T181
Test name
Test status
Simulation time 361545704 ps
CPU time 41.23 seconds
Started May 07 03:15:39 PM PDT 24
Finished May 07 03:16:21 PM PDT 24
Peak memory 245120 kb
Host smart-63168356-49cb-41fa-b0e6-76f768f0e2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3872502294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3872502294
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1008414440
Short name T160
Test name
Test status
Simulation time 767462514 ps
CPU time 88.65 seconds
Started May 07 03:16:00 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 257176 kb
Host smart-a482376b-4b72-482f-bcc4-0623fe20d4d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1008414440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1008414440
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2221903747
Short name T177
Test name
Test status
Simulation time 5177681709 ps
CPU time 86.06 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:17:13 PM PDT 24
Peak memory 238256 kb
Host smart-3fc50cb5-dbcb-4a34-9a2b-f9a99710e687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2221903747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2221903747
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2692292668
Short name T169
Test name
Test status
Simulation time 8691141949 ps
CPU time 270.28 seconds
Started May 07 03:15:36 PM PDT 24
Finished May 07 03:20:07 PM PDT 24
Peak memory 265528 kb
Host smart-ed14aed9-733e-4c75-abd0-a5cb8fa3a634
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692292668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2692292668
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.697270846
Short name T179
Test name
Test status
Simulation time 507426332 ps
CPU time 3.96 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:04 PM PDT 24
Peak memory 236952 kb
Host smart-aae9a8f4-9aae-42aa-b34f-93344771ef14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=697270846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.697270846
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2260311613
Short name T180
Test name
Test status
Simulation time 112429655 ps
CPU time 4.17 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:04 PM PDT 24
Peak memory 237280 kb
Host smart-b05e5eeb-c405-413f-9b71-00884d703445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2260311613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2260311613
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.28938931
Short name T162
Test name
Test status
Simulation time 5093577133 ps
CPU time 88.45 seconds
Started May 07 03:15:57 PM PDT 24
Finished May 07 03:17:26 PM PDT 24
Peak memory 265432 kb
Host smart-274bf67d-c221-4513-9f22-5e595e80ecd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=28938931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_error
s.28938931
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.860971428
Short name T185
Test name
Test status
Simulation time 1843091415 ps
CPU time 67.27 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:17:07 PM PDT 24
Peak memory 239820 kb
Host smart-51613ae0-8be4-4c35-87d9-89e35ee2b650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=860971428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.860971428
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.182010591
Short name T172
Test name
Test status
Simulation time 711725041 ps
CPU time 49.65 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:16:56 PM PDT 24
Peak memory 249936 kb
Host smart-cf270096-c8bc-4fb1-9951-3233cbd9eaff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=182010591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.182010591
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2217359778
Short name T171
Test name
Test status
Simulation time 121758877 ps
CPU time 5.9 seconds
Started May 07 03:15:45 PM PDT 24
Finished May 07 03:15:52 PM PDT 24
Peak memory 236952 kb
Host smart-d55a7c63-0a5f-4764-9946-69c51cab6dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2217359778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2217359778
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.173214665
Short name T182
Test name
Test status
Simulation time 106590079 ps
CPU time 2.75 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:16:00 PM PDT 24
Peak memory 235980 kb
Host smart-77a06bd1-b74c-40f7-8621-fcb4991f86b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=173214665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.173214665
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.63133378
Short name T183
Test name
Test status
Simulation time 115201620 ps
CPU time 2.79 seconds
Started May 07 03:15:57 PM PDT 24
Finished May 07 03:16:00 PM PDT 24
Peak memory 235824 kb
Host smart-6cf054fe-928b-4aad-af46-cb0a743b140e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=63133378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.63133378
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3948440588
Short name T186
Test name
Test status
Simulation time 1154173434 ps
CPU time 69.14 seconds
Started May 07 03:15:37 PM PDT 24
Finished May 07 03:16:48 PM PDT 24
Peak memory 237380 kb
Host smart-43a7430b-23c9-4b5b-8ec2-f5268abc15ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3948440588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3948440588
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.962905700
Short name T192
Test name
Test status
Simulation time 998935946 ps
CPU time 18.5 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:16:21 PM PDT 24
Peak memory 245328 kb
Host smart-07dd9ee1-eca7-424d-9743-c62ff5066a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=962905700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.962905700
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1546151041
Short name T193
Test name
Test status
Simulation time 35167744 ps
CPU time 2.17 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:15:50 PM PDT 24
Peak memory 236940 kb
Host smart-587aaaa0-073b-45fa-9fb7-8b116b7b8756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1546151041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1546151041
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.517313349
Short name T191
Test name
Test status
Simulation time 105337550 ps
CPU time 2.46 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:15:49 PM PDT 24
Peak memory 237412 kb
Host smart-233674da-b028-4a25-a5f0-62e6e8bc62aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=517313349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.517313349
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2494168026
Short name T173
Test name
Test status
Simulation time 95377515 ps
CPU time 2.58 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:15:55 PM PDT 24
Peak memory 237332 kb
Host smart-8a062e12-767a-427d-9f52-a0c5f456f61e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2494168026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2494168026
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.810066524
Short name T22
Test name
Test status
Simulation time 73760779574 ps
CPU time 2411.87 seconds
Started May 07 02:08:33 PM PDT 24
Finished May 07 02:48:46 PM PDT 24
Peak memory 281604 kb
Host smart-e2c4f807-6094-4d57-8e12-020a1ef9da89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810066524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.810066524
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1331690377
Short name T187
Test name
Test status
Simulation time 13587119674 ps
CPU time 154.84 seconds
Started May 07 03:15:33 PM PDT 24
Finished May 07 03:18:09 PM PDT 24
Peak memory 240500 kb
Host smart-4a0d29b6-5850-4899-ab58-3516ae43061f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1331690377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1331690377
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2471264674
Short name T742
Test name
Test status
Simulation time 243772610 ps
CPU time 9.41 seconds
Started May 07 03:15:32 PM PDT 24
Finished May 07 03:15:42 PM PDT 24
Peak memory 240496 kb
Host smart-4f70df51-b80a-435c-9dbe-e000a180b00c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2471264674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2471264674
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3982255616
Short name T799
Test name
Test status
Simulation time 198265320 ps
CPU time 7.76 seconds
Started May 07 03:15:35 PM PDT 24
Finished May 07 03:15:43 PM PDT 24
Peak memory 239120 kb
Host smart-c51b7609-f18f-4ff5-8209-37a70b4d7712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982255616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3982255616
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.216506880
Short name T804
Test name
Test status
Simulation time 63155805 ps
CPU time 3.13 seconds
Started May 07 03:15:34 PM PDT 24
Finished May 07 03:15:38 PM PDT 24
Peak memory 236820 kb
Host smart-e810c102-7ac5-4f97-a7c4-1f15a7f9a16c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=216506880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.216506880
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.584768644
Short name T369
Test name
Test status
Simulation time 11489527 ps
CPU time 1.53 seconds
Started May 07 03:15:36 PM PDT 24
Finished May 07 03:15:38 PM PDT 24
Peak memory 235988 kb
Host smart-3204a254-5342-49a7-a7f6-c78a6ada47cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=584768644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.584768644
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2540446520
Short name T767
Test name
Test status
Simulation time 678864584 ps
CPU time 22.58 seconds
Started May 07 03:15:34 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 245148 kb
Host smart-58e1ecbe-9d89-401a-a5b6-8506c039de83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2540446520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2540446520
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1879738958
Short name T141
Test name
Test status
Simulation time 4093878976 ps
CPU time 152.05 seconds
Started May 07 03:15:32 PM PDT 24
Finished May 07 03:18:05 PM PDT 24
Peak memory 257240 kb
Host smart-5dc26e8d-c68a-4254-a5f1-ea6e5a239cb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1879738958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1879738958
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.788481078
Short name T167
Test name
Test status
Simulation time 34571762367 ps
CPU time 484.52 seconds
Started May 07 03:15:32 PM PDT 24
Finished May 07 03:23:37 PM PDT 24
Peak memory 265420 kb
Host smart-7c5188dc-727e-4aa3-abef-adc237da6e8b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788481078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.788481078
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1319016968
Short name T738
Test name
Test status
Simulation time 246198385 ps
CPU time 16.75 seconds
Started May 07 03:15:28 PM PDT 24
Finished May 07 03:15:46 PM PDT 24
Peak memory 248764 kb
Host smart-7a535eaa-c104-406d-96e5-efe468ec905a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1319016968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1319016968
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1781560141
Short name T376
Test name
Test status
Simulation time 1776374983 ps
CPU time 95.19 seconds
Started May 07 03:15:34 PM PDT 24
Finished May 07 03:17:10 PM PDT 24
Peak memory 236956 kb
Host smart-88cd3057-078f-40cc-bca5-7809be5fc794
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1781560141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1781560141
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3490152532
Short name T744
Test name
Test status
Simulation time 16336433774 ps
CPU time 108.54 seconds
Started May 07 03:15:33 PM PDT 24
Finished May 07 03:17:22 PM PDT 24
Peak memory 236816 kb
Host smart-3b5ea371-0cfc-4864-ae4b-bf531d172e52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3490152532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3490152532
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.19561190
Short name T792
Test name
Test status
Simulation time 317755877 ps
CPU time 6 seconds
Started May 07 03:15:34 PM PDT 24
Finished May 07 03:15:40 PM PDT 24
Peak memory 240416 kb
Host smart-81e69f92-e858-4c5a-91ae-4358bbed531b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=19561190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.19561190
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3508719015
Short name T807
Test name
Test status
Simulation time 870634905 ps
CPU time 7.8 seconds
Started May 07 03:15:33 PM PDT 24
Finished May 07 03:15:42 PM PDT 24
Peak memory 239724 kb
Host smart-620e3a23-5b58-455d-aeaa-bf8d2b3bfb4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508719015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3508719015
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3615209905
Short name T835
Test name
Test status
Simulation time 49268697 ps
CPU time 4.45 seconds
Started May 07 03:15:36 PM PDT 24
Finished May 07 03:15:41 PM PDT 24
Peak memory 236880 kb
Host smart-01d9a60b-3de2-49cb-8726-5957fd0e482c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3615209905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3615209905
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2742861671
Short name T743
Test name
Test status
Simulation time 9639040 ps
CPU time 1.31 seconds
Started May 07 03:15:32 PM PDT 24
Finished May 07 03:15:34 PM PDT 24
Peak memory 236972 kb
Host smart-9d0f0685-2ec3-437e-9740-09b15896fd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2742861671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2742861671
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.113177008
Short name T780
Test name
Test status
Simulation time 1444145077 ps
CPU time 25.23 seconds
Started May 07 03:15:36 PM PDT 24
Finished May 07 03:16:02 PM PDT 24
Peak memory 248660 kb
Host smart-5a0028ef-1e92-4796-a1ac-caf23d0eb7f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=113177008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.113177008
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3647116966
Short name T764
Test name
Test status
Simulation time 774441834 ps
CPU time 10.05 seconds
Started May 07 03:15:35 PM PDT 24
Finished May 07 03:15:46 PM PDT 24
Peak memory 248736 kb
Host smart-52a5d3a5-c283-4f1a-8e6a-38675035e6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3647116966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3647116966
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1898186099
Short name T374
Test name
Test status
Simulation time 34641978 ps
CPU time 5.29 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:05 PM PDT 24
Peak memory 241360 kb
Host smart-e085a52f-1728-4a26-9778-61c532cfdd87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898186099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1898186099
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3122672545
Short name T797
Test name
Test status
Simulation time 19740702 ps
CPU time 3.65 seconds
Started May 07 03:15:54 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 236868 kb
Host smart-d3a970a1-820e-4328-b06e-6616c5c6fc9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3122672545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3122672545
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2454642819
Short name T803
Test name
Test status
Simulation time 27203515 ps
CPU time 1.38 seconds
Started May 07 03:15:51 PM PDT 24
Finished May 07 03:15:54 PM PDT 24
Peak memory 236956 kb
Host smart-c2c36a20-4d26-49f3-a98e-cfe654ea1518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2454642819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2454642819
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1728766632
Short name T210
Test name
Test status
Simulation time 335027328 ps
CPU time 21.39 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:21 PM PDT 24
Peak memory 245108 kb
Host smart-9b28e07e-e65c-4205-b371-14800065e9f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1728766632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1728766632
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1452749233
Short name T830
Test name
Test status
Simulation time 2366403991 ps
CPU time 259.39 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:20:12 PM PDT 24
Peak memory 265480 kb
Host smart-69416b91-e85a-4893-932c-c8a0e0107afe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452749233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1452749233
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3091416077
Short name T731
Test name
Test status
Simulation time 534973532 ps
CPU time 7.54 seconds
Started May 07 03:16:00 PM PDT 24
Finished May 07 03:16:08 PM PDT 24
Peak memory 247176 kb
Host smart-a07a340b-59bc-4d8a-9231-b1f1c6ba3f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3091416077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3091416077
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1111722614
Short name T824
Test name
Test status
Simulation time 98720120 ps
CPU time 4.71 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 237096 kb
Host smart-6280163f-d838-4063-8584-dbb971682447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111722614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1111722614
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1201772843
Short name T810
Test name
Test status
Simulation time 363217520 ps
CPU time 7.4 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:16:04 PM PDT 24
Peak memory 240368 kb
Host smart-e4d871f2-dcd5-46e0-a620-a8d8f5764a61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1201772843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1201772843
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1381763566
Short name T370
Test name
Test status
Simulation time 12007838 ps
CPU time 1.29 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:15:59 PM PDT 24
Peak memory 236932 kb
Host smart-78d08be6-38ce-45b9-ad37-592b23e1ca65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1381763566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1381763566
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4260898189
Short name T737
Test name
Test status
Simulation time 529100497 ps
CPU time 37.66 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:16:33 PM PDT 24
Peak memory 245208 kb
Host smart-156ed48f-3e01-4c58-a191-0e25fa77b0d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4260898189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4260898189
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1870865732
Short name T164
Test name
Test status
Simulation time 10299555318 ps
CPU time 166.91 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:18:43 PM PDT 24
Peak memory 265432 kb
Host smart-2b544c72-f602-4d7b-9064-603e75c02af3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1870865732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1870865732
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2865770314
Short name T730
Test name
Test status
Simulation time 28446392 ps
CPU time 3.85 seconds
Started May 07 03:15:53 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 240556 kb
Host smart-045e6348-bd88-4954-accf-19cb85fcdfec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865770314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2865770314
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4283003977
Short name T785
Test name
Test status
Simulation time 32985101 ps
CPU time 5.3 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 241388 kb
Host smart-fe43266f-3c20-4490-9ac6-7ff767df701f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283003977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4283003977
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3689017866
Short name T748
Test name
Test status
Simulation time 98970748 ps
CPU time 8.89 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:09 PM PDT 24
Peak memory 236832 kb
Host smart-68e06293-626a-4ca2-9e78-2c93b227cc78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3689017866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3689017866
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2149784725
Short name T839
Test name
Test status
Simulation time 18073510 ps
CPU time 1.45 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 236976 kb
Host smart-db6a3e95-0866-4ca9-b4f9-168e32fcf392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149784725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2149784725
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1410445032
Short name T747
Test name
Test status
Simulation time 1045204529 ps
CPU time 33.34 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:34 PM PDT 24
Peak memory 245136 kb
Host smart-dd83ed99-d3d5-4460-9b10-4ec733727b6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1410445032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1410445032
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2738968665
Short name T154
Test name
Test status
Simulation time 4845571049 ps
CPU time 145.88 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:18:23 PM PDT 24
Peak memory 265604 kb
Host smart-21bd49d3-9952-4974-8076-5528775275fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2738968665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2738968665
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2360660114
Short name T166
Test name
Test status
Simulation time 15396222702 ps
CPU time 653.42 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:26:49 PM PDT 24
Peak memory 265388 kb
Host smart-2dedc625-77d6-4a35-ae88-ed2456a57923
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360660114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2360660114
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.694256633
Short name T729
Test name
Test status
Simulation time 742852879 ps
CPU time 13.1 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 248744 kb
Host smart-bf6de6d2-a9a6-49ec-8012-8f3b1f39c596
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=694256633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.694256633
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.452564165
Short name T761
Test name
Test status
Simulation time 134007723 ps
CPU time 11.47 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 251096 kb
Host smart-969c4799-816e-499a-a1fb-0e51af83b354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452564165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.452564165
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2933899025
Short name T813
Test name
Test status
Simulation time 33878751 ps
CPU time 3.4 seconds
Started May 07 03:16:00 PM PDT 24
Finished May 07 03:16:04 PM PDT 24
Peak memory 239712 kb
Host smart-27ea55ff-7a39-4979-9c28-946ff5890312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2933899025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2933899025
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2728014471
Short name T831
Test name
Test status
Simulation time 9879012 ps
CPU time 1.57 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:01 PM PDT 24
Peak memory 236944 kb
Host smart-d8772793-2269-4d4c-a0cc-66e6ebb76e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728014471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2728014471
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2067315902
Short name T753
Test name
Test status
Simulation time 700490313 ps
CPU time 47.14 seconds
Started May 07 03:15:57 PM PDT 24
Finished May 07 03:16:46 PM PDT 24
Peak memory 248684 kb
Host smart-a51742bf-a491-46c5-b6b0-ea3d4420b2ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2067315902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2067315902
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1930410307
Short name T149
Test name
Test status
Simulation time 6070867629 ps
CPU time 397.32 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:22:35 PM PDT 24
Peak memory 265432 kb
Host smart-f09568e2-ccdc-4ab1-878d-270c2fc22ec4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1930410307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1930410307
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2482914173
Short name T159
Test name
Test status
Simulation time 49448539081 ps
CPU time 483.7 seconds
Started May 07 03:15:56 PM PDT 24
Finished May 07 03:24:01 PM PDT 24
Peak memory 265420 kb
Host smart-76ab8373-c43f-44de-b9f9-025f47ef1e65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482914173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2482914173
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.623478158
Short name T818
Test name
Test status
Simulation time 529392998 ps
CPU time 8.17 seconds
Started May 07 03:15:57 PM PDT 24
Finished May 07 03:16:07 PM PDT 24
Peak memory 253080 kb
Host smart-04db8c77-97c0-4a19-8a6b-6e4566b0313f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=623478158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.623478158
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2249419347
Short name T812
Test name
Test status
Simulation time 603696729 ps
CPU time 18.69 seconds
Started May 07 03:16:00 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 239724 kb
Host smart-d5fb30d0-b71a-4a0e-ae91-368ba743ab16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2249419347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2249419347
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.409270295
Short name T790
Test name
Test status
Simulation time 128646020 ps
CPU time 5.12 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:16:01 PM PDT 24
Peak memory 248848 kb
Host smart-4db4d469-9061-4e9e-a12c-6cf75dde2c69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409270295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.409270295
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.567298846
Short name T377
Test name
Test status
Simulation time 147319674 ps
CPU time 3.45 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:16:10 PM PDT 24
Peak memory 236876 kb
Host smart-945c4231-80a7-4b32-ae67-ed99ccfeb237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=567298846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.567298846
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3924898417
Short name T189
Test name
Test status
Simulation time 540804756 ps
CPU time 10.91 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 248684 kb
Host smart-715286ba-00a0-4ac2-9d2f-f4376c8bed60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3924898417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3924898417
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.344910033
Short name T822
Test name
Test status
Simulation time 210583363 ps
CPU time 14.08 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 253308 kb
Host smart-39d288b1-822f-485e-9922-f5c77484bcca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344910033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.344910033
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3076443141
Short name T763
Test name
Test status
Simulation time 112026097 ps
CPU time 4.62 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:05 PM PDT 24
Peak memory 239148 kb
Host smart-358d7870-5d6c-4f85-8b84-66834764c036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076443141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3076443141
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1629826731
Short name T751
Test name
Test status
Simulation time 120342837 ps
CPU time 9.13 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:09 PM PDT 24
Peak memory 240368 kb
Host smart-7c627e30-9a26-416b-8ae0-2584c04a6f4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1629826731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1629826731
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3511115086
Short name T734
Test name
Test status
Simulation time 722168819 ps
CPU time 22.54 seconds
Started May 07 03:15:58 PM PDT 24
Finished May 07 03:16:22 PM PDT 24
Peak memory 245084 kb
Host smart-250d3d46-5272-43ba-8d4b-197028845484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3511115086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3511115086
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1638430651
Short name T151
Test name
Test status
Simulation time 6166870772 ps
CPU time 461.54 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:23:48 PM PDT 24
Peak memory 271764 kb
Host smart-e3689993-93b9-4892-9399-e10ea373e8d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638430651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1638430651
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2954894304
Short name T275
Test name
Test status
Simulation time 175674473 ps
CPU time 11.48 seconds
Started May 07 03:15:59 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 246856 kb
Host smart-67dc5251-81b3-41da-9626-1234bd836689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2954894304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2954894304
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.363338560
Short name T789
Test name
Test status
Simulation time 206677843 ps
CPU time 7.19 seconds
Started May 07 03:16:03 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 239824 kb
Host smart-53b8bf16-8628-4a65-8347-bd4add1e3cda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363338560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.363338560
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1349604707
Short name T209
Test name
Test status
Simulation time 187828698 ps
CPU time 4.09 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:16:07 PM PDT 24
Peak memory 236864 kb
Host smart-68e05a3b-40af-4b36-85d0-f704eae1634c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1349604707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1349604707
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3124605590
Short name T276
Test name
Test status
Simulation time 21742181 ps
CPU time 1.29 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:16:06 PM PDT 24
Peak memory 235024 kb
Host smart-99ffe17f-be59-4d57-871c-22a47685b800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3124605590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3124605590
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3648627679
Short name T211
Test name
Test status
Simulation time 2607961262 ps
CPU time 20.51 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:16:26 PM PDT 24
Peak memory 245204 kb
Host smart-f8526c2f-772e-4fe2-9992-f99ac8be14e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3648627679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3648627679
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2717010885
Short name T833
Test name
Test status
Simulation time 1008114976 ps
CPU time 100.31 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:17:44 PM PDT 24
Peak memory 257132 kb
Host smart-c9b03bf4-4394-40c6-8beb-22c6f4d60721
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2717010885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2717010885
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.336787719
Short name T155
Test name
Test status
Simulation time 7051185676 ps
CPU time 463.2 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:23:46 PM PDT 24
Peak memory 269016 kb
Host smart-44178609-160d-4da5-97cc-097e33be1212
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336787719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.336787719
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2653557738
Short name T736
Test name
Test status
Simulation time 151994376 ps
CPU time 10.56 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 248136 kb
Host smart-061da4a2-72c7-4f54-82c3-9ec307ce9b43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2653557738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2653557738
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3362337557
Short name T739
Test name
Test status
Simulation time 42918069 ps
CPU time 5.44 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:16:08 PM PDT 24
Peak memory 256732 kb
Host smart-21cfa8aa-bf79-4b0c-bbfa-581101d7dd36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362337557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3362337557
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2285138634
Short name T190
Test name
Test status
Simulation time 106560746 ps
CPU time 3.24 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 236868 kb
Host smart-59b2f2a9-0793-4acc-ba26-89045b650a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2285138634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2285138634
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.80194532
Short name T823
Test name
Test status
Simulation time 12011098 ps
CPU time 1.58 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 236964 kb
Host smart-19b2e6a4-e24e-429b-9f5a-fe7a4a28319a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=80194532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.80194532
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3392823610
Short name T188
Test name
Test status
Simulation time 4027952332 ps
CPU time 45.03 seconds
Started May 07 03:16:03 PM PDT 24
Finished May 07 03:16:50 PM PDT 24
Peak memory 248748 kb
Host smart-771d4529-c715-4ed9-9c24-3873bcddb8db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3392823610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3392823610
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3407690156
Short name T787
Test name
Test status
Simulation time 1367136881 ps
CPU time 20.57 seconds
Started May 07 03:16:01 PM PDT 24
Finished May 07 03:16:22 PM PDT 24
Peak memory 248308 kb
Host smart-f8c47889-c387-4c9c-8608-44c5b413f8c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3407690156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3407690156
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.59450039
Short name T302
Test name
Test status
Simulation time 124165808 ps
CPU time 2.67 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:16:08 PM PDT 24
Peak memory 237024 kb
Host smart-5468b2cf-3f1f-47d8-a433-5e9f9bd54b63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=59450039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.59450039
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2400300445
Short name T793
Test name
Test status
Simulation time 94636975 ps
CPU time 7 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 240340 kb
Host smart-14c77ece-b658-4db6-85a3-460e06f208bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2400300445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2400300445
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.464685769
Short name T768
Test name
Test status
Simulation time 9046132 ps
CPU time 1.55 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:16:08 PM PDT 24
Peak memory 236984 kb
Host smart-b3f7cc8a-e399-4a1e-b4cd-35b41c5ae422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464685769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.464685769
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1965623884
Short name T836
Test name
Test status
Simulation time 484424441 ps
CPU time 17.04 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 245128 kb
Host smart-c25dddde-d982-4ab1-bc37-472ed2318be3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1965623884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1965623884
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2701168705
Short name T158
Test name
Test status
Simulation time 4992688268 ps
CPU time 316.16 seconds
Started May 07 03:16:04 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 269360 kb
Host smart-7bb34078-5208-4f19-b80b-b37c574e69e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701168705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2701168705
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3275506865
Short name T837
Test name
Test status
Simulation time 2589916844 ps
CPU time 13.93 seconds
Started May 07 03:16:06 PM PDT 24
Finished May 07 03:16:21 PM PDT 24
Peak memory 248384 kb
Host smart-ee12c6e8-7640-4252-997f-37cd6082ca51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3275506865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3275506865
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1137492933
Short name T840
Test name
Test status
Simulation time 35895806 ps
CPU time 5.25 seconds
Started May 07 03:16:03 PM PDT 24
Finished May 07 03:16:09 PM PDT 24
Peak memory 256928 kb
Host smart-81b4f01d-ec44-448d-8e45-951381bb2a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137492933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1137492933
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.121767409
Short name T208
Test name
Test status
Simulation time 121208780 ps
CPU time 4.81 seconds
Started May 07 03:16:02 PM PDT 24
Finished May 07 03:16:08 PM PDT 24
Peak memory 236124 kb
Host smart-d23211d1-fbdc-4ff9-bb35-aed0d3aa68db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=121767409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.121767409
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4117210541
Short name T829
Test name
Test status
Simulation time 10087559 ps
CPU time 1.47 seconds
Started May 07 03:16:03 PM PDT 24
Finished May 07 03:16:06 PM PDT 24
Peak memory 236012 kb
Host smart-9b7e5ba6-0a45-4b33-a90d-81b41b802a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4117210541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4117210541
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2055517069
Short name T838
Test name
Test status
Simulation time 9496767999 ps
CPU time 29.6 seconds
Started May 07 03:16:03 PM PDT 24
Finished May 07 03:16:33 PM PDT 24
Peak memory 244228 kb
Host smart-73ca38c9-3100-426c-a6f6-bee70a5c9a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2055517069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2055517069
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3481550519
Short name T759
Test name
Test status
Simulation time 156209797 ps
CPU time 14.99 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:16:21 PM PDT 24
Peak memory 248420 kb
Host smart-8bb574f3-620e-42e0-ae26-e9d2ef2917ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3481550519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3481550519
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3666340423
Short name T783
Test name
Test status
Simulation time 937424759 ps
CPU time 34.4 seconds
Started May 07 03:16:05 PM PDT 24
Finished May 07 03:16:41 PM PDT 24
Peak memory 237064 kb
Host smart-6cd8e249-5d9b-4120-9f5e-47ae413d9795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3666340423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3666340423
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2341740141
Short name T273
Test name
Test status
Simulation time 18005642132 ps
CPU time 295.2 seconds
Started May 07 03:15:42 PM PDT 24
Finished May 07 03:20:38 PM PDT 24
Peak memory 238612 kb
Host smart-d44e366d-7230-4289-b703-343752680423
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2341740141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2341740141
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1930485738
Short name T796
Test name
Test status
Simulation time 1636991595 ps
CPU time 101.27 seconds
Started May 07 03:15:41 PM PDT 24
Finished May 07 03:17:23 PM PDT 24
Peak memory 240404 kb
Host smart-b707478b-0759-41e7-97af-49eaa7eae48d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1930485738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1930485738
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1244341423
Short name T741
Test name
Test status
Simulation time 480050899 ps
CPU time 9.57 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:15:50 PM PDT 24
Peak memory 240428 kb
Host smart-71eba60e-57c0-4683-89ac-8e427244299d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1244341423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1244341423
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3793749111
Short name T769
Test name
Test status
Simulation time 63217460 ps
CPU time 9.33 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:15:50 PM PDT 24
Peak memory 252824 kb
Host smart-cb135a92-67d1-4a72-92d6-206a0f9ee1a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793749111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3793749111
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1821380479
Short name T755
Test name
Test status
Simulation time 377721988 ps
CPU time 7.57 seconds
Started May 07 03:15:41 PM PDT 24
Finished May 07 03:15:49 PM PDT 24
Peak memory 240308 kb
Host smart-458726e5-a11e-4e7d-a859-857f663ad78a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1821380479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1821380479
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4215460713
Short name T175
Test name
Test status
Simulation time 6529106 ps
CPU time 1.45 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:15:42 PM PDT 24
Peak memory 236940 kb
Host smart-284b79f7-5f1d-49ac-a5a9-54812d1b8005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4215460713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4215460713
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4037376580
Short name T801
Test name
Test status
Simulation time 123941964 ps
CPU time 10.53 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:15:52 PM PDT 24
Peak memory 248692 kb
Host smart-262fd608-1d3c-47e1-be98-37d1dd04db5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4037376580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4037376580
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4061849870
Short name T143
Test name
Test status
Simulation time 1089424037 ps
CPU time 107.3 seconds
Started May 07 03:15:32 PM PDT 24
Finished May 07 03:17:20 PM PDT 24
Peak memory 265380 kb
Host smart-dfb029cc-c840-4851-8457-fa6357308691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4061849870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4061849870
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2229773275
Short name T773
Test name
Test status
Simulation time 199473721 ps
CPU time 6.37 seconds
Started May 07 03:15:35 PM PDT 24
Finished May 07 03:15:42 PM PDT 24
Peak memory 247812 kb
Host smart-6b1281a6-4c1f-4b14-9be8-ee2192eaf874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2229773275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2229773275
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2897701900
Short name T749
Test name
Test status
Simulation time 16028166 ps
CPU time 1.76 seconds
Started May 07 03:16:13 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 236032 kb
Host smart-09851a6f-0605-4263-a818-91d82b2e215d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2897701900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2897701900
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1414417543
Short name T816
Test name
Test status
Simulation time 7060623 ps
CPU time 1.39 seconds
Started May 07 03:16:08 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 236980 kb
Host smart-c70895b7-c0db-4ceb-a14f-bc9c6296a6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1414417543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1414417543
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1440135271
Short name T746
Test name
Test status
Simulation time 9715844 ps
CPU time 1.49 seconds
Started May 07 03:16:13 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 234996 kb
Host smart-842e7737-650e-4bd7-ae33-ec5320f853e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1440135271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1440135271
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.7547878
Short name T778
Test name
Test status
Simulation time 11453794 ps
CPU time 1.36 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 236940 kb
Host smart-da1a7377-eb0c-4d85-8b23-730601897e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=7547878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.7547878
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2353492051
Short name T811
Test name
Test status
Simulation time 8892042 ps
CPU time 1.5 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 234988 kb
Host smart-86ae2874-bff2-4c29-aac6-19c0096fd153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2353492051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2353492051
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.701037820
Short name T770
Test name
Test status
Simulation time 11375580 ps
CPU time 1.64 seconds
Started May 07 03:16:16 PM PDT 24
Finished May 07 03:16:20 PM PDT 24
Peak memory 236972 kb
Host smart-3c2a632e-9c96-4748-9311-0f79eea69a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701037820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.701037820
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3685298878
Short name T754
Test name
Test status
Simulation time 12671511 ps
CPU time 1.4 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 235952 kb
Host smart-45a75406-efde-4fc2-9812-c8852f8dc726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685298878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3685298878
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4140139193
Short name T777
Test name
Test status
Simulation time 6343937 ps
CPU time 1.29 seconds
Started May 07 03:16:08 PM PDT 24
Finished May 07 03:16:10 PM PDT 24
Peak memory 236964 kb
Host smart-4c88f625-119c-4f36-8d86-a68d83f0ba19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4140139193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4140139193
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3407499717
Short name T809
Test name
Test status
Simulation time 14998833 ps
CPU time 1.36 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 237028 kb
Host smart-c9114af0-c89b-441b-8a5f-c9642781e30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3407499717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3407499717
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.353749725
Short name T367
Test name
Test status
Simulation time 9849136 ps
CPU time 1.59 seconds
Started May 07 03:16:11 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 235924 kb
Host smart-070c7c74-bf67-41a1-a522-2b47ab8fd8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=353749725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.353749725
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.115257517
Short name T264
Test name
Test status
Simulation time 4796649199 ps
CPU time 294.49 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:20:42 PM PDT 24
Peak memory 240468 kb
Host smart-80605bcf-a415-44e6-8577-9772da4e12de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=115257517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.115257517
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3967083896
Short name T775
Test name
Test status
Simulation time 95180749122 ps
CPU time 360.33 seconds
Started May 07 03:15:42 PM PDT 24
Finished May 07 03:21:43 PM PDT 24
Peak memory 240492 kb
Host smart-e1efc297-ca1f-4a27-be7d-0685faf24f0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3967083896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3967083896
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3970737967
Short name T779
Test name
Test status
Simulation time 22455803 ps
CPU time 3.46 seconds
Started May 07 03:15:43 PM PDT 24
Finished May 07 03:15:48 PM PDT 24
Peak memory 240424 kb
Host smart-484218d9-5a7e-4947-891d-d2d0f8c3e1d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3970737967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3970737967
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3394140953
Short name T263
Test name
Test status
Simulation time 408594270 ps
CPU time 7.55 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:15:54 PM PDT 24
Peak memory 240516 kb
Host smart-889dbc5a-6d1a-407d-b9ac-a7ddddf01b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394140953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3394140953
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4009788448
Short name T776
Test name
Test status
Simulation time 529226398 ps
CPU time 7.98 seconds
Started May 07 03:15:38 PM PDT 24
Finished May 07 03:15:47 PM PDT 24
Peak memory 235904 kb
Host smart-63834277-a8fb-436a-a5e4-fa11361e0c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4009788448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4009788448
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.557531336
Short name T805
Test name
Test status
Simulation time 16081582 ps
CPU time 1.7 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:15:43 PM PDT 24
Peak memory 236960 kb
Host smart-40425416-e624-4724-a539-98f3f849f54b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=557531336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.557531336
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.395814194
Short name T752
Test name
Test status
Simulation time 1156339062 ps
CPU time 37.94 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:16:25 PM PDT 24
Peak memory 244196 kb
Host smart-2c27ebe8-3e13-403f-b1e4-bb1da2e38c1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=395814194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.395814194
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.613158257
Short name T147
Test name
Test status
Simulation time 30578133176 ps
CPU time 556.81 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:25:04 PM PDT 24
Peak memory 265192 kb
Host smart-c25656ef-ab22-4ec0-b183-88f4cbebdf87
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613158257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.613158257
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1894368061
Short name T732
Test name
Test status
Simulation time 164737144 ps
CPU time 12.72 seconds
Started May 07 03:15:39 PM PDT 24
Finished May 07 03:15:53 PM PDT 24
Peak memory 252544 kb
Host smart-c3ce1f27-b21a-40c2-ad0d-c5345cdf143d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1894368061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1894368061
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3536578834
Short name T806
Test name
Test status
Simulation time 7048421 ps
CPU time 1.32 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 236980 kb
Host smart-a8283c2d-1117-4765-b9b7-4206b77fd0d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3536578834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3536578834
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3248044311
Short name T815
Test name
Test status
Simulation time 6699750 ps
CPU time 1.44 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 236016 kb
Host smart-a802740e-0bd0-4754-81c5-0eca7d60b0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3248044311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3248044311
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.868936353
Short name T366
Test name
Test status
Simulation time 18023314 ps
CPU time 1.3 seconds
Started May 07 03:16:13 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 236964 kb
Host smart-8f3c55ff-4fac-4ddd-8e76-0c3206549963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=868936353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.868936353
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2802227694
Short name T176
Test name
Test status
Simulation time 10721823 ps
CPU time 1.34 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 234788 kb
Host smart-16e4612b-e4ed-4249-8a55-e35b329262b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2802227694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2802227694
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3927097497
Short name T757
Test name
Test status
Simulation time 9152800 ps
CPU time 1.49 seconds
Started May 07 03:16:07 PM PDT 24
Finished May 07 03:16:09 PM PDT 24
Peak memory 236012 kb
Host smart-c71adbc3-6e68-46a2-9e1e-67170cea6a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3927097497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3927097497
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3524229845
Short name T368
Test name
Test status
Simulation time 10648718 ps
CPU time 1.23 seconds
Started May 07 03:16:12 PM PDT 24
Finished May 07 03:16:15 PM PDT 24
Peak memory 236980 kb
Host smart-f2be560e-5d33-4b8d-bf4a-c237ae45d1d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3524229845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3524229845
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3627658036
Short name T772
Test name
Test status
Simulation time 7563474 ps
CPU time 1.29 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 235980 kb
Host smart-80db967d-70aa-4f75-a657-94cd6cfcc015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3627658036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3627658036
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3301206542
Short name T820
Test name
Test status
Simulation time 32519572 ps
CPU time 1.24 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 236004 kb
Host smart-42418f4a-692a-47ef-8809-cb9e13d4e10b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3301206542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3301206542
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2741015271
Short name T766
Test name
Test status
Simulation time 13730924 ps
CPU time 1.47 seconds
Started May 07 03:16:12 PM PDT 24
Finished May 07 03:16:15 PM PDT 24
Peak memory 236004 kb
Host smart-b2037950-187c-4676-911e-8833b9340443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2741015271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2741015271
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2222222777
Short name T791
Test name
Test status
Simulation time 25372356 ps
CPU time 1.46 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 236976 kb
Host smart-acd7bc6a-ce99-4618-9e84-aeb440533f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2222222777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2222222777
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3443969637
Short name T825
Test name
Test status
Simulation time 1631243484 ps
CPU time 116.79 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:17:38 PM PDT 24
Peak memory 236892 kb
Host smart-d43c4307-8b40-472d-9cbb-084fe85e14df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3443969637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3443969637
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2383805824
Short name T378
Test name
Test status
Simulation time 14263187567 ps
CPU time 378.75 seconds
Started May 07 03:15:47 PM PDT 24
Finished May 07 03:22:07 PM PDT 24
Peak memory 236004 kb
Host smart-0a9311a6-758f-46f3-b2ea-3dfec4c7550d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2383805824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2383805824
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1082022024
Short name T760
Test name
Test status
Simulation time 152054983 ps
CPU time 11.12 seconds
Started May 07 03:15:41 PM PDT 24
Finished May 07 03:15:53 PM PDT 24
Peak memory 240428 kb
Host smart-0aa69d6d-7082-46b1-80fc-2ca31a9befe7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1082022024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1082022024
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2841387098
Short name T375
Test name
Test status
Simulation time 154476804 ps
CPU time 12.31 seconds
Started May 07 03:15:43 PM PDT 24
Finished May 07 03:15:56 PM PDT 24
Peak memory 242792 kb
Host smart-7d762aad-30f4-458d-8de0-6588d4a4ae88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841387098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2841387098
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1898169746
Short name T782
Test name
Test status
Simulation time 20547061 ps
CPU time 3.8 seconds
Started May 07 03:15:37 PM PDT 24
Finished May 07 03:15:42 PM PDT 24
Peak memory 239708 kb
Host smart-7f9cce06-6af5-4f56-8357-c52530f7460b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1898169746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1898169746
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4145253325
Short name T821
Test name
Test status
Simulation time 22434299 ps
CPU time 1.4 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:15:48 PM PDT 24
Peak memory 236820 kb
Host smart-69be4404-bcda-4001-82f1-9993ba9c2585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145253325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4145253325
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.233752240
Short name T795
Test name
Test status
Simulation time 1525221272 ps
CPU time 25.34 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:16:06 PM PDT 24
Peak memory 245148 kb
Host smart-fb87b2df-9f00-4991-9393-441f09c65d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=233752240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.233752240
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3001234571
Short name T133
Test name
Test status
Simulation time 1012374888 ps
CPU time 119.8 seconds
Started May 07 03:15:40 PM PDT 24
Finished May 07 03:17:41 PM PDT 24
Peak memory 265392 kb
Host smart-ff2e912e-88a4-4cbd-92f1-8dc4950dadfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3001234571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3001234571
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3693456163
Short name T170
Test name
Test status
Simulation time 28269712164 ps
CPU time 923.13 seconds
Started May 07 03:15:41 PM PDT 24
Finished May 07 03:31:05 PM PDT 24
Peak memory 265436 kb
Host smart-14a1ee1a-702e-43c2-b601-6e3352731065
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693456163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3693456163
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3027960511
Short name T765
Test name
Test status
Simulation time 1841308955 ps
CPU time 28.73 seconds
Started May 07 03:15:39 PM PDT 24
Finished May 07 03:16:09 PM PDT 24
Peak memory 248708 kb
Host smart-9cbded35-c0ba-4746-81ee-a709ac752fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027960511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3027960511
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3933897761
Short name T827
Test name
Test status
Simulation time 8294186 ps
CPU time 1.47 seconds
Started May 07 03:16:10 PM PDT 24
Finished May 07 03:16:13 PM PDT 24
Peak memory 237028 kb
Host smart-f7e3ff2b-b84f-4425-a0ec-f3831e58deca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933897761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3933897761
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3136244594
Short name T794
Test name
Test status
Simulation time 9934043 ps
CPU time 1.21 seconds
Started May 07 03:16:09 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 236960 kb
Host smart-283c2044-203d-45fe-9110-cb550c70c178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136244594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3136244594
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2540427316
Short name T814
Test name
Test status
Simulation time 25957065 ps
CPU time 1.42 seconds
Started May 07 03:16:08 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 236964 kb
Host smart-35d3e57a-264f-4432-823c-55e1591f2763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2540427316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2540427316
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3394557474
Short name T826
Test name
Test status
Simulation time 7545137 ps
CPU time 1.46 seconds
Started May 07 03:16:11 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 236044 kb
Host smart-882f8ef0-88b5-4189-9484-8e65cac4e562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3394557474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3394557474
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.422235848
Short name T781
Test name
Test status
Simulation time 7720424 ps
CPU time 1.3 seconds
Started May 07 03:16:11 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 234988 kb
Host smart-ca7a7e94-cc3b-4642-a1ad-3e02373574c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=422235848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.422235848
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.637732802
Short name T758
Test name
Test status
Simulation time 8604018 ps
CPU time 1.36 seconds
Started May 07 03:16:12 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 237148 kb
Host smart-238c503e-a925-4a5f-8354-449070f6850d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=637732802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.637732802
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1100189683
Short name T817
Test name
Test status
Simulation time 11938186 ps
CPU time 1.38 seconds
Started May 07 03:16:11 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 236924 kb
Host smart-ea5bf18a-8844-4909-8faf-1cc7806b96f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1100189683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1100189683
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.686811480
Short name T784
Test name
Test status
Simulation time 9825669 ps
CPU time 1.56 seconds
Started May 07 03:16:11 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 236040 kb
Host smart-19f343bb-2290-495e-9a6a-f709ad198daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=686811480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.686811480
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.269059980
Short name T800
Test name
Test status
Simulation time 7763427 ps
CPU time 1.32 seconds
Started May 07 03:16:12 PM PDT 24
Finished May 07 03:16:14 PM PDT 24
Peak memory 237148 kb
Host smart-b7976b5d-325e-4718-8bb2-3dd3be54b909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=269059980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.269059980
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.4003881455
Short name T798
Test name
Test status
Simulation time 13401000 ps
CPU time 1.31 seconds
Started May 07 03:16:15 PM PDT 24
Finished May 07 03:16:19 PM PDT 24
Peak memory 235024 kb
Host smart-fba55b11-05ed-465d-ab79-799b92abc01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4003881455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.4003881455
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.142831947
Short name T786
Test name
Test status
Simulation time 54231355 ps
CPU time 7.8 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:15:54 PM PDT 24
Peak memory 251684 kb
Host smart-4b345b9d-98ae-46d3-ae02-a05f262beb55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142831947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.142831947
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3131568083
Short name T834
Test name
Test status
Simulation time 329463485 ps
CPU time 8.03 seconds
Started May 07 03:15:50 PM PDT 24
Finished May 07 03:15:59 PM PDT 24
Peak memory 236864 kb
Host smart-7dda4130-310c-462c-809a-91bea13c431a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3131568083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3131568083
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2740007371
Short name T762
Test name
Test status
Simulation time 59885290 ps
CPU time 1.4 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:15:49 PM PDT 24
Peak memory 235896 kb
Host smart-00cdc42d-615c-4946-ba00-a29112bb1c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2740007371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2740007371
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1973118532
Short name T212
Test name
Test status
Simulation time 170972189 ps
CPU time 21.8 seconds
Started May 07 03:15:50 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 245140 kb
Host smart-b831a8c5-74d8-4d3d-b1c4-80ecdd3e5d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1973118532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1973118532
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1534285191
Short name T148
Test name
Test status
Simulation time 3228341139 ps
CPU time 101.6 seconds
Started May 07 03:15:48 PM PDT 24
Finished May 07 03:17:30 PM PDT 24
Peak memory 257244 kb
Host smart-c3ff8009-f22a-4826-aa64-6c94bcc24116
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1534285191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1534285191
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2706631360
Short name T819
Test name
Test status
Simulation time 1112450286 ps
CPU time 18.51 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:16:05 PM PDT 24
Peak memory 248392 kb
Host smart-eaaae89b-ddb7-42db-bf4a-1c5edb45afd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2706631360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2706631360
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2762422617
Short name T808
Test name
Test status
Simulation time 199099318 ps
CPU time 9.5 seconds
Started May 07 03:15:49 PM PDT 24
Finished May 07 03:15:59 PM PDT 24
Peak memory 239524 kb
Host smart-11194749-29fb-4e2a-8842-84cb3c7b135b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762422617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2762422617
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.659553953
Short name T788
Test name
Test status
Simulation time 119495816 ps
CPU time 5.32 seconds
Started May 07 03:15:48 PM PDT 24
Finished May 07 03:15:54 PM PDT 24
Peak memory 236868 kb
Host smart-26e00823-094f-48cc-ab6f-a7e03891c2c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=659553953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.659553953
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2630076196
Short name T174
Test name
Test status
Simulation time 12397856 ps
CPU time 1.28 seconds
Started May 07 03:15:45 PM PDT 24
Finished May 07 03:15:48 PM PDT 24
Peak memory 236028 kb
Host smart-6d112dcd-2577-49bf-a067-e39b73c7dacc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2630076196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2630076196
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2654498369
Short name T774
Test name
Test status
Simulation time 90260132 ps
CPU time 10.42 seconds
Started May 07 03:15:47 PM PDT 24
Finished May 07 03:15:59 PM PDT 24
Peak memory 240432 kb
Host smart-6fc2ec09-2d08-4c64-8ae1-15935559c155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2654498369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2654498369
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3173037649
Short name T156
Test name
Test status
Simulation time 7832032055 ps
CPU time 190.96 seconds
Started May 07 03:15:48 PM PDT 24
Finished May 07 03:18:59 PM PDT 24
Peak memory 271776 kb
Host smart-0835c979-072c-439b-b56f-4dde0eb2ea39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3173037649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3173037649
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2404888858
Short name T163
Test name
Test status
Simulation time 12662705127 ps
CPU time 915.66 seconds
Started May 07 03:15:48 PM PDT 24
Finished May 07 03:31:04 PM PDT 24
Peak memory 265452 kb
Host smart-89328032-39f0-488b-bec2-a02a2323446c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404888858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2404888858
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3938074980
Short name T733
Test name
Test status
Simulation time 1110755703 ps
CPU time 23.57 seconds
Started May 07 03:15:47 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 248256 kb
Host smart-c3064238-99f8-471b-ba36-b4aa38eeb535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3938074980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3938074980
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2782994388
Short name T373
Test name
Test status
Simulation time 99329296 ps
CPU time 7.56 seconds
Started May 07 03:15:49 PM PDT 24
Finished May 07 03:15:58 PM PDT 24
Peak memory 240556 kb
Host smart-926a5983-4dc0-49e0-ab31-2003044acccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782994388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2782994388
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2822412306
Short name T740
Test name
Test status
Simulation time 95763866 ps
CPU time 4 seconds
Started May 07 03:15:44 PM PDT 24
Finished May 07 03:15:49 PM PDT 24
Peak memory 235920 kb
Host smart-a2991a92-51e0-417a-9e4f-99596a430586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2822412306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2822412306
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2853030152
Short name T832
Test name
Test status
Simulation time 8777470 ps
CPU time 1.53 seconds
Started May 07 03:15:45 PM PDT 24
Finished May 07 03:15:47 PM PDT 24
Peak memory 236948 kb
Host smart-31f43414-3b74-43be-966a-15bc5164df34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2853030152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2853030152
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2185665933
Short name T735
Test name
Test status
Simulation time 169390118 ps
CPU time 24.68 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:16:12 PM PDT 24
Peak memory 248620 kb
Host smart-dcdc1007-2de8-4bfb-9e7e-51356ffd789a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2185665933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2185665933
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.739608404
Short name T153
Test name
Test status
Simulation time 21622468017 ps
CPU time 134.08 seconds
Started May 07 03:15:46 PM PDT 24
Finished May 07 03:18:01 PM PDT 24
Peak memory 257244 kb
Host smart-bd654217-c920-4a87-b1ba-6816cc6fc21a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=739608404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.739608404
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1022911109
Short name T274
Test name
Test status
Simulation time 185249617 ps
CPU time 14.22 seconds
Started May 07 03:15:45 PM PDT 24
Finished May 07 03:16:00 PM PDT 24
Peak memory 248464 kb
Host smart-942c49f0-f622-4ade-817b-f05e81b229ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1022911109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1022911109
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2835538243
Short name T756
Test name
Test status
Simulation time 99403244 ps
CPU time 7.46 seconds
Started May 07 03:15:54 PM PDT 24
Finished May 07 03:16:02 PM PDT 24
Peak memory 240524 kb
Host smart-ff3b7522-5ae1-4618-b531-536dec685e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835538243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2835538243
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4189954513
Short name T771
Test name
Test status
Simulation time 69967520 ps
CPU time 5.5 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:16:01 PM PDT 24
Peak memory 239656 kb
Host smart-4d2ea87f-83f1-4d5b-86f7-5cbc309508bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4189954513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.4189954513
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2016047699
Short name T364
Test name
Test status
Simulation time 12586800 ps
CPU time 1.28 seconds
Started May 07 03:15:55 PM PDT 24
Finished May 07 03:15:57 PM PDT 24
Peak memory 236972 kb
Host smart-ed30ee09-6dcf-42a0-8d6d-a01f5f40b65a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2016047699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2016047699
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.914314417
Short name T828
Test name
Test status
Simulation time 729890218 ps
CPU time 41.73 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:16:35 PM PDT 24
Peak memory 240376 kb
Host smart-f2dd87c5-6ad4-41c9-b872-cff31cf6a288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=914314417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.914314417
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3227513159
Short name T152
Test name
Test status
Simulation time 2466161357 ps
CPU time 360.24 seconds
Started May 07 03:15:48 PM PDT 24
Finished May 07 03:21:49 PM PDT 24
Peak memory 270380 kb
Host smart-f84402d2-75bd-431c-8a07-16cac2e00fe4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227513159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3227513159
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3471003427
Short name T802
Test name
Test status
Simulation time 515012057 ps
CPU time 9.83 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:16:02 PM PDT 24
Peak memory 248704 kb
Host smart-3e7530dc-561d-4298-9bb2-7e790f6ab0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3471003427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3471003427
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3950715499
Short name T745
Test name
Test status
Simulation time 54787103 ps
CPU time 4.59 seconds
Started May 07 03:15:53 PM PDT 24
Finished May 07 03:15:59 PM PDT 24
Peak memory 239388 kb
Host smart-b1d9a438-e498-4da4-b793-fa187e9b5d93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950715499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3950715499
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2551166112
Short name T207
Test name
Test status
Simulation time 96379929 ps
CPU time 7.9 seconds
Started May 07 03:16:00 PM PDT 24
Finished May 07 03:16:09 PM PDT 24
Peak memory 236840 kb
Host smart-b807a868-990e-40a7-9749-948456a506a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2551166112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2551166112
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1613556509
Short name T206
Test name
Test status
Simulation time 205744752 ps
CPU time 23.68 seconds
Started May 07 03:15:52 PM PDT 24
Finished May 07 03:16:17 PM PDT 24
Peak memory 245136 kb
Host smart-f122a69d-ef60-4687-9208-5668b72d7d29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1613556509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1613556509
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2889408549
Short name T750
Test name
Test status
Simulation time 571429997 ps
CPU time 7.16 seconds
Started May 07 03:15:53 PM PDT 24
Finished May 07 03:16:01 PM PDT 24
Peak memory 248656 kb
Host smart-e8e479b5-116a-48b3-8f66-c4d678f14d4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2889408549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2889408549
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.809025637
Short name T51
Test name
Test status
Simulation time 118007548327 ps
CPU time 1559.74 seconds
Started May 07 02:08:16 PM PDT 24
Finished May 07 02:34:17 PM PDT 24
Peak memory 273436 kb
Host smart-ae87dcdc-8259-4cab-8a86-c922ddf884bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809025637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.809025637
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1586861022
Short name T559
Test name
Test status
Simulation time 559595941 ps
CPU time 21.53 seconds
Started May 07 02:08:19 PM PDT 24
Finished May 07 02:08:41 PM PDT 24
Peak memory 240552 kb
Host smart-1e82c87c-c2c4-437c-b1fb-3a910518f0b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1586861022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1586861022
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.170355509
Short name T701
Test name
Test status
Simulation time 4140731088 ps
CPU time 75.51 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:09:30 PM PDT 24
Peak memory 256544 kb
Host smart-045cfb7a-c877-47d0-b7a7-b294f8f4d321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17035
5509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.170355509
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1989582828
Short name T91
Test name
Test status
Simulation time 802915009 ps
CPU time 25.18 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:08:41 PM PDT 24
Peak memory 248800 kb
Host smart-939e9013-855a-43ff-b2cc-b41087e6e5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
82828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1989582828
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2698791620
Short name T679
Test name
Test status
Simulation time 13745575551 ps
CPU time 159.07 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:10:54 PM PDT 24
Peak memory 247080 kb
Host smart-5c0bcfc2-ee58-4801-938b-bac9b633851d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698791620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2698791620
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3969423789
Short name T547
Test name
Test status
Simulation time 206428212 ps
CPU time 21.29 seconds
Started May 07 02:08:13 PM PDT 24
Finished May 07 02:08:36 PM PDT 24
Peak memory 248836 kb
Host smart-75fd60d7-3c5c-468c-abe4-276e66408f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39694
23789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3969423789
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.752096465
Short name T107
Test name
Test status
Simulation time 516084049 ps
CPU time 25.72 seconds
Started May 07 02:08:15 PM PDT 24
Finished May 07 02:08:42 PM PDT 24
Peak memory 255360 kb
Host smart-71f12007-c1af-4f6a-9259-061027ec4442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75209
6465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.752096465
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.83611503
Short name T31
Test name
Test status
Simulation time 432721556 ps
CPU time 23.05 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:08:38 PM PDT 24
Peak memory 274404 kb
Host smart-2db0c0ae-af6b-4457-9461-bc481be62619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=83611503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.83611503
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.122517564
Short name T549
Test name
Test status
Simulation time 333624239 ps
CPU time 20.83 seconds
Started May 07 02:08:16 PM PDT 24
Finished May 07 02:08:38 PM PDT 24
Peak memory 248896 kb
Host smart-d9e24d7f-e7ef-4d12-b81a-76db8b31427b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
7564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.122517564
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1620818523
Short name T566
Test name
Test status
Simulation time 386446209 ps
CPU time 37.56 seconds
Started May 07 02:08:14 PM PDT 24
Finished May 07 02:08:53 PM PDT 24
Peak memory 255160 kb
Host smart-ff6c2281-2080-42a9-8d82-9b810d0baef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208
18523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1620818523
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3981492553
Short name T59
Test name
Test status
Simulation time 35599634782 ps
CPU time 2171.49 seconds
Started May 07 02:08:15 PM PDT 24
Finished May 07 02:44:28 PM PDT 24
Peak memory 288508 kb
Host smart-801bb33b-8c22-4305-9189-8e59fb0e3445
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981492553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3981492553
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3504403025
Short name T626
Test name
Test status
Simulation time 52528743332 ps
CPU time 4779.32 seconds
Started May 07 02:08:12 PM PDT 24
Finished May 07 03:27:53 PM PDT 24
Peak memory 337768 kb
Host smart-43f870d4-fa9c-47a8-8cc7-63a297de16f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504403025 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3504403025
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.639780221
Short name T121
Test name
Test status
Simulation time 14403681254 ps
CPU time 1452.54 seconds
Started May 07 02:08:18 PM PDT 24
Finished May 07 02:32:32 PM PDT 24
Peak memory 289532 kb
Host smart-31dc9204-be81-4db8-aecc-bbc371f83c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639780221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.639780221
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3865282399
Short name T404
Test name
Test status
Simulation time 706163833 ps
CPU time 16.22 seconds
Started May 07 02:08:18 PM PDT 24
Finished May 07 02:08:35 PM PDT 24
Peak memory 248800 kb
Host smart-f172f769-e3b8-489a-ba67-f0dd40365070
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3865282399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3865282399
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2739636138
Short name T266
Test name
Test status
Simulation time 30641281317 ps
CPU time 135.08 seconds
Started May 07 02:08:13 PM PDT 24
Finished May 07 02:10:29 PM PDT 24
Peak memory 248900 kb
Host smart-8373d8dd-31f4-464b-8ad7-4b1f2512af56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27396
36138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2739636138
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3072230859
Short name T36
Test name
Test status
Simulation time 2994619279 ps
CPU time 26 seconds
Started May 07 02:08:13 PM PDT 24
Finished May 07 02:08:40 PM PDT 24
Peak memory 248772 kb
Host smart-3eda2b28-2258-441d-a096-f43b4a8edd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722
30859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3072230859
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1810345139
Short name T480
Test name
Test status
Simulation time 65198946328 ps
CPU time 2157.69 seconds
Started May 07 02:08:19 PM PDT 24
Finished May 07 02:44:18 PM PDT 24
Peak memory 270724 kb
Host smart-57444574-14e1-45d6-94ab-77fa5e1c0bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810345139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1810345139
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1777083058
Short name T330
Test name
Test status
Simulation time 50670214432 ps
CPU time 528.19 seconds
Started May 07 02:08:23 PM PDT 24
Finished May 07 02:17:11 PM PDT 24
Peak memory 248056 kb
Host smart-e93102e4-5df7-4ffd-b245-3d68e8166720
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777083058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1777083058
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.283052697
Short name T392
Test name
Test status
Simulation time 1040977385 ps
CPU time 60.03 seconds
Started May 07 02:08:19 PM PDT 24
Finished May 07 02:09:20 PM PDT 24
Peak memory 248748 kb
Host smart-783e93cd-7e00-4ffe-9036-ecf7a4773006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28305
2697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.283052697
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3552092454
Short name T680
Test name
Test status
Simulation time 726382942 ps
CPU time 28.84 seconds
Started May 07 02:08:17 PM PDT 24
Finished May 07 02:08:47 PM PDT 24
Peak memory 255980 kb
Host smart-fa4d459e-9964-4bae-8d73-881962d4d39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520
92454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3552092454
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1977797315
Short name T486
Test name
Test status
Simulation time 180468652 ps
CPU time 7.36 seconds
Started May 07 02:08:22 PM PDT 24
Finished May 07 02:08:30 PM PDT 24
Peak memory 248412 kb
Host smart-eb270537-1356-4d2b-8a85-6fb8d59770d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19777
97315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1977797315
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.11579979
Short name T509
Test name
Test status
Simulation time 1668509164 ps
CPU time 26.26 seconds
Started May 07 02:08:16 PM PDT 24
Finished May 07 02:08:43 PM PDT 24
Peak memory 248752 kb
Host smart-6a74af37-b3e2-48b2-8e1f-cbdbc46fb119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11579
979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.11579979
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1999032335
Short name T64
Test name
Test status
Simulation time 208955125400 ps
CPU time 1988.88 seconds
Started May 07 02:08:19 PM PDT 24
Finished May 07 02:41:30 PM PDT 24
Peak memory 273416 kb
Host smart-6f09e5ee-8cd6-49ee-b9f9-72a76a303422
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999032335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1999032335
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.582305519
Short name T236
Test name
Test status
Simulation time 100426912 ps
CPU time 3.59 seconds
Started May 07 02:08:55 PM PDT 24
Finished May 07 02:08:59 PM PDT 24
Peak memory 248948 kb
Host smart-770c461c-0710-4a17-b03d-a12638c00835
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=582305519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.582305519
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2704400969
Short name T462
Test name
Test status
Simulation time 358881353721 ps
CPU time 1237.09 seconds
Started May 07 02:08:50 PM PDT 24
Finished May 07 02:29:28 PM PDT 24
Peak memory 265284 kb
Host smart-54fafbeb-c60a-418c-882b-5b400464877b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704400969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2704400969
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2073360089
Short name T429
Test name
Test status
Simulation time 3276230950 ps
CPU time 34.46 seconds
Started May 07 02:08:53 PM PDT 24
Finished May 07 02:09:28 PM PDT 24
Peak memory 248828 kb
Host smart-aa9cfc20-2898-4c18-a1ac-0ae2bcceecb1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2073360089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2073360089
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3892234194
Short name T401
Test name
Test status
Simulation time 20006025 ps
CPU time 2.72 seconds
Started May 07 02:08:47 PM PDT 24
Finished May 07 02:08:51 PM PDT 24
Peak memory 239300 kb
Host smart-c9c7d981-da03-4431-9a51-3391affe3fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
34194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3892234194
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1614253305
Short name T563
Test name
Test status
Simulation time 286225142 ps
CPU time 25.25 seconds
Started May 07 02:08:49 PM PDT 24
Finished May 07 02:09:15 PM PDT 24
Peak memory 255920 kb
Host smart-c0b44717-85f0-40d1-b5e0-4db868ba516b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142
53305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1614253305
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1900710036
Short name T546
Test name
Test status
Simulation time 23022716351 ps
CPU time 1426.7 seconds
Started May 07 02:08:50 PM PDT 24
Finished May 07 02:32:37 PM PDT 24
Peak memory 269360 kb
Host smart-7b1e1be9-0f26-4664-891d-6de5895eeb7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900710036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1900710036
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4203178588
Short name T727
Test name
Test status
Simulation time 79964075006 ps
CPU time 1490.67 seconds
Started May 07 02:08:54 PM PDT 24
Finished May 07 02:33:46 PM PDT 24
Peak memory 289124 kb
Host smart-65ba15d8-a8ff-4ea8-a81f-72a9e2a1ecc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203178588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4203178588
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.742035347
Short name T37
Test name
Test status
Simulation time 3683360908 ps
CPU time 143.16 seconds
Started May 07 02:08:48 PM PDT 24
Finished May 07 02:11:12 PM PDT 24
Peak memory 247096 kb
Host smart-875228bc-571b-4a29-a120-a82a98da1b58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742035347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.742035347
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.758141855
Short name T726
Test name
Test status
Simulation time 4637042139 ps
CPU time 57.97 seconds
Started May 07 02:08:48 PM PDT 24
Finished May 07 02:09:47 PM PDT 24
Peak memory 248468 kb
Host smart-af118afd-53c4-4a84-8b92-e9f8903b8603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75814
1855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.758141855
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2721322330
Short name T534
Test name
Test status
Simulation time 201040167 ps
CPU time 12.93 seconds
Started May 07 02:08:50 PM PDT 24
Finished May 07 02:09:03 PM PDT 24
Peak memory 248628 kb
Host smart-3dd73820-9d7d-4612-aa75-1f93c11be8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27213
22330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2721322330
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.24497213
Short name T108
Test name
Test status
Simulation time 807083076 ps
CPU time 41.71 seconds
Started May 07 02:08:46 PM PDT 24
Finished May 07 02:09:29 PM PDT 24
Peak memory 255936 kb
Host smart-9bdf8141-b745-4ef1-91ed-f18274a3c36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.24497213
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.909250284
Short name T643
Test name
Test status
Simulation time 1407702488 ps
CPU time 50.3 seconds
Started May 07 02:08:50 PM PDT 24
Finished May 07 02:09:40 PM PDT 24
Peak memory 248984 kb
Host smart-21fb5447-8f65-4c12-ab3d-dbccdb151f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90925
0284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.909250284
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3678064055
Short name T237
Test name
Test status
Simulation time 46808247 ps
CPU time 3.56 seconds
Started May 07 02:09:05 PM PDT 24
Finished May 07 02:09:09 PM PDT 24
Peak memory 248960 kb
Host smart-461407fa-8f2b-421b-a4d8-16f87fe86e51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3678064055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3678064055
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3822003935
Short name T460
Test name
Test status
Simulation time 24302855553 ps
CPU time 1598.39 seconds
Started May 07 02:08:57 PM PDT 24
Finished May 07 02:35:36 PM PDT 24
Peak memory 270404 kb
Host smart-07a3382b-f4a4-4bee-be20-7c4c07c6a63d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822003935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3822003935
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2749134167
Short name T489
Test name
Test status
Simulation time 179631635 ps
CPU time 9.86 seconds
Started May 07 02:09:04 PM PDT 24
Finished May 07 02:09:15 PM PDT 24
Peak memory 240536 kb
Host smart-7f4c132e-35af-428d-a0cf-031e7cf7c664
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2749134167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2749134167
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1677686523
Short name T568
Test name
Test status
Simulation time 11590065952 ps
CPU time 310.07 seconds
Started May 07 02:08:58 PM PDT 24
Finished May 07 02:14:09 PM PDT 24
Peak memory 256944 kb
Host smart-b260f4c5-d253-4847-96eb-bbe3d7c6b8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16776
86523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1677686523
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4145524806
Short name T625
Test name
Test status
Simulation time 146051620 ps
CPU time 5.12 seconds
Started May 07 02:08:58 PM PDT 24
Finished May 07 02:09:04 PM PDT 24
Peak memory 240564 kb
Host smart-6d69f958-91d0-421b-ba50-dca2339ca327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41455
24806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4145524806
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2181668693
Short name T254
Test name
Test status
Simulation time 85503341392 ps
CPU time 726.84 seconds
Started May 07 02:08:58 PM PDT 24
Finished May 07 02:21:06 PM PDT 24
Peak memory 269788 kb
Host smart-a2192f8e-7415-41da-b69f-d639804e61f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181668693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2181668693
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2745458474
Short name T579
Test name
Test status
Simulation time 9400970901 ps
CPU time 918.27 seconds
Started May 07 02:09:04 PM PDT 24
Finished May 07 02:24:22 PM PDT 24
Peak memory 288928 kb
Host smart-83f5af8d-f415-4550-abe6-0d1ea205e168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745458474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2745458474
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1455879615
Short name T329
Test name
Test status
Simulation time 6625024855 ps
CPU time 283.7 seconds
Started May 07 02:08:59 PM PDT 24
Finished May 07 02:13:43 PM PDT 24
Peak memory 247116 kb
Host smart-60dac5b4-45bc-4d8f-a1a7-da784f3a8eb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455879615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1455879615
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3103379342
Short name T49
Test name
Test status
Simulation time 229834508 ps
CPU time 21.73 seconds
Started May 07 02:08:54 PM PDT 24
Finished May 07 02:09:16 PM PDT 24
Peak memory 248784 kb
Host smart-703c5f5e-e76f-450e-9da5-197f1d95410c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
79342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3103379342
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2956908738
Short name T715
Test name
Test status
Simulation time 834612371 ps
CPU time 22.9 seconds
Started May 07 02:08:52 PM PDT 24
Finished May 07 02:09:16 PM PDT 24
Peak memory 248824 kb
Host smart-f5e145e6-20ed-4a82-a490-cc764320e262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29569
08738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2956908738
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.426554327
Short name T648
Test name
Test status
Simulation time 370420300 ps
CPU time 25.45 seconds
Started May 07 02:09:01 PM PDT 24
Finished May 07 02:09:27 PM PDT 24
Peak memory 248776 kb
Host smart-9f318940-7915-44aa-8e65-4e696e7589ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
4327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.426554327
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2949744602
Short name T500
Test name
Test status
Simulation time 1224603626 ps
CPU time 44.06 seconds
Started May 07 02:08:57 PM PDT 24
Finished May 07 02:09:42 PM PDT 24
Peak memory 255944 kb
Host smart-5501c762-d02d-46f6-b9ff-27926fbaf602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29497
44602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2949744602
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2231230408
Short name T265
Test name
Test status
Simulation time 15771057426 ps
CPU time 1469.28 seconds
Started May 07 02:09:05 PM PDT 24
Finished May 07 02:33:35 PM PDT 24
Peak memory 289636 kb
Host smart-e1b4d847-1d95-4e05-9ec2-719dffc048b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231230408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2231230408
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2399639919
Short name T544
Test name
Test status
Simulation time 149768046760 ps
CPU time 2244.75 seconds
Started May 07 02:09:04 PM PDT 24
Finished May 07 02:46:30 PM PDT 24
Peak memory 281608 kb
Host smart-b426f60c-dcb2-4b6a-a03a-6bb21d9946a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399639919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2399639919
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1351165376
Short name T618
Test name
Test status
Simulation time 2271325318 ps
CPU time 10.84 seconds
Started May 07 02:09:08 PM PDT 24
Finished May 07 02:09:19 PM PDT 24
Peak memory 252556 kb
Host smart-eed44583-a9ba-4cbe-b753-2d4a1a01aa00
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1351165376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1351165376
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2895604689
Short name T409
Test name
Test status
Simulation time 63892796 ps
CPU time 4.84 seconds
Started May 07 02:09:04 PM PDT 24
Finished May 07 02:09:10 PM PDT 24
Peak memory 239264 kb
Host smart-399c60e9-0d61-4054-9a14-28a3714f90f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28956
04689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2895604689
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1893926905
Short name T540
Test name
Test status
Simulation time 329711190 ps
CPU time 28.27 seconds
Started May 07 02:09:06 PM PDT 24
Finished May 07 02:09:35 PM PDT 24
Peak memory 248816 kb
Host smart-d5f76a85-1d75-4f0e-90c8-0bdc673427c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
26905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1893926905
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3562281524
Short name T3
Test name
Test status
Simulation time 19793532174 ps
CPU time 810.12 seconds
Started May 07 02:09:10 PM PDT 24
Finished May 07 02:22:41 PM PDT 24
Peak memory 266264 kb
Host smart-4bb59d23-a9e6-45e7-996c-146db33130c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562281524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3562281524
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2594018078
Short name T248
Test name
Test status
Simulation time 33328677460 ps
CPU time 1278.77 seconds
Started May 07 02:09:09 PM PDT 24
Finished May 07 02:30:29 PM PDT 24
Peak memory 273316 kb
Host smart-41b3913f-f599-455b-8f25-abb7923be029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594018078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2594018078
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2857806853
Short name T706
Test name
Test status
Simulation time 12743007113 ps
CPU time 267.78 seconds
Started May 07 02:09:10 PM PDT 24
Finished May 07 02:13:39 PM PDT 24
Peak memory 247092 kb
Host smart-98e14d1f-6b1a-42a9-8ebc-1b9f84f2f654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857806853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2857806853
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3355449781
Short name T30
Test name
Test status
Simulation time 540716616 ps
CPU time 38.66 seconds
Started May 07 02:09:03 PM PDT 24
Finished May 07 02:09:42 PM PDT 24
Peak memory 248836 kb
Host smart-21c2f36f-5cbd-462d-85ca-42a6b14e9e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33554
49781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3355449781
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1313180625
Short name T548
Test name
Test status
Simulation time 3514942758 ps
CPU time 57.07 seconds
Started May 07 02:09:05 PM PDT 24
Finished May 07 02:10:02 PM PDT 24
Peak memory 255940 kb
Host smart-5c4308c9-40fa-45b6-a6e7-332954541a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131
80625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1313180625
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3983205350
Short name T294
Test name
Test status
Simulation time 116363899 ps
CPU time 14.36 seconds
Started May 07 02:09:03 PM PDT 24
Finished May 07 02:09:18 PM PDT 24
Peak memory 254848 kb
Host smart-1b9a17dc-e5a5-487c-8a02-05797c8f392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39832
05350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3983205350
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3582399369
Short name T722
Test name
Test status
Simulation time 1038364495 ps
CPU time 13.6 seconds
Started May 07 02:09:03 PM PDT 24
Finished May 07 02:09:17 PM PDT 24
Peak memory 248964 kb
Host smart-aa05f23b-b592-42ec-bd21-c4aa532c9797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35823
99369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3582399369
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2465980538
Short name T48
Test name
Test status
Simulation time 14999607225 ps
CPU time 1299.58 seconds
Started May 07 02:09:10 PM PDT 24
Finished May 07 02:30:50 PM PDT 24
Peak memory 289040 kb
Host smart-f1ef0ec2-b669-4c6a-96ef-18343d360d43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465980538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2465980538
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3795119325
Short name T97
Test name
Test status
Simulation time 51474168 ps
CPU time 2.43 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:09:19 PM PDT 24
Peak memory 248920 kb
Host smart-d034848e-19f5-48dc-91cc-0d53d4b65510
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3795119325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3795119325
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3582103877
Short name T111
Test name
Test status
Simulation time 60671303208 ps
CPU time 1056.57 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:26:54 PM PDT 24
Peak memory 289800 kb
Host smart-ad0c8848-2293-4fa3-bdd3-5a1cdf348c6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582103877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3582103877
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.956349178
Short name T260
Test name
Test status
Simulation time 267014764 ps
CPU time 13.76 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:09:31 PM PDT 24
Peak memory 240600 kb
Host smart-7c5cabe2-4bdc-4903-8b73-f1f5a7080f66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=956349178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.956349178
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3727153343
Short name T518
Test name
Test status
Simulation time 3489541377 ps
CPU time 167.18 seconds
Started May 07 02:09:08 PM PDT 24
Finished May 07 02:11:56 PM PDT 24
Peak memory 257020 kb
Host smart-e159806b-3270-4fff-9f24-d51a5abdebc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37271
53343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3727153343
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4002509658
Short name T478
Test name
Test status
Simulation time 8853691933 ps
CPU time 81.67 seconds
Started May 07 02:09:09 PM PDT 24
Finished May 07 02:10:32 PM PDT 24
Peak memory 257012 kb
Host smart-cb551d5d-8eef-4d86-8623-933f66238a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
09658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4002509658
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.339485256
Short name T417
Test name
Test status
Simulation time 52516789447 ps
CPU time 1369.66 seconds
Started May 07 02:09:15 PM PDT 24
Finished May 07 02:32:05 PM PDT 24
Peak memory 273372 kb
Host smart-ba16e147-6796-4f6c-a65f-c7c678b515ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339485256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.339485256
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.509449778
Short name T339
Test name
Test status
Simulation time 24776081704 ps
CPU time 252.81 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:13:30 PM PDT 24
Peak memory 248256 kb
Host smart-4d0b8c85-a262-4c2a-8a06-09f0508f3911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509449778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.509449778
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.89343842
Short name T50
Test name
Test status
Simulation time 4553503148 ps
CPU time 59.23 seconds
Started May 07 02:09:10 PM PDT 24
Finished May 07 02:10:10 PM PDT 24
Peak memory 248816 kb
Host smart-98f99d10-5a89-47bf-a750-1a07d56e3dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89343
842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.89343842
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4182049911
Short name T633
Test name
Test status
Simulation time 1565089756 ps
CPU time 22.3 seconds
Started May 07 02:09:08 PM PDT 24
Finished May 07 02:09:31 PM PDT 24
Peak memory 254476 kb
Host smart-f3af7c0a-10c9-4973-a732-b70317dcfb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41820
49911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4182049911
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1221253816
Short name T127
Test name
Test status
Simulation time 908163162 ps
CPU time 26.84 seconds
Started May 07 02:09:10 PM PDT 24
Finished May 07 02:09:37 PM PDT 24
Peak memory 248780 kb
Host smart-a13efbaa-7a4b-4f93-bfaf-515f79ccfdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12212
53816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1221253816
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1814924765
Short name T647
Test name
Test status
Simulation time 1836345618 ps
CPU time 27.36 seconds
Started May 07 02:09:11 PM PDT 24
Finished May 07 02:09:39 PM PDT 24
Peak memory 248780 kb
Host smart-2e070ca1-5cca-4826-97d5-9bc3f8c6b3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18149
24765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1814924765
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2395159450
Short name T115
Test name
Test status
Simulation time 27442022627 ps
CPU time 1639.25 seconds
Started May 07 02:09:15 PM PDT 24
Finished May 07 02:36:36 PM PDT 24
Peak memory 284716 kb
Host smart-ae9c5a9e-efe4-4ea1-b9c2-fa4fbaa3d595
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395159450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2395159450
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2546276369
Short name T490
Test name
Test status
Simulation time 80262531192 ps
CPU time 7602.24 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 04:16:00 PM PDT 24
Peak memory 355012 kb
Host smart-941139e6-c0d3-48dd-8a5a-73aa3a97b301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546276369 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2546276369
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2188063117
Short name T240
Test name
Test status
Simulation time 215201824 ps
CPU time 4.66 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:09:22 PM PDT 24
Peak memory 248988 kb
Host smart-e18ddf45-d148-4da7-9532-0137a2d7f118
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2188063117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2188063117
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1195031583
Short name T43
Test name
Test status
Simulation time 11128995504 ps
CPU time 1016.93 seconds
Started May 07 02:09:18 PM PDT 24
Finished May 07 02:26:16 PM PDT 24
Peak memory 273168 kb
Host smart-225c93f9-d874-4d99-885d-ac435efa1d85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195031583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1195031583
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3735383207
Short name T259
Test name
Test status
Simulation time 733293714 ps
CPU time 9.83 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:09:27 PM PDT 24
Peak memory 240552 kb
Host smart-894a55e4-366e-4e0e-91e0-13a2dbd65555
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3735383207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3735383207
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1608618113
Short name T308
Test name
Test status
Simulation time 36443191511 ps
CPU time 149.01 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:11:50 PM PDT 24
Peak memory 256900 kb
Host smart-d4fdf2d5-bed5-4dc2-a8be-37a203f2ce49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16086
18113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1608618113
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3417845167
Short name T67
Test name
Test status
Simulation time 5563134196 ps
CPU time 38.63 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:10:00 PM PDT 24
Peak memory 256892 kb
Host smart-778179b4-de37-470c-91f7-6dd76cea2302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34178
45167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3417845167
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3965757426
Short name T712
Test name
Test status
Simulation time 36561635561 ps
CPU time 2188.97 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:45:46 PM PDT 24
Peak memory 281652 kb
Host smart-308326fc-32ed-4b50-8454-78d337f38e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965757426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3965757426
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.616575171
Short name T340
Test name
Test status
Simulation time 3683056420 ps
CPU time 145.23 seconds
Started May 07 02:09:17 PM PDT 24
Finished May 07 02:11:43 PM PDT 24
Peak memory 248268 kb
Host smart-f8637fb1-0fcf-4045-9fd2-689ebba7b057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616575171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.616575171
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3820678278
Short name T717
Test name
Test status
Simulation time 1345439383 ps
CPU time 27.98 seconds
Started May 07 02:09:15 PM PDT 24
Finished May 07 02:09:43 PM PDT 24
Peak memory 255772 kb
Host smart-e980254f-26f1-48b4-895d-3c73bbe41742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38206
78278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3820678278
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3664373324
Short name T419
Test name
Test status
Simulation time 76728288 ps
CPU time 9.44 seconds
Started May 07 02:09:19 PM PDT 24
Finished May 07 02:09:30 PM PDT 24
Peak memory 247376 kb
Host smart-ae1397ac-2f9e-4fff-9cfd-13da7c26ff44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36643
73324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3664373324
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.415931767
Short name T607
Test name
Test status
Simulation time 274822126 ps
CPU time 23.34 seconds
Started May 07 02:09:18 PM PDT 24
Finished May 07 02:09:41 PM PDT 24
Peak memory 255448 kb
Host smart-7557c4df-b759-4cb5-8956-3c88f18fe955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41593
1767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.415931767
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3610416613
Short name T72
Test name
Test status
Simulation time 7953807688 ps
CPU time 26.09 seconds
Started May 07 02:09:15 PM PDT 24
Finished May 07 02:09:42 PM PDT 24
Peak memory 248852 kb
Host smart-6b30df00-2ea7-4809-b3d7-df23888e76a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36104
16613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3610416613
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2994771144
Short name T89
Test name
Test status
Simulation time 218390686953 ps
CPU time 3008.49 seconds
Started May 07 02:09:16 PM PDT 24
Finished May 07 02:59:25 PM PDT 24
Peak memory 289072 kb
Host smart-eba24ccd-c647-426e-877d-21960f5f72e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994771144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2994771144
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3864750980
Short name T716
Test name
Test status
Simulation time 246207770006 ps
CPU time 1178.52 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:28:59 PM PDT 24
Peak memory 265244 kb
Host smart-17699da9-2d61-4cab-a772-ce49951fcade
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864750980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3864750980
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3784300302
Short name T631
Test name
Test status
Simulation time 1210653205 ps
CPU time 8.38 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:09:33 PM PDT 24
Peak memory 240592 kb
Host smart-ed220e51-e3b8-4802-a865-ea59881408bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3784300302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3784300302
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3686555755
Short name T539
Test name
Test status
Simulation time 16707483211 ps
CPU time 224.51 seconds
Started May 07 02:09:19 PM PDT 24
Finished May 07 02:13:05 PM PDT 24
Peak memory 256924 kb
Host smart-8444f488-fa42-49b2-bf74-886c2f6dd6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36865
55755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3686555755
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3245207929
Short name T79
Test name
Test status
Simulation time 3802356195 ps
CPU time 54.21 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:10:17 PM PDT 24
Peak memory 255760 kb
Host smart-2a9c7f9b-248d-4481-ac51-82fe5cca0b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
07929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3245207929
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2849042517
Short name T363
Test name
Test status
Simulation time 16800807462 ps
CPU time 1402.92 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:32:46 PM PDT 24
Peak memory 289044 kb
Host smart-e9f3cdb8-a5c6-41ad-81db-62e77fb5f7a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849042517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2849042517
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4202066342
Short name T504
Test name
Test status
Simulation time 8660697496 ps
CPU time 725.01 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:21:29 PM PDT 24
Peak memory 272184 kb
Host smart-6478bba1-d28b-4f2a-8976-89a914df7903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202066342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4202066342
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1273256663
Short name T659
Test name
Test status
Simulation time 238930816 ps
CPU time 25.61 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:09:46 PM PDT 24
Peak memory 248768 kb
Host smart-99d99856-1565-43d0-aab8-c0dc65ad40c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12732
56663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1273256663
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.582769479
Short name T465
Test name
Test status
Simulation time 200603375 ps
CPU time 12.46 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:09:34 PM PDT 24
Peak memory 251240 kb
Host smart-ebcad85a-b46c-453a-aa83-f07e32e01b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58276
9479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.582769479
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2252912976
Short name T528
Test name
Test status
Simulation time 963096964 ps
CPU time 29.13 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:09:53 PM PDT 24
Peak memory 247520 kb
Host smart-89910371-40a6-4f56-accf-565cd11baa20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22529
12976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2252912976
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1502342614
Short name T96
Test name
Test status
Simulation time 34138630 ps
CPU time 2.94 seconds
Started May 07 02:09:18 PM PDT 24
Finished May 07 02:09:22 PM PDT 24
Peak memory 240588 kb
Host smart-791611b0-d4fc-4887-8220-7fdd5d010160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15023
42614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1502342614
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3176990106
Short name T503
Test name
Test status
Simulation time 68103116768 ps
CPU time 1202.59 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:29:27 PM PDT 24
Peak memory 281604 kb
Host smart-5f1ff8ca-90d5-4600-83dd-e0bcb1c7799e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176990106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3176990106
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3030478439
Short name T582
Test name
Test status
Simulation time 38237035097 ps
CPU time 754.92 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:21:58 PM PDT 24
Peak memory 273576 kb
Host smart-bd5aca23-ec49-4387-b552-8cea92bdb335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030478439 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3030478439
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4254532697
Short name T228
Test name
Test status
Simulation time 38009932 ps
CPU time 3.62 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:09:27 PM PDT 24
Peak memory 248928 kb
Host smart-11da10fe-37b2-4859-b67b-a5c6f2dc115f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4254532697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4254532697
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.704256569
Short name T74
Test name
Test status
Simulation time 47951360306 ps
CPU time 2967.62 seconds
Started May 07 02:09:21 PM PDT 24
Finished May 07 02:58:50 PM PDT 24
Peak memory 281636 kb
Host smart-22906bc2-d8f9-4d00-b574-0f6697627bd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704256569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.704256569
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.385626928
Short name T554
Test name
Test status
Simulation time 232622771 ps
CPU time 12.56 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:09:36 PM PDT 24
Peak memory 248796 kb
Host smart-c719d9a0-fcb5-46cf-94e4-53988266c43a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=385626928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.385626928
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1921444429
Short name T41
Test name
Test status
Simulation time 14997135387 ps
CPU time 213.3 seconds
Started May 07 02:09:21 PM PDT 24
Finished May 07 02:12:55 PM PDT 24
Peak memory 256944 kb
Host smart-3b7ffa60-2407-4084-b7d7-bcd2a9b82733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214
44429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1921444429
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2123044398
Short name T606
Test name
Test status
Simulation time 3055425070 ps
CPU time 24.99 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:09:45 PM PDT 24
Peak memory 256160 kb
Host smart-30824c5d-2e16-4ce6-b2fa-9a117499d4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
44398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2123044398
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2953495813
Short name T11
Test name
Test status
Simulation time 12364208491 ps
CPU time 1188.23 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:29:11 PM PDT 24
Peak memory 281608 kb
Host smart-3f7beb89-840a-405c-8d27-d7a4a0703e30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953495813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2953495813
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.748476067
Short name T673
Test name
Test status
Simulation time 33749227155 ps
CPU time 788.75 seconds
Started May 07 02:09:24 PM PDT 24
Finished May 07 02:22:33 PM PDT 24
Peak memory 282652 kb
Host smart-b592038f-e290-4a35-9341-094addde05e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748476067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.748476067
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2551949469
Short name T325
Test name
Test status
Simulation time 43286412673 ps
CPU time 748.05 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:21:52 PM PDT 24
Peak memory 247876 kb
Host smart-b85b3e3f-5c5c-4469-ade9-a293dfbdc0d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551949469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2551949469
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3085428758
Short name T73
Test name
Test status
Simulation time 2077326177 ps
CPU time 29.01 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:09:52 PM PDT 24
Peak memory 249008 kb
Host smart-6fad4f56-3798-465a-bf89-0845e02edaca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30854
28758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3085428758
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1996443619
Short name T662
Test name
Test status
Simulation time 51631029 ps
CPU time 6.06 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:09:30 PM PDT 24
Peak memory 253844 kb
Host smart-4189af31-5736-47b7-a744-f33b21f5fb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19964
43619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1996443619
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2461868380
Short name T677
Test name
Test status
Simulation time 801083107 ps
CPU time 23.07 seconds
Started May 07 02:09:21 PM PDT 24
Finished May 07 02:09:45 PM PDT 24
Peak memory 247496 kb
Host smart-1460cca8-99cb-48e0-b93b-ea662309b6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24618
68380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2461868380
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.185995034
Short name T531
Test name
Test status
Simulation time 561084036 ps
CPU time 15.42 seconds
Started May 07 02:09:20 PM PDT 24
Finished May 07 02:09:36 PM PDT 24
Peak memory 248796 kb
Host smart-440c45eb-cc0f-4310-b250-5a757c478b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18599
5034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.185995034
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.769174546
Short name T522
Test name
Test status
Simulation time 58144103965 ps
CPU time 201.53 seconds
Started May 07 02:09:23 PM PDT 24
Finished May 07 02:12:45 PM PDT 24
Peak memory 256552 kb
Host smart-0a920787-a52c-4d27-b955-388475d9b678
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769174546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.769174546
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2618940838
Short name T681
Test name
Test status
Simulation time 224624908802 ps
CPU time 2988.97 seconds
Started May 07 02:09:22 PM PDT 24
Finished May 07 02:59:12 PM PDT 24
Peak memory 321752 kb
Host smart-8beace5b-530e-4f12-805b-b157a2671309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618940838 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2618940838
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2480573234
Short name T235
Test name
Test status
Simulation time 78965146 ps
CPU time 3.71 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:09:36 PM PDT 24
Peak memory 248940 kb
Host smart-1b1a93e0-b08a-414e-bc0c-ba8979a4ceff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2480573234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2480573234
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.915787999
Short name T635
Test name
Test status
Simulation time 42623067385 ps
CPU time 2336.12 seconds
Started May 07 02:09:27 PM PDT 24
Finished May 07 02:48:24 PM PDT 24
Peak memory 281644 kb
Host smart-2957ce3e-4eb3-46e0-9b82-0003e07e995f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915787999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.915787999
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4080581883
Short name T437
Test name
Test status
Simulation time 1159418633 ps
CPU time 44.62 seconds
Started May 07 02:09:26 PM PDT 24
Finished May 07 02:10:12 PM PDT 24
Peak memory 248752 kb
Host smart-a4d119fd-f5d8-4243-8072-fffb14d03a09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4080581883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4080581883
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2734844979
Short name T116
Test name
Test status
Simulation time 9358967139 ps
CPU time 163.22 seconds
Started May 07 02:09:33 PM PDT 24
Finished May 07 02:12:17 PM PDT 24
Peak memory 251400 kb
Host smart-5fdc76ef-7abc-4282-889a-669acb448d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
44979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2734844979
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2215962453
Short name T515
Test name
Test status
Simulation time 6207254782 ps
CPU time 48.82 seconds
Started May 07 02:09:26 PM PDT 24
Finished May 07 02:10:16 PM PDT 24
Peak memory 256088 kb
Host smart-62258826-a1f2-4529-b6f3-635343458bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159
62453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2215962453
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3118115492
Short name T319
Test name
Test status
Simulation time 49059218808 ps
CPU time 1505.74 seconds
Started May 07 02:09:28 PM PDT 24
Finished May 07 02:34:35 PM PDT 24
Peak memory 273420 kb
Host smart-d82565cd-9284-43c5-bc2f-51320e625928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118115492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3118115492
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3804705060
Short name T682
Test name
Test status
Simulation time 19629222329 ps
CPU time 714.07 seconds
Started May 07 02:09:26 PM PDT 24
Finished May 07 02:21:21 PM PDT 24
Peak memory 268312 kb
Host smart-38eb59c6-d79f-401c-acde-d65477705c71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804705060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3804705060
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1900014932
Short name T629
Test name
Test status
Simulation time 4139077049 ps
CPU time 169.99 seconds
Started May 07 02:09:26 PM PDT 24
Finished May 07 02:12:17 PM PDT 24
Peak memory 248132 kb
Host smart-d5a6f5ad-de50-47f5-bb5c-99cffa8a6d61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900014932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1900014932
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3591278150
Short name T411
Test name
Test status
Simulation time 865557255 ps
CPU time 51.4 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:10:25 PM PDT 24
Peak memory 256016 kb
Host smart-b2d68f5e-aa55-4958-91e7-95532ecd0150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
78150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3591278150
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1023245328
Short name T436
Test name
Test status
Simulation time 1216694876 ps
CPU time 43.8 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:10:16 PM PDT 24
Peak memory 255068 kb
Host smart-fc92a34f-c862-4768-922c-a1952553ad2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10232
45328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1023245328
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4191793229
Short name T678
Test name
Test status
Simulation time 1328434166 ps
CPU time 31.2 seconds
Started May 07 02:09:28 PM PDT 24
Finished May 07 02:10:01 PM PDT 24
Peak memory 248800 kb
Host smart-8355af26-11f7-4643-875f-7a2ffa62b2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
93229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4191793229
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1705478112
Short name T426
Test name
Test status
Simulation time 2848918193 ps
CPU time 40.24 seconds
Started May 07 02:09:33 PM PDT 24
Finished May 07 02:10:14 PM PDT 24
Peak memory 248884 kb
Host smart-50ba1ac1-bb81-48a3-be68-542d3a2555a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17054
78112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1705478112
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2139478438
Short name T63
Test name
Test status
Simulation time 114327090014 ps
CPU time 3045.75 seconds
Started May 07 02:09:27 PM PDT 24
Finished May 07 03:00:14 PM PDT 24
Peak memory 317992 kb
Host smart-ffdacf74-2361-4741-97b7-030538d69da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139478438 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2139478438
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2683584752
Short name T238
Test name
Test status
Simulation time 50965168 ps
CPU time 2.23 seconds
Started May 07 02:09:31 PM PDT 24
Finished May 07 02:09:34 PM PDT 24
Peak memory 248956 kb
Host smart-7f237ff5-cdb5-4f98-bece-df019e1ffe51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2683584752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2683584752
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2890022698
Short name T28
Test name
Test status
Simulation time 18315605291 ps
CPU time 629.65 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:20:02 PM PDT 24
Peak memory 272900 kb
Host smart-29c58e44-b4ec-48c5-8a8f-4b43a42c65dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890022698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2890022698
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2750097609
Short name T256
Test name
Test status
Simulation time 645456863 ps
CPU time 14.74 seconds
Started May 07 02:09:31 PM PDT 24
Finished May 07 02:09:47 PM PDT 24
Peak memory 248772 kb
Host smart-3b47a55d-d933-4fcb-b0c5-2822bba54f01
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2750097609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2750097609
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3492602807
Short name T398
Test name
Test status
Simulation time 24974029664 ps
CPU time 328.99 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:15:02 PM PDT 24
Peak memory 257004 kb
Host smart-0a61540f-d67b-478e-9f6d-5cf33bda70aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34926
02807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3492602807
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2366465940
Short name T612
Test name
Test status
Simulation time 2500264922 ps
CPU time 39.11 seconds
Started May 07 02:09:27 PM PDT 24
Finished May 07 02:10:07 PM PDT 24
Peak memory 248840 kb
Host smart-a375677f-ff86-4784-b35f-4775fd8c327e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23664
65940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2366465940
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.745756360
Short name T463
Test name
Test status
Simulation time 37014341517 ps
CPU time 1893.14 seconds
Started May 07 02:09:36 PM PDT 24
Finished May 07 02:41:10 PM PDT 24
Peak memory 289032 kb
Host smart-d78bba12-a493-4722-b0ef-bddf41ec3c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745756360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.745756360
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1762570841
Short name T614
Test name
Test status
Simulation time 3821489655 ps
CPU time 52.07 seconds
Started May 07 02:09:25 PM PDT 24
Finished May 07 02:10:19 PM PDT 24
Peak memory 248852 kb
Host smart-3824dd97-04a6-4f79-9fde-b46eb2b65afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17625
70841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1762570841
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.262585439
Short name T575
Test name
Test status
Simulation time 2275630423 ps
CPU time 61.19 seconds
Started May 07 02:09:33 PM PDT 24
Finished May 07 02:10:35 PM PDT 24
Peak memory 256328 kb
Host smart-6a09dd5a-fa52-4c04-986a-d088c09f7fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26258
5439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.262585439
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3828408867
Short name T296
Test name
Test status
Simulation time 310766090 ps
CPU time 19.72 seconds
Started May 07 02:09:35 PM PDT 24
Finished May 07 02:09:56 PM PDT 24
Peak memory 255148 kb
Host smart-de198e1f-b11b-4fdf-8665-05581741eb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38284
08867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3828408867
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1541431620
Short name T205
Test name
Test status
Simulation time 1251335864 ps
CPU time 70.67 seconds
Started May 07 02:09:33 PM PDT 24
Finished May 07 02:10:44 PM PDT 24
Peak memory 256000 kb
Host smart-35e12297-ba2d-449d-a21d-bce5349027e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414
31620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1541431620
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.417715469
Short name T552
Test name
Test status
Simulation time 63240210129 ps
CPU time 1082.79 seconds
Started May 07 02:09:32 PM PDT 24
Finished May 07 02:27:35 PM PDT 24
Peak memory 273376 kb
Host smart-cb2e2a11-af2f-4a11-a6aa-d3c8f3dd0d57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417715469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.417715469
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.564600545
Short name T692
Test name
Test status
Simulation time 373479711575 ps
CPU time 5144.29 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 03:35:24 PM PDT 24
Peak memory 371400 kb
Host smart-b5a61832-e71d-489d-8ea2-a6a4dcde94d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564600545 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.564600545
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3249891182
Short name T242
Test name
Test status
Simulation time 52601384 ps
CPU time 2.83 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:09:42 PM PDT 24
Peak memory 248928 kb
Host smart-31d9b874-068b-43a5-a29a-002b3fb0602a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3249891182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3249891182
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3778140163
Short name T541
Test name
Test status
Simulation time 186093103907 ps
CPU time 2561.13 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:52:20 PM PDT 24
Peak memory 286420 kb
Host smart-86fdad69-94d8-4485-9d86-aac5a5a274e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778140163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3778140163
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4170396147
Short name T583
Test name
Test status
Simulation time 9258968563 ps
CPU time 29.21 seconds
Started May 07 02:09:37 PM PDT 24
Finished May 07 02:10:07 PM PDT 24
Peak memory 248836 kb
Host smart-0cbfaaea-93ff-4d5f-9f0f-080060b1f855
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4170396147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4170396147
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.735231509
Short name T452
Test name
Test status
Simulation time 2200774529 ps
CPU time 124.77 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:11:43 PM PDT 24
Peak memory 250936 kb
Host smart-54d98d74-741e-4b95-bd66-56de11458e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73523
1509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.735231509
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3864989883
Short name T82
Test name
Test status
Simulation time 3313707481 ps
CPU time 53.03 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:10:32 PM PDT 24
Peak memory 249304 kb
Host smart-558ee8ab-234f-4ec2-9060-2515d5a8d848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
89883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3864989883
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3543766887
Short name T12
Test name
Test status
Simulation time 715119499745 ps
CPU time 3022.33 seconds
Started May 07 02:09:37 PM PDT 24
Finished May 07 03:00:01 PM PDT 24
Peak memory 288372 kb
Host smart-ae5bb043-a3d0-4b3e-85e2-6c5d70f48c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543766887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3543766887
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.855039668
Short name T200
Test name
Test status
Simulation time 29007097424 ps
CPU time 280.07 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:14:20 PM PDT 24
Peak memory 248368 kb
Host smart-c21f0279-b597-4bb3-b15e-80abd49d3784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855039668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.855039668
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1725995141
Short name T581
Test name
Test status
Simulation time 1724072789 ps
CPU time 29.93 seconds
Started May 07 02:09:39 PM PDT 24
Finished May 07 02:10:10 PM PDT 24
Peak memory 248796 kb
Host smart-0bf82353-fafc-43a3-ab4a-a6751996f4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17259
95141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1725995141
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1461494094
Short name T309
Test name
Test status
Simulation time 814081766 ps
CPU time 20.46 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:09:59 PM PDT 24
Peak memory 255768 kb
Host smart-b2a0d185-c21d-47d5-b855-b83e84b6c8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14614
94094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1461494094
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1749688230
Short name T709
Test name
Test status
Simulation time 549468328 ps
CPU time 26.64 seconds
Started May 07 02:09:37 PM PDT 24
Finished May 07 02:10:04 PM PDT 24
Peak memory 255656 kb
Host smart-8b6396e9-51ec-4e6d-a320-9f79da76f30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
88230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1749688230
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3365765073
Short name T689
Test name
Test status
Simulation time 1515462482 ps
CPU time 45.95 seconds
Started May 07 02:09:38 PM PDT 24
Finished May 07 02:10:25 PM PDT 24
Peak memory 248732 kb
Host smart-bcabac3d-cd19-4eda-8ebd-3bf606ee2283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33657
65073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3365765073
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1921344997
Short name T119
Test name
Test status
Simulation time 133156659540 ps
CPU time 638.98 seconds
Started May 07 02:09:37 PM PDT 24
Finished May 07 02:20:17 PM PDT 24
Peak memory 268920 kb
Host smart-0959e504-4dde-4298-8ceb-9786eb011623
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921344997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1921344997
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1682223051
Short name T92
Test name
Test status
Simulation time 401623732477 ps
CPU time 8982.8 seconds
Started May 07 02:09:50 PM PDT 24
Finished May 07 04:39:34 PM PDT 24
Peak memory 338580 kb
Host smart-113f75cf-335b-4c23-bc82-52bc7b41de4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682223051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1682223051
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1905345422
Short name T230
Test name
Test status
Simulation time 62898546 ps
CPU time 2.78 seconds
Started May 07 02:08:25 PM PDT 24
Finished May 07 02:08:29 PM PDT 24
Peak memory 248940 kb
Host smart-1b8873b0-aa11-4595-816a-17feef3fd2d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1905345422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1905345422
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1445899260
Short name T595
Test name
Test status
Simulation time 17189826871 ps
CPU time 1640.04 seconds
Started May 07 02:08:27 PM PDT 24
Finished May 07 02:35:48 PM PDT 24
Peak memory 288588 kb
Host smart-1cbf2330-1202-4289-a44b-72e9d275577e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445899260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1445899260
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1480131826
Short name T393
Test name
Test status
Simulation time 1401685308 ps
CPU time 17.63 seconds
Started May 07 02:08:28 PM PDT 24
Finished May 07 02:08:46 PM PDT 24
Peak memory 248752 kb
Host smart-581130eb-b56f-4f3f-baab-17271fb4fe39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1480131826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1480131826
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1073865329
Short name T391
Test name
Test status
Simulation time 10181432875 ps
CPU time 151.58 seconds
Started May 07 02:08:25 PM PDT 24
Finished May 07 02:10:57 PM PDT 24
Peak memory 257008 kb
Host smart-86ca08e1-8dca-403b-b8cd-ebeb8e791ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
65329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1073865329
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3300718201
Short name T556
Test name
Test status
Simulation time 539593450 ps
CPU time 9.77 seconds
Started May 07 02:08:25 PM PDT 24
Finished May 07 02:08:36 PM PDT 24
Peak memory 248812 kb
Host smart-14c3d235-324f-4269-9546-bd5883143726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007
18201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3300718201
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2439579702
Short name T253
Test name
Test status
Simulation time 54396168827 ps
CPU time 1044.67 seconds
Started May 07 02:08:25 PM PDT 24
Finished May 07 02:25:50 PM PDT 24
Peak memory 282324 kb
Host smart-ea8c0894-ecb2-4f45-bbeb-1aeb683ffbd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439579702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2439579702
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2649160410
Short name T482
Test name
Test status
Simulation time 14841923042 ps
CPU time 1064.56 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:26:20 PM PDT 24
Peak memory 281592 kb
Host smart-9a7fb439-5fa2-4732-9ec4-19cfe920ab61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649160410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2649160410
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.445017580
Short name T129
Test name
Test status
Simulation time 7409550525 ps
CPU time 303.93 seconds
Started May 07 02:08:26 PM PDT 24
Finished May 07 02:13:31 PM PDT 24
Peak memory 248376 kb
Host smart-03c0a54a-4e92-46b1-982b-975a78d4e676
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445017580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.445017580
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2812375021
Short name T608
Test name
Test status
Simulation time 460744945 ps
CPU time 8.97 seconds
Started May 07 02:08:20 PM PDT 24
Finished May 07 02:08:30 PM PDT 24
Peak memory 248756 kb
Host smart-03abe989-ebb0-4b0d-9e2d-15ec5398788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
75021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2812375021
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3777095580
Short name T551
Test name
Test status
Simulation time 895751765 ps
CPU time 9.05 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:08:45 PM PDT 24
Peak memory 250880 kb
Host smart-44e541ee-9025-4680-8342-abb32a59aa1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37770
95580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3777095580
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3505168580
Short name T8
Test name
Test status
Simulation time 1697406887 ps
CPU time 19.65 seconds
Started May 07 02:08:27 PM PDT 24
Finished May 07 02:08:47 PM PDT 24
Peak memory 277636 kb
Host smart-eb71a7d4-6983-4140-b11e-222e692b591c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3505168580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3505168580
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3037351944
Short name T496
Test name
Test status
Simulation time 191834604 ps
CPU time 19.53 seconds
Started May 07 02:08:26 PM PDT 24
Finished May 07 02:08:46 PM PDT 24
Peak memory 247372 kb
Host smart-8f82acd8-31ed-4082-b2ad-53de2b43ec24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30373
51944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3037351944
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3067562276
Short name T249
Test name
Test status
Simulation time 2490452931 ps
CPU time 18.69 seconds
Started May 07 02:08:19 PM PDT 24
Finished May 07 02:08:39 PM PDT 24
Peak memory 248844 kb
Host smart-6b6b40cc-e963-4de2-a80b-2fa7da55bf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
62276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3067562276
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2979747357
Short name T99
Test name
Test status
Simulation time 49589721923 ps
CPU time 1019.47 seconds
Started May 07 02:08:27 PM PDT 24
Finished May 07 02:25:28 PM PDT 24
Peak memory 273132 kb
Host smart-36cb1c72-cb02-4618-89e3-d3dd4bbcdf50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979747357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2979747357
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2186777013
Short name T222
Test name
Test status
Simulation time 74094030200 ps
CPU time 2044.8 seconds
Started May 07 02:08:24 PM PDT 24
Finished May 07 02:42:30 PM PDT 24
Peak memory 301512 kb
Host smart-0ca1a3be-2658-4aa3-b372-74f088370930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186777013 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2186777013
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1368966925
Short name T396
Test name
Test status
Simulation time 108751462 ps
CPU time 6.13 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:09:54 PM PDT 24
Peak memory 240664 kb
Host smart-0b17cc7a-32fc-4928-b113-d77ee5983c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13689
66925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1368966925
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1611979507
Short name T580
Test name
Test status
Simulation time 2053208214 ps
CPU time 36.15 seconds
Started May 07 02:09:50 PM PDT 24
Finished May 07 02:10:27 PM PDT 24
Peak memory 256036 kb
Host smart-cba68f2f-7933-4c50-b157-01bbb9bc8ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
79507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1611979507
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.901739022
Short name T395
Test name
Test status
Simulation time 71340305916 ps
CPU time 2221.11 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:46:50 PM PDT 24
Peak memory 287292 kb
Host smart-3f4f6cc3-f2d7-4950-98a3-53661c738f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901739022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.901739022
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4148345781
Short name T637
Test name
Test status
Simulation time 5190972901 ps
CPU time 205.4 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:13:14 PM PDT 24
Peak memory 248268 kb
Host smart-780b2a64-e889-46a3-85f0-52ef4955b128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148345781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4148345781
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2085656054
Short name T270
Test name
Test status
Simulation time 2187358998 ps
CPU time 30.91 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:10:18 PM PDT 24
Peak memory 248836 kb
Host smart-ea95e39f-bc7b-4d89-b4fa-97af71e417fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20856
56054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2085656054
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.203955672
Short name T561
Test name
Test status
Simulation time 460754283 ps
CPU time 16.1 seconds
Started May 07 02:09:48 PM PDT 24
Finished May 07 02:10:05 PM PDT 24
Peak memory 256048 kb
Host smart-d4a55512-bc14-4940-a213-c59d819b8249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20395
5672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.203955672
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4151746204
Short name T440
Test name
Test status
Simulation time 60916006 ps
CPU time 6.69 seconds
Started May 07 02:09:49 PM PDT 24
Finished May 07 02:09:56 PM PDT 24
Peak memory 253000 kb
Host smart-930809d8-fb9a-4c8a-b58d-51cec86b8262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
46204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4151746204
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1000887360
Short name T245
Test name
Test status
Simulation time 507554925 ps
CPU time 23.12 seconds
Started May 07 02:09:48 PM PDT 24
Finished May 07 02:10:12 PM PDT 24
Peak memory 248760 kb
Host smart-7bef128c-f947-4ff5-9157-387cd53081d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10008
87360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1000887360
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3704698109
Short name T53
Test name
Test status
Simulation time 108007692092 ps
CPU time 1649.53 seconds
Started May 07 02:09:47 PM PDT 24
Finished May 07 02:37:17 PM PDT 24
Peak memory 289352 kb
Host smart-030d1bba-5791-431d-86d3-9bdc733d00e7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704698109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3704698109
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1281660755
Short name T591
Test name
Test status
Simulation time 9777479899 ps
CPU time 1012.08 seconds
Started May 07 02:09:49 PM PDT 24
Finished May 07 02:26:42 PM PDT 24
Peak memory 286264 kb
Host smart-c366a98c-87b2-499a-98ba-feba306d0152
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281660755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1281660755
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1773844464
Short name T694
Test name
Test status
Simulation time 7941512777 ps
CPU time 202.96 seconds
Started May 07 02:09:50 PM PDT 24
Finished May 07 02:13:14 PM PDT 24
Peak memory 250304 kb
Host smart-dab66738-51be-419b-ac3b-d850c4fc7896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17738
44464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1773844464
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1493733032
Short name T519
Test name
Test status
Simulation time 2131513454 ps
CPU time 24.52 seconds
Started May 07 02:09:50 PM PDT 24
Finished May 07 02:10:15 PM PDT 24
Peak memory 248808 kb
Host smart-d020ee4c-8d4c-4456-ae07-31024b349b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14937
33032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1493733032
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1932303181
Short name T355
Test name
Test status
Simulation time 17910851842 ps
CPU time 1115.55 seconds
Started May 07 02:09:54 PM PDT 24
Finished May 07 02:28:31 PM PDT 24
Peak memory 272712 kb
Host smart-97ab4178-d3f3-4785-b46c-9a31b722cb12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932303181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1932303181
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1376602486
Short name T199
Test name
Test status
Simulation time 9376187548 ps
CPU time 714.29 seconds
Started May 07 02:09:51 PM PDT 24
Finished May 07 02:21:46 PM PDT 24
Peak memory 265236 kb
Host smart-be030d37-5bc5-44ac-96b0-8f275b74dfb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376602486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1376602486
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1824770700
Short name T118
Test name
Test status
Simulation time 4862612429 ps
CPU time 210.17 seconds
Started May 07 02:09:55 PM PDT 24
Finished May 07 02:13:26 PM PDT 24
Peak memory 253940 kb
Host smart-06db689c-63fd-461b-b8ba-83878cb7a2e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824770700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1824770700
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.152314184
Short name T578
Test name
Test status
Simulation time 116119712 ps
CPU time 4.47 seconds
Started May 07 02:09:51 PM PDT 24
Finished May 07 02:09:56 PM PDT 24
Peak memory 240560 kb
Host smart-2e10bb37-903e-42b7-9497-3ec641ccac20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15231
4184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.152314184
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1301765535
Short name T104
Test name
Test status
Simulation time 1939481596 ps
CPU time 31.16 seconds
Started May 07 02:09:49 PM PDT 24
Finished May 07 02:10:21 PM PDT 24
Peak memory 248844 kb
Host smart-5fea8bf4-3e62-4aa4-b618-c801f233dfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13017
65535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1301765535
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.781129050
Short name T403
Test name
Test status
Simulation time 389006035 ps
CPU time 7.41 seconds
Started May 07 02:09:50 PM PDT 24
Finished May 07 02:09:58 PM PDT 24
Peak memory 248740 kb
Host smart-1838e3fb-16f4-4a7d-95ee-06baf8e55ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78112
9050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.781129050
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3080566687
Short name T687
Test name
Test status
Simulation time 6679360400 ps
CPU time 74.93 seconds
Started May 07 02:09:58 PM PDT 24
Finished May 07 02:11:13 PM PDT 24
Peak memory 257008 kb
Host smart-5e71cb26-4e37-4575-b48b-f83efa86d66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30805
66687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3080566687
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2331306958
Short name T85
Test name
Test status
Simulation time 403155482 ps
CPU time 26.7 seconds
Started May 07 02:09:57 PM PDT 24
Finished May 07 02:10:24 PM PDT 24
Peak memory 248760 kb
Host smart-ec1da447-a44d-467c-afa7-2657673fbe2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
06958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2331306958
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.40544920
Short name T360
Test name
Test status
Simulation time 185403660530 ps
CPU time 2461.11 seconds
Started May 07 02:09:57 PM PDT 24
Finished May 07 02:50:59 PM PDT 24
Peak memory 289088 kb
Host smart-6d13a399-6aba-4c42-a2c7-bae6423cbc5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40544920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.40544920
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1929303056
Short name T75
Test name
Test status
Simulation time 9416261487 ps
CPU time 769.78 seconds
Started May 07 02:09:55 PM PDT 24
Finished May 07 02:22:45 PM PDT 24
Peak memory 273388 kb
Host smart-8a5ed0eb-f11b-4730-b5ba-09c0584969db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929303056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1929303056
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.601803387
Short name T526
Test name
Test status
Simulation time 86760877 ps
CPU time 6.87 seconds
Started May 07 02:09:56 PM PDT 24
Finished May 07 02:10:04 PM PDT 24
Peak memory 248756 kb
Host smart-0b232223-4fec-40ea-a47a-2f93550c5686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60180
3387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.601803387
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3654786546
Short name T656
Test name
Test status
Simulation time 4492441862 ps
CPU time 50.12 seconds
Started May 07 02:09:55 PM PDT 24
Finished May 07 02:10:46 PM PDT 24
Peak memory 248848 kb
Host smart-4e95d386-0b14-45d2-ae73-231911d47416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36547
86546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3654786546
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1650814081
Short name T420
Test name
Test status
Simulation time 2091898110 ps
CPU time 42.89 seconds
Started May 07 02:09:55 PM PDT 24
Finished May 07 02:10:39 PM PDT 24
Peak memory 256756 kb
Host smart-b18a4a86-498c-41f4-9ebf-8f4ed46e0921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
14081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1650814081
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4079451512
Short name T81
Test name
Test status
Simulation time 2795077487 ps
CPU time 46.53 seconds
Started May 07 02:09:57 PM PDT 24
Finished May 07 02:10:44 PM PDT 24
Peak memory 248860 kb
Host smart-31d270ed-1807-4d58-95ce-a29d9af38a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40794
51512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4079451512
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.562826051
Short name T422
Test name
Test status
Simulation time 2245290775 ps
CPU time 34.45 seconds
Started May 07 02:10:02 PM PDT 24
Finished May 07 02:10:37 PM PDT 24
Peak memory 256168 kb
Host smart-4e9ebed3-8529-4998-9079-248e82ff5dfd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562826051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.562826051
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.4123380762
Short name T536
Test name
Test status
Simulation time 11610156067 ps
CPU time 931.05 seconds
Started May 07 02:10:08 PM PDT 24
Finished May 07 02:25:40 PM PDT 24
Peak memory 282612 kb
Host smart-83ca5bcd-fa78-4f77-a3e0-0ef2de05dfd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123380762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4123380762
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2106783511
Short name T517
Test name
Test status
Simulation time 20793266892 ps
CPU time 133.5 seconds
Started May 07 02:10:02 PM PDT 24
Finished May 07 02:12:16 PM PDT 24
Peak memory 256952 kb
Host smart-4821e1f3-118e-4ae9-9c3a-1a4c79720052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21067
83511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2106783511
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3811562466
Short name T600
Test name
Test status
Simulation time 470557731 ps
CPU time 20.83 seconds
Started May 07 02:10:02 PM PDT 24
Finished May 07 02:10:23 PM PDT 24
Peak memory 256040 kb
Host smart-dc8ab3c5-b58e-40de-9d06-a27a7c2c5f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
62466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3811562466
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.701158862
Short name T131
Test name
Test status
Simulation time 71294348785 ps
CPU time 1162.09 seconds
Started May 07 02:10:08 PM PDT 24
Finished May 07 02:29:32 PM PDT 24
Peak memory 265208 kb
Host smart-2c8483f2-f2e3-4722-a3d7-f2dfa4c2ac46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701158862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.701158862
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3791292135
Short name T620
Test name
Test status
Simulation time 20168036266 ps
CPU time 552.36 seconds
Started May 07 02:10:09 PM PDT 24
Finished May 07 02:19:23 PM PDT 24
Peak memory 265520 kb
Host smart-df938187-b2e1-46b6-bb0f-a8f32a1aa631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791292135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3791292135
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1658384359
Short name T693
Test name
Test status
Simulation time 5775028843 ps
CPU time 238.37 seconds
Started May 07 02:10:08 PM PDT 24
Finished May 07 02:14:07 PM PDT 24
Peak memory 248376 kb
Host smart-8b815ffd-3466-4cf4-b831-5073d15b25dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658384359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1658384359
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2292162890
Short name T698
Test name
Test status
Simulation time 168441456 ps
CPU time 8.76 seconds
Started May 07 02:10:02 PM PDT 24
Finished May 07 02:10:12 PM PDT 24
Peak memory 248832 kb
Host smart-4a5771a9-735e-4384-8b03-cf3278b4f843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22921
62890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2292162890
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.683644786
Short name T123
Test name
Test status
Simulation time 1344215500 ps
CPU time 40.61 seconds
Started May 07 02:10:02 PM PDT 24
Finished May 07 02:10:44 PM PDT 24
Peak memory 248888 kb
Host smart-a711ed45-13df-4401-86f6-ba1cde297667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68364
4786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.683644786
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3684175713
Short name T282
Test name
Test status
Simulation time 280506320 ps
CPU time 9.54 seconds
Started May 07 02:10:03 PM PDT 24
Finished May 07 02:10:14 PM PDT 24
Peak memory 253132 kb
Host smart-1c564c23-b692-415d-b4ec-fbab674aa78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36841
75713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3684175713
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2464759622
Short name T431
Test name
Test status
Simulation time 48636497 ps
CPU time 7.11 seconds
Started May 07 02:10:04 PM PDT 24
Finished May 07 02:10:11 PM PDT 24
Peak memory 254144 kb
Host smart-4d6fff57-e580-46a0-976a-8b08c1c3b2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
59622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2464759622
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2045934299
Short name T537
Test name
Test status
Simulation time 60291836570 ps
CPU time 1437.92 seconds
Started May 07 02:10:12 PM PDT 24
Finished May 07 02:34:11 PM PDT 24
Peak memory 272312 kb
Host smart-0d948e3e-bb3d-43de-a98a-722d7e0ab407
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045934299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2045934299
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1700469126
Short name T464
Test name
Test status
Simulation time 57040591176 ps
CPU time 4631.91 seconds
Started May 07 02:10:08 PM PDT 24
Finished May 07 03:27:22 PM PDT 24
Peak memory 349232 kb
Host smart-1a596c46-1c1a-47fa-bd09-417e086f1386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700469126 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1700469126
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1114281003
Short name T476
Test name
Test status
Simulation time 14655205504 ps
CPU time 750.16 seconds
Started May 07 02:10:12 PM PDT 24
Finished May 07 02:22:43 PM PDT 24
Peak memory 266316 kb
Host smart-b6357162-8bbc-4185-96b5-ff035058dfac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114281003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1114281003
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1567667454
Short name T311
Test name
Test status
Simulation time 13571098137 ps
CPU time 178.25 seconds
Started May 07 02:10:07 PM PDT 24
Finished May 07 02:13:06 PM PDT 24
Peak memory 256936 kb
Host smart-75cc4509-14e8-441f-9ac4-9956bce7b0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15676
67454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1567667454
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.338290981
Short name T414
Test name
Test status
Simulation time 16076980518 ps
CPU time 57.14 seconds
Started May 07 02:10:07 PM PDT 24
Finished May 07 02:11:06 PM PDT 24
Peak memory 256408 kb
Host smart-8edc61c9-9126-4956-878d-7f0647dc7546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33829
0981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.338290981
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3354632913
Short name T699
Test name
Test status
Simulation time 134985694434 ps
CPU time 1995.36 seconds
Started May 07 02:10:06 PM PDT 24
Finished May 07 02:43:23 PM PDT 24
Peak memory 268308 kb
Host smart-b0f50579-dc65-476c-b5e3-b4b3543853ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354632913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3354632913
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.729198056
Short name T33
Test name
Test status
Simulation time 223119216107 ps
CPU time 1722.36 seconds
Started May 07 02:10:13 PM PDT 24
Finished May 07 02:38:56 PM PDT 24
Peak memory 289252 kb
Host smart-2bf301ad-4c72-4c29-92fc-6d751fab7f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729198056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.729198056
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3247038443
Short name T337
Test name
Test status
Simulation time 31567616887 ps
CPU time 225.64 seconds
Started May 07 02:10:11 PM PDT 24
Finished May 07 02:13:58 PM PDT 24
Peak memory 248140 kb
Host smart-86e5cae9-bd1b-43e0-8dfc-9b5e546d7eb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247038443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3247038443
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1012690419
Short name T590
Test name
Test status
Simulation time 1162150040 ps
CPU time 65.07 seconds
Started May 07 02:10:07 PM PDT 24
Finished May 07 02:11:14 PM PDT 24
Peak memory 256012 kb
Host smart-bae5eadf-8bb0-4ae6-a92e-5adcc4682bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10126
90419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1012690419
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1312587136
Short name T553
Test name
Test status
Simulation time 779533218 ps
CPU time 49.74 seconds
Started May 07 02:10:08 PM PDT 24
Finished May 07 02:10:59 PM PDT 24
Peak memory 255736 kb
Host smart-23c28607-d0dc-45eb-8b64-96f8d2c67cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13125
87136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1312587136
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3046763075
Short name T704
Test name
Test status
Simulation time 601005069 ps
CPU time 37.19 seconds
Started May 07 02:10:13 PM PDT 24
Finished May 07 02:10:51 PM PDT 24
Peak memory 247728 kb
Host smart-3b332348-f4b5-49a0-9c2b-a1991c6b8281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30467
63075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3046763075
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3494314640
Short name T447
Test name
Test status
Simulation time 300183726 ps
CPU time 19.55 seconds
Started May 07 02:10:08 PM PDT 24
Finished May 07 02:10:29 PM PDT 24
Peak memory 248732 kb
Host smart-8baf4a5c-1d19-46d2-ab01-bc2532d07473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34943
14640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3494314640
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2761934334
Short name T88
Test name
Test status
Simulation time 14987345761 ps
CPU time 1290.52 seconds
Started May 07 02:10:14 PM PDT 24
Finished May 07 02:31:46 PM PDT 24
Peak memory 289064 kb
Host smart-5b548f50-553c-4876-8253-1c7ecf648cda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761934334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2761934334
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1352823498
Short name T481
Test name
Test status
Simulation time 660261051478 ps
CPU time 3165.8 seconds
Started May 07 02:10:13 PM PDT 24
Finished May 07 03:03:00 PM PDT 24
Peak memory 322052 kb
Host smart-35cff889-2600-4976-9260-331c961f4540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352823498 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1352823498
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2249830127
Short name T424
Test name
Test status
Simulation time 69037406048 ps
CPU time 1082.41 seconds
Started May 07 02:10:25 PM PDT 24
Finished May 07 02:28:28 PM PDT 24
Peak memory 272044 kb
Host smart-71e66ecb-9639-4947-89ce-012aec445a73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249830127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2249830127
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3975139628
Short name T388
Test name
Test status
Simulation time 1548063771 ps
CPU time 52.92 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:11:14 PM PDT 24
Peak memory 248772 kb
Host smart-e452f18f-aa63-486c-9798-c15bc726da5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751
39628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3975139628
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4048490116
Short name T697
Test name
Test status
Simulation time 69040974 ps
CPU time 9.36 seconds
Started May 07 02:10:14 PM PDT 24
Finished May 07 02:10:24 PM PDT 24
Peak memory 248884 kb
Host smart-1c292800-c2a7-4d2a-8d04-4ab35deaa194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40484
90116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4048490116
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3614847506
Short name T683
Test name
Test status
Simulation time 162312474663 ps
CPU time 2297.92 seconds
Started May 07 02:10:19 PM PDT 24
Finished May 07 02:48:38 PM PDT 24
Peak memory 284056 kb
Host smart-ff0a983d-5f54-4cd5-bbdb-4660e7745c42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614847506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3614847506
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1118944106
Short name T461
Test name
Test status
Simulation time 97210833003 ps
CPU time 2018.57 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:44:00 PM PDT 24
Peak memory 273428 kb
Host smart-7dc9a61c-a7c9-4282-becb-0703e0997252
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118944106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1118944106
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3054734024
Short name T653
Test name
Test status
Simulation time 59541159306 ps
CPU time 530.11 seconds
Started May 07 02:10:26 PM PDT 24
Finished May 07 02:19:16 PM PDT 24
Peak memory 247096 kb
Host smart-f5c2f354-2ad9-496b-931e-16143e44fd3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054734024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3054734024
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3311836344
Short name T663
Test name
Test status
Simulation time 22944146 ps
CPU time 3.17 seconds
Started May 07 02:10:14 PM PDT 24
Finished May 07 02:10:18 PM PDT 24
Peak memory 240588 kb
Host smart-22287144-5986-4a3e-b770-afaa07da3ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
36344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3311836344
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3971226534
Short name T492
Test name
Test status
Simulation time 54293462 ps
CPU time 5.96 seconds
Started May 07 02:10:12 PM PDT 24
Finished May 07 02:10:18 PM PDT 24
Peak memory 247492 kb
Host smart-bcc89015-f80c-4ded-8951-a3b19ff34e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
26534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3971226534
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2484310109
Short name T622
Test name
Test status
Simulation time 295194613 ps
CPU time 34.04 seconds
Started May 07 02:10:21 PM PDT 24
Finished May 07 02:10:56 PM PDT 24
Peak memory 256784 kb
Host smart-f6ae8a78-9dc4-4cc8-a4d4-b53a85492d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24843
10109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2484310109
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1404527646
Short name T394
Test name
Test status
Simulation time 465614662 ps
CPU time 7.87 seconds
Started May 07 02:10:14 PM PDT 24
Finished May 07 02:10:22 PM PDT 24
Peak memory 248776 kb
Host smart-900def86-8cbc-45a2-ab5c-b7fa205750ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14045
27646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1404527646
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2606768310
Short name T516
Test name
Test status
Simulation time 79748672814 ps
CPU time 2535.18 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:52:36 PM PDT 24
Peak memory 289792 kb
Host smart-10b49601-e4dc-4958-b7a4-08ec8e221841
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606768310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2606768310
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3665944115
Short name T610
Test name
Test status
Simulation time 15546861081 ps
CPU time 1381.2 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:33:22 PM PDT 24
Peak memory 288920 kb
Host smart-64a0bf3b-7168-4492-b6f8-0245b650dbce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665944115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3665944115
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.432557940
Short name T218
Test name
Test status
Simulation time 1886642431 ps
CPU time 145.37 seconds
Started May 07 02:10:21 PM PDT 24
Finished May 07 02:12:47 PM PDT 24
Peak memory 256936 kb
Host smart-c40f3bfa-5877-45fc-a3a0-37dd3a88ec93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43255
7940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.432557940
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1608574261
Short name T413
Test name
Test status
Simulation time 153876858 ps
CPU time 18.78 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:10:39 PM PDT 24
Peak memory 249272 kb
Host smart-932937b2-c3db-4eac-8851-143e2c37e5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16085
74261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1608574261
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3281678632
Short name T349
Test name
Test status
Simulation time 39113868303 ps
CPU time 1836.62 seconds
Started May 07 02:10:25 PM PDT 24
Finished May 07 02:41:02 PM PDT 24
Peak memory 288360 kb
Host smart-324199a1-7bb5-422d-88c7-b55d3003b089
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281678632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3281678632
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1629103470
Short name T13
Test name
Test status
Simulation time 41159202999 ps
CPU time 2344.63 seconds
Started May 07 02:10:24 PM PDT 24
Finished May 07 02:49:29 PM PDT 24
Peak memory 288368 kb
Host smart-91765a79-d21b-4fb7-a212-92c6dd8a3af8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629103470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1629103470
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.560713979
Short name T611
Test name
Test status
Simulation time 46162986359 ps
CPU time 430.86 seconds
Started May 07 02:10:25 PM PDT 24
Finished May 07 02:17:37 PM PDT 24
Peak memory 248244 kb
Host smart-d5d4ac7d-1245-4783-8b0b-21ddda3d26ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560713979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.560713979
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4268685675
Short name T672
Test name
Test status
Simulation time 298754092 ps
CPU time 32.59 seconds
Started May 07 02:10:24 PM PDT 24
Finished May 07 02:10:58 PM PDT 24
Peak memory 248772 kb
Host smart-59441776-1bd7-4701-a96e-68c24ef23360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
85675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4268685675
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1898001640
Short name T54
Test name
Test status
Simulation time 686853294 ps
CPU time 43.47 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:11:05 PM PDT 24
Peak memory 255632 kb
Host smart-1cfe7ff9-8e6f-4a8e-be19-4e6717f86aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18980
01640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1898001640
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.434476440
Short name T289
Test name
Test status
Simulation time 161267946 ps
CPU time 15.59 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:10:36 PM PDT 24
Peak memory 248752 kb
Host smart-7a9bbd0f-21ff-48a7-8767-b6a561934f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43447
6440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.434476440
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1809288513
Short name T26
Test name
Test status
Simulation time 95498344 ps
CPU time 8.67 seconds
Started May 07 02:10:20 PM PDT 24
Finished May 07 02:10:30 PM PDT 24
Peak memory 254148 kb
Host smart-8cbdaa05-1398-4bde-b73c-7ac14e37d665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18092
88513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1809288513
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.128585470
Short name T593
Test name
Test status
Simulation time 53306393204 ps
CPU time 5427.82 seconds
Started May 07 02:10:24 PM PDT 24
Finished May 07 03:40:53 PM PDT 24
Peak memory 354896 kb
Host smart-a0b9779c-e196-4fcf-9d3e-30e998f70637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128585470 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.128585470
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2915830353
Short name T56
Test name
Test status
Simulation time 30287905376 ps
CPU time 624.5 seconds
Started May 07 02:10:31 PM PDT 24
Finished May 07 02:20:56 PM PDT 24
Peak memory 265264 kb
Host smart-a4374db8-5727-44ba-802d-ba3af694f349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915830353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2915830353
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3916457758
Short name T438
Test name
Test status
Simulation time 16678352300 ps
CPU time 259.26 seconds
Started May 07 02:10:34 PM PDT 24
Finished May 07 02:14:54 PM PDT 24
Peak memory 257000 kb
Host smart-5f980b5f-cf47-466e-895b-312590c64eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39164
57758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3916457758
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2304894545
Short name T621
Test name
Test status
Simulation time 1424938411 ps
CPU time 20.13 seconds
Started May 07 02:10:30 PM PDT 24
Finished May 07 02:10:50 PM PDT 24
Peak memory 254884 kb
Host smart-90adc584-b1d3-42f1-ba27-f502f0597c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23048
94545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2304894545
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.501360565
Short name T362
Test name
Test status
Simulation time 59552593335 ps
CPU time 3183.59 seconds
Started May 07 02:10:38 PM PDT 24
Finished May 07 03:03:43 PM PDT 24
Peak memory 289036 kb
Host smart-e57cd802-e9b9-43e9-8635-e76214482723
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501360565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.501360565
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3611203648
Short name T571
Test name
Test status
Simulation time 46785276805 ps
CPU time 980.96 seconds
Started May 07 02:10:36 PM PDT 24
Finished May 07 02:26:58 PM PDT 24
Peak memory 281604 kb
Host smart-1edb3bc7-60fa-46b7-9ed4-6b4a9fef810f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611203648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3611203648
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3998092780
Short name T251
Test name
Test status
Simulation time 27951619069 ps
CPU time 270.17 seconds
Started May 07 02:10:37 PM PDT 24
Finished May 07 02:15:08 PM PDT 24
Peak memory 247304 kb
Host smart-583d751f-5ad5-47bf-b8d8-870af17d7f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998092780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3998092780
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3977957316
Short name T410
Test name
Test status
Simulation time 3890745085 ps
CPU time 47.37 seconds
Started May 07 02:10:31 PM PDT 24
Finished May 07 02:11:19 PM PDT 24
Peak memory 256240 kb
Host smart-5affd116-1a9b-4019-9a4a-ff925a053114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39779
57316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3977957316
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2652116996
Short name T387
Test name
Test status
Simulation time 2639454600 ps
CPU time 26.74 seconds
Started May 07 02:10:32 PM PDT 24
Finished May 07 02:10:59 PM PDT 24
Peak memory 255672 kb
Host smart-b21b7398-a2f3-4bc5-98e3-866c838c09a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26521
16996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2652116996
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1943587725
Short name T62
Test name
Test status
Simulation time 794979284 ps
CPU time 24.67 seconds
Started May 07 02:10:33 PM PDT 24
Finished May 07 02:10:58 PM PDT 24
Peak memory 255312 kb
Host smart-e6bd5dbd-ded9-451c-8e82-b2dab0b360c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19435
87725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1943587725
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3624968153
Short name T307
Test name
Test status
Simulation time 476263787 ps
CPU time 46.58 seconds
Started May 07 02:10:27 PM PDT 24
Finished May 07 02:11:15 PM PDT 24
Peak memory 248772 kb
Host smart-d64f6d46-5a0d-4c2e-aa41-80e1e947a447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
68153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3624968153
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.4017971089
Short name T572
Test name
Test status
Simulation time 47131560083 ps
CPU time 4394.5 seconds
Started May 07 02:10:37 PM PDT 24
Finished May 07 03:23:52 PM PDT 24
Peak memory 321992 kb
Host smart-38f161f4-6adc-4fa1-8979-c714f71ec7f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017971089 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.4017971089
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.865026508
Short name T246
Test name
Test status
Simulation time 25979456780 ps
CPU time 1213.98 seconds
Started May 07 02:10:41 PM PDT 24
Finished May 07 02:30:56 PM PDT 24
Peak memory 281784 kb
Host smart-53a55f20-a80b-4385-954f-c537e56b6632
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865026508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.865026508
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1022928756
Short name T84
Test name
Test status
Simulation time 510389113 ps
CPU time 20.43 seconds
Started May 07 02:10:42 PM PDT 24
Finished May 07 02:11:03 PM PDT 24
Peak memory 248664 kb
Host smart-b6c76340-1ab9-4af1-9cd8-60683fb6079d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
28756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1022928756
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2095229401
Short name T348
Test name
Test status
Simulation time 19085736068 ps
CPU time 1044.98 seconds
Started May 07 02:10:42 PM PDT 24
Finished May 07 02:28:08 PM PDT 24
Peak memory 265224 kb
Host smart-a35c8e5b-6b9e-4a49-9a73-d267412e2019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095229401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2095229401
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.836553128
Short name T545
Test name
Test status
Simulation time 51070374023 ps
CPU time 675.42 seconds
Started May 07 02:10:41 PM PDT 24
Finished May 07 02:21:58 PM PDT 24
Peak memory 265436 kb
Host smart-6752ab9a-b06b-43f2-a13a-0566edbc9cf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836553128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.836553128
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2928825534
Short name T40
Test name
Test status
Simulation time 8346840257 ps
CPU time 353.28 seconds
Started May 07 02:10:41 PM PDT 24
Finished May 07 02:16:35 PM PDT 24
Peak memory 254736 kb
Host smart-ad05b144-1c30-4d80-bff8-39f591353dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928825534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2928825534
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1728751645
Short name T669
Test name
Test status
Simulation time 371503735 ps
CPU time 25.65 seconds
Started May 07 02:10:37 PM PDT 24
Finished May 07 02:11:03 PM PDT 24
Peak memory 248904 kb
Host smart-8bb457ab-a460-44f5-ba27-3f220f3fb406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
51645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1728751645
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1176741620
Short name T61
Test name
Test status
Simulation time 322586253 ps
CPU time 22.03 seconds
Started May 07 02:10:42 PM PDT 24
Finished May 07 02:11:05 PM PDT 24
Peak memory 255244 kb
Host smart-fbaf03c0-388a-436e-bd14-0cac9eff3feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11767
41620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1176741620
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1227527509
Short name T406
Test name
Test status
Simulation time 219043566 ps
CPU time 15.03 seconds
Started May 07 02:10:40 PM PDT 24
Finished May 07 02:10:56 PM PDT 24
Peak memory 248780 kb
Host smart-534cb8bd-fdb9-47cd-9564-3d9c14c57b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12275
27509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1227527509
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2123617750
Short name T252
Test name
Test status
Simulation time 1161576807 ps
CPU time 27.96 seconds
Started May 07 02:10:37 PM PDT 24
Finished May 07 02:11:06 PM PDT 24
Peak memory 256004 kb
Host smart-8d5bc04b-275e-432e-9ae0-d143a35bf7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236
17750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2123617750
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2731014529
Short name T124
Test name
Test status
Simulation time 153935809951 ps
CPU time 1932.73 seconds
Started May 07 02:10:42 PM PDT 24
Finished May 07 02:42:55 PM PDT 24
Peak memory 273400 kb
Host smart-d504a61c-6a28-4254-a3a9-32902ac49899
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731014529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2731014529
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4064342393
Short name T120
Test name
Test status
Simulation time 41906544217 ps
CPU time 708.73 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:22:39 PM PDT 24
Peak memory 267368 kb
Host smart-ed72270a-d6d5-4fd7-8834-087ef421b7f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064342393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4064342393
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1940976394
Short name T405
Test name
Test status
Simulation time 113826821 ps
CPU time 9.16 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:10:58 PM PDT 24
Peak memory 248756 kb
Host smart-02360b68-5cab-4bb9-9bb1-3c1bdaa98df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19409
76394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1940976394
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.14827370
Short name T569
Test name
Test status
Simulation time 538563213 ps
CPU time 12.59 seconds
Started May 07 02:10:48 PM PDT 24
Finished May 07 02:11:01 PM PDT 24
Peak memory 254804 kb
Host smart-01d79937-73f0-40e8-bdf7-63dac4b736dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14827
370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.14827370
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.181458149
Short name T707
Test name
Test status
Simulation time 306030214293 ps
CPU time 1517.11 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:36:07 PM PDT 24
Peak memory 273412 kb
Host smart-137c8cea-eba2-4899-be6e-66b27659e78d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181458149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.181458149
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2996332378
Short name T497
Test name
Test status
Simulation time 141249465095 ps
CPU time 2195.68 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:47:26 PM PDT 24
Peak memory 273504 kb
Host smart-84114400-edd6-4a56-80af-9f4800fedf96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996332378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2996332378
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2137959764
Short name T335
Test name
Test status
Simulation time 2414042887 ps
CPU time 106.43 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:12:36 PM PDT 24
Peak memory 253724 kb
Host smart-803fcffd-c90a-4c29-b7cd-9c7deb17a94e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137959764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2137959764
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1115537473
Short name T80
Test name
Test status
Simulation time 215034108 ps
CPU time 26.36 seconds
Started May 07 02:10:50 PM PDT 24
Finished May 07 02:11:17 PM PDT 24
Peak memory 248780 kb
Host smart-ba76a447-7384-4d0a-a143-ebfc56f83779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11155
37473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1115537473
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3179318974
Short name T641
Test name
Test status
Simulation time 2292848631 ps
CPU time 60.93 seconds
Started May 07 02:10:48 PM PDT 24
Finished May 07 02:11:50 PM PDT 24
Peak memory 256068 kb
Host smart-7d7fab92-4bf7-4e32-9dc1-51477e2f685b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31793
18974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3179318974
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.707048797
Short name T674
Test name
Test status
Simulation time 247754190 ps
CPU time 7.66 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:10:58 PM PDT 24
Peak memory 253428 kb
Host smart-0035f01c-aef0-4afe-a79e-8457d2f78893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70704
8797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.707048797
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4210878448
Short name T651
Test name
Test status
Simulation time 249654594 ps
CPU time 15.1 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:11:04 PM PDT 24
Peak memory 254632 kb
Host smart-386211ee-36fa-49e8-8210-dd4981b063cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42108
78448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4210878448
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1701447023
Short name T649
Test name
Test status
Simulation time 19699237620 ps
CPU time 1596.98 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:37:27 PM PDT 24
Peak memory 289352 kb
Host smart-28fa28fd-bc52-4c10-ad43-e019a5057e88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701447023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1701447023
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1233700948
Short name T220
Test name
Test status
Simulation time 55986449 ps
CPU time 3.25 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:35 PM PDT 24
Peak memory 248940 kb
Host smart-ae4be517-e4d1-4c54-bd57-279c3f515c79
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1233700948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1233700948
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1237036028
Short name T451
Test name
Test status
Simulation time 49776017274 ps
CPU time 2839.36 seconds
Started May 07 02:08:25 PM PDT 24
Finished May 07 02:55:45 PM PDT 24
Peak memory 288184 kb
Host smart-06abbfe8-c73f-40ce-95a3-2a58ded9ae48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237036028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1237036028
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1238897371
Short name T688
Test name
Test status
Simulation time 369417815 ps
CPU time 11.07 seconds
Started May 07 02:08:26 PM PDT 24
Finished May 07 02:08:38 PM PDT 24
Peak memory 248800 kb
Host smart-f0500a3b-b9e3-4f58-a352-668828259a38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1238897371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1238897371
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.761440398
Short name T603
Test name
Test status
Simulation time 788808692 ps
CPU time 66.4 seconds
Started May 07 02:08:26 PM PDT 24
Finished May 07 02:09:33 PM PDT 24
Peak memory 256792 kb
Host smart-910d8bac-32db-4ac4-8cc4-0a3790eeb2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76144
0398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.761440398
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2159890681
Short name T627
Test name
Test status
Simulation time 1264009149 ps
CPU time 33.99 seconds
Started May 07 02:08:25 PM PDT 24
Finished May 07 02:08:59 PM PDT 24
Peak memory 256900 kb
Host smart-c772a2c9-d012-4ced-8aa8-718f7300d9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21598
90681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2159890681
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2058832751
Short name T100
Test name
Test status
Simulation time 33397730217 ps
CPU time 655.13 seconds
Started May 07 02:08:24 PM PDT 24
Finished May 07 02:19:20 PM PDT 24
Peak memory 272788 kb
Host smart-f1edb721-78cf-4089-8a3c-92e62bc2f070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058832751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2058832751
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2703810139
Short name T630
Test name
Test status
Simulation time 25584372655 ps
CPU time 603.34 seconds
Started May 07 02:08:34 PM PDT 24
Finished May 07 02:18:38 PM PDT 24
Peak memory 272484 kb
Host smart-9a067a58-39e6-4db1-a502-d83e8441f854
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703810139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2703810139
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2518085306
Short name T343
Test name
Test status
Simulation time 16393830713 ps
CPU time 179.07 seconds
Started May 07 02:08:24 PM PDT 24
Finished May 07 02:11:24 PM PDT 24
Peak memory 248008 kb
Host smart-c5a27b50-2b0c-41db-8a01-b7fee00e138d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518085306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2518085306
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2416315451
Short name T675
Test name
Test status
Simulation time 43054399 ps
CPU time 2.93 seconds
Started May 07 02:08:24 PM PDT 24
Finished May 07 02:08:27 PM PDT 24
Peak memory 240540 kb
Host smart-0241ec58-06bf-4b52-bbea-707674271d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
15451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2416315451
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1200080049
Short name T439
Test name
Test status
Simulation time 571939827 ps
CPU time 10.64 seconds
Started May 07 02:08:26 PM PDT 24
Finished May 07 02:08:37 PM PDT 24
Peak memory 254232 kb
Host smart-3737174e-9169-4907-a50f-1e85246973cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
80049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1200080049
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3571990059
Short name T10
Test name
Test status
Simulation time 695027440 ps
CPU time 17.2 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:08:50 PM PDT 24
Peak memory 270196 kb
Host smart-d182b2ca-7205-4672-b07e-fae2e7760cdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3571990059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3571990059
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.697270836
Short name T380
Test name
Test status
Simulation time 189992595 ps
CPU time 16.18 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:08:52 PM PDT 24
Peak memory 255316 kb
Host smart-e526fd90-1807-41c3-b008-6c2359d829ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69727
0836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.697270836
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1242321751
Short name T714
Test name
Test status
Simulation time 2225011701 ps
CPU time 34.61 seconds
Started May 07 02:08:28 PM PDT 24
Finished May 07 02:09:03 PM PDT 24
Peak memory 248848 kb
Host smart-762a71ee-6f8b-4f38-b0af-e697f249e120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12423
21751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1242321751
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.635118391
Short name T19
Test name
Test status
Simulation time 12116253111 ps
CPU time 273.47 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:13:06 PM PDT 24
Peak memory 257028 kb
Host smart-b9bb36a3-b3cd-4d9b-acaf-b0243267ddcf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635118391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.635118391
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1384674539
Short name T684
Test name
Test status
Simulation time 28761579292 ps
CPU time 1529.63 seconds
Started May 07 02:10:53 PM PDT 24
Finished May 07 02:36:24 PM PDT 24
Peak memory 273404 kb
Host smart-69c12df1-ec28-4783-8160-1e0241a609ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384674539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1384674539
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.552490239
Short name T16
Test name
Test status
Simulation time 7952772184 ps
CPU time 106.5 seconds
Started May 07 02:10:54 PM PDT 24
Finished May 07 02:12:41 PM PDT 24
Peak memory 249900 kb
Host smart-013c869d-ace2-46cd-a200-09fdb4bc25aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55249
0239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.552490239
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1633114342
Short name T381
Test name
Test status
Simulation time 99891057 ps
CPU time 4.37 seconds
Started May 07 02:10:55 PM PDT 24
Finished May 07 02:11:00 PM PDT 24
Peak memory 240732 kb
Host smart-36729247-42b1-499d-ad64-5ba97342a275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16331
14342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1633114342
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1137593234
Short name T38
Test name
Test status
Simulation time 14935747757 ps
CPU time 1286.52 seconds
Started May 07 02:10:55 PM PDT 24
Finished May 07 02:32:22 PM PDT 24
Peak memory 289164 kb
Host smart-1e489dff-80d4-4aec-87cc-c829ba70c994
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137593234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1137593234
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.683092857
Short name T703
Test name
Test status
Simulation time 12363641699 ps
CPU time 480.51 seconds
Started May 07 02:10:54 PM PDT 24
Finished May 07 02:18:56 PM PDT 24
Peak memory 254592 kb
Host smart-473f361e-2218-41e5-8d95-e15135ba49f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683092857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.683092857
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3084499310
Short name T98
Test name
Test status
Simulation time 782160228 ps
CPU time 26.83 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:11:17 PM PDT 24
Peak memory 248776 kb
Host smart-33abf5d4-78cf-4dc6-9173-d52d39910886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844
99310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3084499310
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1347021811
Short name T76
Test name
Test status
Simulation time 256771274 ps
CPU time 14.12 seconds
Started May 07 02:10:47 PM PDT 24
Finished May 07 02:11:02 PM PDT 24
Peak memory 255068 kb
Host smart-0f0ea625-3bab-4457-b478-eb0146aa014d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
21811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1347021811
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3529963526
Short name T313
Test name
Test status
Simulation time 1177047886 ps
CPU time 18.02 seconds
Started May 07 02:10:53 PM PDT 24
Finished May 07 02:11:12 PM PDT 24
Peak memory 248788 kb
Host smart-23675670-2e9a-4fbc-9f43-2552670755de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35299
63526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3529963526
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2634591924
Short name T65
Test name
Test status
Simulation time 142773058 ps
CPU time 10.16 seconds
Started May 07 02:10:49 PM PDT 24
Finished May 07 02:11:00 PM PDT 24
Peak memory 248824 kb
Host smart-82b010c9-4c60-4536-8eac-9ed784a09334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26345
91924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2634591924
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.4249905139
Short name T194
Test name
Test status
Simulation time 29711858605 ps
CPU time 3500.42 seconds
Started May 07 02:10:54 PM PDT 24
Finished May 07 03:09:15 PM PDT 24
Peak memory 330884 kb
Host smart-0558b481-62d8-4f7a-bbde-a9d76a7bba49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249905139 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.4249905139
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1849004855
Short name T386
Test name
Test status
Simulation time 8858472659 ps
CPU time 167.14 seconds
Started May 07 02:11:01 PM PDT 24
Finished May 07 02:13:49 PM PDT 24
Peak memory 250896 kb
Host smart-1c6248aa-b2e3-4eb6-8815-3e0d9865b905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18490
04855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1849004855
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1204365403
Short name T441
Test name
Test status
Simulation time 1011249913 ps
CPU time 15.88 seconds
Started May 07 02:11:04 PM PDT 24
Finished May 07 02:11:20 PM PDT 24
Peak memory 252980 kb
Host smart-ffb31946-bf97-4025-bf14-97a24f8198e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043
65403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1204365403
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.319624471
Short name T353
Test name
Test status
Simulation time 27791935789 ps
CPU time 1367.42 seconds
Started May 07 02:10:59 PM PDT 24
Finished May 07 02:33:47 PM PDT 24
Peak memory 289784 kb
Host smart-9f639d07-022e-4e6e-b362-fc381f13144b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319624471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.319624471
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3766294289
Short name T312
Test name
Test status
Simulation time 233929960210 ps
CPU time 2444.47 seconds
Started May 07 02:11:06 PM PDT 24
Finished May 07 02:51:52 PM PDT 24
Peak memory 281600 kb
Host smart-fa5a8334-b397-4e0d-9034-c98d4eaa9c6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766294289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3766294289
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2334296480
Short name T666
Test name
Test status
Simulation time 5627780424 ps
CPU time 68.03 seconds
Started May 07 02:10:53 PM PDT 24
Finished May 07 02:12:01 PM PDT 24
Peak memory 248848 kb
Host smart-b94e78a5-4f23-4b22-9d91-5b2513a35831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23342
96480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2334296480
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3964180111
Short name T112
Test name
Test status
Simulation time 3663391646 ps
CPU time 28.19 seconds
Started May 07 02:11:00 PM PDT 24
Finished May 07 02:11:29 PM PDT 24
Peak memory 247628 kb
Host smart-bd33f545-9976-46c2-977c-545602da1a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39641
80111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3964180111
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2845379786
Short name T132
Test name
Test status
Simulation time 1305884229 ps
CPU time 24.66 seconds
Started May 07 02:10:55 PM PDT 24
Finished May 07 02:11:20 PM PDT 24
Peak memory 248784 kb
Host smart-6108d789-75c1-4513-a474-29a3e9da0281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28453
79786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2845379786
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1335246217
Short name T103
Test name
Test status
Simulation time 195740505667 ps
CPU time 3026.27 seconds
Started May 07 02:11:05 PM PDT 24
Finished May 07 03:01:33 PM PDT 24
Peak memory 305916 kb
Host smart-1077bfbf-8290-47fc-8d00-26ea77a7aaef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335246217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1335246217
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1624186105
Short name T676
Test name
Test status
Simulation time 47868612035 ps
CPU time 3420.32 seconds
Started May 07 02:11:06 PM PDT 24
Finished May 07 03:08:08 PM PDT 24
Peak memory 297776 kb
Host smart-106effea-842f-40b9-b15e-72cdbbb7f39e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624186105 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1624186105
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4166978422
Short name T483
Test name
Test status
Simulation time 12633417904 ps
CPU time 124.82 seconds
Started May 07 02:11:13 PM PDT 24
Finished May 07 02:13:18 PM PDT 24
Peak memory 256940 kb
Host smart-561e3dc3-3e7f-4eec-93a1-1bb2916c2ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41669
78422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4166978422
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2199912870
Short name T638
Test name
Test status
Simulation time 966622611 ps
CPU time 38.2 seconds
Started May 07 02:11:11 PM PDT 24
Finished May 07 02:11:50 PM PDT 24
Peak memory 256080 kb
Host smart-3d2d79b0-5f0a-4c89-b205-88cc3a26f9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
12870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2199912870
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1281577576
Short name T354
Test name
Test status
Simulation time 100182520465 ps
CPU time 1514.68 seconds
Started May 07 02:11:11 PM PDT 24
Finished May 07 02:36:27 PM PDT 24
Peak memory 266244 kb
Host smart-6a70228b-e6c7-4a0c-8265-c72159065dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281577576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1281577576
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.738632363
Short name T382
Test name
Test status
Simulation time 16067114011 ps
CPU time 1553.42 seconds
Started May 07 02:11:19 PM PDT 24
Finished May 07 02:37:13 PM PDT 24
Peak memory 288796 kb
Host smart-fa8f932a-3538-45d3-a1ab-ba5b507770b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738632363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.738632363
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2032904397
Short name T217
Test name
Test status
Simulation time 802230771 ps
CPU time 48.65 seconds
Started May 07 02:11:05 PM PDT 24
Finished May 07 02:11:55 PM PDT 24
Peak memory 248792 kb
Host smart-61924c25-88a4-4ac0-8503-ceee95d9c5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
04397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2032904397
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3361497146
Short name T510
Test name
Test status
Simulation time 276215811 ps
CPU time 17.09 seconds
Started May 07 02:11:06 PM PDT 24
Finished May 07 02:11:24 PM PDT 24
Peak memory 254924 kb
Host smart-e8e848af-d155-4e45-9c86-c4f5d06d0fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
97146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3361497146
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3616828662
Short name T708
Test name
Test status
Simulation time 412018613 ps
CPU time 30.95 seconds
Started May 07 02:11:13 PM PDT 24
Finished May 07 02:11:45 PM PDT 24
Peak memory 248700 kb
Host smart-32bd16ec-4117-4446-ab5d-1be9744c3e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168
28662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3616828662
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4209008548
Short name T453
Test name
Test status
Simulation time 111897575 ps
CPU time 9.32 seconds
Started May 07 02:11:06 PM PDT 24
Finished May 07 02:11:16 PM PDT 24
Peak memory 254452 kb
Host smart-10a0c915-6ce6-45aa-be3e-4d4affd6bdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
08548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4209008548
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1543532827
Short name T60
Test name
Test status
Simulation time 58534581925 ps
CPU time 3359.8 seconds
Started May 07 02:11:17 PM PDT 24
Finished May 07 03:07:18 PM PDT 24
Peak memory 322456 kb
Host smart-0398e834-7213-4503-9e68-16ffa86657e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543532827 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1543532827
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.302550673
Short name T434
Test name
Test status
Simulation time 56296941988 ps
CPU time 3252.96 seconds
Started May 07 02:11:31 PM PDT 24
Finished May 07 03:05:45 PM PDT 24
Peak memory 289592 kb
Host smart-6536b14c-7f7c-4d9a-a8b2-20556ebec22a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302550673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.302550673
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3895909025
Short name T427
Test name
Test status
Simulation time 1295185617 ps
CPU time 34.8 seconds
Started May 07 02:11:25 PM PDT 24
Finished May 07 02:12:00 PM PDT 24
Peak memory 256140 kb
Host smart-dbf6087b-17b3-46a1-9419-d35266189101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38959
09025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3895909025
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1917260931
Short name T47
Test name
Test status
Simulation time 649397165 ps
CPU time 9.12 seconds
Started May 07 02:11:25 PM PDT 24
Finished May 07 02:11:34 PM PDT 24
Peak memory 252528 kb
Host smart-c33fc843-0d2b-4032-9fd6-d8f47c479a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19172
60931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1917260931
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3703586305
Short name T605
Test name
Test status
Simulation time 39911012982 ps
CPU time 1317.16 seconds
Started May 07 02:11:29 PM PDT 24
Finished May 07 02:33:27 PM PDT 24
Peak memory 265252 kb
Host smart-c0ff6ba7-f245-4ad1-8da1-a3fe735468f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703586305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3703586305
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2331749923
Short name T474
Test name
Test status
Simulation time 184554672730 ps
CPU time 2481.4 seconds
Started May 07 02:11:30 PM PDT 24
Finished May 07 02:52:53 PM PDT 24
Peak memory 281524 kb
Host smart-e096ebde-665e-4425-b1d0-d99de19b9748
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331749923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2331749923
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3137410009
Short name T336
Test name
Test status
Simulation time 31351658514 ps
CPU time 209.9 seconds
Started May 07 02:11:33 PM PDT 24
Finished May 07 02:15:04 PM PDT 24
Peak memory 248268 kb
Host smart-007aac2b-00c9-4a97-8dfa-1512291e3b5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137410009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3137410009
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2407272767
Short name T538
Test name
Test status
Simulation time 924145008 ps
CPU time 53.31 seconds
Started May 07 02:11:17 PM PDT 24
Finished May 07 02:12:11 PM PDT 24
Peak memory 248956 kb
Host smart-d7f2cc1f-b01f-4cf9-8b98-2df0de8eeb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24072
72767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2407272767
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1087995522
Short name T654
Test name
Test status
Simulation time 3704328119 ps
CPU time 56.05 seconds
Started May 07 02:11:26 PM PDT 24
Finished May 07 02:12:23 PM PDT 24
Peak memory 254448 kb
Host smart-1eb5685f-ba4f-4c86-ace8-141b15a2a936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10879
95522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1087995522
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.529509379
Short name T467
Test name
Test status
Simulation time 928916663 ps
CPU time 24.36 seconds
Started May 07 02:11:25 PM PDT 24
Finished May 07 02:11:50 PM PDT 24
Peak memory 256512 kb
Host smart-32885c73-7031-40fc-b7bd-46c0ee1adffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52950
9379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.529509379
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3566416701
Short name T573
Test name
Test status
Simulation time 294111616 ps
CPU time 15.94 seconds
Started May 07 02:11:19 PM PDT 24
Finished May 07 02:11:35 PM PDT 24
Peak memory 248712 kb
Host smart-1ea14e02-22a9-4362-8686-8150954ae8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35664
16701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3566416701
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3666079568
Short name T125
Test name
Test status
Simulation time 89636979902 ps
CPU time 3024.22 seconds
Started May 07 02:11:33 PM PDT 24
Finished May 07 03:01:58 PM PDT 24
Peak memory 289588 kb
Host smart-9e39316a-e9c9-4007-83b7-7889863d155f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666079568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3666079568
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.798770993
Short name T195
Test name
Test status
Simulation time 18599262395 ps
CPU time 1576.41 seconds
Started May 07 02:11:30 PM PDT 24
Finished May 07 02:37:47 PM PDT 24
Peak memory 289864 kb
Host smart-a032490c-df75-4eb4-bc6a-160b33a313f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798770993 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.798770993
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.510559007
Short name T532
Test name
Test status
Simulation time 557873300127 ps
CPU time 2009.9 seconds
Started May 07 02:11:37 PM PDT 24
Finished May 07 02:45:07 PM PDT 24
Peak memory 289344 kb
Host smart-0d235571-a159-4edc-9ea6-859f5500530f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510559007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.510559007
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3375893558
Short name T585
Test name
Test status
Simulation time 1356872195 ps
CPU time 70.98 seconds
Started May 07 02:11:36 PM PDT 24
Finished May 07 02:12:48 PM PDT 24
Peak memory 256680 kb
Host smart-3db28486-cd71-47a5-8d14-54a6af775728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33758
93558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3375893558
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1138613536
Short name T646
Test name
Test status
Simulation time 1393163066 ps
CPU time 19.6 seconds
Started May 07 02:11:37 PM PDT 24
Finished May 07 02:11:57 PM PDT 24
Peak memory 249196 kb
Host smart-d285a6de-6d48-408a-b750-9482d33c5cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11386
13536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1138613536
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2733520732
Short name T710
Test name
Test status
Simulation time 564988196928 ps
CPU time 2273.71 seconds
Started May 07 02:11:37 PM PDT 24
Finished May 07 02:49:32 PM PDT 24
Peak memory 288764 kb
Host smart-7f89b66c-bd08-44df-b5ca-74700c48a678
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733520732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2733520732
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1807892135
Short name T596
Test name
Test status
Simulation time 104988819826 ps
CPU time 1670.23 seconds
Started May 07 02:11:37 PM PDT 24
Finished May 07 02:39:28 PM PDT 24
Peak memory 273096 kb
Host smart-6f6501fb-0b32-46ca-b767-b67e57b9cb75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807892135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1807892135
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3206040936
Short name T323
Test name
Test status
Simulation time 17474098541 ps
CPU time 342.68 seconds
Started May 07 02:11:36 PM PDT 24
Finished May 07 02:17:20 PM PDT 24
Peak memory 247104 kb
Host smart-ae8a4f37-258c-48a4-bf2a-839f38064138
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206040936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3206040936
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.543799475
Short name T458
Test name
Test status
Simulation time 1584027245 ps
CPU time 23.45 seconds
Started May 07 02:11:32 PM PDT 24
Finished May 07 02:11:56 PM PDT 24
Peak memory 256044 kb
Host smart-d8a8dfc9-7890-47c3-8083-dbf18385e777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54379
9475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.543799475
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2562950631
Short name T524
Test name
Test status
Simulation time 166003244 ps
CPU time 10.92 seconds
Started May 07 02:11:35 PM PDT 24
Finished May 07 02:11:47 PM PDT 24
Peak memory 253016 kb
Host smart-eb07f9e2-8efb-40f4-87fd-ca9294260bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25629
50631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2562950631
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1460885620
Short name T316
Test name
Test status
Simulation time 963260963 ps
CPU time 56.44 seconds
Started May 07 02:11:37 PM PDT 24
Finished May 07 02:12:34 PM PDT 24
Peak memory 247708 kb
Host smart-6ca76597-a375-4722-bc59-1b25d61adfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
85620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1460885620
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1189537169
Short name T272
Test name
Test status
Simulation time 675442308 ps
CPU time 26.89 seconds
Started May 07 02:11:31 PM PDT 24
Finished May 07 02:11:59 PM PDT 24
Peak memory 248788 kb
Host smart-7991c7a3-e8e2-4df6-9119-9728b7e7d3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11895
37169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1189537169
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.103740790
Short name T278
Test name
Test status
Simulation time 22051196889 ps
CPU time 1745.52 seconds
Started May 07 02:11:36 PM PDT 24
Finished May 07 02:40:43 PM PDT 24
Peak memory 306104 kb
Host smart-d3791a84-0c23-4fe0-b878-ebc577a62ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103740790 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.103740790
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2297820174
Short name T399
Test name
Test status
Simulation time 20140700369 ps
CPU time 1156.07 seconds
Started May 07 02:11:43 PM PDT 24
Finished May 07 02:31:00 PM PDT 24
Peak memory 287784 kb
Host smart-ef111c48-521a-4623-b043-6da51f54a03c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297820174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2297820174
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.927444602
Short name T657
Test name
Test status
Simulation time 11157062972 ps
CPU time 300.73 seconds
Started May 07 02:11:42 PM PDT 24
Finished May 07 02:16:44 PM PDT 24
Peak memory 257012 kb
Host smart-c9d537ea-7cc3-466b-8e5e-6066c29b8e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92744
4602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.927444602
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.959823720
Short name T444
Test name
Test status
Simulation time 610969806 ps
CPU time 32.97 seconds
Started May 07 02:11:44 PM PDT 24
Finished May 07 02:12:17 PM PDT 24
Peak memory 248788 kb
Host smart-20b2fe2f-fd7f-4142-b740-fae106ad8333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95982
3720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.959823720
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1251241645
Short name T599
Test name
Test status
Simulation time 54182540357 ps
CPU time 1184.69 seconds
Started May 07 02:11:48 PM PDT 24
Finished May 07 02:31:34 PM PDT 24
Peak memory 285764 kb
Host smart-2c2de239-63bb-4aae-9c15-d3893d07e076
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251241645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1251241645
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4258212619
Short name T197
Test name
Test status
Simulation time 663868949384 ps
CPU time 2075.03 seconds
Started May 07 02:11:49 PM PDT 24
Finished May 07 02:46:25 PM PDT 24
Peak memory 289184 kb
Host smart-029d3771-7bb1-4017-9ac6-a400169971dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258212619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4258212619
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1200820120
Short name T327
Test name
Test status
Simulation time 50448965151 ps
CPU time 480.85 seconds
Started May 07 02:11:44 PM PDT 24
Finished May 07 02:19:45 PM PDT 24
Peak memory 248188 kb
Host smart-aab43386-742f-4f71-9ec9-6ecb805312c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200820120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1200820120
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3832002971
Short name T609
Test name
Test status
Simulation time 552136619 ps
CPU time 19.64 seconds
Started May 07 02:11:44 PM PDT 24
Finished May 07 02:12:05 PM PDT 24
Peak memory 248796 kb
Host smart-bd58c702-99b7-4a2b-894e-4a9732f029a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38320
02971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3832002971
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2939165001
Short name T695
Test name
Test status
Simulation time 234880934 ps
CPU time 23.81 seconds
Started May 07 02:11:42 PM PDT 24
Finished May 07 02:12:07 PM PDT 24
Peak memory 247436 kb
Host smart-c5d53c20-c0ba-4765-adcf-19865e7b78d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
65001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2939165001
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2611800903
Short name T389
Test name
Test status
Simulation time 350753878 ps
CPU time 34.98 seconds
Started May 07 02:11:42 PM PDT 24
Finished May 07 02:12:17 PM PDT 24
Peak memory 248276 kb
Host smart-37d095b3-faf4-4ec6-ab99-4faed621ad91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
00903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2611800903
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.695747849
Short name T379
Test name
Test status
Simulation time 179863536 ps
CPU time 7.05 seconds
Started May 07 02:11:36 PM PDT 24
Finished May 07 02:11:44 PM PDT 24
Peak memory 248776 kb
Host smart-94d4ed16-d970-404d-ade2-fa0f792c4d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69574
7849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.695747849
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.458238469
Short name T587
Test name
Test status
Simulation time 11527788904 ps
CPU time 1097.51 seconds
Started May 07 02:11:53 PM PDT 24
Finished May 07 02:30:12 PM PDT 24
Peak memory 281668 kb
Host smart-b6aa6363-1b60-4e4d-a87c-cb5e7d8b652e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458238469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.458238469
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1612674353
Short name T415
Test name
Test status
Simulation time 1498859544 ps
CPU time 107.43 seconds
Started May 07 02:11:54 PM PDT 24
Finished May 07 02:13:42 PM PDT 24
Peak memory 256952 kb
Host smart-a31c0d27-c9ca-4787-bd94-8902ff5f27fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16126
74353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1612674353
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1655532969
Short name T616
Test name
Test status
Simulation time 3171598148 ps
CPU time 47.2 seconds
Started May 07 02:11:47 PM PDT 24
Finished May 07 02:12:35 PM PDT 24
Peak memory 256812 kb
Host smart-77f7c58d-1dd1-404e-89f8-06dd9cf09d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16555
32969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1655532969
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2928133132
Short name T201
Test name
Test status
Simulation time 41600758490 ps
CPU time 2500.11 seconds
Started May 07 02:11:53 PM PDT 24
Finished May 07 02:53:34 PM PDT 24
Peak memory 289460 kb
Host smart-beae3d06-8be0-4dde-96a2-4a4f8c4162bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928133132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2928133132
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1733420158
Short name T344
Test name
Test status
Simulation time 7636188473 ps
CPU time 161.61 seconds
Started May 07 02:11:54 PM PDT 24
Finished May 07 02:14:36 PM PDT 24
Peak memory 248356 kb
Host smart-3ab9bdb3-6dbc-4ff1-bda5-4f3dd8b7045e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733420158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1733420158
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1408494044
Short name T723
Test name
Test status
Simulation time 229548312 ps
CPU time 15.62 seconds
Started May 07 02:11:48 PM PDT 24
Finished May 07 02:12:04 PM PDT 24
Peak memory 254288 kb
Host smart-52f85949-c6ea-496b-8387-1fd4055aa3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084
94044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1408494044
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2208337643
Short name T586
Test name
Test status
Simulation time 637612340 ps
CPU time 27.17 seconds
Started May 07 02:11:47 PM PDT 24
Finished May 07 02:12:15 PM PDT 24
Peak memory 248784 kb
Host smart-b64829f7-fa3e-4aab-81a2-2a0fcfcb5df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22083
37643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2208337643
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.850510899
Short name T432
Test name
Test status
Simulation time 384974933 ps
CPU time 20.32 seconds
Started May 07 02:11:55 PM PDT 24
Finished May 07 02:12:16 PM PDT 24
Peak memory 254780 kb
Host smart-1eeea9f2-d9ef-43ec-bc77-f4e0004e4cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85051
0899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.850510899
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1677661124
Short name T597
Test name
Test status
Simulation time 544053594 ps
CPU time 22.06 seconds
Started May 07 02:11:49 PM PDT 24
Finished May 07 02:12:12 PM PDT 24
Peak memory 254588 kb
Host smart-ddf7cf9f-2c1a-45a2-a2d8-7c1e27725385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16776
61124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1677661124
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2240534450
Short name T204
Test name
Test status
Simulation time 11913684262 ps
CPU time 1210.09 seconds
Started May 07 02:11:52 PM PDT 24
Finished May 07 02:32:03 PM PDT 24
Peak memory 288792 kb
Host smart-89f7aeb3-f699-4b74-a1a5-4e2d25c8375f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240534450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2240534450
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3653565628
Short name T52
Test name
Test status
Simulation time 1059372365378 ps
CPU time 6198.51 seconds
Started May 07 02:11:55 PM PDT 24
Finished May 07 03:55:14 PM PDT 24
Peak memory 371116 kb
Host smart-8d5cd8bb-c3c1-451c-a1b5-4dbd40d899bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653565628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3653565628
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1347437347
Short name T78
Test name
Test status
Simulation time 240972517489 ps
CPU time 2967.85 seconds
Started May 07 02:12:11 PM PDT 24
Finished May 07 03:01:40 PM PDT 24
Peak memory 289260 kb
Host smart-8de799b6-726b-4b00-b35a-11000660e925
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347437347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1347437347
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2163242750
Short name T470
Test name
Test status
Simulation time 2652506517 ps
CPU time 51.62 seconds
Started May 07 02:12:00 PM PDT 24
Finished May 07 02:12:52 PM PDT 24
Peak memory 256892 kb
Host smart-f90c1fba-4a56-4594-ae29-c19b0fbcaf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
42750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2163242750
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1321803528
Short name T416
Test name
Test status
Simulation time 590444201 ps
CPU time 43.88 seconds
Started May 07 02:12:00 PM PDT 24
Finished May 07 02:12:44 PM PDT 24
Peak memory 248900 kb
Host smart-f99ad37c-eae1-41ca-a21c-72c6445fdc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13218
03528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1321803528
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2988907504
Short name T271
Test name
Test status
Simulation time 22928818118 ps
CPU time 1208.29 seconds
Started May 07 02:12:16 PM PDT 24
Finished May 07 02:32:25 PM PDT 24
Peak memory 272704 kb
Host smart-a8d9bc79-94bd-4aa2-a8df-bf0d9923939e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988907504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2988907504
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.649497239
Short name T521
Test name
Test status
Simulation time 156591861554 ps
CPU time 2186.99 seconds
Started May 07 02:12:20 PM PDT 24
Finished May 07 02:48:48 PM PDT 24
Peak memory 289588 kb
Host smart-124616c9-c2ba-458f-93ca-f4d9bcae0207
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649497239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.649497239
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2727678917
Short name T333
Test name
Test status
Simulation time 8736172293 ps
CPU time 97.65 seconds
Started May 07 02:12:16 PM PDT 24
Finished May 07 02:13:55 PM PDT 24
Peak memory 248208 kb
Host smart-96ff21fe-9f4d-4fe2-91b8-035a48b5b4da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727678917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2727678917
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.825406747
Short name T128
Test name
Test status
Simulation time 2815873804 ps
CPU time 35.81 seconds
Started May 07 02:11:53 PM PDT 24
Finished May 07 02:12:30 PM PDT 24
Peak memory 256348 kb
Host smart-f0740700-1019-4eb0-822e-f7abbf924cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82540
6747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.825406747
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1993228400
Short name T634
Test name
Test status
Simulation time 218235131 ps
CPU time 4.35 seconds
Started May 07 02:11:59 PM PDT 24
Finished May 07 02:12:04 PM PDT 24
Peak memory 239264 kb
Host smart-60b95367-b09d-4388-a698-37a91303648f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
28400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1993228400
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4149606531
Short name T473
Test name
Test status
Simulation time 176554425 ps
CPU time 18.83 seconds
Started May 07 02:12:06 PM PDT 24
Finished May 07 02:12:25 PM PDT 24
Peak memory 248748 kb
Host smart-74816895-a27a-4522-b47b-4173d90a0954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41496
06531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4149606531
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3693261697
Short name T584
Test name
Test status
Simulation time 599140659 ps
CPU time 12.03 seconds
Started May 07 02:11:53 PM PDT 24
Finished May 07 02:12:06 PM PDT 24
Peak memory 248760 kb
Host smart-500d0714-d784-42a2-b0a3-188565c76428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36932
61697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3693261697
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3895632089
Short name T58
Test name
Test status
Simulation time 3673790764 ps
CPU time 104.06 seconds
Started May 07 02:12:19 PM PDT 24
Finished May 07 02:14:03 PM PDT 24
Peak memory 256984 kb
Host smart-a58588cc-0439-4141-a408-76429660704e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895632089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3895632089
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2988869146
Short name T491
Test name
Test status
Simulation time 17018715109 ps
CPU time 1412.27 seconds
Started May 07 02:12:24 PM PDT 24
Finished May 07 02:35:57 PM PDT 24
Peak memory 289132 kb
Host smart-d3c77964-2b24-47c2-8836-d29d75ef79c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988869146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2988869146
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1028384842
Short name T602
Test name
Test status
Simulation time 4941115151 ps
CPU time 268.1 seconds
Started May 07 02:12:26 PM PDT 24
Finished May 07 02:16:55 PM PDT 24
Peak memory 257008 kb
Host smart-8381d9e3-387a-4fc4-89a6-fdf2c77f121c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10283
84842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1028384842
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1476190168
Short name T667
Test name
Test status
Simulation time 906054247 ps
CPU time 34.71 seconds
Started May 07 02:12:27 PM PDT 24
Finished May 07 02:13:02 PM PDT 24
Peak memory 248772 kb
Host smart-90b119ca-de67-482e-9019-96053b205500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761
90168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1476190168
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1186407683
Short name T46
Test name
Test status
Simulation time 86832682762 ps
CPU time 2440.02 seconds
Started May 07 02:12:30 PM PDT 24
Finished May 07 02:53:11 PM PDT 24
Peak memory 289416 kb
Host smart-20c5d769-d5eb-4f82-b818-71f54f5f4cc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186407683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1186407683
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.912792224
Short name T14
Test name
Test status
Simulation time 15212084352 ps
CPU time 1160.84 seconds
Started May 07 02:12:30 PM PDT 24
Finished May 07 02:31:52 PM PDT 24
Peak memory 289364 kb
Host smart-87b8e363-0a41-4d37-a6bd-bd06c33acc54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912792224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.912792224
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4184322028
Short name T34
Test name
Test status
Simulation time 17205708788 ps
CPU time 160.5 seconds
Started May 07 02:12:23 PM PDT 24
Finished May 07 02:15:05 PM PDT 24
Peak memory 247116 kb
Host smart-d87d063f-6976-418f-8852-7215d14bd33a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184322028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4184322028
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3878381598
Short name T435
Test name
Test status
Simulation time 1534912275 ps
CPU time 52.88 seconds
Started May 07 02:12:24 PM PDT 24
Finished May 07 02:13:17 PM PDT 24
Peak memory 256940 kb
Host smart-ce4ff6bb-a446-43d9-923d-2990a80061a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38783
81598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3878381598
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3899217421
Short name T533
Test name
Test status
Simulation time 3910934613 ps
CPU time 59.67 seconds
Started May 07 02:12:27 PM PDT 24
Finished May 07 02:13:27 PM PDT 24
Peak memory 249156 kb
Host smart-bd70a8d1-70a9-41d6-bfc1-e52a23f1c9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992
17421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3899217421
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2593282863
Short name T402
Test name
Test status
Simulation time 909718626 ps
CPU time 61.45 seconds
Started May 07 02:12:23 PM PDT 24
Finished May 07 02:13:25 PM PDT 24
Peak memory 248884 kb
Host smart-50df84ee-b488-4e79-ad77-33a09fddd15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25932
82863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2593282863
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1534004891
Short name T29
Test name
Test status
Simulation time 1201880471 ps
CPU time 63.88 seconds
Started May 07 02:12:25 PM PDT 24
Finished May 07 02:13:29 PM PDT 24
Peak memory 248756 kb
Host smart-452b5fa1-51d5-43ab-a553-c10458dffe89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15340
04891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1534004891
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.884171981
Short name T718
Test name
Test status
Simulation time 15484952131 ps
CPU time 255.61 seconds
Started May 07 02:12:31 PM PDT 24
Finished May 07 02:16:47 PM PDT 24
Peak memory 257032 kb
Host smart-d975e0ac-09b1-4bcb-b1a9-15b4825e6a00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884171981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.884171981
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2009281375
Short name T77
Test name
Test status
Simulation time 123602795082 ps
CPU time 1567.29 seconds
Started May 07 02:12:41 PM PDT 24
Finished May 07 02:38:50 PM PDT 24
Peak memory 273388 kb
Host smart-723c1213-ea35-4425-af24-3cc0a629c010
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009281375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2009281375
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2564764831
Short name T542
Test name
Test status
Simulation time 1357772340 ps
CPU time 87.5 seconds
Started May 07 02:12:35 PM PDT 24
Finished May 07 02:14:03 PM PDT 24
Peak memory 248768 kb
Host smart-d1c04d24-32a7-475c-87d1-7eac55b37eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25647
64831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2564764831
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3381590698
Short name T493
Test name
Test status
Simulation time 1266144333 ps
CPU time 30.75 seconds
Started May 07 02:12:36 PM PDT 24
Finished May 07 02:13:07 PM PDT 24
Peak memory 255996 kb
Host smart-48ea496c-e43d-43c7-8568-fbbbc20996be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33815
90698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3381590698
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1120314362
Short name T390
Test name
Test status
Simulation time 26186860875 ps
CPU time 1620.38 seconds
Started May 07 02:12:42 PM PDT 24
Finished May 07 02:39:44 PM PDT 24
Peak memory 289060 kb
Host smart-02e7a5f3-ee7f-4286-a25b-aa763fbffa16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120314362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1120314362
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2809714598
Short name T598
Test name
Test status
Simulation time 1439759906 ps
CPU time 33.36 seconds
Started May 07 02:12:35 PM PDT 24
Finished May 07 02:13:09 PM PDT 24
Peak memory 248776 kb
Host smart-aa8703db-318b-460c-a05c-8a3dd065a9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
14598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2809714598
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2743319033
Short name T315
Test name
Test status
Simulation time 892490751 ps
CPU time 53.3 seconds
Started May 07 02:12:36 PM PDT 24
Finished May 07 02:13:30 PM PDT 24
Peak memory 256048 kb
Host smart-455ab56e-38e8-4d03-b5c2-12151f0b5290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
19033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2743319033
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3581618554
Short name T484
Test name
Test status
Simulation time 347164332 ps
CPU time 12.69 seconds
Started May 07 02:12:42 PM PDT 24
Finished May 07 02:12:56 PM PDT 24
Peak memory 249032 kb
Host smart-1b8d2ea7-ca47-481a-8d2b-0c577d7e0623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35816
18554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3581618554
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3006453527
Short name T685
Test name
Test status
Simulation time 1109797050 ps
CPU time 27.74 seconds
Started May 07 02:12:37 PM PDT 24
Finished May 07 02:13:05 PM PDT 24
Peak memory 248784 kb
Host smart-3875f2ed-b66d-4129-b3fc-4ad28069e9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30064
53527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3006453527
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2477406415
Short name T279
Test name
Test status
Simulation time 45296201128 ps
CPU time 2830.32 seconds
Started May 07 02:12:42 PM PDT 24
Finished May 07 02:59:54 PM PDT 24
Peak memory 289752 kb
Host smart-60e84636-392f-4af8-99df-5e1a6e28e577
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477406415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2477406415
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1794682812
Short name T24
Test name
Test status
Simulation time 254439190114 ps
CPU time 4082.78 seconds
Started May 07 02:12:42 PM PDT 24
Finished May 07 03:20:46 PM PDT 24
Peak memory 302516 kb
Host smart-749d60e0-5104-4ca2-a533-517f55850f9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794682812 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1794682812
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4165431080
Short name T229
Test name
Test status
Simulation time 82834021 ps
CPU time 3.79 seconds
Started May 07 02:08:30 PM PDT 24
Finished May 07 02:08:35 PM PDT 24
Peak memory 248912 kb
Host smart-f7f41d7f-2a1f-4c89-9ac8-62bd6d063461
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4165431080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4165431080
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2764440880
Short name T487
Test name
Test status
Simulation time 39258659344 ps
CPU time 2148.39 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:44:22 PM PDT 24
Peak memory 273404 kb
Host smart-b428f966-9d29-4c0e-b2e8-290efd52112b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764440880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2764440880
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4022460320
Short name T454
Test name
Test status
Simulation time 369193821 ps
CPU time 19.36 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:52 PM PDT 24
Peak memory 240580 kb
Host smart-f2180fc0-9cc4-445c-b4ae-9926c03c42aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4022460320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4022460320
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.885109644
Short name T505
Test name
Test status
Simulation time 2177520685 ps
CPU time 106.59 seconds
Started May 07 02:08:33 PM PDT 24
Finished May 07 02:10:21 PM PDT 24
Peak memory 256984 kb
Host smart-a44ecfe9-df37-4193-8c9f-140abb4be29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88510
9644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.885109644
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3125816804
Short name T711
Test name
Test status
Simulation time 1370154208 ps
CPU time 63.22 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:09:35 PM PDT 24
Peak memory 248788 kb
Host smart-ebe4c0c8-ae4d-40a7-9748-5da633d7a9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31258
16804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3125816804
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1260830515
Short name T215
Test name
Test status
Simulation time 36541800329 ps
CPU time 881.29 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:23:15 PM PDT 24
Peak memory 273388 kb
Host smart-c8b313bd-c6a7-47d7-b988-e12e6b0d7cf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260830515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1260830515
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3070349984
Short name T617
Test name
Test status
Simulation time 15089355426 ps
CPU time 147.48 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:11:00 PM PDT 24
Peak memory 248292 kb
Host smart-c7d4861b-ac11-4eb5-8da8-af369d8ad824
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070349984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3070349984
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4113738324
Short name T255
Test name
Test status
Simulation time 308642905 ps
CPU time 29.6 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:09:05 PM PDT 24
Peak memory 248768 kb
Host smart-3277eb7b-ed60-42f9-b248-a010ddba9f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
38324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4113738324
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1889286651
Short name T639
Test name
Test status
Simulation time 882597960 ps
CPU time 50.35 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:09:23 PM PDT 24
Peak memory 255796 kb
Host smart-9dd1c72e-0671-4e24-92ea-ba3bb2e7cfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18892
86651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1889286651
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.619248469
Short name T32
Test name
Test status
Simulation time 342287076 ps
CPU time 11.28 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:08:45 PM PDT 24
Peak memory 270268 kb
Host smart-45244e5e-8ab1-4391-8480-6d892068deaa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=619248469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.619248469
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.32583802
Short name T297
Test name
Test status
Simulation time 92077965 ps
CPU time 10.66 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:43 PM PDT 24
Peak memory 249124 kb
Host smart-56d4a550-c3fa-4148-986b-4b544b5f70c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32583
802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.32583802
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1200512730
Short name T17
Test name
Test status
Simulation time 5115530294 ps
CPU time 27.76 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:09:00 PM PDT 24
Peak memory 248836 kb
Host smart-e92ada0f-e35f-4655-8c39-7753b68c05a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12005
12730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1200512730
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2371097603
Short name T446
Test name
Test status
Simulation time 83213096 ps
CPU time 5.99 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:39 PM PDT 24
Peak memory 248756 kb
Host smart-d5c46833-8d3a-4d80-839d-eaf5177d9a4b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371097603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2371097603
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3145901171
Short name T221
Test name
Test status
Simulation time 507982234013 ps
CPU time 6662.76 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 03:59:36 PM PDT 24
Peak memory 333948 kb
Host smart-a00afb08-8a82-4761-9bc0-f02f18b1c678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145901171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3145901171
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3916358480
Short name T442
Test name
Test status
Simulation time 19932834283 ps
CPU time 582.45 seconds
Started May 07 02:12:46 PM PDT 24
Finished May 07 02:22:30 PM PDT 24
Peak memory 265200 kb
Host smart-502fb256-2c41-4706-a306-66f23c00358d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916358480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3916358480
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2046544544
Short name T15
Test name
Test status
Simulation time 4171540409 ps
CPU time 260.5 seconds
Started May 07 02:12:47 PM PDT 24
Finished May 07 02:17:09 PM PDT 24
Peak memory 257044 kb
Host smart-f98560df-e1d1-4b7c-8468-5d3b976badec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20465
44544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2046544544
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2086813938
Short name T664
Test name
Test status
Simulation time 1031358442 ps
CPU time 27.45 seconds
Started May 07 02:12:47 PM PDT 24
Finished May 07 02:13:15 PM PDT 24
Peak memory 255688 kb
Host smart-6590487b-2fa9-4b61-9d0a-fafdc47f012f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20868
13938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2086813938
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1072296765
Short name T359
Test name
Test status
Simulation time 13518911002 ps
CPU time 1076.86 seconds
Started May 07 02:12:47 PM PDT 24
Finished May 07 02:30:45 PM PDT 24
Peak memory 289008 kb
Host smart-3fa28a17-0d82-4c8a-8f11-122279886cef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072296765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1072296765
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3835433649
Short name T459
Test name
Test status
Simulation time 109165747448 ps
CPU time 2062.62 seconds
Started May 07 02:12:52 PM PDT 24
Finished May 07 02:47:16 PM PDT 24
Peak memory 289516 kb
Host smart-47b7f460-16dc-41e9-b74d-0f61c56e07ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835433649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3835433649
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1118233735
Short name T331
Test name
Test status
Simulation time 41442307031 ps
CPU time 570.78 seconds
Started May 07 02:12:48 PM PDT 24
Finished May 07 02:22:20 PM PDT 24
Peak memory 255216 kb
Host smart-7485998a-6674-43fc-a2c3-19c1186c2fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118233735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1118233735
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1278430298
Short name T645
Test name
Test status
Simulation time 650255391 ps
CPU time 40.54 seconds
Started May 07 02:12:41 PM PDT 24
Finished May 07 02:13:23 PM PDT 24
Peak memory 248676 kb
Host smart-84e23c6f-9a06-4c46-88c6-dd43c7280929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12784
30298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1278430298
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2373139296
Short name T535
Test name
Test status
Simulation time 1006631428 ps
CPU time 27.06 seconds
Started May 07 02:12:47 PM PDT 24
Finished May 07 02:13:15 PM PDT 24
Peak memory 255420 kb
Host smart-97650c27-0c5b-4b30-9db2-6892990fc69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23731
39296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2373139296
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3352650119
Short name T615
Test name
Test status
Simulation time 2922889181 ps
CPU time 52.06 seconds
Started May 07 02:12:46 PM PDT 24
Finished May 07 02:13:39 PM PDT 24
Peak memory 249848 kb
Host smart-b032da3f-a003-4c61-8bb0-9d2b97d07325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33526
50119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3352650119
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.992077166
Short name T623
Test name
Test status
Simulation time 1251336586 ps
CPU time 17.72 seconds
Started May 07 02:12:41 PM PDT 24
Finished May 07 02:13:00 PM PDT 24
Peak memory 248760 kb
Host smart-9e98ca0d-e57f-498f-9f6d-849d146f7675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99207
7166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.992077166
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4018520695
Short name T284
Test name
Test status
Simulation time 17279425477 ps
CPU time 1468.47 seconds
Started May 07 02:12:52 PM PDT 24
Finished May 07 02:37:22 PM PDT 24
Peak memory 289284 kb
Host smart-0318a815-ff62-41fd-b342-35dc6a0202fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018520695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4018520695
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4058817593
Short name T262
Test name
Test status
Simulation time 151487969340 ps
CPU time 2247.33 seconds
Started May 07 02:12:53 PM PDT 24
Finished May 07 02:50:21 PM PDT 24
Peak memory 289968 kb
Host smart-948d708e-be5f-4051-b1e2-9784947a3506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058817593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4058817593
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2554224222
Short name T652
Test name
Test status
Simulation time 264496400826 ps
CPU time 2194.24 seconds
Started May 07 02:12:58 PM PDT 24
Finished May 07 02:49:33 PM PDT 24
Peak memory 273412 kb
Host smart-6062ef19-a8cf-4051-bfe9-85e8529ef51c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554224222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2554224222
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2893696284
Short name T728
Test name
Test status
Simulation time 981125424 ps
CPU time 62.21 seconds
Started May 07 02:12:52 PM PDT 24
Finished May 07 02:13:55 PM PDT 24
Peak memory 249160 kb
Host smart-41925972-11c5-4c78-b8cb-356529d222e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28936
96284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2893696284
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2203152420
Short name T443
Test name
Test status
Simulation time 1261671356 ps
CPU time 37.55 seconds
Started May 07 02:12:52 PM PDT 24
Finished May 07 02:13:31 PM PDT 24
Peak memory 256856 kb
Host smart-f5c7c0a2-43b3-4d61-953c-9da898933977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22031
52420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2203152420
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2481749783
Short name T45
Test name
Test status
Simulation time 41421422732 ps
CPU time 1444.49 seconds
Started May 07 02:12:59 PM PDT 24
Finished May 07 02:37:04 PM PDT 24
Peak memory 289368 kb
Host smart-3a6f10c4-25b5-4f81-99f9-049bc0c97501
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481749783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2481749783
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3073644247
Short name T268
Test name
Test status
Simulation time 32705079045 ps
CPU time 1759.32 seconds
Started May 07 02:12:58 PM PDT 24
Finished May 07 02:42:18 PM PDT 24
Peak memory 285192 kb
Host smart-f0e1b55c-a62b-425c-bdd3-935f7ff6b8b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073644247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3073644247
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3927780045
Short name T4
Test name
Test status
Simulation time 4602311185 ps
CPU time 185.21 seconds
Started May 07 02:12:58 PM PDT 24
Finished May 07 02:16:03 PM PDT 24
Peak memory 255096 kb
Host smart-9716cf92-0cc9-4907-8788-256f8b5f8714
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927780045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3927780045
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.185540764
Short name T55
Test name
Test status
Simulation time 562458222 ps
CPU time 36.25 seconds
Started May 07 02:12:52 PM PDT 24
Finished May 07 02:13:28 PM PDT 24
Peak memory 248772 kb
Host smart-9ed984db-0cf0-41e9-bcf3-73d46a7a88a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
0764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.185540764
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2060523111
Short name T613
Test name
Test status
Simulation time 1503443061 ps
CPU time 46.61 seconds
Started May 07 02:12:54 PM PDT 24
Finished May 07 02:13:41 PM PDT 24
Peak memory 248828 kb
Host smart-b0f041c0-d557-4b92-827c-c504be9ffe08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
23111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2060523111
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3487345863
Short name T287
Test name
Test status
Simulation time 681262437 ps
CPU time 14.21 seconds
Started May 07 02:12:50 PM PDT 24
Finished May 07 02:13:05 PM PDT 24
Peak memory 253932 kb
Host smart-a2bd9d77-83de-4222-94e0-27908a2ecf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34873
45863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3487345863
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3704912240
Short name T564
Test name
Test status
Simulation time 674005213 ps
CPU time 19.84 seconds
Started May 07 02:12:53 PM PDT 24
Finished May 07 02:13:13 PM PDT 24
Peak memory 248784 kb
Host smart-49f844f1-6996-4ddd-a349-55194986fedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37049
12240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3704912240
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.240452870
Short name T90
Test name
Test status
Simulation time 34834162429 ps
CPU time 2149.85 seconds
Started May 07 02:13:04 PM PDT 24
Finished May 07 02:48:55 PM PDT 24
Peak memory 289148 kb
Host smart-aef61eaf-1fc9-4fae-bd96-5834893d8f86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240452870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.240452870
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3117453374
Short name T244
Test name
Test status
Simulation time 242400420450 ps
CPU time 3069.15 seconds
Started May 07 02:13:22 PM PDT 24
Finished May 07 03:04:32 PM PDT 24
Peak memory 289236 kb
Host smart-322bf8a3-59e1-4d71-961f-fc3a24dd8a88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117453374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3117453374
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.904203788
Short name T202
Test name
Test status
Simulation time 39301730407 ps
CPU time 311.55 seconds
Started May 07 02:13:16 PM PDT 24
Finished May 07 02:18:28 PM PDT 24
Peak memory 257008 kb
Host smart-56764444-cd63-403a-a28b-c40e5e2e92be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90420
3788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.904203788
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4068811312
Short name T570
Test name
Test status
Simulation time 118921573 ps
CPU time 5.65 seconds
Started May 07 02:13:12 PM PDT 24
Finished May 07 02:13:18 PM PDT 24
Peak memory 248780 kb
Host smart-8ff70696-79cf-46cf-81a6-cd36143f8814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40688
11312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4068811312
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2720719492
Short name T94
Test name
Test status
Simulation time 34318947327 ps
CPU time 1702.61 seconds
Started May 07 02:13:24 PM PDT 24
Finished May 07 02:41:47 PM PDT 24
Peak memory 270672 kb
Host smart-2d6739a7-45c2-472b-8fb1-098701bffe2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720719492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2720719492
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2930993084
Short name T668
Test name
Test status
Simulation time 53308646050 ps
CPU time 1173.27 seconds
Started May 07 02:13:22 PM PDT 24
Finished May 07 02:32:56 PM PDT 24
Peak memory 285676 kb
Host smart-c999b914-4764-4d2a-b716-ea93c503428a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930993084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2930993084
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2112852116
Short name T321
Test name
Test status
Simulation time 22619413491 ps
CPU time 441.7 seconds
Started May 07 02:13:23 PM PDT 24
Finished May 07 02:20:46 PM PDT 24
Peak memory 248064 kb
Host smart-066a1cf7-582a-4d4a-9805-7aa487d512af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112852116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2112852116
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.981977939
Short name T530
Test name
Test status
Simulation time 709940337 ps
CPU time 35.61 seconds
Started May 07 02:13:11 PM PDT 24
Finished May 07 02:13:47 PM PDT 24
Peak memory 256976 kb
Host smart-330b0871-6574-44f8-9457-e01b84afc9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98197
7939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.981977939
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3833864027
Short name T655
Test name
Test status
Simulation time 1015536609 ps
CPU time 32.54 seconds
Started May 07 02:13:11 PM PDT 24
Finished May 07 02:13:45 PM PDT 24
Peak memory 247640 kb
Host smart-908ea281-6c40-4e76-89bc-783f2311c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38338
64027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3833864027
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3235259735
Short name T44
Test name
Test status
Simulation time 2056235194 ps
CPU time 35.28 seconds
Started May 07 02:13:17 PM PDT 24
Finished May 07 02:13:53 PM PDT 24
Peak memory 256020 kb
Host smart-2eb7e29c-3064-4130-8e3a-3a87c92995d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32352
59735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3235259735
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.617650900
Short name T550
Test name
Test status
Simulation time 2196423472 ps
CPU time 28.7 seconds
Started May 07 02:13:10 PM PDT 24
Finished May 07 02:13:40 PM PDT 24
Peak memory 248816 kb
Host smart-dfdd7635-bb3b-4c46-801c-bdac74675726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61765
0900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.617650900
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.955957605
Short name T658
Test name
Test status
Simulation time 21269757978 ps
CPU time 1223.53 seconds
Started May 07 02:13:42 PM PDT 24
Finished May 07 02:34:06 PM PDT 24
Peak memory 281616 kb
Host smart-faa91f42-305c-4af9-97ef-e69e0d7d1429
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955957605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.955957605
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3704895484
Short name T425
Test name
Test status
Simulation time 2357923786 ps
CPU time 45.29 seconds
Started May 07 02:13:36 PM PDT 24
Finished May 07 02:14:22 PM PDT 24
Peak memory 249864 kb
Host smart-7dd813c2-eeb7-4f59-af42-b4ac8bfbc34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37048
95484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3704895484
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3814890921
Short name T430
Test name
Test status
Simulation time 2555876734 ps
CPU time 38.79 seconds
Started May 07 02:13:35 PM PDT 24
Finished May 07 02:14:15 PM PDT 24
Peak memory 255984 kb
Host smart-8b2cc7f6-2180-49c0-8d26-e3323a577f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148
90921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3814890921
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3630236576
Short name T247
Test name
Test status
Simulation time 26071530312 ps
CPU time 1403.12 seconds
Started May 07 02:13:41 PM PDT 24
Finished May 07 02:37:05 PM PDT 24
Peak memory 269304 kb
Host smart-fab57274-2be1-4422-9713-a275003e333d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630236576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3630236576
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.744106195
Short name T700
Test name
Test status
Simulation time 26715099316 ps
CPU time 626.84 seconds
Started May 07 02:13:41 PM PDT 24
Finished May 07 02:24:09 PM PDT 24
Peak memory 273360 kb
Host smart-1df79f78-bb1d-496c-9b12-0066e016d198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744106195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.744106195
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2847682403
Short name T696
Test name
Test status
Simulation time 4397722842 ps
CPU time 88.66 seconds
Started May 07 02:13:39 PM PDT 24
Finished May 07 02:15:08 PM PDT 24
Peak memory 252816 kb
Host smart-79e95b8d-1ca8-43e4-a165-d1201995b060
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847682403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2847682403
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3097217650
Short name T494
Test name
Test status
Simulation time 148316303 ps
CPU time 18.35 seconds
Started May 07 02:13:29 PM PDT 24
Finished May 07 02:13:48 PM PDT 24
Peak memory 248864 kb
Host smart-39718392-b2b9-49e6-8f77-a8edbcea954e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30972
17650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3097217650
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3696625329
Short name T450
Test name
Test status
Simulation time 574334749 ps
CPU time 9.37 seconds
Started May 07 02:13:29 PM PDT 24
Finished May 07 02:13:39 PM PDT 24
Peak memory 251040 kb
Host smart-85ec0505-95b8-4f44-8cfd-1625cf6da66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36966
25329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3696625329
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4075066361
Short name T298
Test name
Test status
Simulation time 3146737170 ps
CPU time 44.28 seconds
Started May 07 02:13:35 PM PDT 24
Finished May 07 02:14:20 PM PDT 24
Peak memory 248840 kb
Host smart-93de6f36-6ce5-4af6-a3cc-2b1e9d3c4399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40750
66361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4075066361
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.591987445
Short name T671
Test name
Test status
Simulation time 525014463 ps
CPU time 23.36 seconds
Started May 07 02:13:30 PM PDT 24
Finished May 07 02:13:53 PM PDT 24
Peak memory 248964 kb
Host smart-8fb2b105-7478-4c05-9b0a-f34888dd6661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59198
7445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.591987445
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1302425928
Short name T592
Test name
Test status
Simulation time 46545189231 ps
CPU time 2391.3 seconds
Started May 07 02:13:40 PM PDT 24
Finished May 07 02:53:32 PM PDT 24
Peak memory 305628 kb
Host smart-db5a6039-a39b-4425-b5e4-82a0d8182669
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302425928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1302425928
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.327637059
Short name T555
Test name
Test status
Simulation time 69042188158 ps
CPU time 1276.23 seconds
Started May 07 02:13:42 PM PDT 24
Finished May 07 02:34:59 PM PDT 24
Peak memory 281732 kb
Host smart-5d2930a3-3a1f-4a35-bb4d-cc547168d826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327637059 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.327637059
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1551270969
Short name T640
Test name
Test status
Simulation time 88937203743 ps
CPU time 1607.16 seconds
Started May 07 02:13:45 PM PDT 24
Finished May 07 02:40:33 PM PDT 24
Peak memory 282636 kb
Host smart-5d772653-834b-425e-a7d9-c3ee39f843df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551270969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1551270969
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3965887494
Short name T457
Test name
Test status
Simulation time 2863612124 ps
CPU time 156.16 seconds
Started May 07 02:13:47 PM PDT 24
Finished May 07 02:16:24 PM PDT 24
Peak memory 257012 kb
Host smart-9ebc0b94-84e8-433a-8e0f-ac00d32b4a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
87494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3965887494
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1039891018
Short name T577
Test name
Test status
Simulation time 482775547 ps
CPU time 18.27 seconds
Started May 07 02:13:46 PM PDT 24
Finished May 07 02:14:05 PM PDT 24
Peak memory 255756 kb
Host smart-e472c618-7fa5-43d0-b448-fc331a2826e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
91018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1039891018
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4097863069
Short name T357
Test name
Test status
Simulation time 39306126075 ps
CPU time 750.89 seconds
Started May 07 02:13:53 PM PDT 24
Finished May 07 02:26:25 PM PDT 24
Peak memory 266240 kb
Host smart-cf57d547-24b9-45e3-b633-d598074abe66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097863069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4097863069
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2820376130
Short name T433
Test name
Test status
Simulation time 43944660337 ps
CPU time 2546.29 seconds
Started May 07 02:13:53 PM PDT 24
Finished May 07 02:56:20 PM PDT 24
Peak memory 286064 kb
Host smart-83f9d1d0-5dc1-4b88-bce9-84170e39a828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820376130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2820376130
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1013936802
Short name T400
Test name
Test status
Simulation time 358024204 ps
CPU time 14.84 seconds
Started May 07 02:13:41 PM PDT 24
Finished May 07 02:13:57 PM PDT 24
Peak memory 248700 kb
Host smart-f6a4075f-af55-4e8c-a0f6-3a7caac92b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
36802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1013936802
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1619340698
Short name T267
Test name
Test status
Simulation time 490475427 ps
CPU time 16.92 seconds
Started May 07 02:13:40 PM PDT 24
Finished May 07 02:13:58 PM PDT 24
Peak memory 247436 kb
Host smart-9833f474-77a4-428d-8a89-9f749623af81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16193
40698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1619340698
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1855339703
Short name T18
Test name
Test status
Simulation time 238718780 ps
CPU time 26.26 seconds
Started May 07 02:13:48 PM PDT 24
Finished May 07 02:14:15 PM PDT 24
Peak memory 255948 kb
Host smart-548b81aa-7c9d-42ab-b27d-84380d982fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18553
39703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1855339703
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4148038728
Short name T69
Test name
Test status
Simulation time 1601034961 ps
CPU time 45.07 seconds
Started May 07 02:13:40 PM PDT 24
Finished May 07 02:14:26 PM PDT 24
Peak memory 248760 kb
Host smart-29551bf5-b107-4e31-aae3-79406da61c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
38728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4148038728
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3483020453
Short name T285
Test name
Test status
Simulation time 85083722273 ps
CPU time 2183.34 seconds
Started May 07 02:13:53 PM PDT 24
Finished May 07 02:50:17 PM PDT 24
Peak memory 306308 kb
Host smart-1d04e0d6-229c-4403-b12b-a0bc552d8481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483020453 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3483020453
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3872686565
Short name T576
Test name
Test status
Simulation time 51645498031 ps
CPU time 1179.77 seconds
Started May 07 02:13:59 PM PDT 24
Finished May 07 02:33:40 PM PDT 24
Peak memory 285204 kb
Host smart-7c57ca18-b615-41ec-a1fe-6da9082e89c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872686565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3872686565
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2745980952
Short name T449
Test name
Test status
Simulation time 38466358786 ps
CPU time 173.38 seconds
Started May 07 02:13:58 PM PDT 24
Finished May 07 02:16:52 PM PDT 24
Peak memory 256708 kb
Host smart-fa483e87-90b0-4399-a84e-d0e78fbd61eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459
80952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2745980952
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3010799629
Short name T665
Test name
Test status
Simulation time 1234190887 ps
CPU time 21.38 seconds
Started May 07 02:13:59 PM PDT 24
Finished May 07 02:14:21 PM PDT 24
Peak memory 254932 kb
Host smart-68f83790-c53b-4a2b-a080-ddcf7222337c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30107
99629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3010799629
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1846777902
Short name T498
Test name
Test status
Simulation time 140677340396 ps
CPU time 1904.04 seconds
Started May 07 02:13:59 PM PDT 24
Finished May 07 02:45:44 PM PDT 24
Peak memory 273200 kb
Host smart-bec26de0-d6f6-43d2-ba13-84f678bee95e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846777902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1846777902
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3835090665
Short name T479
Test name
Test status
Simulation time 50208856991 ps
CPU time 1274.65 seconds
Started May 07 02:14:06 PM PDT 24
Finished May 07 02:35:21 PM PDT 24
Peak memory 289288 kb
Host smart-ee6ac8da-4da5-4177-82a4-db81c6e39dc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835090665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3835090665
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.4268285690
Short name T324
Test name
Test status
Simulation time 5310813942 ps
CPU time 223.93 seconds
Started May 07 02:13:59 PM PDT 24
Finished May 07 02:17:43 PM PDT 24
Peak memory 248032 kb
Host smart-f8502fbc-d012-4bd0-8884-2c714f3c7504
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268285690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4268285690
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2107857555
Short name T720
Test name
Test status
Simulation time 5293269332 ps
CPU time 53.36 seconds
Started May 07 02:13:54 PM PDT 24
Finished May 07 02:14:48 PM PDT 24
Peak memory 248812 kb
Host smart-db27c5f3-f29c-4a29-b42f-cef70fc3f599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21078
57555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2107857555
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1562150677
Short name T110
Test name
Test status
Simulation time 6299837061 ps
CPU time 35.31 seconds
Started May 07 02:13:59 PM PDT 24
Finished May 07 02:14:35 PM PDT 24
Peak memory 255176 kb
Host smart-3b8be5fd-da31-4001-991c-e3fd0966fa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15621
50677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1562150677
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3733477566
Short name T113
Test name
Test status
Simulation time 290707011 ps
CPU time 17.05 seconds
Started May 07 02:13:58 PM PDT 24
Finished May 07 02:14:15 PM PDT 24
Peak memory 248948 kb
Host smart-b467ea11-dd99-47af-8f34-5be549afebaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
77566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3733477566
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2235723322
Short name T529
Test name
Test status
Simulation time 1275293043 ps
CPU time 34.94 seconds
Started May 07 02:13:54 PM PDT 24
Finished May 07 02:14:30 PM PDT 24
Peak memory 248776 kb
Host smart-b8cf3127-33f9-4c2d-aa74-bea200317ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22357
23322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2235723322
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2957972936
Short name T558
Test name
Test status
Simulation time 12878395263 ps
CPU time 1087.88 seconds
Started May 07 02:14:06 PM PDT 24
Finished May 07 02:32:15 PM PDT 24
Peak memory 282264 kb
Host smart-131feb97-5674-4213-bd02-2afc033dc401
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957972936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2957972936
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2322491463
Short name T636
Test name
Test status
Simulation time 28715804637 ps
CPU time 1552.49 seconds
Started May 07 02:14:10 PM PDT 24
Finished May 07 02:40:03 PM PDT 24
Peak memory 273232 kb
Host smart-7c90764d-6dbc-463a-881a-e1d323b74b27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322491463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2322491463
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.592415054
Short name T502
Test name
Test status
Simulation time 973969661 ps
CPU time 58.58 seconds
Started May 07 02:14:06 PM PDT 24
Finished May 07 02:15:06 PM PDT 24
Peak memory 256788 kb
Host smart-bbccfb2b-11ce-44db-8b29-502c283f55d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59241
5054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.592415054
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.328566129
Short name T471
Test name
Test status
Simulation time 202179118 ps
CPU time 18.78 seconds
Started May 07 02:14:05 PM PDT 24
Finished May 07 02:14:25 PM PDT 24
Peak memory 249244 kb
Host smart-e792e528-8f50-4d20-a7f4-9df7f6bc93ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856
6129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.328566129
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4019202555
Short name T347
Test name
Test status
Simulation time 69190030340 ps
CPU time 1339.81 seconds
Started May 07 02:14:16 PM PDT 24
Finished May 07 02:36:36 PM PDT 24
Peak memory 286808 kb
Host smart-e98c95d4-9651-42c5-8944-ef6f3294953a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019202555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4019202555
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4142643957
Short name T624
Test name
Test status
Simulation time 205366594968 ps
CPU time 2815.5 seconds
Started May 07 02:14:16 PM PDT 24
Finished May 07 03:01:12 PM PDT 24
Peak memory 289396 kb
Host smart-a14eb915-02ca-4643-a2c2-0136b9fe1950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142643957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4142643957
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.735540414
Short name T690
Test name
Test status
Simulation time 1479424112 ps
CPU time 12.84 seconds
Started May 07 02:14:06 PM PDT 24
Finished May 07 02:14:20 PM PDT 24
Peak memory 248780 kb
Host smart-a3b8a33e-2f91-4b36-9fc7-272617017fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73554
0414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.735540414
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.301274965
Short name T122
Test name
Test status
Simulation time 2072210408 ps
CPU time 32.77 seconds
Started May 07 02:14:05 PM PDT 24
Finished May 07 02:14:38 PM PDT 24
Peak memory 249216 kb
Host smart-64df4fb7-c3c2-4275-9fc7-556cca5f40d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
4965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.301274965
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2927263031
Short name T520
Test name
Test status
Simulation time 1703029686 ps
CPU time 18.1 seconds
Started May 07 02:14:05 PM PDT 24
Finished May 07 02:14:24 PM PDT 24
Peak memory 256304 kb
Host smart-fa8d84af-6c5a-47f6-ade8-3e682e19daeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272
63031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2927263031
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1691842442
Short name T501
Test name
Test status
Simulation time 56272694 ps
CPU time 6.82 seconds
Started May 07 02:14:07 PM PDT 24
Finished May 07 02:14:14 PM PDT 24
Peak memory 248772 kb
Host smart-a06b8d99-7d97-4472-9014-2563382ae6ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
42442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1691842442
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1964218591
Short name T317
Test name
Test status
Simulation time 118964627475 ps
CPU time 4808.35 seconds
Started May 07 02:14:18 PM PDT 24
Finished May 07 03:34:27 PM PDT 24
Peak memory 322268 kb
Host smart-bba4aa9e-b890-4847-8ef0-c9b91e75fe56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964218591 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1964218591
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.354033424
Short name T456
Test name
Test status
Simulation time 13313222123 ps
CPU time 1096.45 seconds
Started May 07 02:14:29 PM PDT 24
Finished May 07 02:32:46 PM PDT 24
Peak memory 272448 kb
Host smart-38a9b002-e0aa-4969-b961-7a47eff3a2e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354033424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.354033424
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.398028562
Short name T562
Test name
Test status
Simulation time 12861540506 ps
CPU time 248.81 seconds
Started May 07 02:14:22 PM PDT 24
Finished May 07 02:18:32 PM PDT 24
Peak memory 251692 kb
Host smart-0dd821f6-bc99-47ea-b7f4-b6300c7309ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802
8562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.398028562
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1179633173
Short name T619
Test name
Test status
Simulation time 1443145241 ps
CPU time 23.52 seconds
Started May 07 02:14:23 PM PDT 24
Finished May 07 02:14:47 PM PDT 24
Peak memory 248832 kb
Host smart-90dec76e-5656-4570-8b83-7a47651e0934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11796
33173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1179633173
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2832714997
Short name T328
Test name
Test status
Simulation time 33641943408 ps
CPU time 2140.62 seconds
Started May 07 02:14:28 PM PDT 24
Finished May 07 02:50:10 PM PDT 24
Peak memory 285804 kb
Host smart-88e015fc-9c15-441e-9ce5-90f0056f8f29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832714997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2832714997
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4287595149
Short name T650
Test name
Test status
Simulation time 136514759057 ps
CPU time 2639.57 seconds
Started May 07 02:14:29 PM PDT 24
Finished May 07 02:58:29 PM PDT 24
Peak memory 289088 kb
Host smart-e53aaeeb-6618-4e7b-9994-6fe3d45e45b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287595149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4287595149
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3863815743
Short name T499
Test name
Test status
Simulation time 12586209157 ps
CPU time 264.63 seconds
Started May 07 02:14:30 PM PDT 24
Finished May 07 02:18:55 PM PDT 24
Peak memory 247884 kb
Host smart-0969397c-5ad5-42e8-b370-fa5d57e7ef78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863815743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3863815743
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4058663346
Short name T445
Test name
Test status
Simulation time 1324115652 ps
CPU time 30.57 seconds
Started May 07 02:14:17 PM PDT 24
Finished May 07 02:14:49 PM PDT 24
Peak memory 248764 kb
Host smart-f27e4a0a-d3e5-40e5-ab49-444d9f328a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40586
63346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4058663346
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3480009403
Short name T589
Test name
Test status
Simulation time 713021008 ps
CPU time 16.8 seconds
Started May 07 02:14:22 PM PDT 24
Finished May 07 02:14:39 PM PDT 24
Peak memory 255300 kb
Host smart-ca1b36f6-ba44-4314-927f-60aef4143ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34800
09403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3480009403
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1081138100
Short name T691
Test name
Test status
Simulation time 33367607 ps
CPU time 3.45 seconds
Started May 07 02:14:24 PM PDT 24
Finished May 07 02:14:28 PM PDT 24
Peak memory 240572 kb
Host smart-c316ec86-5e62-4567-8393-28263e3284e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10811
38100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1081138100
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3931506646
Short name T495
Test name
Test status
Simulation time 519134046 ps
CPU time 16.44 seconds
Started May 07 02:14:15 PM PDT 24
Finished May 07 02:14:32 PM PDT 24
Peak memory 254956 kb
Host smart-bb3d2935-c3bb-4705-8c9b-96537c2d8dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
06646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3931506646
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.854851888
Short name T277
Test name
Test status
Simulation time 155059099177 ps
CPU time 2167.03 seconds
Started May 07 02:14:28 PM PDT 24
Finished May 07 02:50:36 PM PDT 24
Peak memory 283964 kb
Host smart-0e1cb52a-491c-4cd0-8fdb-c9431f64f8a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854851888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.854851888
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1657674070
Short name T261
Test name
Test status
Simulation time 97496764362 ps
CPU time 2990.55 seconds
Started May 07 02:14:34 PM PDT 24
Finished May 07 03:04:25 PM PDT 24
Peak memory 289948 kb
Host smart-12c20d08-7f60-4d29-94cc-27c03e079520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657674070 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1657674070
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2821416368
Short name T477
Test name
Test status
Simulation time 44885040001 ps
CPU time 1343.11 seconds
Started May 07 02:14:40 PM PDT 24
Finished May 07 02:37:04 PM PDT 24
Peak memory 289460 kb
Host smart-dbb46b90-ebbc-47f6-9b0a-320057958cb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821416368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2821416368
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.197767438
Short name T507
Test name
Test status
Simulation time 664684267 ps
CPU time 53.84 seconds
Started May 07 02:14:34 PM PDT 24
Finished May 07 02:15:28 PM PDT 24
Peak memory 249212 kb
Host smart-ce9b5cee-099f-416d-95d3-3f6c062b7f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19776
7438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.197767438
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2170282119
Short name T83
Test name
Test status
Simulation time 914960293 ps
CPU time 60.91 seconds
Started May 07 02:14:35 PM PDT 24
Finished May 07 02:15:36 PM PDT 24
Peak memory 256944 kb
Host smart-df687b46-8b35-4fe9-b468-9ad127a6bcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21702
82119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2170282119
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1590359132
Short name T117
Test name
Test status
Simulation time 13203141453 ps
CPU time 1288.35 seconds
Started May 07 02:14:40 PM PDT 24
Finished May 07 02:36:09 PM PDT 24
Peak memory 288724 kb
Host smart-c4251811-264e-4058-bdc5-acafd5a3f5db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590359132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1590359132
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.708866487
Short name T512
Test name
Test status
Simulation time 151643682808 ps
CPU time 2459.67 seconds
Started May 07 02:14:46 PM PDT 24
Finished May 07 02:55:47 PM PDT 24
Peak memory 289144 kb
Host smart-15b636d9-f11c-4e63-a20c-959837d3f9bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708866487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.708866487
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3048499847
Short name T320
Test name
Test status
Simulation time 62551315131 ps
CPU time 507.97 seconds
Started May 07 02:14:40 PM PDT 24
Finished May 07 02:23:08 PM PDT 24
Peak memory 254540 kb
Host smart-de1b1adf-f448-4bc7-b6d9-97c96325b7c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048499847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3048499847
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1689447413
Short name T384
Test name
Test status
Simulation time 374848108 ps
CPU time 32.56 seconds
Started May 07 02:14:36 PM PDT 24
Finished May 07 02:15:09 PM PDT 24
Peak memory 248960 kb
Host smart-1a0fbad3-4c25-4a2a-a1df-d63e1156b6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16894
47413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1689447413
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.108218328
Short name T421
Test name
Test status
Simulation time 785411638 ps
CPU time 32.42 seconds
Started May 07 02:14:33 PM PDT 24
Finished May 07 02:15:06 PM PDT 24
Peak memory 255620 kb
Host smart-0296eca0-f9d5-4039-b20b-14d4a3f57c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10821
8328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.108218328
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1102134827
Short name T574
Test name
Test status
Simulation time 240835836 ps
CPU time 15.91 seconds
Started May 07 02:14:41 PM PDT 24
Finished May 07 02:14:57 PM PDT 24
Peak memory 247748 kb
Host smart-e3d24ce9-8ffc-403e-a47f-f73a0fad8378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11021
34827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1102134827
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3017936041
Short name T68
Test name
Test status
Simulation time 909833483 ps
CPU time 32.79 seconds
Started May 07 02:14:34 PM PDT 24
Finished May 07 02:15:08 PM PDT 24
Peak memory 248844 kb
Host smart-f1f364fb-bb9d-444e-a080-cb792c43a67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179
36041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3017936041
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3490986061
Short name T594
Test name
Test status
Simulation time 22143376059 ps
CPU time 389.03 seconds
Started May 07 02:14:51 PM PDT 24
Finished May 07 02:21:21 PM PDT 24
Peak memory 273284 kb
Host smart-d31d3a5a-23c2-4f36-9116-a5ade39e8d57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490986061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3490986061
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2119207530
Short name T557
Test name
Test status
Simulation time 24284495531 ps
CPU time 1571.95 seconds
Started May 07 02:14:59 PM PDT 24
Finished May 07 02:41:12 PM PDT 24
Peak memory 273324 kb
Host smart-f588a8d5-6e39-47c4-bef8-00073c0d1d2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119207530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2119207530
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1497161583
Short name T472
Test name
Test status
Simulation time 33116473 ps
CPU time 5.58 seconds
Started May 07 02:14:55 PM PDT 24
Finished May 07 02:15:01 PM PDT 24
Peak memory 251036 kb
Host smart-23da50e2-7f5e-4c5e-a957-1d7331561a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14971
61583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1497161583
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3928646818
Short name T383
Test name
Test status
Simulation time 688170432 ps
CPU time 40.04 seconds
Started May 07 02:14:55 PM PDT 24
Finished May 07 02:15:35 PM PDT 24
Peak memory 248736 kb
Host smart-4ca6ac26-1ace-435e-851d-1d0307577df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39286
46818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3928646818
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2126600217
Short name T346
Test name
Test status
Simulation time 13852602563 ps
CPU time 1343.69 seconds
Started May 07 02:14:58 PM PDT 24
Finished May 07 02:37:23 PM PDT 24
Peak memory 289156 kb
Host smart-ad9def4c-f2c3-4caf-8ff6-e76fb1870f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126600217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2126600217
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4236218618
Short name T628
Test name
Test status
Simulation time 37076124275 ps
CPU time 857.72 seconds
Started May 07 02:14:59 PM PDT 24
Finished May 07 02:29:17 PM PDT 24
Peak memory 273452 kb
Host smart-a6f4c215-584b-4eb9-a467-6e769abeda68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236218618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4236218618
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3587568044
Short name T332
Test name
Test status
Simulation time 6597645584 ps
CPU time 248.2 seconds
Started May 07 02:14:58 PM PDT 24
Finished May 07 02:19:07 PM PDT 24
Peak memory 247108 kb
Host smart-3a22102b-c821-453f-afdd-83b1bbcc3d3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587568044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3587568044
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1499601843
Short name T423
Test name
Test status
Simulation time 2086667555 ps
CPU time 48.21 seconds
Started May 07 02:14:53 PM PDT 24
Finished May 07 02:15:41 PM PDT 24
Peak memory 248760 kb
Host smart-330c3f65-05a9-47f6-a253-473eee5fa6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14996
01843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1499601843
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2359768392
Short name T466
Test name
Test status
Simulation time 971885328 ps
CPU time 56.11 seconds
Started May 07 02:14:54 PM PDT 24
Finished May 07 02:15:51 PM PDT 24
Peak memory 255712 kb
Host smart-b41775bf-9164-41d1-8fef-4d259a56ec18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23597
68392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2359768392
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1175202891
Short name T306
Test name
Test status
Simulation time 372711411 ps
CPU time 40.43 seconds
Started May 07 02:14:54 PM PDT 24
Finished May 07 02:15:35 PM PDT 24
Peak memory 255516 kb
Host smart-2519c271-652e-4b09-a756-766fff06ad8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11752
02891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1175202891
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1425025688
Short name T66
Test name
Test status
Simulation time 68669874 ps
CPU time 5.05 seconds
Started May 07 02:14:46 PM PDT 24
Finished May 07 02:14:52 PM PDT 24
Peak memory 240552 kb
Host smart-93005ef1-7892-4c5b-8ae3-22f83d2313a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250
25688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1425025688
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2439287833
Short name T87
Test name
Test status
Simulation time 47044746997 ps
CPU time 2386.47 seconds
Started May 07 02:14:59 PM PDT 24
Finished May 07 02:54:47 PM PDT 24
Peak memory 289560 kb
Host smart-f8769669-4778-4e63-a76b-b5ddb95e8fe6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439287833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2439287833
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1811006358
Short name T93
Test name
Test status
Simulation time 101419615285 ps
CPU time 8675.38 seconds
Started May 07 02:14:57 PM PDT 24
Finished May 07 04:39:34 PM PDT 24
Peak memory 395260 kb
Host smart-b9fdc281-b571-4869-96ec-aa6923fe96c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811006358 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1811006358
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.345878586
Short name T227
Test name
Test status
Simulation time 96608524 ps
CPU time 4.31 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:37 PM PDT 24
Peak memory 248968 kb
Host smart-67cdbd8b-c6e2-4aba-a6d6-1dc405835020
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=345878586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.345878586
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4048553568
Short name T511
Test name
Test status
Simulation time 600945421 ps
CPU time 7.23 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:40 PM PDT 24
Peak memory 248768 kb
Host smart-5f1a0126-d801-4f80-9a02-33a1a6ec1d77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4048553568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4048553568
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1216069873
Short name T514
Test name
Test status
Simulation time 12108936757 ps
CPU time 108.77 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:10:22 PM PDT 24
Peak memory 248856 kb
Host smart-14967294-c2ce-4937-b5df-b063f3f4a5e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
69873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1216069873
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3273660763
Short name T686
Test name
Test status
Simulation time 779336824 ps
CPU time 13.21 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:08:47 PM PDT 24
Peak memory 248788 kb
Host smart-dd790774-c0f4-4cee-8783-773a689662df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32736
60763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3273660763
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3702819395
Short name T351
Test name
Test status
Simulation time 82682870997 ps
CPU time 1421.31 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:32:14 PM PDT 24
Peak memory 273380 kb
Host smart-90cb6e63-77b6-4f83-8013-7b2bf9ed91c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702819395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3702819395
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3534275404
Short name T588
Test name
Test status
Simulation time 115889125122 ps
CPU time 2138.99 seconds
Started May 07 02:08:30 PM PDT 24
Finished May 07 02:44:11 PM PDT 24
Peak memory 289104 kb
Host smart-ac197b4a-4e5d-49f5-9364-9aec065650ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534275404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3534275404
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1661926305
Short name T385
Test name
Test status
Simulation time 465746044 ps
CPU time 40.15 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:09:13 PM PDT 24
Peak memory 248776 kb
Host smart-ab103124-8dff-4350-ada0-bbf58511aed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16619
26305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1661926305
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.14885610
Short name T216
Test name
Test status
Simulation time 121051326 ps
CPU time 11.51 seconds
Started May 07 02:08:32 PM PDT 24
Finished May 07 02:08:45 PM PDT 24
Peak memory 247468 kb
Host smart-704a5fd7-e70c-4384-b317-838a637d43f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.14885610
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2624229999
Short name T565
Test name
Test status
Simulation time 941228992 ps
CPU time 30.68 seconds
Started May 07 02:08:33 PM PDT 24
Finished May 07 02:09:05 PM PDT 24
Peak memory 255380 kb
Host smart-4a34dd3a-ade6-465d-a8e9-7ddc4baf303f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26242
29999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2624229999
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.38653565
Short name T508
Test name
Test status
Simulation time 772390064 ps
CPU time 14.23 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:08:46 PM PDT 24
Peak memory 248768 kb
Host smart-96792d6e-872f-470c-b2e8-bfeebca6a6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38653
565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.38653565
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2250207612
Short name T705
Test name
Test status
Simulation time 2291161437 ps
CPU time 38.67 seconds
Started May 07 02:08:31 PM PDT 24
Finished May 07 02:09:12 PM PDT 24
Peak memory 255300 kb
Host smart-4e73c162-256f-4e1e-b12d-100467fdbd35
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250207612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2250207612
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1470216862
Short name T239
Test name
Test status
Simulation time 30688305 ps
CPU time 3.08 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:08:43 PM PDT 24
Peak memory 248936 kb
Host smart-720d7565-0c85-4e29-a5d4-32fd7fb3ef46
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1470216862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1470216862
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2001056498
Short name T469
Test name
Test status
Simulation time 26616568635 ps
CPU time 1796.07 seconds
Started May 07 02:08:41 PM PDT 24
Finished May 07 02:38:38 PM PDT 24
Peak memory 273460 kb
Host smart-35186b02-47d6-414b-9b28-cf12919e5ab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001056498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2001056498
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3383688624
Short name T198
Test name
Test status
Simulation time 385282153 ps
CPU time 6.1 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:08:41 PM PDT 24
Peak memory 248788 kb
Host smart-6d5d6b4b-cbaf-4989-9c43-746ffdbff175
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3383688624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3383688624
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2879844407
Short name T407
Test name
Test status
Simulation time 2456305229 ps
CPU time 65.2 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:09:42 PM PDT 24
Peak memory 256568 kb
Host smart-32e6b873-f4b5-43d0-98e5-e426fe6558d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
44407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2879844407
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2473654438
Short name T661
Test name
Test status
Simulation time 715291634 ps
CPU time 6.75 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:08:47 PM PDT 24
Peak memory 251108 kb
Host smart-46cf07a9-38cd-4414-b50d-6738b6b3d0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24736
54438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2473654438
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3537723928
Short name T642
Test name
Test status
Simulation time 14195322219 ps
CPU time 1383.06 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:31:42 PM PDT 24
Peak memory 285328 kb
Host smart-016b7009-e62f-4c48-bec5-cd83a6035bc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537723928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3537723928
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.409052446
Short name T527
Test name
Test status
Simulation time 53603392821 ps
CPU time 1411.83 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:32:12 PM PDT 24
Peak memory 272764 kb
Host smart-f28e2438-d522-4e8c-a84b-40a64ded106f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409052446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.409052446
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3883338465
Short name T338
Test name
Test status
Simulation time 6490669297 ps
CPU time 136.02 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:10:54 PM PDT 24
Peak memory 248104 kb
Host smart-db8b780e-5503-4fb4-968f-ccd5c59f11d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883338465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3883338465
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2991585801
Short name T257
Test name
Test status
Simulation time 330212673 ps
CPU time 27.34 seconds
Started May 07 02:08:38 PM PDT 24
Finished May 07 02:09:06 PM PDT 24
Peak memory 255972 kb
Host smart-b7fe4a97-f764-4afe-9de9-0762b610f1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
85801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2991585801
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1857570262
Short name T475
Test name
Test status
Simulation time 326103987 ps
CPU time 16.19 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:08:52 PM PDT 24
Peak memory 247464 kb
Host smart-bf94f6d0-4854-4e42-9cee-21b12453571b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575
70262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1857570262
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2587395634
Short name T523
Test name
Test status
Simulation time 748161954 ps
CPU time 44.61 seconds
Started May 07 02:08:38 PM PDT 24
Finished May 07 02:09:23 PM PDT 24
Peak memory 255604 kb
Host smart-a534a82d-4297-462c-8f6b-4aeaddfdd30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25873
95634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2587395634
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.127164683
Short name T35
Test name
Test status
Simulation time 1078447400 ps
CPU time 69.29 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:09:48 PM PDT 24
Peak memory 248792 kb
Host smart-3dabcae9-ae43-410a-bf26-d4a03854b8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
4683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.127164683
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.794035017
Short name T290
Test name
Test status
Simulation time 206467028282 ps
CPU time 2979.64 seconds
Started May 07 02:08:36 PM PDT 24
Finished May 07 02:58:16 PM PDT 24
Peak memory 289800 kb
Host smart-75bb074c-7344-4a9f-bf62-abb8b83e714c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794035017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.794035017
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3581760590
Short name T233
Test name
Test status
Simulation time 47063986 ps
CPU time 3.14 seconds
Started May 07 02:08:38 PM PDT 24
Finished May 07 02:08:42 PM PDT 24
Peak memory 248896 kb
Host smart-a1dcd37d-bfc7-4be5-807e-72f8e509c861
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3581760590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3581760590
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3524473807
Short name T719
Test name
Test status
Simulation time 150238974761 ps
CPU time 1795.52 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:38:38 PM PDT 24
Peak memory 284440 kb
Host smart-cee78e3e-690e-4afe-a839-175d5cb0da00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524473807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3524473807
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2287892304
Short name T506
Test name
Test status
Simulation time 436843422 ps
CPU time 20.02 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:08:59 PM PDT 24
Peak memory 240656 kb
Host smart-0db31bc9-f19f-4ab5-9646-9300c0ed9838
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2287892304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2287892304
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2735705327
Short name T408
Test name
Test status
Simulation time 107116865 ps
CPU time 6.18 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:08:45 PM PDT 24
Peak memory 249288 kb
Host smart-c5319cea-71e9-4d2b-8ade-a0302f5aa26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27357
05327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2735705327
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.924223142
Short name T632
Test name
Test status
Simulation time 69157517 ps
CPU time 4.87 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:08:44 PM PDT 24
Peak memory 240560 kb
Host smart-aadd5664-01bd-4634-92ce-9e066385d4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92422
3142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.924223142
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1350958392
Short name T724
Test name
Test status
Simulation time 34103191196 ps
CPU time 1473.64 seconds
Started May 07 02:08:41 PM PDT 24
Finished May 07 02:33:15 PM PDT 24
Peak memory 281612 kb
Host smart-a4c1139f-7b1b-4a76-aac0-27b950a5c9e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350958392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1350958392
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3204935028
Short name T397
Test name
Test status
Simulation time 32099474690 ps
CPU time 754.32 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:21:14 PM PDT 24
Peak memory 267264 kb
Host smart-321523d6-6467-4e81-858a-b57fbf6b40bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204935028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3204935028
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3128148865
Short name T341
Test name
Test status
Simulation time 8071086523 ps
CPU time 225.5 seconds
Started May 07 02:08:36 PM PDT 24
Finished May 07 02:12:22 PM PDT 24
Peak memory 248100 kb
Host smart-de990a83-236b-4093-9508-9a9e7717fe5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128148865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3128148865
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2567002165
Short name T314
Test name
Test status
Simulation time 3907726410 ps
CPU time 50.53 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:09:28 PM PDT 24
Peak memory 248828 kb
Host smart-2df77b85-85a3-425a-9c0d-0f44f4de8b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25670
02165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2567002165
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1295734713
Short name T310
Test name
Test status
Simulation time 591735962 ps
CPU time 37.86 seconds
Started May 07 02:08:38 PM PDT 24
Finished May 07 02:09:18 PM PDT 24
Peak memory 255632 kb
Host smart-ea20354a-d1df-42ab-8db8-e1bf0db36404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12957
34713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1295734713
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2467118071
Short name T86
Test name
Test status
Simulation time 667638468 ps
CPU time 39.79 seconds
Started May 07 02:08:38 PM PDT 24
Finished May 07 02:09:19 PM PDT 24
Peak memory 248712 kb
Host smart-84f4b05a-0a46-4399-a0aa-1b78b8a48340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24671
18071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2467118071
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1082425503
Short name T428
Test name
Test status
Simulation time 135988136 ps
CPU time 11.93 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:08:48 PM PDT 24
Peak memory 248788 kb
Host smart-a623ad9d-a388-441d-ac02-cb0cef066158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10824
25503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1082425503
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2809653317
Short name T114
Test name
Test status
Simulation time 113039043002 ps
CPU time 2229.1 seconds
Started May 07 02:08:35 PM PDT 24
Finished May 07 02:45:45 PM PDT 24
Peak memory 289508 kb
Host smart-796ea171-3682-4f90-9c76-51cb6c23b1d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809653317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2809653317
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.438193109
Short name T57
Test name
Test status
Simulation time 48988878989 ps
CPU time 1405.27 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:32:03 PM PDT 24
Peak memory 301224 kb
Host smart-c3e66bac-8192-448f-b79a-9d61c3e3fc0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438193109 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.438193109
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3100440117
Short name T226
Test name
Test status
Simulation time 49193057 ps
CPU time 3.91 seconds
Started May 07 02:08:41 PM PDT 24
Finished May 07 02:08:46 PM PDT 24
Peak memory 248928 kb
Host smart-eb42c16b-1416-4b9a-8aaf-b0821033f35b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3100440117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3100440117
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3801989948
Short name T560
Test name
Test status
Simulation time 59599200711 ps
CPU time 952.79 seconds
Started May 07 02:08:43 PM PDT 24
Finished May 07 02:24:37 PM PDT 24
Peak memory 272108 kb
Host smart-b01e1711-e094-49b1-ac95-d5131376a9fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801989948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3801989948
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2008879097
Short name T203
Test name
Test status
Simulation time 14442404669 ps
CPU time 36.42 seconds
Started May 07 02:08:46 PM PDT 24
Finished May 07 02:09:24 PM PDT 24
Peak memory 248824 kb
Host smart-7e6ee78d-60da-43f9-8653-01b03255eb84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2008879097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2008879097
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1436340930
Short name T567
Test name
Test status
Simulation time 5842898969 ps
CPU time 168.91 seconds
Started May 07 02:08:43 PM PDT 24
Finished May 07 02:11:33 PM PDT 24
Peak memory 249852 kb
Host smart-39847b44-e6f4-4a5b-82ae-9401be6f139d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363
40930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1436340930
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2078799567
Short name T105
Test name
Test status
Simulation time 838585666 ps
CPU time 20.68 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:09:01 PM PDT 24
Peak memory 254864 kb
Host smart-622745a0-d3f5-47dd-937e-ce6d84612f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20787
99567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2078799567
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1615680497
Short name T713
Test name
Test status
Simulation time 184283970551 ps
CPU time 2710.37 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:53:54 PM PDT 24
Peak memory 289256 kb
Host smart-65dc6009-0cc7-4719-a78c-a424b670433d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615680497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1615680497
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.189266024
Short name T412
Test name
Test status
Simulation time 152754259104 ps
CPU time 2355.01 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:47:58 PM PDT 24
Peak memory 289676 kb
Host smart-d4363905-760f-4c2f-a622-1001c0b3a4ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189266024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.189266024
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3322022518
Short name T2
Test name
Test status
Simulation time 15020767979 ps
CPU time 143.61 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:11:07 PM PDT 24
Peak memory 248068 kb
Host smart-32187e18-4de5-4a43-82f7-73693163c24c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322022518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3322022518
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.110366321
Short name T513
Test name
Test status
Simulation time 349491036 ps
CPU time 22.82 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:09:03 PM PDT 24
Peak memory 248784 kb
Host smart-1e6d4e5d-ee98-4eee-a5b2-57feda2ade42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11036
6321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.110366321
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.940839645
Short name T269
Test name
Test status
Simulation time 881651267 ps
CPU time 30.46 seconds
Started May 07 02:08:39 PM PDT 24
Finished May 07 02:09:11 PM PDT 24
Peak memory 248772 kb
Host smart-e2379635-b64e-4eab-bb73-c704df45b7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94083
9645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.940839645
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3300142044
Short name T295
Test name
Test status
Simulation time 276201602 ps
CPU time 19.26 seconds
Started May 07 02:08:41 PM PDT 24
Finished May 07 02:09:02 PM PDT 24
Peak memory 255748 kb
Host smart-74a9ca98-7e6d-4ab5-9280-9eef887ddaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33001
42044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3300142044
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2988124294
Short name T70
Test name
Test status
Simulation time 508020930 ps
CPU time 23.28 seconds
Started May 07 02:08:37 PM PDT 24
Finished May 07 02:09:02 PM PDT 24
Peak memory 248788 kb
Host smart-9ea48af6-c64e-4f83-854d-df91fc4a9c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
24294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2988124294
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.968632986
Short name T418
Test name
Test status
Simulation time 7704742917 ps
CPU time 198.45 seconds
Started May 07 02:08:46 PM PDT 24
Finished May 07 02:12:06 PM PDT 24
Peak memory 256992 kb
Host smart-2712bd3c-e328-409d-aa7c-8ae9515b9e7d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968632986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.968632986
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3001636525
Short name T525
Test name
Test status
Simulation time 124262033150 ps
CPU time 3104.96 seconds
Started May 07 02:08:43 PM PDT 24
Finished May 07 03:00:29 PM PDT 24
Peak memory 306280 kb
Host smart-56a4146d-619f-4883-ab50-fff5adf1b76e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001636525 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3001636525
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2403335290
Short name T243
Test name
Test status
Simulation time 55897815 ps
CPU time 3.32 seconds
Started May 07 02:08:49 PM PDT 24
Finished May 07 02:08:53 PM PDT 24
Peak memory 248956 kb
Host smart-57af5730-d24c-4324-8858-9d74bf6541f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2403335290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2403335290
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4164952258
Short name T488
Test name
Test status
Simulation time 19186152821 ps
CPU time 1106.56 seconds
Started May 07 02:08:45 PM PDT 24
Finished May 07 02:27:13 PM PDT 24
Peak memory 281580 kb
Host smart-c8ff8897-a868-4044-829e-21236ecd4660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164952258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4164952258
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.171051469
Short name T660
Test name
Test status
Simulation time 559317506 ps
CPU time 8.42 seconds
Started May 07 02:08:41 PM PDT 24
Finished May 07 02:08:50 PM PDT 24
Peak memory 248808 kb
Host smart-02c40ea0-7dc2-4cea-8a4b-1b177505e0a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=171051469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.171051469
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4197361208
Short name T721
Test name
Test status
Simulation time 6878552233 ps
CPU time 210.51 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:12:14 PM PDT 24
Peak memory 250956 kb
Host smart-b7b1f21a-dbd6-44f4-a799-b97e723295e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973
61208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4197361208
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.864989029
Short name T455
Test name
Test status
Simulation time 2262040972 ps
CPU time 41.15 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:09:25 PM PDT 24
Peak memory 248824 kb
Host smart-88edb428-9f5b-4286-b122-ec0cedfcc8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86498
9029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.864989029
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1341346874
Short name T361
Test name
Test status
Simulation time 119344984053 ps
CPU time 1496.5 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:33:40 PM PDT 24
Peak memory 267516 kb
Host smart-dbbf10a2-cb25-441b-9c8f-3c3747082c3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341346874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1341346874
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.514887341
Short name T468
Test name
Test status
Simulation time 78440110736 ps
CPU time 1344.28 seconds
Started May 07 02:08:45 PM PDT 24
Finished May 07 02:31:10 PM PDT 24
Peak memory 273392 kb
Host smart-29aa1145-cc21-49d0-a5b6-3087e8166fd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514887341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.514887341
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2961753982
Short name T601
Test name
Test status
Simulation time 43060217989 ps
CPU time 91.8 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:10:15 PM PDT 24
Peak memory 248820 kb
Host smart-08976292-eb32-4729-8c33-0d8f43236c69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961753982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2961753982
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1353116342
Short name T448
Test name
Test status
Simulation time 467644597 ps
CPU time 32.36 seconds
Started May 07 02:08:47 PM PDT 24
Finished May 07 02:09:20 PM PDT 24
Peak memory 248856 kb
Host smart-4eba5c39-60ce-4bd0-b534-3281665b7d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
16342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1353116342
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4112588262
Short name T543
Test name
Test status
Simulation time 756881853 ps
CPU time 19.85 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:09:02 PM PDT 24
Peak memory 247424 kb
Host smart-711de3ad-e90c-4ac1-b4c4-cd721246e92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41125
88262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4112588262
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.295967287
Short name T95
Test name
Test status
Simulation time 327156518 ps
CPU time 6.62 seconds
Started May 07 02:08:41 PM PDT 24
Finished May 07 02:08:48 PM PDT 24
Peak memory 240576 kb
Host smart-c1812040-8a7c-419d-a320-8b2f9f4d8c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29596
7287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.295967287
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.878306080
Short name T725
Test name
Test status
Simulation time 1029178475 ps
CPU time 22.68 seconds
Started May 07 02:08:42 PM PDT 24
Finished May 07 02:09:06 PM PDT 24
Peak memory 248792 kb
Host smart-35a401ba-6920-4b6e-8b53-410ad61f5691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87830
6080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.878306080
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2228974892
Short name T644
Test name
Test status
Simulation time 7408247952 ps
CPU time 386.03 seconds
Started May 07 02:08:46 PM PDT 24
Finished May 07 02:15:14 PM PDT 24
Peak memory 256992 kb
Host smart-5b80fa98-5ea7-471b-9df8-5c4871436448
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228974892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2228974892
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4280315448
Short name T485
Test name
Test status
Simulation time 205030447825 ps
CPU time 2929.2 seconds
Started May 07 02:08:47 PM PDT 24
Finished May 07 02:57:38 PM PDT 24
Peak memory 305704 kb
Host smart-93383fff-a2b9-48f2-bdbc-24233a2e1d16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280315448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4280315448
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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