Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	60813	1			T1	112		T18	4000		T5	1
class_i[0x1]	71423	1			T1	1609		T16	1		T5	1
class_i[0x2]	58357	1			T1	4		T5	8		T46	4
class_i[0x3]	59482	1			T1	14		T16	168		T18	20

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63837	1			T1	473		T16	39		T18	969
alert[0x1]	63981	1			T1	402		T16	22		T18	1075
alert[0x2]	59178	1			T1	420		T16	56		T18	994
alert[0x3]	63079	1			T1	444		T16	52		T18	982

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

249812

1

T1

1739

T16

169

T18

4020

esc_ping_fail

263

1

T5

10

T6

8

T7

10

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63769	1			T1	473		T16	39		T18	969
esc_integrity_fail	alert[0x1]	63918	1			T1	402		T16	22		T18	1075
esc_integrity_fail	alert[0x2]	59108	1			T1	420		T16	56		T18	994
esc_integrity_fail	alert[0x3]	63017	1			T1	444		T16	52		T18	982
esc_ping_fail	alert[0x0]	68	1			T5	2		T6	1		T7	2
esc_ping_fail	alert[0x1]	63	1			T5	2		T6	3		T7	2
esc_ping_fail	alert[0x2]	70	1			T5	3		T6	2		T7	3
esc_ping_fail	alert[0x3]	62	1			T5	3		T6	2		T7	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	60726	1			T1	112		T18	4000		T108	2
esc_integrity_fail	class_i[0x1]	71380	1			T1	1609		T16	1		T6	16
esc_integrity_fail	class_i[0x2]	58296	1			T1	4		T46	4		T23	568
esc_integrity_fail	class_i[0x3]	59410	1			T1	14		T16	168		T18	20
esc_ping_fail	class_i[0x0]	87	1			T5	1		T6	8		T235	1
esc_ping_fail	class_i[0x1]	43	1			T5	1		T97	1		T304	5
esc_ping_fail	class_i[0x2]	61	1			T5	8		T235	1		T228	1
esc_ping_fail	class_i[0x3]	72	1			T7	10		T235	1		T108	3