Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T16	3		T21	1		T22	1
class_index[0x1]	51	1			T25	1		T31	1		T77	1
class_index[0x2]	64	1			T23	2		T77	2		T89	1
class_index[0x3]	67	1			T16	1		T25	1		T31	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	117	1			T16	4		T22	1		T25	2
intr_timeout_cnt[1]	56	1			T21	1		T77	2		T87	1
intr_timeout_cnt[2]	22	1			T76	1		T31	1		T77	2
intr_timeout_cnt[3]	8	1			T23	2		T89	1		T55	1
intr_timeout_cnt[4]	12	1			T58	2		T102	1		T259	2
intr_timeout_cnt[5]	9	1			T48	2		T59	1		T193	1
intr_timeout_cnt[6]	4	1			T55	1		T59	1		T260	2
intr_timeout_cnt[7]	7	1			T49	1		T261	1		T106	1
intr_timeout_cnt[8]	9	1			T23	1		T77	1		T122	1
intr_timeout_cnt[9]	3	1			T87	1		T56	1		T262	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[3] , intr_timeout_cnt[4]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T16	3		T22	1		T88	1
class_index[0x0]	intr_timeout_cnt[1]	20	1			T21	1		T77	1		T91	1
class_index[0x0]	intr_timeout_cnt[2]	4	1			T76	1		T102	1		T194	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T55	1		T242	1		T263	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T259	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T264	1		T260	2		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T265	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T23	1		T122	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	23	1			T25	1		T87	1		T49	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T77	1		T87	1		T102	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T31	1		T92	1		T266	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T48	2		T193	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T55	1		T260	2		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T261	1		T106	1		T265	2
class_index[0x1]	intr_timeout_cnt[8]	3	1			T237	1		T267	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T56	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	33	1			T77	1		T68	1		T49	2
class_index[0x2]	intr_timeout_cnt[1]	13	1			T102	2		T268	2		T269	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T73	2		T113	1		T270	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T23	2		T89	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T58	1		T259	1		T271	2
class_index[0x2]	intr_timeout_cnt[6]	1	1			T59	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T237	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T77	1		T272	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T87	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	31	1			T16	1		T25	1		T31	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T50	1		T131	1		T132	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T77	2		T130	1		T262	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T273	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	7	1			T58	1		T102	1		T274	1
class_index[0x3]	intr_timeout_cnt[5]	3	1			T59	1		T27	1		T275	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T49	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T193	1		T274	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T262	1		-	-		-	-