Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	366607	1			T1	1101		T2	1483		T3	829
all_values[1]	366607	1			T1	1101		T2	1483		T3	829
all_values[2]	366607	1			T1	1101		T2	1483		T3	829
all_values[3]	366607	1			T1	1101		T2	1483		T3	829

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

729680

1

T1

2238

T2

3023

T3

1613

auto[1]

736748

1

T1

2166

T2

2909

T3

1703

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870457

1

T1

2504

T2

3030

T3

2232

auto[1]

595971

1

T1

1900

T2

2902

T3

1084

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	105782	1			T1	266		T2	387		T3	282
all_values[0]	auto[0]	auto[1]	76666	1			T1	267		T2	362		T3	168
all_values[0]	auto[1]	auto[0]	107476	1			T1	280		T2	380		T3	244
all_values[0]	auto[1]	auto[1]	76683	1			T1	288		T2	354		T3	135
all_values[1]	auto[0]	auto[0]	108299	1			T1	344		T2	369		T3	215
all_values[1]	auto[0]	auto[1]	74206	1			T1	240		T2	368		T3	167
all_values[1]	auto[1]	auto[0]	109736	1			T1	307		T2	373		T3	261
all_values[1]	auto[1]	auto[1]	74366	1			T1	210		T2	373		T3	186
all_values[2]	auto[0]	auto[0]	108731	1			T1	344		T2	381		T3	311
all_values[2]	auto[0]	auto[1]	74149	1			T1	222		T2	378		T3	99
all_values[2]	auto[1]	auto[0]	109747	1			T1	328		T2	363		T3	320
all_values[2]	auto[1]	auto[1]	73980	1			T1	207		T2	361		T3	99
all_values[3]	auto[0]	auto[0]	109269	1			T1	323		T2	408		T3	261
all_values[3]	auto[0]	auto[1]	72578	1			T1	232		T2	370		T3	110
all_values[3]	auto[1]	auto[0]	111417	1			T1	312		T2	369		T3	338
all_values[3]	auto[1]	auto[1]	73343	1			T1	234		T2	336		T3	120