Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	366607	1			T1	1101		T2	1483		T3	829
all_pins[1]	366607	1			T1	1101		T2	1483		T3	829
all_pins[2]	366607	1			T1	1101		T2	1483		T3	829
all_pins[3]	366607	1			T1	1101		T2	1483		T3	829

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1168056	1			T1	3465		T2	4508		T3	2776
values[0x1]	298372	1			T1	939		T2	1424		T3	540
transitions[0x0=>0x1]	197999	1			T1	637		T2	919		T3	406
transitions[0x1=>0x0]	198220	1			T1	637		T2	920		T3	406

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	289924	1			T1	813		T2	1129		T3	694
all_pins[0]	values[0x1]	76683	1			T1	288		T2	354		T3	135
all_pins[0]	transitions[0x0=>0x1]	76081	1			T1	285		T2	353		T3	135
all_pins[0]	transitions[0x1=>0x0]	72962	1			T1	231		T2	336		T3	120
all_pins[1]	values[0x0]	292241	1			T1	891		T2	1110		T3	643
all_pins[1]	values[0x1]	74366	1			T1	210		T2	373		T3	186
all_pins[1]	transitions[0x0=>0x1]	40990	1			T1	99		T2	215		T3	120
all_pins[1]	transitions[0x1=>0x0]	43307	1			T1	177		T2	196		T3	69
all_pins[2]	values[0x0]	292627	1			T1	894		T2	1122		T3	730
all_pins[2]	values[0x1]	73980	1			T1	207		T2	361		T3	99
all_pins[2]	transitions[0x0=>0x1]	40774	1			T1	112		T2	189		T3	56
all_pins[2]	transitions[0x1=>0x0]	41160	1			T1	115		T2	201		T3	143
all_pins[3]	values[0x0]	293264	1			T1	867		T2	1147		T3	709
all_pins[3]	values[0x1]	73343	1			T1	234		T2	336		T3	120
all_pins[3]	transitions[0x0=>0x1]	40154	1			T1	141		T2	162		T3	95
all_pins[3]	transitions[0x1=>0x0]	40791	1			T1	114		T2	187		T3	74