Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 287 1 T173 4 T174 4 T231 7
all_values[1] 287 1 T173 4 T174 4 T231 7
all_values[2] 287 1 T173 4 T174 4 T231 7
all_values[3] 287 1 T173 4 T174 4 T231 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 625 1 T173 11 T174 8 T231 17
auto[1] 523 1 T173 5 T174 8 T231 11



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 415 1 T173 3 T174 8 T231 10
auto[1] 733 1 T173 13 T174 8 T231 18



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 672 1 T173 7 T174 11 T231 15
auto[1] 476 1 T173 9 T174 5 T231 13



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 50 1 T173 1 T174 1 T231 3
all_values[0] auto[0] auto[0] auto[1] 30 1 T231 1 T232 2 T353 1
all_values[0] auto[0] auto[1] auto[0] 45 1 T173 1 T174 1 T231 2
all_values[0] auto[0] auto[1] auto[1] 46 1 T173 1 T174 1 T354 1
all_values[0] auto[1] auto[0] auto[1] 66 1 T232 3 T354 1 T355 2
all_values[0] auto[1] auto[1] auto[1] 50 1 T173 1 T174 1 T231 1
all_values[1] auto[0] auto[0] auto[0] 50 1 T174 1 T231 2 T232 2
all_values[1] auto[0] auto[0] auto[1] 36 1 T173 1 T174 1 T231 2
all_values[1] auto[0] auto[1] auto[0] 56 1 T173 1 T231 1 T251 1
all_values[1] auto[0] auto[1] auto[1] 22 1 T354 1 T355 1 T356 1
all_values[1] auto[1] auto[0] auto[1] 77 1 T173 2 T231 2 T232 5
all_values[1] auto[1] auto[1] auto[1] 46 1 T174 2 T251 1 T354 1
all_values[2] auto[0] auto[0] auto[0] 52 1 T174 4 T231 1 T232 1
all_values[2] auto[0] auto[0] auto[1] 36 1 T173 1 T231 1 T232 3
all_values[2] auto[0] auto[1] auto[0] 47 1 T251 1 T357 1 T355 1
all_values[2] auto[0] auto[1] auto[1] 34 1 T231 1 T354 2 T355 1
all_values[2] auto[1] auto[0] auto[1] 59 1 T173 2 T231 1 T232 3
all_values[2] auto[1] auto[1] auto[1] 59 1 T173 1 T231 3 T354 2
all_values[3] auto[0] auto[0] auto[0] 69 1 T174 1 T232 1 T354 1
all_values[3] auto[0] auto[0] auto[1] 24 1 T173 1 T251 1 T354 1
all_values[3] auto[0] auto[1] auto[0] 46 1 T231 1 T232 3 T251 1
all_values[3] auto[0] auto[1] auto[1] 29 1 T174 1 T232 1 T355 1
all_values[3] auto[1] auto[0] auto[1] 76 1 T173 3 T231 4 T251 1
all_values[3] auto[1] auto[1] auto[1] 43 1 T174 2 T231 2 T232 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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