Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91165	1			T1	59		T2	443		T18	348
accum_cnt_1000	235985	1			T1	1262		T2	607		T3	791
accum_cnt_100	26334	1			T1	142		T2	34		T3	228
accum_cnt_50	69728	1			T1	909		T2	30		T3	154
accum_cnt_10	205180	1			T1	87		T2	2265		T3	1260
accum_cnt_0	402303	1			T1	813		T2	1141		T3	11

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	270981	1			T1	818		T2	1130		T3	611
class_index[0x1]	270981	1			T1	818		T2	1130		T3	611
class_index[0x2]	270981	1			T1	818		T2	1130		T3	611
class_index[0x3]	270981	1			T1	818		T2	1130		T3	611

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24235	1			T18	348		T11	421		T46	26
class_index[0x0]	accum_cnt_1000	54647	1			T1	619		T3	466		T16	58
class_index[0x0]	accum_cnt_100	6327	1			T1	77		T3	87		T16	72
class_index[0x0]	accum_cnt_50	18382	1			T1	55		T3	40		T15	13
class_index[0x0]	accum_cnt_10	45716	1			T1	18		T3	14		T15	2
class_index[0x0]	accum_cnt_0	109109	1			T1	49		T2	1130		T3	4
class_index[0x1]	accum_cnt_2000	19624	1			T115	665		T76	566		T129	559
class_index[0x1]	accum_cnt_1000	52003	1			T16	10		T4	528		T13	541
class_index[0x1]	accum_cnt_100	6035	1			T16	36		T18	11		T4	159
class_index[0x1]	accum_cnt_50	14327	1			T1	409		T16	108		T18	21
class_index[0x1]	accum_cnt_10	59512	1			T1	12		T2	1126		T3	611
class_index[0x1]	accum_cnt_0	107867	1			T1	397		T2	4		T15	15
class_index[0x2]	accum_cnt_2000	24209	1			T1	59		T2	443		T46	57
class_index[0x2]	accum_cnt_1000	62624	1			T1	479		T2	607		T3	325
class_index[0x2]	accum_cnt_100	6813	1			T1	34		T2	34		T3	141
class_index[0x2]	accum_cnt_50	17935	1			T1	32		T2	30		T3	114
class_index[0x2]	accum_cnt_10	49829	1			T1	27		T2	11		T3	24
class_index[0x2]	accum_cnt_0	97917	1			T1	187		T2	5		T3	7
class_index[0x3]	accum_cnt_2000	23097	1			T115	646		T129	477		T31	604
class_index[0x3]	accum_cnt_1000	66711	1			T1	164		T16	57		T14	1020
class_index[0x3]	accum_cnt_100	7159	1			T1	31		T16	51		T14	159
class_index[0x3]	accum_cnt_50	19084	1			T1	413		T16	57		T18	82
class_index[0x3]	accum_cnt_10	50123	1			T1	30		T2	1128		T3	611
class_index[0x3]	accum_cnt_0	87410	1			T1	180		T2	2		T15	15