Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3344	1			T5	1		T6	1		T46	5
alert[0x1]	6200	1			T1	39		T46	76		T23	4
alert[0x2]	15810	1			T1	95		T108	1		T76	5372
alert[0x3]	5510	1			T1	2		T7	1		T110	1
alert[0x4]	7774	1			T108	1		T29	235		T78	164
alert[0x5]	9117	1			T1	444		T6	1		T25	2
alert[0x6]	11008	1			T1	1		T45	3		T66	1
alert[0x7]	8766	1			T5	1		T29	29		T78	325
alert[0x8]	3616	1			T5	1		T108	1		T76	670
alert[0x9]	2258	1			T5	1		T76	284		T110	2
alert[0xa]	5039	1			T46	156		T97	1		T29	106
alert[0xb]	7340	1			T1	10		T228	1		T81	23
alert[0xc]	22179	1			T1	6		T16	1		T6	3
alert[0xd]	7369	1			T7	1		T81	185		T78	34
alert[0xe]	9918	1			T46	1		T7	2		T228	1
alert[0xf]	3639	1			T1	6		T7	1		T76	33
alert[0x10]	3968	1			T1	37		T7	1		T235	1
alert[0x11]	7234	1			T1	1		T45	13		T7	1
alert[0x12]	12049	1			T7	1		T228	1		T97	2
alert[0x13]	4878	1			T1	134		T5	1		T46	277
alert[0x14]	7808	1			T76	36		T99	1		T29	179
alert[0x15]	4339	1			T1	1		T228	1		T76	27
alert[0x16]	17799	1			T1	5		T5	1		T76	148
alert[0x17]	8623	1			T1	6		T46	12		T32	3192
alert[0x18]	5191	1			T6	1		T46	110		T97	1
alert[0x19]	4223	1			T228	1		T31	2		T29	84
alert[0x1a]	6773	1			T46	23		T23	4		T78	578
alert[0x1b]	10076	1			T1	94		T6	1		T7	3
alert[0x1c]	8103	1			T235	1		T25	2		T31	1
alert[0x1d]	16555	1			T5	1		T46	121		T235	1
alert[0x1e]	5289	1			T46	11		T108	1		T76	120
alert[0x1f]	12647	1			T46	102		T7	1		T81	54
alert[0x20]	3945	1			T5	1		T6	1		T46	68
alert[0x21]	3512	1			T5	1		T46	12		T7	1
alert[0x22]	7509	1			T1	6		T5	1		T46	11
alert[0x23]	10402	1			T5	1		T45	24		T46	79
alert[0x24]	8761	1			T1	22		T22	4		T23	55
alert[0x25]	6804	1			T6	1		T108	1		T29	121
alert[0x26]	4703	1			T7	1		T76	444		T110	1
alert[0x27]	5821	1			T46	7		T7	2		T76	493
alert[0x28]	4081	1			T1	42		T3	1		T45	2
alert[0x29]	9199	1			T1	3		T108	2		T76	19
alert[0x2a]	10007	1			T1	5		T5	1		T46	77
alert[0x2b]	12091	1			T5	1		T46	43		T81	34
alert[0x2c]	3221	1			T46	75		T76	29		T97	1
alert[0x2d]	9899	1			T1	7		T46	36		T78	14
alert[0x2e]	7000	1			T1	78		T6	1		T46	342
alert[0x2f]	6798	1			T6	1		T46	59		T81	21
alert[0x30]	3622	1			T1	70		T46	183		T99	1
alert[0x31]	7982	1			T16	66		T46	573		T81	575
alert[0x32]	4027	1			T46	9		T110	1		T78	1
alert[0x33]	15369	1			T1	28		T81	55		T78	229
alert[0x34]	11622	1			T81	360		T97	1		T31	2
alert[0x35]	4822	1			T46	57		T81	362		T97	1
alert[0x36]	9962	1			T46	131		T76	546		T32	189
alert[0x37]	6445	1			T6	1		T46	324		T228	1
alert[0x38]	5620	1			T1	96		T6	1		T29	357
alert[0x39]	6291	1			T108	1		T76	26		T29	25
alert[0x3a]	10862	1			T5	1		T46	15		T108	1
alert[0x3b]	9345	1			T1	1		T6	1		T46	309
alert[0x3c]	7934	1			T235	1		T29	987		T32	1540
alert[0x3d]	6318	1			T46	335		T108	1		T81	419
alert[0x3e]	7851	1			T1	19		T5	1		T6	1
alert[0x3f]	5535	1			T16	9		T81	88		T29	51
alert[0x40]	5575	1			T1	356		T46	47		T76	120

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	149073	1			T1	28		T16	76		T5	1
class_i[0x1]	89768	1			T1	3		T6	1		T7	1
class_i[0x2]	105105	1			T1	1582		T3	1		T5	14
class_i[0x3]	163431	1			T1	1		T45	8		T46	4033

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

506707

1

T1

1614

T16

76

T45

42

alert_ping_fail

670

1

T3

1

T5

15

T6

15

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3335	1			T46	5		T29	51		T32	28
alert_integrity_fail	alert[0x1]	6191	1			T1	39		T46	76		T23	4
alert_integrity_fail	alert[0x2]	15800	1			T1	95		T76	5372		T81	529
alert_integrity_fail	alert[0x3]	5500	1			T1	2		T81	10		T29	65
alert_integrity_fail	alert[0x4]	7761	1			T29	235		T78	164		T36	6
alert_integrity_fail	alert[0x5]	9108	1			T1	444		T25	2		T29	267
alert_integrity_fail	alert[0x6]	10994	1			T1	1		T45	3		T53	1
alert_integrity_fail	alert[0x7]	8756	1			T29	29		T78	325		T49	1952
alert_integrity_fail	alert[0x8]	3606	1			T76	670		T86	159		T36	6
alert_integrity_fail	alert[0x9]	2245	1			T76	284		T81	82		T86	31
alert_integrity_fail	alert[0xa]	5026	1			T46	156		T29	106		T32	1028
alert_integrity_fail	alert[0xb]	7331	1			T1	10		T81	23		T29	9
alert_integrity_fail	alert[0xc]	22164	1			T1	6		T16	1		T46	352
alert_integrity_fail	alert[0xd]	7364	1			T81	185		T78	34		T32	3377
alert_integrity_fail	alert[0xe]	9906	1			T46	1		T25	3		T29	121
alert_integrity_fail	alert[0xf]	3629	1			T1	6		T76	33		T25	1
alert_integrity_fail	alert[0x10]	3959	1			T1	37		T76	5		T29	5
alert_integrity_fail	alert[0x11]	7221	1			T1	1		T45	13		T81	25
alert_integrity_fail	alert[0x12]	12039	1			T29	1870		T78	241		T32	99
alert_integrity_fail	alert[0x13]	4861	1			T1	134		T46	277		T76	25
alert_integrity_fail	alert[0x14]	7799	1			T76	36		T29	179		T32	271
alert_integrity_fail	alert[0x15]	4332	1			T1	1		T76	27		T81	19
alert_integrity_fail	alert[0x16]	17785	1			T1	5		T76	148		T81	106
alert_integrity_fail	alert[0x17]	8612	1			T1	6		T46	12		T32	3192
alert_integrity_fail	alert[0x18]	5182	1			T46	110		T78	279		T86	21
alert_integrity_fail	alert[0x19]	4215	1			T31	2		T29	84		T85	1
alert_integrity_fail	alert[0x1a]	6768	1			T46	23		T23	4		T78	578
alert_integrity_fail	alert[0x1b]	10064	1			T1	94		T22	18		T23	3
alert_integrity_fail	alert[0x1c]	8090	1			T25	2		T31	1		T29	103
alert_integrity_fail	alert[0x1d]	16546	1			T46	121		T81	266		T78	106
alert_integrity_fail	alert[0x1e]	5281	1			T46	11		T76	120		T81	545
alert_integrity_fail	alert[0x1f]	12634	1			T46	102		T81	54		T78	17
alert_integrity_fail	alert[0x20]	3929	1			T46	68		T29	15		T78	37
alert_integrity_fail	alert[0x21]	3501	1			T46	12		T29	687		T78	87
alert_integrity_fail	alert[0x22]	7491	1			T1	6		T46	11		T81	48
alert_integrity_fail	alert[0x23]	10391	1			T45	24		T46	79		T81	87
alert_integrity_fail	alert[0x24]	8757	1			T1	22		T22	4		T23	55
alert_integrity_fail	alert[0x25]	6798	1			T29	121		T78	171		T32	45
alert_integrity_fail	alert[0x26]	4690	1			T76	444		T81	418		T87	1
alert_integrity_fail	alert[0x27]	5811	1			T46	7		T76	493		T81	7
alert_integrity_fail	alert[0x28]	4068	1			T1	42		T45	2		T76	2
alert_integrity_fail	alert[0x29]	9187	1			T1	3		T76	19		T81	13
alert_integrity_fail	alert[0x2a]	9988	1			T1	5		T46	77		T76	335
alert_integrity_fail	alert[0x2b]	12074	1			T46	43		T81	34		T29	75
alert_integrity_fail	alert[0x2c]	3207	1			T46	75		T76	29		T85	1
alert_integrity_fail	alert[0x2d]	9886	1			T1	7		T46	36		T78	14
alert_integrity_fail	alert[0x2e]	6991	1			T1	78		T46	342		T23	1
alert_integrity_fail	alert[0x2f]	6793	1			T46	59		T81	21		T86	780
alert_integrity_fail	alert[0x30]	3611	1			T1	70		T46	183		T78	21
alert_integrity_fail	alert[0x31]	7973	1			T16	66		T46	573		T81	575
alert_integrity_fail	alert[0x32]	4020	1			T46	9		T78	1		T73	1
alert_integrity_fail	alert[0x33]	15363	1			T1	28		T81	55		T78	229
alert_integrity_fail	alert[0x34]	11620	1			T81	360		T31	2		T85	1
alert_integrity_fail	alert[0x35]	4813	1			T46	57		T81	362		T29	37
alert_integrity_fail	alert[0x36]	9952	1			T46	131		T76	546		T32	189
alert_integrity_fail	alert[0x37]	6433	1			T46	324		T81	2298		T29	68
alert_integrity_fail	alert[0x38]	5609	1			T1	96		T29	357		T86	176
alert_integrity_fail	alert[0x39]	6287	1			T76	26		T29	25		T78	1300
alert_integrity_fail	alert[0x3a]	10848	1			T46	15		T76	1158		T29	90
alert_integrity_fail	alert[0x3b]	9330	1			T1	1		T46	309		T76	3806
alert_integrity_fail	alert[0x3c]	7927	1			T29	987		T32	1540		T86	95
alert_integrity_fail	alert[0x3d]	6310	1			T46	335		T81	419		T29	13
alert_integrity_fail	alert[0x3e]	7838	1			T1	19		T29	74		T78	21
alert_integrity_fail	alert[0x3f]	5533	1			T16	9		T81	88		T29	51
alert_integrity_fail	alert[0x40]	5574	1			T1	356		T46	47		T76	120
alert_ping_fail	alert[0x0]	9	1			T5	1		T6	1		T304	1
alert_ping_fail	alert[0x1]	9	1			T110	2		T304	1		T305	1
alert_ping_fail	alert[0x2]	10	1			T108	1		T306	1		T307	2
alert_ping_fail	alert[0x3]	10	1			T7	1		T110	1		T308	1
alert_ping_fail	alert[0x4]	13	1			T108	1		T37	1		T304	1
alert_ping_fail	alert[0x5]	9	1			T6	1		T304	1		T309	1
alert_ping_fail	alert[0x6]	14	1			T66	1		T300	1		T305	1
alert_ping_fail	alert[0x7]	10	1			T5	1		T310	1		T311	1
alert_ping_fail	alert[0x8]	10	1			T5	1		T108	1		T234	1
alert_ping_fail	alert[0x9]	13	1			T5	1		T110	2		T99	1
alert_ping_fail	alert[0xa]	13	1			T97	1		T66	1		T312	1
alert_ping_fail	alert[0xb]	9	1			T228	1		T66	1		T304	1
alert_ping_fail	alert[0xc]	15	1			T6	3		T97	1		T66	1
alert_ping_fail	alert[0xd]	5	1			T7	1		T313	1		T307	1
alert_ping_fail	alert[0xe]	12	1			T7	2		T228	1		T108	1
alert_ping_fail	alert[0xf]	10	1			T7	1		T37	1		T312	1
alert_ping_fail	alert[0x10]	9	1			T7	1		T235	1		T97	1
alert_ping_fail	alert[0x11]	13	1			T7	1		T37	1		T313	1
alert_ping_fail	alert[0x12]	10	1			T7	1		T228	1		T97	2
alert_ping_fail	alert[0x13]	17	1			T5	1		T308	1		T305	1
alert_ping_fail	alert[0x14]	9	1			T99	1		T309	1		T314	1
alert_ping_fail	alert[0x15]	7	1			T228	1		T99	1		T315	1
alert_ping_fail	alert[0x16]	14	1			T5	1		T97	1		T299	1
alert_ping_fail	alert[0x17]	11	1			T304	1		T309	1		T316	1
alert_ping_fail	alert[0x18]	9	1			T6	1		T97	1		T66	1
alert_ping_fail	alert[0x19]	8	1			T228	1		T317	1		T315	1
alert_ping_fail	alert[0x1a]	5	1			T318	1		T319	1		T285	1
alert_ping_fail	alert[0x1b]	12	1			T6	1		T7	3		T97	1
alert_ping_fail	alert[0x1c]	13	1			T235	1		T66	1		T317	1
alert_ping_fail	alert[0x1d]	9	1			T5	1		T235	1		T305	1
alert_ping_fail	alert[0x1e]	8	1			T108	1		T317	1		T320	1
alert_ping_fail	alert[0x1f]	13	1			T7	1		T66	2		T299	1
alert_ping_fail	alert[0x20]	16	1			T5	1		T6	1		T97	1
alert_ping_fail	alert[0x21]	11	1			T5	1		T7	1		T110	1
alert_ping_fail	alert[0x22]	18	1			T5	1		T7	1		T110	1
alert_ping_fail	alert[0x23]	11	1			T5	1		T110	1		T99	1
alert_ping_fail	alert[0x24]	4	1			T99	1		T66	1		T315	1
alert_ping_fail	alert[0x25]	6	1			T6	1		T108	1		T317	1
alert_ping_fail	alert[0x26]	13	1			T7	1		T110	1		T97	2
alert_ping_fail	alert[0x27]	10	1			T7	2		T317	1		T309	1
alert_ping_fail	alert[0x28]	13	1			T3	1		T235	1		T108	1
alert_ping_fail	alert[0x29]	12	1			T108	2		T66	1		T315	1
alert_ping_fail	alert[0x2a]	19	1			T5	1		T7	1		T108	2
alert_ping_fail	alert[0x2b]	17	1			T5	1		T66	1		T299	1
alert_ping_fail	alert[0x2c]	14	1			T97	1		T321	1		T288	3
alert_ping_fail	alert[0x2d]	13	1			T66	1		T317	1		T313	1
alert_ping_fail	alert[0x2e]	9	1			T6	1		T7	1		T228	1
alert_ping_fail	alert[0x2f]	5	1			T6	1		T304	1		T315	1
alert_ping_fail	alert[0x30]	11	1			T99	1		T66	1		T315	1
alert_ping_fail	alert[0x31]	9	1			T317	1		T315	1		T320	1
alert_ping_fail	alert[0x32]	7	1			T110	1		T66	1		T307	1
alert_ping_fail	alert[0x33]	6	1			T306	1		T318	1		T322	2
alert_ping_fail	alert[0x34]	2	1			T97	1		T316	1		-	-
alert_ping_fail	alert[0x35]	9	1			T97	1		T312	1		T309	1
alert_ping_fail	alert[0x36]	10	1			T309	1		T316	1		T323	1
alert_ping_fail	alert[0x37]	12	1			T6	1		T228	1		T97	1
alert_ping_fail	alert[0x38]	11	1			T6	1		T304	1		T312	2
alert_ping_fail	alert[0x39]	4	1			T108	1		T317	1		T306	1
alert_ping_fail	alert[0x3a]	14	1			T5	1		T108	1		T97	1
alert_ping_fail	alert[0x3b]	15	1			T6	1		T66	1		T308	2
alert_ping_fail	alert[0x3c]	7	1			T235	1		T318	1		T324	2
alert_ping_fail	alert[0x3d]	8	1			T108	1		T315	1		T309	1
alert_ping_fail	alert[0x3e]	13	1			T5	1		T6	1		T312	1
alert_ping_fail	alert[0x3f]	2	1			T66	1		T325	1		-	-
alert_ping_fail	alert[0x40]	1	1			T316	1		-	-		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	148932	1			T1	28		T16	76		T45	16
alert_integrity_fail	class_i[0x1]	89633	1			T1	3		T76	74		T25	26
alert_integrity_fail	class_i[0x2]	104880	1			T1	1582		T45	18		T46	5
alert_integrity_fail	class_i[0x3]	163262	1			T1	1		T45	8		T46	4033
alert_ping_fail	class_i[0x0]	141	1			T5	1		T235	3		T108	2
alert_ping_fail	class_i[0x1]	135	1			T6	1		T7	1		T235	1
alert_ping_fail	class_i[0x2]	225	1			T3	1		T5	14		T6	14
alert_ping_fail	class_i[0x3]	169	1			T7	18		T235	1		T228	2