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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.74 100.00 100.00 100.00 99.38 99.36


Total test records in report: 833
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T769 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2528959363 May 09 03:05:42 PM PDT 24 May 09 03:09:12 PM PDT 24 5826438710 ps
T770 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.614941878 May 09 03:08:40 PM PDT 24 May 09 03:08:44 PM PDT 24 12710209 ps
T771 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.836252225 May 09 03:06:50 PM PDT 24 May 09 03:06:59 PM PDT 24 192865509 ps
T772 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1435084735 May 09 03:07:44 PM PDT 24 May 09 03:07:56 PM PDT 24 672544134 ps
T162 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2996311028 May 09 03:08:32 PM PDT 24 May 09 03:16:36 PM PDT 24 28882173060 ps
T157 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3278327340 May 09 03:07:21 PM PDT 24 May 09 03:10:38 PM PDT 24 1678440075 ps
T773 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1994194163 May 09 03:06:40 PM PDT 24 May 09 03:06:46 PM PDT 24 136079500 ps
T774 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3918898006 May 09 03:07:32 PM PDT 24 May 09 03:07:38 PM PDT 24 51674254 ps
T775 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.201516830 May 09 03:08:50 PM PDT 24 May 09 03:08:52 PM PDT 24 13507855 ps
T776 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1403096416 May 09 03:08:31 PM PDT 24 May 09 03:08:36 PM PDT 24 8198532 ps
T777 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2046066451 May 09 03:06:08 PM PDT 24 May 09 03:06:32 PM PDT 24 277164761 ps
T778 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3558733653 May 09 03:08:17 PM PDT 24 May 09 03:08:47 PM PDT 24 556352182 ps
T779 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3777438729 May 09 03:07:52 PM PDT 24 May 09 03:08:03 PM PDT 24 798464391 ps
T780 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2301172366 May 09 03:07:21 PM PDT 24 May 09 03:07:34 PM PDT 24 156829480 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2108676477 May 09 03:06:30 PM PDT 24 May 09 03:06:32 PM PDT 24 9327569 ps
T177 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1418491739 May 09 03:07:54 PM PDT 24 May 09 03:07:59 PM PDT 24 94526222 ps
T161 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1769061803 May 09 03:08:30 PM PDT 24 May 09 03:13:25 PM PDT 24 4305883325 ps
T782 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1827253068 May 09 03:07:54 PM PDT 24 May 09 03:08:04 PM PDT 24 104816944 ps
T783 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2249939502 May 09 03:08:04 PM PDT 24 May 09 03:08:15 PM PDT 24 415109361 ps
T166 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1663183087 May 09 03:05:42 PM PDT 24 May 09 03:09:01 PM PDT 24 2978019152 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3357807366 May 09 03:08:02 PM PDT 24 May 09 03:08:06 PM PDT 24 58343884 ps
T361 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1371747897 May 09 03:07:43 PM PDT 24 May 09 03:12:49 PM PDT 24 2299880151 ps
T785 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1058752130 May 09 03:08:49 PM PDT 24 May 09 03:08:52 PM PDT 24 13651709 ps
T786 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2688525128 May 09 03:06:18 PM PDT 24 May 09 03:10:02 PM PDT 24 2980451343 ps
T147 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2050279803 May 09 03:06:29 PM PDT 24 May 09 03:09:19 PM PDT 24 2614806512 ps
T787 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1848421267 May 09 03:07:12 PM PDT 24 May 09 03:07:22 PM PDT 24 113779171 ps
T175 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4204392310 May 09 03:08:31 PM PDT 24 May 09 03:09:44 PM PDT 24 3683188151 ps
T788 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3240779767 May 09 03:08:22 PM PDT 24 May 09 03:08:25 PM PDT 24 8973702 ps
T789 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4155457855 May 09 03:08:39 PM PDT 24 May 09 03:08:43 PM PDT 24 12165024 ps
T790 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1619429611 May 09 03:08:30 PM PDT 24 May 09 03:08:35 PM PDT 24 17569715 ps
T791 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.176818652 May 09 03:08:18 PM PDT 24 May 09 03:08:26 PM PDT 24 124426769 ps
T792 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1742449471 May 09 03:08:32 PM PDT 24 May 09 03:08:37 PM PDT 24 10890227 ps
T793 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2790130144 May 09 03:07:23 PM PDT 24 May 09 03:07:30 PM PDT 24 177671757 ps
T794 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2799551312 May 09 03:08:03 PM PDT 24 May 09 03:08:06 PM PDT 24 27935635 ps
T795 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2631820933 May 09 03:08:22 PM PDT 24 May 09 03:08:46 PM PDT 24 327987581 ps
T796 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1039725550 May 09 03:07:32 PM PDT 24 May 09 03:08:25 PM PDT 24 2664080236 ps
T185 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.561632623 May 09 03:05:55 PM PDT 24 May 09 03:06:00 PM PDT 24 38992512 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3221655303 May 09 03:05:55 PM PDT 24 May 09 03:06:24 PM PDT 24 183507919 ps
T798 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1448170302 May 09 03:07:51 PM PDT 24 May 09 03:13:02 PM PDT 24 7853748965 ps
T799 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1561440930 May 09 03:08:18 PM PDT 24 May 09 03:08:32 PM PDT 24 85989478 ps
T800 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1692977331 May 09 03:08:17 PM PDT 24 May 09 03:08:30 PM PDT 24 213754295 ps
T801 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2135082659 May 09 03:08:34 PM PDT 24 May 09 03:08:39 PM PDT 24 10116847 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.346689876 May 09 03:06:10 PM PDT 24 May 09 03:06:18 PM PDT 24 56708957 ps
T803 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1931150518 May 09 03:08:35 PM PDT 24 May 09 03:08:40 PM PDT 24 19503096 ps
T148 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1874782113 May 09 03:07:14 PM PDT 24 May 09 03:12:48 PM PDT 24 4305070153 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1546456458 May 09 03:06:08 PM PDT 24 May 09 03:08:02 PM PDT 24 6742536173 ps
T805 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1075132420 May 09 03:08:32 PM PDT 24 May 09 03:08:42 PM PDT 24 114229413 ps
T806 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.744616788 May 09 03:08:41 PM PDT 24 May 09 03:08:44 PM PDT 24 6376044 ps
T807 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3514855601 May 09 03:07:12 PM PDT 24 May 09 03:07:38 PM PDT 24 661737165 ps
T808 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.494215731 May 09 03:08:31 PM PDT 24 May 09 03:08:41 PM PDT 24 68415764 ps
T168 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3266829218 May 09 03:07:13 PM PDT 24 May 09 03:17:31 PM PDT 24 16497922193 ps
T809 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2281655211 May 09 03:08:31 PM PDT 24 May 09 03:08:37 PM PDT 24 15067401 ps
T810 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2597306658 May 09 03:07:13 PM PDT 24 May 09 03:07:20 PM PDT 24 38281676 ps
T811 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4062990331 May 09 03:06:28 PM PDT 24 May 09 03:06:34 PM PDT 24 57341088 ps
T812 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2952366321 May 09 03:07:22 PM PDT 24 May 09 03:16:21 PM PDT 24 60518726628 ps
T813 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.894105564 May 09 03:05:54 PM PDT 24 May 09 03:06:25 PM PDT 24 431443438 ps
T814 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1247693987 May 09 03:07:35 PM PDT 24 May 09 03:07:38 PM PDT 24 8530374 ps
T186 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2652696454 May 09 03:06:29 PM PDT 24 May 09 03:07:09 PM PDT 24 575225369 ps
T815 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3537340446 May 09 03:08:49 PM PDT 24 May 09 03:08:52 PM PDT 24 9581116 ps
T167 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3119432167 May 09 03:07:01 PM PDT 24 May 09 03:19:13 PM PDT 24 4337401546 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4093883018 May 09 03:06:29 PM PDT 24 May 09 03:06:52 PM PDT 24 554930383 ps
T817 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4257641876 May 09 03:07:00 PM PDT 24 May 09 03:07:19 PM PDT 24 250999797 ps
T818 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.70673852 May 09 03:07:23 PM PDT 24 May 09 03:07:32 PM PDT 24 33298858 ps
T819 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3997483872 May 09 03:08:15 PM PDT 24 May 09 03:08:27 PM PDT 24 130387204 ps
T820 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.997730310 May 09 03:08:49 PM PDT 24 May 09 03:08:52 PM PDT 24 8797546 ps
T821 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.248411047 May 09 03:07:01 PM PDT 24 May 09 03:07:13 PM PDT 24 320839902 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1825801115 May 09 03:08:17 PM PDT 24 May 09 03:25:19 PM PDT 24 12497606707 ps
T822 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.802040390 May 09 03:08:38 PM PDT 24 May 09 03:08:43 PM PDT 24 9420659 ps
T823 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2564740961 May 09 03:08:16 PM PDT 24 May 09 03:08:36 PM PDT 24 934826985 ps
T184 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2342954452 May 09 03:07:44 PM PDT 24 May 09 03:07:50 PM PDT 24 54075002 ps
T824 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2360201471 May 09 03:06:19 PM PDT 24 May 09 03:06:26 PM PDT 24 103790485 ps
T825 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3195201147 May 09 03:06:59 PM PDT 24 May 09 03:07:09 PM PDT 24 410769680 ps
T826 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.318760242 May 09 03:08:04 PM PDT 24 May 09 03:08:15 PM PDT 24 57023822 ps
T827 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.514761119 May 09 03:08:50 PM PDT 24 May 09 03:08:53 PM PDT 24 8201530 ps
T828 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1374026969 May 09 03:06:39 PM PDT 24 May 09 03:10:51 PM PDT 24 13604144023 ps
T829 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3055788139 May 09 03:06:29 PM PDT 24 May 09 03:07:08 PM PDT 24 8758245460 ps
T189 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4017526281 May 09 03:08:17 PM PDT 24 May 09 03:09:49 PM PDT 24 1240422402 ps
T830 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1116234414 May 09 03:08:37 PM PDT 24 May 09 03:08:41 PM PDT 24 35667679 ps
T831 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2985065869 May 09 03:07:33 PM PDT 24 May 09 03:07:45 PM PDT 24 422009408 ps
T183 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4127262376 May 09 03:07:12 PM PDT 24 May 09 03:07:17 PM PDT 24 156067861 ps
T832 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2779250909 May 09 03:05:44 PM PDT 24 May 09 03:05:48 PM PDT 24 11628913 ps
T362 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3440860962 May 09 03:08:31 PM PDT 24 May 09 03:14:33 PM PDT 24 2072102676 ps
T833 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.347188232 May 09 03:07:52 PM PDT 24 May 09 03:07:56 PM PDT 24 10987471 ps

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2575489276
Short name T1
Test name
Test status
Simulation time 36734185015 ps
CPU time 1746.89 seconds
Started May 09 03:18:34 PM PDT 24
Finished May 09 03:47:42 PM PDT 24
Peak memory 289764 kb
Host smart-b4e5758b-3970-48f9-8ae3-564dfa20c7d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575489276 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2575489276
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4176893678
Short name T8
Test name
Test status
Simulation time 893067800 ps
CPU time 24.45 seconds
Started May 09 03:13:41 PM PDT 24
Finished May 09 03:14:08 PM PDT 24
Peak memory 274480 kb
Host smart-d07d31ce-5174-4518-a5a5-61573c98e223
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4176893678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4176893678
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.557195924
Short name T16
Test name
Test status
Simulation time 114678932544 ps
CPU time 2019.43 seconds
Started May 09 03:16:12 PM PDT 24
Finished May 09 03:49:53 PM PDT 24
Peak memory 281632 kb
Host smart-22da36dc-2f70-4adc-ad66-fa1131dd82b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557195924 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.557195924
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.551110187
Short name T141
Test name
Test status
Simulation time 68311501285 ps
CPU time 1126.81 seconds
Started May 09 03:07:51 PM PDT 24
Finished May 09 03:26:40 PM PDT 24
Peak memory 265336 kb
Host smart-7c42c218-4e31-45dc-a453-1c7386aeaa09
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551110187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.551110187
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.4149722844
Short name T49
Test name
Test status
Simulation time 51919052393 ps
CPU time 6061.01 seconds
Started May 09 03:14:17 PM PDT 24
Finished May 09 04:55:20 PM PDT 24
Peak memory 337956 kb
Host smart-cd2235b3-e6f2-4fa8-bf43-a6f19315de36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149722844 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.4149722844
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1998476311
Short name T12
Test name
Test status
Simulation time 1064346837 ps
CPU time 9.99 seconds
Started May 09 03:14:56 PM PDT 24
Finished May 09 03:15:08 PM PDT 24
Peak memory 252404 kb
Host smart-74c8c8b3-bf1e-4fe7-979a-019ff4e70216
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1998476311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1998476311
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.766176358
Short name T171
Test name
Test status
Simulation time 158380972 ps
CPU time 22.52 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:08:43 PM PDT 24
Peak memory 248632 kb
Host smart-75c490b3-6c0b-44e2-8172-cbde0a19dad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=766176358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.766176358
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3680007156
Short name T31
Test name
Test status
Simulation time 205969572946 ps
CPU time 1477.36 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:39:19 PM PDT 24
Peak memory 289160 kb
Host smart-d97f24d3-5697-4da2-843a-63fcd77bc8f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680007156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3680007156
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3241429040
Short name T2
Test name
Test status
Simulation time 14326041744 ps
CPU time 1465.43 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:39:31 PM PDT 24
Peak memory 289024 kb
Host smart-8558a927-c4bd-43ba-b27c-84648d89e297
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241429040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3241429040
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2897725274
Short name T156
Test name
Test status
Simulation time 19539767048 ps
CPU time 337.14 seconds
Started May 09 03:07:43 PM PDT 24
Finished May 09 03:13:21 PM PDT 24
Peak memory 272976 kb
Host smart-130f0d61-89b0-485e-9a8d-461897a68ac0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2897725274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2897725274
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3978707562
Short name T14
Test name
Test status
Simulation time 42456204907 ps
CPU time 1618.99 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:41:41 PM PDT 24
Peak memory 288992 kb
Host smart-fc1581a6-6cb8-432f-a880-80cbd817afd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978707562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3978707562
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2124700400
Short name T107
Test name
Test status
Simulation time 48162822094 ps
CPU time 2858.98 seconds
Started May 09 03:17:57 PM PDT 24
Finished May 09 04:05:39 PM PDT 24
Peak memory 289728 kb
Host smart-072082d5-c316-45c6-870d-0ce57549c61a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124700400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2124700400
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1027127781
Short name T32
Test name
Test status
Simulation time 240415020951 ps
CPU time 1646.04 seconds
Started May 09 03:15:23 PM PDT 24
Finished May 09 03:42:51 PM PDT 24
Peak memory 289588 kb
Host smart-f59cb212-857b-4fcd-8e5d-ee86fca7c07f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027127781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1027127781
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2635274157
Short name T133
Test name
Test status
Simulation time 2139348937 ps
CPU time 208.13 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:09:38 PM PDT 24
Peak memory 270484 kb
Host smart-485018da-3da0-4b76-8847-9fca849d0776
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2635274157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2635274157
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1643475350
Short name T97
Test name
Test status
Simulation time 30752523280 ps
CPU time 645.82 seconds
Started May 09 03:15:57 PM PDT 24
Finished May 09 03:26:44 PM PDT 24
Peak memory 248184 kb
Host smart-872856eb-c7ee-4d5f-b13c-511ee9a10d1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643475350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1643475350
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.966339465
Short name T145
Test name
Test status
Simulation time 12289651711 ps
CPU time 942.65 seconds
Started May 09 03:05:42 PM PDT 24
Finished May 09 03:21:27 PM PDT 24
Peak memory 265460 kb
Host smart-185d66be-d189-4edc-bb46-b553573da8c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966339465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.966339465
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.600831371
Short name T299
Test name
Test status
Simulation time 81889716541 ps
CPU time 2204.25 seconds
Started May 09 03:15:47 PM PDT 24
Finished May 09 03:52:33 PM PDT 24
Peak memory 273116 kb
Host smart-b341ac82-18fb-4deb-808e-33e8d8d260fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600831371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.600831371
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.293405635
Short name T354
Test name
Test status
Simulation time 12469866 ps
CPU time 1.57 seconds
Started May 09 03:08:03 PM PDT 24
Finished May 09 03:08:06 PM PDT 24
Peak memory 236960 kb
Host smart-b96f4cd7-c3fa-4bf5-a9dc-d06cc288d3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=293405635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.293405635
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2122683963
Short name T139
Test name
Test status
Simulation time 24800590916 ps
CPU time 637.93 seconds
Started May 09 03:08:15 PM PDT 24
Finished May 09 03:18:56 PM PDT 24
Peak memory 265436 kb
Host smart-385d2d01-915c-4766-b206-5d079c77fcf7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122683963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2122683963
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1125280298
Short name T333
Test name
Test status
Simulation time 291403359817 ps
CPU time 3047.51 seconds
Started May 09 03:17:26 PM PDT 24
Finished May 09 04:08:15 PM PDT 24
Peak memory 289088 kb
Host smart-d75b96ba-5030-4e07-97e6-0a00ccb4acbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125280298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1125280298
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2431738619
Short name T76
Test name
Test status
Simulation time 22753746363 ps
CPU time 1872.25 seconds
Started May 09 03:21:18 PM PDT 24
Finished May 09 03:52:31 PM PDT 24
Peak memory 298736 kb
Host smart-7355b974-5716-45c7-8497-36bcfe6833c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431738619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2431738619
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2553579646
Short name T160
Test name
Test status
Simulation time 4618317855 ps
CPU time 355.21 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:13:09 PM PDT 24
Peak memory 265432 kb
Host smart-e477ca83-674d-4899-a130-a2db02c55e5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2553579646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2553579646
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3443977108
Short name T66
Test name
Test status
Simulation time 26117915143 ps
CPU time 524.13 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:23:26 PM PDT 24
Peak memory 247880 kb
Host smart-e6ce1c10-83cd-43f7-8c04-4c0ff1150a9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443977108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3443977108
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3938622338
Short name T67
Test name
Test status
Simulation time 190193899644 ps
CPU time 3066.18 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 04:05:33 PM PDT 24
Peak memory 287764 kb
Host smart-25ee587d-dbf3-47eb-b84e-0d3c3b188157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938622338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3938622338
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.269956413
Short name T142
Test name
Test status
Simulation time 28608377311 ps
CPU time 1116.76 seconds
Started May 09 03:06:07 PM PDT 24
Finished May 09 03:24:45 PM PDT 24
Peak memory 265484 kb
Host smart-40e0f4e5-f93f-40e8-b2ee-c7e41018a689
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269956413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.269956413
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3183833407
Short name T5
Test name
Test status
Simulation time 43241554853 ps
CPU time 456.4 seconds
Started May 09 03:15:24 PM PDT 24
Finished May 09 03:23:02 PM PDT 24
Peak memory 255032 kb
Host smart-d310b113-9e5d-4ceb-bf89-516b3f2be206
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183833407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3183833407
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2000092594
Short name T77
Test name
Test status
Simulation time 160888680997 ps
CPU time 2676.54 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 04:03:12 PM PDT 24
Peak memory 289828 kb
Host smart-0803b572-7ddb-4977-82f3-35a3bd364609
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000092594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2000092594
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.185283288
Short name T102
Test name
Test status
Simulation time 58549347404 ps
CPU time 6519.36 seconds
Started May 09 03:15:03 PM PDT 24
Finished May 09 05:03:46 PM PDT 24
Peak memory 351064 kb
Host smart-b9e66952-06e0-47ec-bef9-d34daa02adf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185283288 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.185283288
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3983764152
Short name T323
Test name
Test status
Simulation time 9056368814 ps
CPU time 360.8 seconds
Started May 09 03:13:42 PM PDT 24
Finished May 09 03:19:45 PM PDT 24
Peak memory 248184 kb
Host smart-6bedea67-84de-490f-a23e-d213e6ecdc92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983764152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3983764152
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2198411766
Short name T334
Test name
Test status
Simulation time 137395258816 ps
CPU time 2105.02 seconds
Started May 09 03:20:57 PM PDT 24
Finished May 09 03:56:03 PM PDT 24
Peak memory 283000 kb
Host smart-095c5752-e7a2-47e3-9e29-65f249650142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198411766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2198411766
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.351835211
Short name T146
Test name
Test status
Simulation time 17267666625 ps
CPU time 316.95 seconds
Started May 09 03:07:33 PM PDT 24
Finished May 09 03:12:52 PM PDT 24
Peak memory 265460 kb
Host smart-4f3ec3b1-1bd5-4805-ae89-418f84a5803c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=351835211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.351835211
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4029322132
Short name T59
Test name
Test status
Simulation time 60564884878 ps
CPU time 2196.63 seconds
Started May 09 03:17:15 PM PDT 24
Finished May 09 03:53:53 PM PDT 24
Peak memory 297932 kb
Host smart-c4ef0e73-a55f-467e-9836-7d6923a5f1d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029322132 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4029322132
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2963706489
Short name T304
Test name
Test status
Simulation time 38076480432 ps
CPU time 401.79 seconds
Started May 09 03:15:45 PM PDT 24
Finished May 09 03:22:28 PM PDT 24
Peak memory 248052 kb
Host smart-5446959b-179e-49ee-967b-2538d91c9329
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963706489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2963706489
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1772011858
Short name T138
Test name
Test status
Simulation time 3183804932 ps
CPU time 192.78 seconds
Started May 09 03:05:54 PM PDT 24
Finished May 09 03:09:07 PM PDT 24
Peak memory 265444 kb
Host smart-c155c18f-fa11-419d-9bc1-ca8266c2691c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1772011858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1772011858
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.4061368420
Short name T353
Test name
Test status
Simulation time 28878030 ps
CPU time 1.42 seconds
Started May 09 03:07:45 PM PDT 24
Finished May 09 03:07:47 PM PDT 24
Peak memory 236976 kb
Host smart-ff0941a0-3af0-4f69-b038-5064b076fd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4061368420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.4061368420
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.360794866
Short name T91
Test name
Test status
Simulation time 115071726127 ps
CPU time 2375.62 seconds
Started May 09 03:13:40 PM PDT 24
Finished May 09 03:53:17 PM PDT 24
Peak memory 289368 kb
Host smart-3a06b992-2e42-424d-aab1-4cc6f7e253b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360794866 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.360794866
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3098395937
Short name T121
Test name
Test status
Simulation time 213823115755 ps
CPU time 4370.71 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 04:31:50 PM PDT 24
Peak memory 338416 kb
Host smart-58f58c24-e60a-4d18-b396-a28350815cd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098395937 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3098395937
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.504580112
Short name T318
Test name
Test status
Simulation time 9329410302 ps
CPU time 384.46 seconds
Started May 09 03:21:15 PM PDT 24
Finished May 09 03:27:40 PM PDT 24
Peak memory 247144 kb
Host smart-46ad55e7-6bc9-4505-b372-d2ad5c4aa826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504580112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.504580112
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3087253957
Short name T358
Test name
Test status
Simulation time 63191030 ps
CPU time 5.44 seconds
Started May 09 03:07:35 PM PDT 24
Finished May 09 03:07:42 PM PDT 24
Peak memory 241740 kb
Host smart-73c29aea-6dc7-426c-b132-1348001c5dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087253957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3087253957
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3484787636
Short name T135
Test name
Test status
Simulation time 36641996358 ps
CPU time 527.36 seconds
Started May 09 03:08:02 PM PDT 24
Finished May 09 03:16:51 PM PDT 24
Peak memory 268960 kb
Host smart-04e0d68a-3551-428d-8524-c7fbb4beadb4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484787636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3484787636
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3514021570
Short name T329
Test name
Test status
Simulation time 47149999876 ps
CPU time 2867.44 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 04:01:33 PM PDT 24
Peak memory 289652 kb
Host smart-ecc1bb82-5ad5-4829-9d1f-ba202368a1b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514021570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3514021570
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1825801115
Short name T165
Test name
Test status
Simulation time 12497606707 ps
CPU time 1019.17 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:25:19 PM PDT 24
Peak memory 265388 kb
Host smart-baf06329-d958-4bb2-bcc4-ead1f88de8d8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825801115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1825801115
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3305613249
Short name T87
Test name
Test status
Simulation time 1030473064752 ps
CPU time 8837.52 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 05:42:00 PM PDT 24
Peak memory 371652 kb
Host smart-3af8aba9-11a8-4e6b-8400-6939d7b03c49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305613249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3305613249
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.456385253
Short name T493
Test name
Test status
Simulation time 37970191853 ps
CPU time 784.28 seconds
Started May 09 03:15:12 PM PDT 24
Finished May 09 03:28:18 PM PDT 24
Peak memory 266240 kb
Host smart-73b055a2-2cba-4b58-a61d-14fae6188b9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456385253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.456385253
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2106427777
Short name T55
Test name
Test status
Simulation time 1210199120 ps
CPU time 39.09 seconds
Started May 09 03:17:26 PM PDT 24
Finished May 09 03:18:06 PM PDT 24
Peak memory 247588 kb
Host smart-211ce766-6fb0-466c-bf82-a416218e4c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064
27777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2106427777
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.849861606
Short name T7
Test name
Test status
Simulation time 51925747268 ps
CPU time 545.43 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:34:20 PM PDT 24
Peak memory 248132 kb
Host smart-c7c0a2c5-55ed-454a-ad70-2ca2f967582b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849861606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.849861606
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.412600918
Short name T344
Test name
Test status
Simulation time 118498405034 ps
CPU time 2121.21 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 03:49:39 PM PDT 24
Peak memory 272760 kb
Host smart-674a8406-06a9-4d86-ad83-b907cb60e9d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412600918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.412600918
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.316038016
Short name T181
Test name
Test status
Simulation time 222128685 ps
CPU time 2.59 seconds
Started May 09 03:05:43 PM PDT 24
Finished May 09 03:05:48 PM PDT 24
Peak memory 237120 kb
Host smart-1dadb165-e3a6-448e-882c-d85628c71353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=316038016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.316038016
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2700804135
Short name T211
Test name
Test status
Simulation time 36621077 ps
CPU time 3.68 seconds
Started May 09 03:13:41 PM PDT 24
Finished May 09 03:13:47 PM PDT 24
Peak memory 248936 kb
Host smart-5a66d7dc-dc3c-4efc-9037-98ee36b36518
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2700804135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2700804135
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1855523914
Short name T221
Test name
Test status
Simulation time 14140317 ps
CPU time 2.22 seconds
Started May 09 03:13:44 PM PDT 24
Finished May 09 03:13:48 PM PDT 24
Peak memory 248916 kb
Host smart-e31dac75-14f3-497f-8a4e-6b9b8af761af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1855523914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1855523914
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2766134557
Short name T225
Test name
Test status
Simulation time 17717129 ps
CPU time 2.73 seconds
Started May 09 03:14:27 PM PDT 24
Finished May 09 03:14:32 PM PDT 24
Peak memory 248984 kb
Host smart-a9acdc05-466f-4755-b510-101d512cef82
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2766134557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2766134557
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3753456254
Short name T215
Test name
Test status
Simulation time 122513130 ps
CPU time 2.47 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:14:47 PM PDT 24
Peak memory 248956 kb
Host smart-2b64f545-3a05-4bb7-8e73-0b315358f09b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3753456254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3753456254
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2032278305
Short name T265
Test name
Test status
Simulation time 89191620 ps
CPU time 7 seconds
Started May 09 03:14:56 PM PDT 24
Finished May 09 03:15:06 PM PDT 24
Peak memory 250740 kb
Host smart-ef93cc51-e8c9-4647-aae3-043aa3490100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20322
78305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2032278305
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3532316833
Short name T626
Test name
Test status
Simulation time 34532556183 ps
CPU time 2095.46 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:50:00 PM PDT 24
Peak memory 287300 kb
Host smart-fbe7a863-d449-48ae-8533-30c717b8acc4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532316833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3532316833
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3264756673
Short name T237
Test name
Test status
Simulation time 54127097799 ps
CPU time 2762.22 seconds
Started May 09 03:15:11 PM PDT 24
Finished May 09 04:01:15 PM PDT 24
Peak memory 289864 kb
Host smart-8653da68-243e-48bc-89c6-fcb263945d70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264756673 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3264756673
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1289522885
Short name T342
Test name
Test status
Simulation time 89899996392 ps
CPU time 2451.88 seconds
Started May 09 03:15:11 PM PDT 24
Finished May 09 03:56:04 PM PDT 24
Peak memory 273428 kb
Host smart-1f3e7301-b0b7-4cf1-9fd6-a949515d9ec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289522885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1289522885
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.598706215
Short name T285
Test name
Test status
Simulation time 15881412550 ps
CPU time 317.24 seconds
Started May 09 03:15:51 PM PDT 24
Finished May 09 03:21:09 PM PDT 24
Peak memory 248204 kb
Host smart-3a78e4f1-f782-49fc-aee8-107e6d63e8bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598706215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.598706215
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.899642203
Short name T274
Test name
Test status
Simulation time 171711219589 ps
CPU time 2840.24 seconds
Started May 09 03:16:53 PM PDT 24
Finished May 09 04:04:15 PM PDT 24
Peak memory 288796 kb
Host smart-a9cf29c7-df27-443c-a498-40ed4524cb93
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899642203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.899642203
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.473000208
Short name T259
Test name
Test status
Simulation time 3648605631 ps
CPU time 202.08 seconds
Started May 09 03:24:45 PM PDT 24
Finished May 09 03:28:40 PM PDT 24
Peak memory 257004 kb
Host smart-b998c628-a092-4f70-984c-ebf6d4e13994
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473000208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.473000208
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1866803242
Short name T23
Test name
Test status
Simulation time 1047364404 ps
CPU time 29.99 seconds
Started May 09 03:14:17 PM PDT 24
Finished May 09 03:14:49 PM PDT 24
Peak memory 255516 kb
Host smart-c61301be-955b-41b1-8e09-926f2497060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18668
03242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1866803242
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1448170302
Short name T798
Test name
Test status
Simulation time 7853748965 ps
CPU time 308.76 seconds
Started May 09 03:07:51 PM PDT 24
Finished May 09 03:13:02 PM PDT 24
Peak memory 272204 kb
Host smart-554bb9c5-87a1-4609-ae94-959447e95fa9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1448170302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1448170302
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1590379634
Short name T9
Test name
Test status
Simulation time 2768974915 ps
CPU time 19.41 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:14:05 PM PDT 24
Peak memory 277628 kb
Host smart-65c438df-bcfb-4f8b-93ab-775f640d76c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1590379634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1590379634
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3819269466
Short name T164
Test name
Test status
Simulation time 8739320490 ps
CPU time 326.49 seconds
Started May 09 03:07:32 PM PDT 24
Finished May 09 03:13:00 PM PDT 24
Peak memory 265524 kb
Host smart-93e53261-78ff-4857-aa96-1eb5226249c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819269466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3819269466
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2384863874
Short name T355
Test name
Test status
Simulation time 6847197 ps
CPU time 1.56 seconds
Started May 09 03:08:16 PM PDT 24
Finished May 09 03:08:21 PM PDT 24
Peak memory 236932 kb
Host smart-62a7f633-9eaa-4eee-8a46-882f0f2158cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2384863874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2384863874
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.508797743
Short name T191
Test name
Test status
Simulation time 59974818669 ps
CPU time 1270.68 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:35:38 PM PDT 24
Peak memory 289972 kb
Host smart-3b78edec-5700-403b-bcad-9ec48597f2c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508797743 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.508797743
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3959672876
Short name T29
Test name
Test status
Simulation time 38036611783 ps
CPU time 850.09 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:28:52 PM PDT 24
Peak memory 267300 kb
Host smart-4cb46135-f670-4c54-8dc4-76200d95e696
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959672876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3959672876
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.802198017
Short name T264
Test name
Test status
Simulation time 110880683366 ps
CPU time 3606.35 seconds
Started May 09 03:15:18 PM PDT 24
Finished May 09 04:15:26 PM PDT 24
Peak memory 304040 kb
Host smart-080e0d76-7752-464d-8291-24dce64e1ca6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802198017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.802198017
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3786914940
Short name T273
Test name
Test status
Simulation time 128644025266 ps
CPU time 1714.7 seconds
Started May 09 03:13:52 PM PDT 24
Finished May 09 03:42:27 PM PDT 24
Peak memory 273400 kb
Host smart-978156c2-9232-4087-8562-e1eac5134f15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786914940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3786914940
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3188558701
Short name T296
Test name
Test status
Simulation time 86261921224 ps
CPU time 2224.15 seconds
Started May 09 03:15:12 PM PDT 24
Finished May 09 03:52:18 PM PDT 24
Peak memory 289560 kb
Host smart-427fbd7e-61e9-4412-bb2d-f4a77d0ee416
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188558701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3188558701
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3884496286
Short name T278
Test name
Test status
Simulation time 56745601259 ps
CPU time 3152.61 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 04:08:10 PM PDT 24
Peak memory 289228 kb
Host smart-1abe5a83-052b-4da4-946f-eaeea7836fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884496286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3884496286
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3146642542
Short name T108
Test name
Test status
Simulation time 20530258740 ps
CPU time 409.38 seconds
Started May 09 03:15:36 PM PDT 24
Finished May 09 03:22:28 PM PDT 24
Peak memory 247868 kb
Host smart-6fc3d11a-c2d4-4922-9325-6a32ce2c8278
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146642542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3146642542
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1500590736
Short name T48
Test name
Test status
Simulation time 896959305 ps
CPU time 20.07 seconds
Started May 09 03:15:47 PM PDT 24
Finished May 09 03:16:08 PM PDT 24
Peak memory 247460 kb
Host smart-50566ee8-d0a2-475d-8ec1-653b7aecf000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15005
90736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1500590736
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2002571192
Short name T619
Test name
Test status
Simulation time 278968652980 ps
CPU time 1732.53 seconds
Started May 09 03:16:20 PM PDT 24
Finished May 09 03:45:13 PM PDT 24
Peak memory 273396 kb
Host smart-b2250107-888d-4aad-a58e-cc4b0fd4f916
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002571192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2002571192
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.683854835
Short name T350
Test name
Test status
Simulation time 22812853477 ps
CPU time 1595.46 seconds
Started May 09 03:16:18 PM PDT 24
Finished May 09 03:42:55 PM PDT 24
Peak memory 267308 kb
Host smart-c67ab3ef-fc34-43f7-bc11-476a9ffae9e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683854835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.683854835
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3895793229
Short name T56
Test name
Test status
Simulation time 211788623208 ps
CPU time 5778.45 seconds
Started May 09 03:16:19 PM PDT 24
Finished May 09 04:52:39 PM PDT 24
Peak memory 371292 kb
Host smart-b2fc8959-7784-4569-add1-5379d6be4f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895793229 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3895793229
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.826376113
Short name T327
Test name
Test status
Simulation time 29814641777 ps
CPU time 1507.68 seconds
Started May 09 03:13:53 PM PDT 24
Finished May 09 03:39:03 PM PDT 24
Peak memory 288728 kb
Host smart-40f35130-b753-4adb-b2f8-56111164b0d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826376113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.826376113
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2109762192
Short name T262
Test name
Test status
Simulation time 40676840202 ps
CPU time 2345.93 seconds
Started May 09 03:17:25 PM PDT 24
Finished May 09 03:56:33 PM PDT 24
Peak memory 289872 kb
Host smart-fdaaf496-cf04-4d76-b0ad-67004baf2911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109762192 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2109762192
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3127033024
Short name T113
Test name
Test status
Simulation time 820098127 ps
CPU time 16.56 seconds
Started May 09 03:17:25 PM PDT 24
Finished May 09 03:17:43 PM PDT 24
Peak memory 255684 kb
Host smart-d99a49d5-e68e-433f-9da4-455fefef4ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31270
33024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3127033024
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2674056857
Short name T290
Test name
Test status
Simulation time 12602290570 ps
CPU time 1379.64 seconds
Started May 09 03:14:10 PM PDT 24
Finished May 09 03:37:11 PM PDT 24
Peak memory 288904 kb
Host smart-4d047314-68e1-4c7d-a1cf-26108833d854
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674056857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2674056857
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3892792746
Short name T316
Test name
Test status
Simulation time 47428959383 ps
CPU time 591.24 seconds
Started May 09 03:14:27 PM PDT 24
Finished May 09 03:24:21 PM PDT 24
Peak memory 247144 kb
Host smart-09ac752a-b3d4-4531-b1ac-9bac8d785e49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892792746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3892792746
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3271758139
Short name T170
Test name
Test status
Simulation time 95021109 ps
CPU time 4.27 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:06:14 PM PDT 24
Peak memory 236916 kb
Host smart-99866c59-24d5-4b52-a590-7f2d3d93010d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3271758139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3271758139
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1816539727
Short name T179
Test name
Test status
Simulation time 339596175 ps
CPU time 4.09 seconds
Started May 09 03:07:21 PM PDT 24
Finished May 09 03:07:28 PM PDT 24
Peak memory 235924 kb
Host smart-6950604e-59bf-405c-829b-5357370b03e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1816539727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1816539727
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4204392310
Short name T175
Test name
Test status
Simulation time 3683188151 ps
CPU time 69.58 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:09:44 PM PDT 24
Peak memory 239856 kb
Host smart-c9bf1094-d3d5-45dc-8b99-dcbee7a7c7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4204392310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4204392310
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1874782113
Short name T148
Test name
Test status
Simulation time 4305070153 ps
CPU time 332.76 seconds
Started May 09 03:07:14 PM PDT 24
Finished May 09 03:12:48 PM PDT 24
Peak memory 265412 kb
Host smart-f66e8101-4a92-41cd-b8b7-72b1def08311
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1874782113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1874782113
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1418491739
Short name T177
Test name
Test status
Simulation time 94526222 ps
CPU time 3.77 seconds
Started May 09 03:07:54 PM PDT 24
Finished May 09 03:07:59 PM PDT 24
Peak memory 237380 kb
Host smart-eb92c17f-ec07-4708-88be-b07bb16fd9fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1418491739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1418491739
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1030106608
Short name T180
Test name
Test status
Simulation time 241150939 ps
CPU time 9.09 seconds
Started May 09 03:08:30 PM PDT 24
Finished May 09 03:08:43 PM PDT 24
Peak memory 236928 kb
Host smart-17fdcfdd-b88a-4bde-b880-67dc9f2af5c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1030106608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1030106608
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.561632623
Short name T185
Test name
Test status
Simulation time 38992512 ps
CPU time 4.05 seconds
Started May 09 03:05:55 PM PDT 24
Finished May 09 03:06:00 PM PDT 24
Peak memory 236960 kb
Host smart-bbd0ef19-f944-4fda-a60f-9aa4f353f7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=561632623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.561632623
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2342954452
Short name T184
Test name
Test status
Simulation time 54075002 ps
CPU time 4 seconds
Started May 09 03:07:44 PM PDT 24
Finished May 09 03:07:50 PM PDT 24
Peak memory 236020 kb
Host smart-e3acb222-6705-496a-9bc5-3c123e5454af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2342954452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2342954452
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2652696454
Short name T186
Test name
Test status
Simulation time 575225369 ps
CPU time 37.94 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:07:09 PM PDT 24
Peak memory 248696 kb
Host smart-d458dce3-dee3-494b-a788-608a29bb214d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2652696454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2652696454
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1465433200
Short name T176
Test name
Test status
Simulation time 1271741466 ps
CPU time 54.99 seconds
Started May 09 03:06:50 PM PDT 24
Finished May 09 03:07:46 PM PDT 24
Peak memory 245280 kb
Host smart-eefef1d3-093e-446c-a86f-430a85471dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1465433200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1465433200
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1402894372
Short name T178
Test name
Test status
Simulation time 634935095 ps
CPU time 28.14 seconds
Started May 09 03:06:59 PM PDT 24
Finished May 09 03:07:29 PM PDT 24
Peak memory 239696 kb
Host smart-69acfa5c-12a5-433a-820c-10d163d7d141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1402894372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1402894372
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4127262376
Short name T183
Test name
Test status
Simulation time 156067861 ps
CPU time 3.86 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:17 PM PDT 24
Peak memory 235836 kb
Host smart-08ff8800-b72c-473b-828c-b7dee8572ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4127262376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4127262376
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.364396606
Short name T188
Test name
Test status
Simulation time 198001799 ps
CPU time 3.94 seconds
Started May 09 03:07:36 PM PDT 24
Finished May 09 03:07:41 PM PDT 24
Peak memory 236016 kb
Host smart-630354a7-30f3-48d8-ae6a-7c62c2aa34c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=364396606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.364396606
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.518147846
Short name T182
Test name
Test status
Simulation time 297020883 ps
CPU time 3.54 seconds
Started May 09 03:08:03 PM PDT 24
Finished May 09 03:08:08 PM PDT 24
Peak memory 238296 kb
Host smart-b62e12a6-01dd-4f29-95a5-266a8d3e4101
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=518147846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.518147846
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.644094221
Short name T26
Test name
Test status
Simulation time 215254820 ps
CPU time 20.08 seconds
Started May 09 03:14:39 PM PDT 24
Finished May 09 03:15:01 PM PDT 24
Peak memory 256008 kb
Host smart-9c13383d-1bcd-470e-9cfc-5e384fb8b0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64409
4221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.644094221
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3166392129
Short name T27
Test name
Test status
Simulation time 11012971975 ps
CPU time 1296.89 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:37:24 PM PDT 24
Peak memory 289808 kb
Host smart-2f6f02bb-8b2c-4410-ba5c-6a8c09257403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166392129 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3166392129
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.119983867
Short name T25
Test name
Test status
Simulation time 3603255413 ps
CPU time 332.94 seconds
Started May 09 03:16:11 PM PDT 24
Finished May 09 03:21:45 PM PDT 24
Peak memory 265144 kb
Host smart-981df6cf-e404-41a7-ad1f-aa70a641c191
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119983867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.119983867
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3302593016
Short name T729
Test name
Test status
Simulation time 4730909805 ps
CPU time 166.47 seconds
Started May 09 03:05:44 PM PDT 24
Finished May 09 03:08:32 PM PDT 24
Peak memory 240444 kb
Host smart-058c3b2b-7416-4e7f-be75-5f06e8e802ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3302593016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3302593016
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2528959363
Short name T769
Test name
Test status
Simulation time 5826438710 ps
CPU time 208.56 seconds
Started May 09 03:05:42 PM PDT 24
Finished May 09 03:09:12 PM PDT 24
Peak memory 236932 kb
Host smart-81b1913c-9284-47ee-8136-bc4406d11e48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2528959363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2528959363
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3626276679
Short name T172
Test name
Test status
Simulation time 22130704 ps
CPU time 3.77 seconds
Started May 09 03:05:43 PM PDT 24
Finished May 09 03:05:49 PM PDT 24
Peak memory 240456 kb
Host smart-57496a1f-a3bd-48fd-8652-46ce4df8ca15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3626276679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3626276679
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2493377263
Short name T727
Test name
Test status
Simulation time 281691029 ps
CPU time 6.52 seconds
Started May 09 03:05:55 PM PDT 24
Finished May 09 03:06:03 PM PDT 24
Peak memory 239052 kb
Host smart-239924fc-f85a-4d76-98e1-5ecf6d658237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493377263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2493377263
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.646457680
Short name T765
Test name
Test status
Simulation time 417301225 ps
CPU time 5.12 seconds
Started May 09 03:05:43 PM PDT 24
Finished May 09 03:05:50 PM PDT 24
Peak memory 235976 kb
Host smart-78942e30-d8a2-488e-b3c0-4e9a6e8edee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=646457680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.646457680
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2779250909
Short name T832
Test name
Test status
Simulation time 11628913 ps
CPU time 1.41 seconds
Started May 09 03:05:44 PM PDT 24
Finished May 09 03:05:48 PM PDT 24
Peak memory 234996 kb
Host smart-34e38474-bce5-4662-9e10-efaf106fe366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2779250909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2779250909
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3221655303
Short name T797
Test name
Test status
Simulation time 183507919 ps
CPU time 27.49 seconds
Started May 09 03:05:55 PM PDT 24
Finished May 09 03:06:24 PM PDT 24
Peak memory 245164 kb
Host smart-52317017-b029-48f7-967f-349eceeaf618
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3221655303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3221655303
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1663183087
Short name T166
Test name
Test status
Simulation time 2978019152 ps
CPU time 198 seconds
Started May 09 03:05:42 PM PDT 24
Finished May 09 03:09:01 PM PDT 24
Peak memory 257228 kb
Host smart-45fc8153-5390-49cf-9736-1c6c861ad081
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1663183087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1663183087
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.130806219
Short name T714
Test name
Test status
Simulation time 46007050 ps
CPU time 6.57 seconds
Started May 09 03:05:44 PM PDT 24
Finished May 09 03:05:52 PM PDT 24
Peak memory 248732 kb
Host smart-8fb64792-cad4-4ea2-8d5d-6eb0d172df28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=130806219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.130806219
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1546456458
Short name T804
Test name
Test status
Simulation time 6742536173 ps
CPU time 112.28 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:08:02 PM PDT 24
Peak memory 240488 kb
Host smart-468c04c8-d3a4-45cc-a545-3349a2ed4ddc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1546456458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1546456458
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.746458958
Short name T753
Test name
Test status
Simulation time 838257996 ps
CPU time 100 seconds
Started May 09 03:06:06 PM PDT 24
Finished May 09 03:07:47 PM PDT 24
Peak memory 236860 kb
Host smart-5f5470c2-4382-4439-a2c0-e90890dc0f6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=746458958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.746458958
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.346689876
Short name T802
Test name
Test status
Simulation time 56708957 ps
CPU time 6.25 seconds
Started May 09 03:06:10 PM PDT 24
Finished May 09 03:06:18 PM PDT 24
Peak memory 240444 kb
Host smart-08c068b1-56cb-4914-8e91-56c4c498ecd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=346689876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.346689876
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2178968980
Short name T739
Test name
Test status
Simulation time 296418782 ps
CPU time 10.94 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:06:20 PM PDT 24
Peak memory 250776 kb
Host smart-f8b84aac-41cb-409e-96a5-ab43e9714860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178968980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2178968980
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3062640878
Short name T749
Test name
Test status
Simulation time 180131319 ps
CPU time 5.56 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:06:15 PM PDT 24
Peak memory 239560 kb
Host smart-a0f20e56-b9e4-4d8f-a38c-33ea65681e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3062640878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3062640878
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1079077612
Short name T231
Test name
Test status
Simulation time 10341643 ps
CPU time 1.68 seconds
Started May 09 03:05:53 PM PDT 24
Finished May 09 03:05:56 PM PDT 24
Peak memory 235972 kb
Host smart-45aae092-7e21-4df0-b6b4-511ee3d0b607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1079077612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1079077612
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2046066451
Short name T777
Test name
Test status
Simulation time 277164761 ps
CPU time 22.92 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:06:32 PM PDT 24
Peak memory 245140 kb
Host smart-913c5b38-c276-4617-bd94-c615027efa8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046066451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2046066451
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1127548971
Short name T154
Test name
Test status
Simulation time 37651819397 ps
CPU time 522.45 seconds
Started May 09 03:05:54 PM PDT 24
Finished May 09 03:14:37 PM PDT 24
Peak memory 265404 kb
Host smart-5154f47a-b82e-4152-8978-d001eb344987
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127548971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1127548971
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.894105564
Short name T813
Test name
Test status
Simulation time 431443438 ps
CPU time 29.87 seconds
Started May 09 03:05:54 PM PDT 24
Finished May 09 03:06:25 PM PDT 24
Peak memory 248652 kb
Host smart-6571ac9b-3c87-4edc-baf2-2734c842fe95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=894105564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.894105564
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3429917968
Short name T752
Test name
Test status
Simulation time 805672893 ps
CPU time 17.41 seconds
Started May 09 03:07:35 PM PDT 24
Finished May 09 03:07:54 PM PDT 24
Peak memory 251024 kb
Host smart-1eb58fe2-4351-4de8-9ff6-f93952596591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429917968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3429917968
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3918898006
Short name T774
Test name
Test status
Simulation time 51674254 ps
CPU time 4.39 seconds
Started May 09 03:07:32 PM PDT 24
Finished May 09 03:07:38 PM PDT 24
Peak memory 238768 kb
Host smart-e5c31af4-325b-4aa2-8a3a-abcbd5835710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3918898006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3918898006
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1247693987
Short name T814
Test name
Test status
Simulation time 8530374 ps
CPU time 1.51 seconds
Started May 09 03:07:35 PM PDT 24
Finished May 09 03:07:38 PM PDT 24
Peak memory 236916 kb
Host smart-0dbd90c9-d386-441b-8daa-c694967e1de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1247693987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1247693987
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2924500209
Short name T750
Test name
Test status
Simulation time 165342247 ps
CPU time 26.58 seconds
Started May 09 03:07:33 PM PDT 24
Finished May 09 03:08:01 PM PDT 24
Peak memory 245080 kb
Host smart-c215ad58-df04-4ba2-9aa1-8403152640f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2924500209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2924500209
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2985065869
Short name T831
Test name
Test status
Simulation time 422009408 ps
CPU time 9.78 seconds
Started May 09 03:07:33 PM PDT 24
Finished May 09 03:07:45 PM PDT 24
Peak memory 247948 kb
Host smart-0368045f-d153-4b04-acda-734f094fc774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2985065869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2985065869
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1435084735
Short name T772
Test name
Test status
Simulation time 672544134 ps
CPU time 10.6 seconds
Started May 09 03:07:44 PM PDT 24
Finished May 09 03:07:56 PM PDT 24
Peak memory 240548 kb
Host smart-6d0e47ef-b602-4ef5-938a-9501f0337142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435084735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1435084735
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3561934581
Short name T240
Test name
Test status
Simulation time 507883447 ps
CPU time 10.23 seconds
Started May 09 03:07:42 PM PDT 24
Finished May 09 03:07:53 PM PDT 24
Peak memory 236896 kb
Host smart-d0863ab2-88a8-4260-bd41-1fa57285e862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3561934581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3561934581
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.983237071
Short name T204
Test name
Test status
Simulation time 295081760 ps
CPU time 20.58 seconds
Started May 09 03:07:43 PM PDT 24
Finished May 09 03:08:04 PM PDT 24
Peak memory 248568 kb
Host smart-b05c5390-d570-488e-bfe9-68601f820d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=983237071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.983237071
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3657625914
Short name T155
Test name
Test status
Simulation time 1661310552 ps
CPU time 98.02 seconds
Started May 09 03:07:32 PM PDT 24
Finished May 09 03:09:12 PM PDT 24
Peak memory 265356 kb
Host smart-c9bd2f91-8e38-4aa0-848c-514b51201308
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3657625914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3657625914
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3134619035
Short name T144
Test name
Test status
Simulation time 14506711517 ps
CPU time 513.56 seconds
Started May 09 03:07:33 PM PDT 24
Finished May 09 03:16:09 PM PDT 24
Peak memory 268480 kb
Host smart-36b4f3e7-c0d4-4b32-99ec-9d665dc352e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134619035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3134619035
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3151505334
Short name T761
Test name
Test status
Simulation time 153517088 ps
CPU time 9.81 seconds
Started May 09 03:07:42 PM PDT 24
Finished May 09 03:07:53 PM PDT 24
Peak memory 254376 kb
Host smart-2db80236-2e9f-4f91-a1a1-e1b49582cad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151505334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3151505334
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3767960511
Short name T169
Test name
Test status
Simulation time 35503021 ps
CPU time 2.41 seconds
Started May 09 03:07:43 PM PDT 24
Finished May 09 03:07:47 PM PDT 24
Peak memory 237296 kb
Host smart-e553e04c-5dec-4abf-a657-fcae77feca61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3767960511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3767960511
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1827253068
Short name T782
Test name
Test status
Simulation time 104816944 ps
CPU time 8.2 seconds
Started May 09 03:07:54 PM PDT 24
Finished May 09 03:08:04 PM PDT 24
Peak memory 239804 kb
Host smart-8e5c3680-b4a4-4444-9007-9b7bf0745bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827253068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1827253068
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1040781557
Short name T731
Test name
Test status
Simulation time 35286100 ps
CPU time 5.22 seconds
Started May 09 03:07:54 PM PDT 24
Finished May 09 03:08:01 PM PDT 24
Peak memory 235924 kb
Host smart-42e395f1-c2b2-458f-a7cd-4e83b76f918f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1040781557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1040781557
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.347188232
Short name T833
Test name
Test status
Simulation time 10987471 ps
CPU time 1.67 seconds
Started May 09 03:07:52 PM PDT 24
Finished May 09 03:07:56 PM PDT 24
Peak memory 236988 kb
Host smart-ddc1125b-001d-4374-a5fd-df8a75749762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=347188232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.347188232
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.4212972892
Short name T205
Test name
Test status
Simulation time 939422385 ps
CPU time 20.59 seconds
Started May 09 03:07:51 PM PDT 24
Finished May 09 03:08:13 PM PDT 24
Peak memory 245128 kb
Host smart-a45db850-f5e5-4a34-9ba0-cfd80cb9d385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4212972892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.4212972892
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1371747897
Short name T361
Test name
Test status
Simulation time 2299880151 ps
CPU time 305.32 seconds
Started May 09 03:07:43 PM PDT 24
Finished May 09 03:12:49 PM PDT 24
Peak memory 265572 kb
Host smart-ed5db6fa-3b53-442c-bd9a-448abd5c547a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371747897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1371747897
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2625150119
Short name T721
Test name
Test status
Simulation time 148504409 ps
CPU time 6.1 seconds
Started May 09 03:07:43 PM PDT 24
Finished May 09 03:07:50 PM PDT 24
Peak memory 248760 kb
Host smart-a685e3c2-49a5-4af6-baa7-bf1717d9a1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2625150119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2625150119
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1832936701
Short name T730
Test name
Test status
Simulation time 66388808 ps
CPU time 6.37 seconds
Started May 09 03:08:03 PM PDT 24
Finished May 09 03:08:10 PM PDT 24
Peak memory 239376 kb
Host smart-eab604a0-e7a6-42d2-86b2-354c0687dc54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832936701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1832936701
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3777438729
Short name T779
Test name
Test status
Simulation time 798464391 ps
CPU time 9.16 seconds
Started May 09 03:07:52 PM PDT 24
Finished May 09 03:08:03 PM PDT 24
Peak memory 240416 kb
Host smart-0fd1e84e-e099-4b41-bc05-d5fa8d6ea610
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3777438729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3777438729
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2559541741
Short name T763
Test name
Test status
Simulation time 9765430 ps
CPU time 1.52 seconds
Started May 09 03:07:52 PM PDT 24
Finished May 09 03:07:56 PM PDT 24
Peak memory 236064 kb
Host smart-1acccae6-1586-4359-bbd0-25ac34e8afb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2559541741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2559541741
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2525460324
Short name T738
Test name
Test status
Simulation time 167817520 ps
CPU time 23.08 seconds
Started May 09 03:07:56 PM PDT 24
Finished May 09 03:08:20 PM PDT 24
Peak memory 245156 kb
Host smart-76a66d18-541c-49f3-9df3-2f5c00ce6bfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2525460324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2525460324
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2342998041
Short name T735
Test name
Test status
Simulation time 1285049472 ps
CPU time 17.4 seconds
Started May 09 03:07:51 PM PDT 24
Finished May 09 03:08:10 PM PDT 24
Peak memory 248664 kb
Host smart-35e3dcdb-3cb5-4631-b6c6-b0a1ca7c1e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342998041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2342998041
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.318760242
Short name T826
Test name
Test status
Simulation time 57023822 ps
CPU time 9.56 seconds
Started May 09 03:08:04 PM PDT 24
Finished May 09 03:08:15 PM PDT 24
Peak memory 252320 kb
Host smart-b033d542-b6e8-4197-9a05-dbebc4e5bab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318760242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.318760242
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2058582000
Short name T203
Test name
Test status
Simulation time 66184054 ps
CPU time 3.39 seconds
Started May 09 03:08:03 PM PDT 24
Finished May 09 03:08:08 PM PDT 24
Peak memory 239736 kb
Host smart-0016cd38-494d-42b9-b81d-f1c2292cdb87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2058582000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2058582000
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2498096466
Short name T239
Test name
Test status
Simulation time 347008654 ps
CPU time 23.49 seconds
Started May 09 03:08:04 PM PDT 24
Finished May 09 03:08:29 PM PDT 24
Peak memory 245128 kb
Host smart-059670fd-c8f1-49dc-b51b-e7a636736a68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2498096466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2498096466
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2269612288
Short name T150
Test name
Test status
Simulation time 8894252900 ps
CPU time 177.41 seconds
Started May 09 03:08:04 PM PDT 24
Finished May 09 03:11:03 PM PDT 24
Peak memory 265520 kb
Host smart-3b9012e8-1715-4811-9328-96385dff955c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2269612288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2269612288
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.126393272
Short name T134
Test name
Test status
Simulation time 6443773153 ps
CPU time 479.79 seconds
Started May 09 03:08:02 PM PDT 24
Finished May 09 03:16:04 PM PDT 24
Peak memory 265484 kb
Host smart-1158cc8e-aa95-453d-bf2a-3f7f2674c71a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126393272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.126393272
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2249939502
Short name T783
Test name
Test status
Simulation time 415109361 ps
CPU time 9.06 seconds
Started May 09 03:08:04 PM PDT 24
Finished May 09 03:08:15 PM PDT 24
Peak memory 248280 kb
Host smart-d908e353-5f3a-4f2a-b176-fc8bf0fa3b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2249939502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2249939502
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3357807366
Short name T784
Test name
Test status
Simulation time 58343884 ps
CPU time 2.53 seconds
Started May 09 03:08:02 PM PDT 24
Finished May 09 03:08:06 PM PDT 24
Peak memory 237132 kb
Host smart-e6c5f734-8691-4b93-8aca-078277f9aae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3357807366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3357807366
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2564740961
Short name T823
Test name
Test status
Simulation time 934826985 ps
CPU time 15.81 seconds
Started May 09 03:08:16 PM PDT 24
Finished May 09 03:08:36 PM PDT 24
Peak memory 243556 kb
Host smart-f521e88a-d38b-4acc-86d0-b19855e623cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564740961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2564740961
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2357875425
Short name T249
Test name
Test status
Simulation time 254544479 ps
CPU time 9.44 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:08:29 PM PDT 24
Peak memory 240396 kb
Host smart-1f98adc8-de74-4f7f-8a0d-693dba807099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2357875425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2357875425
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2799551312
Short name T794
Test name
Test status
Simulation time 27935635 ps
CPU time 1.49 seconds
Started May 09 03:08:03 PM PDT 24
Finished May 09 03:08:06 PM PDT 24
Peak memory 236056 kb
Host smart-6bdc8185-6807-4b67-b980-45100f0eb1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2799551312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2799551312
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3997483872
Short name T819
Test name
Test status
Simulation time 130387204 ps
CPU time 10.42 seconds
Started May 09 03:08:15 PM PDT 24
Finished May 09 03:08:27 PM PDT 24
Peak memory 244200 kb
Host smart-0779dd5c-da98-4d1d-bd67-cb30a1e2f4ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3997483872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3997483872
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4166197844
Short name T137
Test name
Test status
Simulation time 4899546615 ps
CPU time 160.76 seconds
Started May 09 03:08:03 PM PDT 24
Finished May 09 03:10:45 PM PDT 24
Peak memory 266868 kb
Host smart-e534747f-055c-4696-8a76-5cb99e9c2e9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4166197844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.4166197844
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2358296598
Short name T241
Test name
Test status
Simulation time 929501397 ps
CPU time 19.89 seconds
Started May 09 03:08:02 PM PDT 24
Finished May 09 03:08:23 PM PDT 24
Peak memory 248300 kb
Host smart-c66cb578-53fb-4aec-8118-1539e07a848f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2358296598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2358296598
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3958644024
Short name T741
Test name
Test status
Simulation time 304408258 ps
CPU time 8.22 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:08:29 PM PDT 24
Peak memory 240288 kb
Host smart-98d23fd0-f711-472e-b325-eee0699bc7f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958644024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3958644024
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.176818652
Short name T791
Test name
Test status
Simulation time 124426769 ps
CPU time 5.65 seconds
Started May 09 03:08:18 PM PDT 24
Finished May 09 03:08:26 PM PDT 24
Peak memory 236872 kb
Host smart-c04d7a78-a5bb-4a5c-a2bc-429e863bd99b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=176818652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.176818652
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1561440930
Short name T799
Test name
Test status
Simulation time 85989478 ps
CPU time 11.47 seconds
Started May 09 03:08:18 PM PDT 24
Finished May 09 03:08:32 PM PDT 24
Peak memory 244220 kb
Host smart-aabdf8ce-a85c-43fb-9f71-72098e48fb74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1561440930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1561440930
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2829451240
Short name T158
Test name
Test status
Simulation time 4143780244 ps
CPU time 147.31 seconds
Started May 09 03:08:15 PM PDT 24
Finished May 09 03:10:46 PM PDT 24
Peak memory 257224 kb
Host smart-418462bc-b15d-4601-9e0d-4cd558242d33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2829451240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2829451240
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.91599534
Short name T728
Test name
Test status
Simulation time 624275464 ps
CPU time 13.18 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:08:33 PM PDT 24
Peak memory 248168 kb
Host smart-67c3cd4d-2e42-4113-a59e-9e67d4838d30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=91599534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.91599534
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.955818837
Short name T209
Test name
Test status
Simulation time 116215173 ps
CPU time 8.24 seconds
Started May 09 03:08:16 PM PDT 24
Finished May 09 03:08:27 PM PDT 24
Peak memory 251452 kb
Host smart-c2561001-c612-42f9-bf7c-d19c087d0bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955818837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.955818837
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1692977331
Short name T800
Test name
Test status
Simulation time 213754295 ps
CPU time 9.05 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:08:30 PM PDT 24
Peak memory 235916 kb
Host smart-5613dfd0-b2fa-46a6-a0e1-f196b25a5918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1692977331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1692977331
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3240779767
Short name T788
Test name
Test status
Simulation time 8973702 ps
CPU time 1.58 seconds
Started May 09 03:08:22 PM PDT 24
Finished May 09 03:08:25 PM PDT 24
Peak memory 236888 kb
Host smart-9c370b3b-44c0-4b8f-b2d6-642756298dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3240779767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3240779767
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2631820933
Short name T795
Test name
Test status
Simulation time 327987581 ps
CPU time 22.5 seconds
Started May 09 03:08:22 PM PDT 24
Finished May 09 03:08:46 PM PDT 24
Peak memory 248596 kb
Host smart-6942d984-7b06-41ff-bf58-f8bfe5f67dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2631820933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2631820933
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4082200909
Short name T140
Test name
Test status
Simulation time 3208541271 ps
CPU time 103.08 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:10:04 PM PDT 24
Peak memory 266572 kb
Host smart-34c4630d-6718-4f24-973e-181f1ef7f0a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4082200909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4082200909
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3558733653
Short name T778
Test name
Test status
Simulation time 556352182 ps
CPU time 26.9 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:08:47 PM PDT 24
Peak memory 248668 kb
Host smart-11295b16-7279-49fa-8b9c-34278f8c190c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3558733653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3558733653
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4017526281
Short name T189
Test name
Test status
Simulation time 1240422402 ps
CPU time 88.88 seconds
Started May 09 03:08:17 PM PDT 24
Finished May 09 03:09:49 PM PDT 24
Peak memory 239852 kb
Host smart-0a594c25-7290-45b9-804a-c525b51c503c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4017526281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4017526281
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4032725215
Short name T359
Test name
Test status
Simulation time 136836164 ps
CPU time 9.38 seconds
Started May 09 03:08:32 PM PDT 24
Finished May 09 03:08:45 PM PDT 24
Peak memory 256464 kb
Host smart-997bbe26-04fb-4a55-b7c4-f6e9dfc2a055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032725215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4032725215
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.927903471
Short name T723
Test name
Test status
Simulation time 91015625 ps
CPU time 4.52 seconds
Started May 09 03:08:29 PM PDT 24
Finished May 09 03:08:36 PM PDT 24
Peak memory 235888 kb
Host smart-90484d15-f888-4b4b-8629-2d5168f18d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=927903471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.927903471
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2135082659
Short name T801
Test name
Test status
Simulation time 10116847 ps
CPU time 1.57 seconds
Started May 09 03:08:34 PM PDT 24
Finished May 09 03:08:39 PM PDT 24
Peak memory 236976 kb
Host smart-5faa485e-a60b-4e04-b843-75dc57c15939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2135082659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2135082659
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2403416622
Short name T722
Test name
Test status
Simulation time 646940445 ps
CPU time 29.76 seconds
Started May 09 03:08:30 PM PDT 24
Finished May 09 03:09:03 PM PDT 24
Peak memory 245176 kb
Host smart-6b1a5cf9-ef24-42ae-9f2f-3307b1d91825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2403416622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2403416622
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3732683559
Short name T153
Test name
Test status
Simulation time 1789251387 ps
CPU time 233.21 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:12:29 PM PDT 24
Peak memory 265376 kb
Host smart-e2c45ba3-0678-465e-9757-e9da9ac2994e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3732683559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3732683559
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2996311028
Short name T162
Test name
Test status
Simulation time 28882173060 ps
CPU time 480.42 seconds
Started May 09 03:08:32 PM PDT 24
Finished May 09 03:16:36 PM PDT 24
Peak memory 265440 kb
Host smart-2fa874fa-dc4f-41ba-a77f-6b3b1646cf12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996311028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2996311028
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.898487213
Short name T745
Test name
Test status
Simulation time 308186008 ps
CPU time 24.62 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:09:00 PM PDT 24
Peak memory 247304 kb
Host smart-e51e6308-95a4-477e-b340-396cf9bdd28c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=898487213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.898487213
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.494215731
Short name T808
Test name
Test status
Simulation time 68415764 ps
CPU time 6.65 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:08:41 PM PDT 24
Peak memory 236996 kb
Host smart-033f2c2b-237a-4bea-bb23-c3d82670a5c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494215731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.494215731
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1075132420
Short name T805
Test name
Test status
Simulation time 114229413 ps
CPU time 5.51 seconds
Started May 09 03:08:32 PM PDT 24
Finished May 09 03:08:42 PM PDT 24
Peak memory 236824 kb
Host smart-8d6d0037-2cb8-451e-906e-68b59d0950bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1075132420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1075132420
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2281655211
Short name T809
Test name
Test status
Simulation time 15067401 ps
CPU time 1.47 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:08:37 PM PDT 24
Peak memory 236988 kb
Host smart-6d486695-e1d5-46b7-b7d5-d41d9535fe37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281655211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2281655211
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3376586541
Short name T744
Test name
Test status
Simulation time 606891518 ps
CPU time 37.13 seconds
Started May 09 03:08:32 PM PDT 24
Finished May 09 03:09:13 PM PDT 24
Peak memory 244192 kb
Host smart-245e206d-7d0d-4ec7-bfcf-344c27eb610c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3376586541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3376586541
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1769061803
Short name T161
Test name
Test status
Simulation time 4305883325 ps
CPU time 292.22 seconds
Started May 09 03:08:30 PM PDT 24
Finished May 09 03:13:25 PM PDT 24
Peak memory 265408 kb
Host smart-c83aa13a-7597-4a5d-ad2e-cf0703034f83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1769061803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1769061803
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3440860962
Short name T362
Test name
Test status
Simulation time 2072102676 ps
CPU time 357.83 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:14:33 PM PDT 24
Peak memory 268528 kb
Host smart-4addf186-45b0-4c77-9b3b-5d7db303d704
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440860962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3440860962
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1958061904
Short name T726
Test name
Test status
Simulation time 308696316 ps
CPU time 4.78 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:08:40 PM PDT 24
Peak memory 249760 kb
Host smart-7f352aad-5d3b-4044-b360-b349ce4d65dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1958061904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1958061904
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.787345389
Short name T718
Test name
Test status
Simulation time 2220532278 ps
CPU time 67.59 seconds
Started May 09 03:06:18 PM PDT 24
Finished May 09 03:07:27 PM PDT 24
Peak memory 236792 kb
Host smart-15df9782-8bb9-4966-b79b-d742aa428308
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=787345389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.787345389
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2688525128
Short name T786
Test name
Test status
Simulation time 2980451343 ps
CPU time 221.97 seconds
Started May 09 03:06:18 PM PDT 24
Finished May 09 03:10:02 PM PDT 24
Peak memory 236928 kb
Host smart-ab0e1c7a-ebe2-4650-bcad-cc08e137eeed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2688525128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2688525128
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2360201471
Short name T824
Test name
Test status
Simulation time 103790485 ps
CPU time 5.29 seconds
Started May 09 03:06:19 PM PDT 24
Finished May 09 03:06:26 PM PDT 24
Peak memory 240376 kb
Host smart-df7e3a31-94d5-4e27-bb9f-cffa2457fae3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2360201471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2360201471
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2528094087
Short name T363
Test name
Test status
Simulation time 581220427 ps
CPU time 14.85 seconds
Started May 09 03:06:19 PM PDT 24
Finished May 09 03:06:35 PM PDT 24
Peak memory 242648 kb
Host smart-ee0bd645-7718-42d0-b6b0-e48a97af8ebc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528094087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2528094087
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.372215597
Short name T758
Test name
Test status
Simulation time 51919929 ps
CPU time 5.97 seconds
Started May 09 03:06:19 PM PDT 24
Finished May 09 03:06:26 PM PDT 24
Peak memory 239800 kb
Host smart-729464d8-cd25-477e-8796-6899e275ce83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=372215597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.372215597
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3050362963
Short name T251
Test name
Test status
Simulation time 11174280 ps
CPU time 1.64 seconds
Started May 09 03:06:09 PM PDT 24
Finished May 09 03:06:13 PM PDT 24
Peak memory 237184 kb
Host smart-cd722873-6ee1-4dea-a168-a2ed881e9aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3050362963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3050362963
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2698342874
Short name T187
Test name
Test status
Simulation time 350848364 ps
CPU time 28.1 seconds
Started May 09 03:06:18 PM PDT 24
Finished May 09 03:06:47 PM PDT 24
Peak memory 245144 kb
Host smart-b3b4e7dd-916a-40f0-9b57-5e8afdd7484d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2698342874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2698342874
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1866603871
Short name T719
Test name
Test status
Simulation time 931704314 ps
CPU time 12.8 seconds
Started May 09 03:06:08 PM PDT 24
Finished May 09 03:06:22 PM PDT 24
Peak memory 252452 kb
Host smart-3e46be46-10a8-4313-9dab-e4755cb7e487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1866603871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1866603871
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1403096416
Short name T776
Test name
Test status
Simulation time 8198532 ps
CPU time 1.44 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:08:36 PM PDT 24
Peak memory 236036 kb
Host smart-9ea28877-74a0-4f70-9698-41cc4943d8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1403096416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1403096416
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2822466190
Short name T356
Test name
Test status
Simulation time 11693523 ps
CPU time 1.32 seconds
Started May 09 03:08:31 PM PDT 24
Finished May 09 03:08:36 PM PDT 24
Peak memory 236000 kb
Host smart-5f9eeb21-6972-4b0e-a7db-2a399320e170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2822466190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2822466190
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1742449471
Short name T792
Test name
Test status
Simulation time 10890227 ps
CPU time 1.42 seconds
Started May 09 03:08:32 PM PDT 24
Finished May 09 03:08:37 PM PDT 24
Peak memory 234972 kb
Host smart-c0d84c20-fec4-48be-a198-d70e1d7eb2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1742449471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1742449471
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1458196361
Short name T751
Test name
Test status
Simulation time 71522148 ps
CPU time 3.86 seconds
Started May 09 03:08:32 PM PDT 24
Finished May 09 03:08:40 PM PDT 24
Peak memory 235064 kb
Host smart-070e36ed-6516-4f15-aa7f-abb6fadc1be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1458196361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1458196361
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1619429611
Short name T790
Test name
Test status
Simulation time 17569715 ps
CPU time 1.42 seconds
Started May 09 03:08:30 PM PDT 24
Finished May 09 03:08:35 PM PDT 24
Peak memory 236972 kb
Host smart-0ccd82b9-bca4-486d-9ed8-8c267a0c358c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1619429611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1619429611
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.329190647
Short name T737
Test name
Test status
Simulation time 7975049 ps
CPU time 1.5 seconds
Started May 09 03:08:37 PM PDT 24
Finished May 09 03:08:42 PM PDT 24
Peak memory 236028 kb
Host smart-08838617-9482-4a48-b6a7-7f52c79ac5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=329190647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.329190647
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3718172270
Short name T747
Test name
Test status
Simulation time 10971990 ps
CPU time 1.75 seconds
Started May 09 03:08:38 PM PDT 24
Finished May 09 03:08:43 PM PDT 24
Peak memory 236972 kb
Host smart-94c09133-ed2a-4cf4-99bd-49a529dcb4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3718172270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3718172270
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.802040390
Short name T822
Test name
Test status
Simulation time 9420659 ps
CPU time 1.51 seconds
Started May 09 03:08:38 PM PDT 24
Finished May 09 03:08:43 PM PDT 24
Peak memory 236056 kb
Host smart-88687b16-ad12-4dfd-a206-b763b6f59a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=802040390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.802040390
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2309614119
Short name T174
Test name
Test status
Simulation time 7486886 ps
CPU time 1.29 seconds
Started May 09 03:08:40 PM PDT 24
Finished May 09 03:08:44 PM PDT 24
Peak memory 236896 kb
Host smart-518b86b9-ed30-4d9a-bb86-3831950b8db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2309614119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2309614119
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1116234414
Short name T830
Test name
Test status
Simulation time 35667679 ps
CPU time 1.35 seconds
Started May 09 03:08:37 PM PDT 24
Finished May 09 03:08:41 PM PDT 24
Peak memory 236976 kb
Host smart-92b8de2c-191b-4453-84b0-104d299e2462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1116234414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1116234414
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1996676290
Short name T206
Test name
Test status
Simulation time 2281922064 ps
CPU time 79.17 seconds
Started May 09 03:06:33 PM PDT 24
Finished May 09 03:07:53 PM PDT 24
Peak memory 236880 kb
Host smart-85841d8f-0c9d-418f-962c-adf26983edbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1996676290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1996676290
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2693142160
Short name T202
Test name
Test status
Simulation time 3335784198 ps
CPU time 243.92 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:10:34 PM PDT 24
Peak memory 240520 kb
Host smart-8b95a8b6-7078-4558-8894-cc96b249fd16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2693142160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2693142160
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.4062990331
Short name T811
Test name
Test status
Simulation time 57341088 ps
CPU time 4.93 seconds
Started May 09 03:06:28 PM PDT 24
Finished May 09 03:06:34 PM PDT 24
Peak memory 240428 kb
Host smart-a8cfd953-5f6c-411f-8797-a4c5a715ed5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4062990331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.4062990331
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1699282154
Short name T766
Test name
Test status
Simulation time 285959785 ps
CPU time 7.88 seconds
Started May 09 03:06:33 PM PDT 24
Finished May 09 03:06:42 PM PDT 24
Peak memory 240304 kb
Host smart-27c24831-b681-497f-b3b2-912485140591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699282154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1699282154
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1776066865
Short name T250
Test name
Test status
Simulation time 71106659 ps
CPU time 5.98 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:06:36 PM PDT 24
Peak memory 236884 kb
Host smart-1b04d551-bed8-402d-8547-3ddb9dd88080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1776066865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1776066865
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2845610787
Short name T743
Test name
Test status
Simulation time 11125638 ps
CPU time 1.55 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:06:32 PM PDT 24
Peak memory 235012 kb
Host smart-4aae0007-2e1a-4deb-8af2-a2bf0d99f548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2845610787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2845610787
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1799394628
Short name T716
Test name
Test status
Simulation time 253945345 ps
CPU time 24.85 seconds
Started May 09 03:06:33 PM PDT 24
Finished May 09 03:06:59 PM PDT 24
Peak memory 245088 kb
Host smart-34c2dd69-4f8e-43da-adf0-e890a1415666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1799394628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1799394628
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3168528488
Short name T152
Test name
Test status
Simulation time 3807491845 ps
CPU time 207.86 seconds
Started May 09 03:06:19 PM PDT 24
Finished May 09 03:09:48 PM PDT 24
Peak memory 265232 kb
Host smart-c7a791a8-5700-4259-9119-7da2aaa709bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3168528488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3168528488
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4003082370
Short name T151
Test name
Test status
Simulation time 2539841635 ps
CPU time 374.85 seconds
Started May 09 03:06:19 PM PDT 24
Finished May 09 03:12:36 PM PDT 24
Peak memory 268512 kb
Host smart-d469d1dd-3cc8-49de-8bfd-658181ab56d6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003082370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4003082370
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.5632907
Short name T733
Test name
Test status
Simulation time 108867571 ps
CPU time 7.2 seconds
Started May 09 03:06:18 PM PDT 24
Finished May 09 03:06:26 PM PDT 24
Peak memory 248204 kb
Host smart-da71906f-dcb3-45dd-9efc-fef150d575bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=5632907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.5632907
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.511088818
Short name T724
Test name
Test status
Simulation time 11945826 ps
CPU time 1.32 seconds
Started May 09 03:08:37 PM PDT 24
Finished May 09 03:08:42 PM PDT 24
Peak memory 236044 kb
Host smart-f154fa9f-e567-4f35-beb3-b20ead04efdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=511088818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.511088818
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.614941878
Short name T770
Test name
Test status
Simulation time 12710209 ps
CPU time 1.4 seconds
Started May 09 03:08:40 PM PDT 24
Finished May 09 03:08:44 PM PDT 24
Peak memory 235940 kb
Host smart-287a3b0e-8c49-4499-9e6e-f53b1099556a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=614941878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.614941878
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2063937319
Short name T232
Test name
Test status
Simulation time 19931797 ps
CPU time 1.51 seconds
Started May 09 03:08:40 PM PDT 24
Finished May 09 03:08:44 PM PDT 24
Peak memory 236008 kb
Host smart-ca582c9d-b584-467f-8cc8-fbf72e933061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2063937319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2063937319
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.744616788
Short name T806
Test name
Test status
Simulation time 6376044 ps
CPU time 1.51 seconds
Started May 09 03:08:41 PM PDT 24
Finished May 09 03:08:44 PM PDT 24
Peak memory 236972 kb
Host smart-9eeb1490-4037-44de-8e1a-478200a49fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=744616788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.744616788
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1778855652
Short name T764
Test name
Test status
Simulation time 12062447 ps
CPU time 1.57 seconds
Started May 09 03:08:40 PM PDT 24
Finished May 09 03:08:44 PM PDT 24
Peak memory 236964 kb
Host smart-b8532fb8-b613-4492-a072-d37882baf1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1778855652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1778855652
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4155457855
Short name T789
Test name
Test status
Simulation time 12165024 ps
CPU time 1.47 seconds
Started May 09 03:08:39 PM PDT 24
Finished May 09 03:08:43 PM PDT 24
Peak memory 236984 kb
Host smart-2db4937e-1859-45b3-8489-6ce020b1ded0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4155457855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4155457855
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1749343668
Short name T252
Test name
Test status
Simulation time 18961667 ps
CPU time 1.41 seconds
Started May 09 03:08:39 PM PDT 24
Finished May 09 03:08:43 PM PDT 24
Peak memory 235012 kb
Host smart-55bdd44d-95af-4833-bf6d-46cd4e682c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1749343668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1749343668
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1931150518
Short name T803
Test name
Test status
Simulation time 19503096 ps
CPU time 1.27 seconds
Started May 09 03:08:35 PM PDT 24
Finished May 09 03:08:40 PM PDT 24
Peak memory 235996 kb
Host smart-c0c49bb1-f6e9-471e-87ae-171cb6a5f3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1931150518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1931150518
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1953585341
Short name T767
Test name
Test status
Simulation time 14898344 ps
CPU time 1.53 seconds
Started May 09 03:08:40 PM PDT 24
Finished May 09 03:08:44 PM PDT 24
Peak memory 236888 kb
Host smart-67932104-c1ef-4e4b-9322-dc4fb20db78e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1953585341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1953585341
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2807407504
Short name T734
Test name
Test status
Simulation time 11956680 ps
CPU time 1.57 seconds
Started May 09 03:08:48 PM PDT 24
Finished May 09 03:08:51 PM PDT 24
Peak memory 236016 kb
Host smart-206738c8-75d2-4f64-ab71-6925ff22a4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807407504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2807407504
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1872938429
Short name T762
Test name
Test status
Simulation time 1834224422 ps
CPU time 133.13 seconds
Started May 09 03:06:40 PM PDT 24
Finished May 09 03:08:54 PM PDT 24
Peak memory 236872 kb
Host smart-9aeaf092-d666-41f3-a92f-7960ac92720e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1872938429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1872938429
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1374026969
Short name T828
Test name
Test status
Simulation time 13604144023 ps
CPU time 250.55 seconds
Started May 09 03:06:39 PM PDT 24
Finished May 09 03:10:51 PM PDT 24
Peak memory 236964 kb
Host smart-6e2bc99e-f170-465f-a41a-da872a7a9436
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1374026969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1374026969
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.4228603803
Short name T715
Test name
Test status
Simulation time 63291958 ps
CPU time 3.26 seconds
Started May 09 03:06:38 PM PDT 24
Finished May 09 03:06:42 PM PDT 24
Peak memory 240340 kb
Host smart-1c31e64b-d0b2-4983-973b-43eeea2212e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4228603803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.4228603803
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1994194163
Short name T773
Test name
Test status
Simulation time 136079500 ps
CPU time 5.45 seconds
Started May 09 03:06:40 PM PDT 24
Finished May 09 03:06:46 PM PDT 24
Peak memory 240544 kb
Host smart-a0525af5-f978-4211-a7b5-d88122b99907
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994194163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1994194163
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.205301040
Short name T748
Test name
Test status
Simulation time 1071211749 ps
CPU time 9.06 seconds
Started May 09 03:06:40 PM PDT 24
Finished May 09 03:06:50 PM PDT 24
Peak memory 236740 kb
Host smart-5479ed24-c22a-42f8-8c29-4959e7540de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=205301040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.205301040
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2108676477
Short name T781
Test name
Test status
Simulation time 9327569 ps
CPU time 1.33 seconds
Started May 09 03:06:30 PM PDT 24
Finished May 09 03:06:32 PM PDT 24
Peak memory 236988 kb
Host smart-2cd92860-343b-4aa5-a7f3-ecc27bcb2438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2108676477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2108676477
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1809680230
Short name T768
Test name
Test status
Simulation time 711526089 ps
CPU time 55.93 seconds
Started May 09 03:06:39 PM PDT 24
Finished May 09 03:07:36 PM PDT 24
Peak memory 245160 kb
Host smart-f03d47ba-014e-4404-86bb-b35d101780db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1809680230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1809680230
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2050279803
Short name T147
Test name
Test status
Simulation time 2614806512 ps
CPU time 168.36 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:09:19 PM PDT 24
Peak memory 265444 kb
Host smart-12751ff9-b7f0-4285-bcf8-f1243943f329
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2050279803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2050279803
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.643359973
Short name T163
Test name
Test status
Simulation time 8852214224 ps
CPU time 681.08 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:17:51 PM PDT 24
Peak memory 265616 kb
Host smart-7f738f8c-b239-4c6b-a70f-fd6339c0238e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643359973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.643359973
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4093883018
Short name T816
Test name
Test status
Simulation time 554930383 ps
CPU time 21.1 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:06:52 PM PDT 24
Peak memory 252764 kb
Host smart-42ac3597-5dae-4d3a-9b60-0db6f1d8f9e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093883018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4093883018
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3055788139
Short name T829
Test name
Test status
Simulation time 8758245460 ps
CPU time 37.14 seconds
Started May 09 03:06:29 PM PDT 24
Finished May 09 03:07:08 PM PDT 24
Peak memory 245320 kb
Host smart-35fc0dd1-d59f-4958-9cd8-389403c1fda3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3055788139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3055788139
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.514761119
Short name T827
Test name
Test status
Simulation time 8201530 ps
CPU time 1.5 seconds
Started May 09 03:08:50 PM PDT 24
Finished May 09 03:08:53 PM PDT 24
Peak memory 236984 kb
Host smart-7a0bc36f-9a9c-4d57-ba94-ef13d23b7464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=514761119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.514761119
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.997730310
Short name T820
Test name
Test status
Simulation time 8797546 ps
CPU time 1.54 seconds
Started May 09 03:08:49 PM PDT 24
Finished May 09 03:08:52 PM PDT 24
Peak memory 236088 kb
Host smart-97c38447-6e7c-4f83-a890-868750afeaa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=997730310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.997730310
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3216139169
Short name T173
Test name
Test status
Simulation time 7962956 ps
CPU time 1.48 seconds
Started May 09 03:08:50 PM PDT 24
Finished May 09 03:08:53 PM PDT 24
Peak memory 236964 kb
Host smart-eb2f31dc-cb93-4a2d-9c96-53ea7dfe57f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216139169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3216139169
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3537340446
Short name T815
Test name
Test status
Simulation time 9581116 ps
CPU time 1.32 seconds
Started May 09 03:08:49 PM PDT 24
Finished May 09 03:08:52 PM PDT 24
Peak memory 236032 kb
Host smart-6f88ee9f-4bc3-4b16-bc6e-12c940dfe56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3537340446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3537340446
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.201516830
Short name T775
Test name
Test status
Simulation time 13507855 ps
CPU time 1.32 seconds
Started May 09 03:08:50 PM PDT 24
Finished May 09 03:08:52 PM PDT 24
Peak memory 236972 kb
Host smart-4110d945-de1d-44f4-a6b3-428d85ba1e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=201516830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.201516830
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3974202427
Short name T736
Test name
Test status
Simulation time 21637936 ps
CPU time 1.5 seconds
Started May 09 03:08:50 PM PDT 24
Finished May 09 03:08:53 PM PDT 24
Peak memory 235912 kb
Host smart-4aff6d4e-54b7-4882-acfd-4337beaae081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3974202427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3974202427
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3846099009
Short name T759
Test name
Test status
Simulation time 12935286 ps
CPU time 1.76 seconds
Started May 09 03:08:48 PM PDT 24
Finished May 09 03:08:51 PM PDT 24
Peak memory 235996 kb
Host smart-42048b8e-5af8-44fb-89a2-eca59c0fdb24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3846099009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3846099009
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2541639290
Short name T755
Test name
Test status
Simulation time 12163401 ps
CPU time 1.3 seconds
Started May 09 03:08:50 PM PDT 24
Finished May 09 03:08:53 PM PDT 24
Peak memory 236052 kb
Host smart-3ff6cef9-34b6-42ce-a76f-726c72f0ee1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2541639290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2541639290
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2181335459
Short name T746
Test name
Test status
Simulation time 11322269 ps
CPU time 1.62 seconds
Started May 09 03:08:51 PM PDT 24
Finished May 09 03:08:54 PM PDT 24
Peak memory 236984 kb
Host smart-2966ea14-e33f-430d-b9e2-14be0aede323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2181335459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2181335459
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1058752130
Short name T785
Test name
Test status
Simulation time 13651709 ps
CPU time 1.49 seconds
Started May 09 03:08:49 PM PDT 24
Finished May 09 03:08:52 PM PDT 24
Peak memory 235004 kb
Host smart-3b74594e-2ffb-4bd9-a824-37a0cd4d09b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1058752130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1058752130
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3195201147
Short name T825
Test name
Test status
Simulation time 410769680 ps
CPU time 8.41 seconds
Started May 09 03:06:59 PM PDT 24
Finished May 09 03:07:09 PM PDT 24
Peak memory 240484 kb
Host smart-d910aa7f-538b-43b5-a156-a717cf44a745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195201147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3195201147
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.248411047
Short name T821
Test name
Test status
Simulation time 320839902 ps
CPU time 10.06 seconds
Started May 09 03:07:01 PM PDT 24
Finished May 09 03:07:13 PM PDT 24
Peak memory 236900 kb
Host smart-275cd7c9-0d5b-4c7b-8dce-df2f78eaf51a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=248411047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.248411047
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3401613274
Short name T760
Test name
Test status
Simulation time 10130865 ps
CPU time 1.78 seconds
Started May 09 03:07:00 PM PDT 24
Finished May 09 03:07:03 PM PDT 24
Peak memory 236936 kb
Host smart-d158b510-41fb-456d-a126-3a6c56b2a0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3401613274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3401613274
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4257641876
Short name T817
Test name
Test status
Simulation time 250999797 ps
CPU time 17.65 seconds
Started May 09 03:07:00 PM PDT 24
Finished May 09 03:07:19 PM PDT 24
Peak memory 245164 kb
Host smart-b84aa1be-71b3-4f13-8253-bf8745984966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4257641876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4257641876
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.687262860
Short name T136
Test name
Test status
Simulation time 2306102488 ps
CPU time 148.61 seconds
Started May 09 03:06:50 PM PDT 24
Finished May 09 03:09:20 PM PDT 24
Peak memory 265436 kb
Host smart-6eb73b2d-522d-4321-ad4f-23fe34653e2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=687262860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.687262860
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1040422750
Short name T149
Test name
Test status
Simulation time 13096262255 ps
CPU time 889.12 seconds
Started May 09 03:06:40 PM PDT 24
Finished May 09 03:21:31 PM PDT 24
Peak memory 265436 kb
Host smart-00f6d46a-aa8d-4f54-a1df-65e3745e4245
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040422750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1040422750
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.836252225
Short name T771
Test name
Test status
Simulation time 192865509 ps
CPU time 6.87 seconds
Started May 09 03:06:50 PM PDT 24
Finished May 09 03:06:59 PM PDT 24
Peak memory 248720 kb
Host smart-f4cf2b9e-4570-4ee4-b289-c06fc7adddd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=836252225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.836252225
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2076661485
Short name T360
Test name
Test status
Simulation time 242336029 ps
CPU time 11.37 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:07:26 PM PDT 24
Peak memory 254428 kb
Host smart-fd739e26-c60c-4201-99e0-9f89a4039aa8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076661485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2076661485
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1848421267
Short name T787
Test name
Test status
Simulation time 113779171 ps
CPU time 8.82 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:22 PM PDT 24
Peak memory 235960 kb
Host smart-bf258e9d-f5b1-4bd1-b05d-3d51de7bf17a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1848421267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1848421267
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3508030869
Short name T732
Test name
Test status
Simulation time 16141707 ps
CPU time 1.53 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:07:16 PM PDT 24
Peak memory 236068 kb
Host smart-6b3b00c1-ae30-4ac3-9853-974f57500913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3508030869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3508030869
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2217199791
Short name T720
Test name
Test status
Simulation time 669248984 ps
CPU time 22.84 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:36 PM PDT 24
Peak memory 245144 kb
Host smart-364844a0-f52a-4969-9d8f-b6c1c64c2816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2217199791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2217199791
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2047785161
Short name T143
Test name
Test status
Simulation time 5448067861 ps
CPU time 127.69 seconds
Started May 09 03:07:01 PM PDT 24
Finished May 09 03:09:10 PM PDT 24
Peak memory 256992 kb
Host smart-4a6caeed-52b3-4d83-be83-6c199ee3fbb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2047785161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2047785161
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3119432167
Short name T167
Test name
Test status
Simulation time 4337401546 ps
CPU time 730.5 seconds
Started May 09 03:07:01 PM PDT 24
Finished May 09 03:19:13 PM PDT 24
Peak memory 265396 kb
Host smart-8f52234b-1b01-4d35-bf7d-dada17aa229e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119432167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3119432167
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3646176678
Short name T740
Test name
Test status
Simulation time 169423741 ps
CPU time 12.64 seconds
Started May 09 03:06:59 PM PDT 24
Finished May 09 03:07:13 PM PDT 24
Peak memory 252160 kb
Host smart-cb9d4ad3-ad8c-495a-94f7-74956185480a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3646176678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3646176678
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2597306658
Short name T810
Test name
Test status
Simulation time 38281676 ps
CPU time 6.1 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:07:20 PM PDT 24
Peak memory 244140 kb
Host smart-a17a29a4-370e-416d-a7a0-786e3dd5911c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597306658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2597306658
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3438468576
Short name T754
Test name
Test status
Simulation time 589034218 ps
CPU time 6.87 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:07:21 PM PDT 24
Peak memory 236724 kb
Host smart-29857226-a0a1-4f43-a850-a6e70a126e61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3438468576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3438468576
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2119657314
Short name T717
Test name
Test status
Simulation time 16464509 ps
CPU time 1.83 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:15 PM PDT 24
Peak memory 236204 kb
Host smart-13f9215f-b6ad-4a07-9708-a477386081ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2119657314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2119657314
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3514855601
Short name T807
Test name
Test status
Simulation time 661737165 ps
CPU time 24.41 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:38 PM PDT 24
Peak memory 245144 kb
Host smart-b76eda42-1f39-46d2-bfc8-42a3799624c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3514855601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3514855601
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1551353099
Short name T159
Test name
Test status
Simulation time 25974026295 ps
CPU time 557.32 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:16:32 PM PDT 24
Peak memory 265416 kb
Host smart-31d1fca1-0930-40e6-b522-7516f2e6ab54
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551353099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1551353099
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.694987350
Short name T725
Test name
Test status
Simulation time 91354771 ps
CPU time 11.86 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:07:26 PM PDT 24
Peak memory 248252 kb
Host smart-6a9820af-c7a2-49ac-80de-d32cc1297d76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=694987350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.694987350
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2301172366
Short name T780
Test name
Test status
Simulation time 156829480 ps
CPU time 9.16 seconds
Started May 09 03:07:21 PM PDT 24
Finished May 09 03:07:34 PM PDT 24
Peak memory 240420 kb
Host smart-f30ea944-4047-4e47-bcf1-daa7e74ee779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301172366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2301172366
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.70673852
Short name T818
Test name
Test status
Simulation time 33298858 ps
CPU time 6.25 seconds
Started May 09 03:07:23 PM PDT 24
Finished May 09 03:07:32 PM PDT 24
Peak memory 235912 kb
Host smart-a30513c1-57b8-4ee2-96e9-c1d99d810def
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=70673852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.70673852
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3001702803
Short name T357
Test name
Test status
Simulation time 14587205 ps
CPU time 1.33 seconds
Started May 09 03:07:22 PM PDT 24
Finished May 09 03:07:26 PM PDT 24
Peak memory 235016 kb
Host smart-ec14fbf7-a4ac-47c9-a390-3a70bbf48ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3001702803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3001702803
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4063894658
Short name T190
Test name
Test status
Simulation time 1588446085 ps
CPU time 12.97 seconds
Started May 09 03:07:21 PM PDT 24
Finished May 09 03:07:37 PM PDT 24
Peak memory 240444 kb
Host smart-d2e417c1-dcaf-4f11-872a-d7fbdd9cb356
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4063894658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4063894658
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3266829218
Short name T168
Test name
Test status
Simulation time 16497922193 ps
CPU time 616.02 seconds
Started May 09 03:07:13 PM PDT 24
Finished May 09 03:17:31 PM PDT 24
Peak memory 265652 kb
Host smart-10c0580e-2480-4567-9431-2b6eba6fd944
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266829218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3266829218
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3941193576
Short name T757
Test name
Test status
Simulation time 101839273 ps
CPU time 11.91 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:26 PM PDT 24
Peak memory 247652 kb
Host smart-abc8fb94-0853-4fe3-beac-2146dc6fc3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3941193576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3941193576
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.25935084
Short name T276
Test name
Test status
Simulation time 2313234971 ps
CPU time 36.9 seconds
Started May 09 03:07:12 PM PDT 24
Finished May 09 03:07:50 PM PDT 24
Peak memory 237200 kb
Host smart-a165c0b1-4bf3-4c6a-b603-dcfdfec72eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=25935084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.25935084
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2790130144
Short name T793
Test name
Test status
Simulation time 177671757 ps
CPU time 4.26 seconds
Started May 09 03:07:23 PM PDT 24
Finished May 09 03:07:30 PM PDT 24
Peak memory 235956 kb
Host smart-87e0e39e-854e-4fba-9c17-1df0609258b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2790130144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2790130144
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.752197450
Short name T756
Test name
Test status
Simulation time 49170982 ps
CPU time 2.97 seconds
Started May 09 03:07:22 PM PDT 24
Finished May 09 03:07:28 PM PDT 24
Peak memory 236080 kb
Host smart-bc1a192b-8ef8-48f3-bf1d-5ef9cf056686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=752197450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.752197450
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1039725550
Short name T796
Test name
Test status
Simulation time 2664080236 ps
CPU time 51.41 seconds
Started May 09 03:07:32 PM PDT 24
Finished May 09 03:08:25 PM PDT 24
Peak memory 245184 kb
Host smart-93adb748-365d-4fe2-b676-6335b51c5bad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1039725550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1039725550
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3278327340
Short name T157
Test name
Test status
Simulation time 1678440075 ps
CPU time 193.44 seconds
Started May 09 03:07:21 PM PDT 24
Finished May 09 03:10:38 PM PDT 24
Peak memory 265364 kb
Host smart-64780474-4238-40af-ac29-8d1ce9ccce34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3278327340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3278327340
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2952366321
Short name T812
Test name
Test status
Simulation time 60518726628 ps
CPU time 536.25 seconds
Started May 09 03:07:22 PM PDT 24
Finished May 09 03:16:21 PM PDT 24
Peak memory 269524 kb
Host smart-588fa499-4af7-4057-bf61-63bdb879f66f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952366321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2952366321
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4001508027
Short name T742
Test name
Test status
Simulation time 914458355 ps
CPU time 14.46 seconds
Started May 09 03:07:21 PM PDT 24
Finished May 09 03:07:38 PM PDT 24
Peak memory 248736 kb
Host smart-07e4c0d9-a768-4914-9d09-390ae7e939ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4001508027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4001508027
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3774910478
Short name T517
Test name
Test status
Simulation time 606581816229 ps
CPU time 2319.63 seconds
Started May 09 03:13:30 PM PDT 24
Finished May 09 03:52:10 PM PDT 24
Peak memory 285208 kb
Host smart-bd372599-88bd-49c1-bb9d-6996677e7023
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774910478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3774910478
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3693971734
Short name T422
Test name
Test status
Simulation time 690349708 ps
CPU time 9.32 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:13:54 PM PDT 24
Peak memory 248784 kb
Host smart-38ca14e6-f0a9-49de-97df-ca3bcbf621bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3693971734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3693971734
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1277485600
Short name T418
Test name
Test status
Simulation time 289415583 ps
CPU time 17.7 seconds
Started May 09 03:13:31 PM PDT 24
Finished May 09 03:13:50 PM PDT 24
Peak memory 249172 kb
Host smart-dc893b25-ad78-44ec-b209-362bab8788dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12774
85600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1277485600
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3183884531
Short name T93
Test name
Test status
Simulation time 1767895865 ps
CPU time 52.62 seconds
Started May 09 03:13:32 PM PDT 24
Finished May 09 03:14:26 PM PDT 24
Peak memory 256088 kb
Host smart-06d65f05-0808-44e6-9172-394e0c613237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838
84531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3183884531
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2018692239
Short name T348
Test name
Test status
Simulation time 39030064836 ps
CPU time 1203.43 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:34:00 PM PDT 24
Peak memory 272668 kb
Host smart-9adadf52-1a2e-4e6e-afe4-dc40c29439c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018692239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2018692239
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2298056414
Short name T433
Test name
Test status
Simulation time 90071929808 ps
CPU time 1668.56 seconds
Started May 09 03:13:40 PM PDT 24
Finished May 09 03:41:29 PM PDT 24
Peak memory 273448 kb
Host smart-5fb454f1-3b8d-4c5f-bc43-c22464fc8531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298056414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2298056414
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.428818857
Short name T315
Test name
Test status
Simulation time 59791317018 ps
CPU time 670.79 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:24:56 PM PDT 24
Peak memory 247104 kb
Host smart-a6ec4076-ede0-41b6-bcbc-8968b510a33b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428818857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.428818857
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.4192368610
Short name T592
Test name
Test status
Simulation time 992005604 ps
CPU time 8.99 seconds
Started May 09 03:13:32 PM PDT 24
Finished May 09 03:13:42 PM PDT 24
Peak memory 248784 kb
Host smart-b115318d-384c-4eb1-9aa3-11a25e75f360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41923
68610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.4192368610
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3808517883
Short name T426
Test name
Test status
Simulation time 361221202 ps
CPU time 27.7 seconds
Started May 09 03:13:41 PM PDT 24
Finished May 09 03:14:11 PM PDT 24
Peak memory 255336 kb
Host smart-1632adce-b7ee-4586-a53a-03996bd77e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38085
17883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3808517883
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2858377378
Short name T104
Test name
Test status
Simulation time 74933422 ps
CPU time 12.54 seconds
Started May 09 03:13:33 PM PDT 24
Finished May 09 03:13:46 PM PDT 24
Peak memory 255632 kb
Host smart-b047d1c4-da12-42ce-8bd7-3794b1cb1ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
77378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2858377378
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3571748391
Short name T434
Test name
Test status
Simulation time 248374374 ps
CPU time 24.44 seconds
Started May 09 03:13:30 PM PDT 24
Finished May 09 03:13:56 PM PDT 24
Peak memory 248788 kb
Host smart-416839ea-a2f9-4bef-9579-186f9b7da1e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
48391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3571748391
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2400142200
Short name T261
Test name
Test status
Simulation time 150356608077 ps
CPU time 2476.8 seconds
Started May 09 03:13:42 PM PDT 24
Finished May 09 03:55:01 PM PDT 24
Peak memory 289360 kb
Host smart-12aa4995-19cd-46ca-ab50-ae928f7059cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400142200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2400142200
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3024699146
Short name T700
Test name
Test status
Simulation time 42166872143 ps
CPU time 1285.66 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:35:11 PM PDT 24
Peak memory 273428 kb
Host smart-492be2ab-4e82-4d70-824a-5499ab4a4f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024699146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3024699146
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.809383018
Short name T408
Test name
Test status
Simulation time 156380376 ps
CPU time 9.74 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:13:54 PM PDT 24
Peak memory 248804 kb
Host smart-fbf4fa85-b845-4ebb-b6df-d1cafda51646
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=809383018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.809383018
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3767357967
Short name T679
Test name
Test status
Simulation time 3710723740 ps
CPU time 59.73 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:14:56 PM PDT 24
Peak memory 256832 kb
Host smart-faf74077-15cb-4dce-861b-0cca29ab0bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37673
57967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3767357967
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4148159285
Short name T83
Test name
Test status
Simulation time 22054605 ps
CPU time 3.37 seconds
Started May 09 03:13:42 PM PDT 24
Finished May 09 03:13:47 PM PDT 24
Peak memory 240608 kb
Host smart-0eee77af-0f8b-43cd-9dd4-cf8b090e88be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41481
59285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4148159285
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3421843440
Short name T504
Test name
Test status
Simulation time 63120974295 ps
CPU time 2107.4 seconds
Started May 09 03:13:41 PM PDT 24
Finished May 09 03:48:51 PM PDT 24
Peak memory 289116 kb
Host smart-3d1f7bd7-e489-4a1c-bc6f-2bba3a03cf0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421843440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3421843440
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.483996479
Short name T521
Test name
Test status
Simulation time 753766574 ps
CPU time 26.57 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:14:12 PM PDT 24
Peak memory 255968 kb
Host smart-9783ccfc-7ce0-4e6e-8869-10afff6adfd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48399
6479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.483996479
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.113695021
Short name T537
Test name
Test status
Simulation time 235292199 ps
CPU time 7.58 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:13:53 PM PDT 24
Peak memory 252724 kb
Host smart-7f7c4a6b-e50e-42a0-9371-e412c560574a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
5021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.113695021
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4085736966
Short name T197
Test name
Test status
Simulation time 2085871467 ps
CPU time 36.13 seconds
Started May 09 03:13:42 PM PDT 24
Finished May 09 03:14:21 PM PDT 24
Peak memory 248768 kb
Host smart-28b1713f-71c0-4f37-979d-606faf7b677a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40857
36966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4085736966
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3870579206
Short name T702
Test name
Test status
Simulation time 3109533106 ps
CPU time 20.83 seconds
Started May 09 03:13:41 PM PDT 24
Finished May 09 03:14:03 PM PDT 24
Peak memory 248996 kb
Host smart-60a79ab0-4b8b-4069-81f3-21a91ab66fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38705
79206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3870579206
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2369666727
Short name T601
Test name
Test status
Simulation time 708203636 ps
CPU time 71.49 seconds
Started May 09 03:13:42 PM PDT 24
Finished May 09 03:14:56 PM PDT 24
Peak memory 249808 kb
Host smart-1bbad9ba-ad18-48d7-bb0b-c433c4074718
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369666727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2369666727
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.487092147
Short name T61
Test name
Test status
Simulation time 33334591239 ps
CPU time 3158.79 seconds
Started May 09 03:13:40 PM PDT 24
Finished May 09 04:06:22 PM PDT 24
Peak memory 298116 kb
Host smart-6cb8d5e1-5dcb-407b-bca1-7aa6cd332d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487092147 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.487092147
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3603204664
Short name T63
Test name
Test status
Simulation time 324474531181 ps
CPU time 1696.7 seconds
Started May 09 03:14:28 PM PDT 24
Finished May 09 03:42:46 PM PDT 24
Peak memory 273420 kb
Host smart-517b8eae-fbb6-42df-8f13-b6078e2dabda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603204664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3603204664
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2527401276
Short name T618
Test name
Test status
Simulation time 302207261 ps
CPU time 14.79 seconds
Started May 09 03:14:29 PM PDT 24
Finished May 09 03:14:46 PM PDT 24
Peak memory 248808 kb
Host smart-71c706f0-605b-4a22-843f-e03d79b65f4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2527401276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2527401276
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2545334868
Short name T654
Test name
Test status
Simulation time 11908762562 ps
CPU time 118.67 seconds
Started May 09 03:14:30 PM PDT 24
Finished May 09 03:16:30 PM PDT 24
Peak memory 249908 kb
Host smart-5abd74f8-ca93-4164-ab26-7117b019ee9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25453
34868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2545334868
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4056996320
Short name T602
Test name
Test status
Simulation time 1150509840 ps
CPU time 23.63 seconds
Started May 09 03:14:31 PM PDT 24
Finished May 09 03:14:55 PM PDT 24
Peak memory 255860 kb
Host smart-d9b8aacd-f39b-4ae5-9958-0cb8af565e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40569
96320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4056996320
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1196626215
Short name T294
Test name
Test status
Simulation time 17797530709 ps
CPU time 1321.4 seconds
Started May 09 03:14:25 PM PDT 24
Finished May 09 03:36:27 PM PDT 24
Peak memory 272972 kb
Host smart-dcf205ed-23c0-449d-98aa-1e82a9216175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196626215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1196626215
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1619329312
Short name T497
Test name
Test status
Simulation time 4065735454 ps
CPU time 163.5 seconds
Started May 09 03:14:30 PM PDT 24
Finished May 09 03:17:15 PM PDT 24
Peak memory 248384 kb
Host smart-d78982cb-9cc5-44fb-8329-71cd07c4655e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619329312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1619329312
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3679846501
Short name T480
Test name
Test status
Simulation time 342371741 ps
CPU time 18.24 seconds
Started May 09 03:14:25 PM PDT 24
Finished May 09 03:14:45 PM PDT 24
Peak memory 248820 kb
Host smart-30718a81-0e59-49d7-bf98-cd68088f3cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36798
46501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3679846501
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.898600157
Short name T472
Test name
Test status
Simulation time 528018697 ps
CPU time 28.51 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:14:57 PM PDT 24
Peak memory 248780 kb
Host smart-8cf326dd-0670-42cf-90db-9ffedf6e1e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89860
0157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.898600157
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4041622186
Short name T582
Test name
Test status
Simulation time 3460536326 ps
CPU time 65.75 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:15:34 PM PDT 24
Peak memory 248836 kb
Host smart-6d282d15-b543-4678-8a81-6129968214a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40416
22186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4041622186
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2647679958
Short name T199
Test name
Test status
Simulation time 9977935886 ps
CPU time 73.96 seconds
Started May 09 03:14:28 PM PDT 24
Finished May 09 03:15:43 PM PDT 24
Peak memory 256160 kb
Host smart-35776bc9-1b45-4cc0-b80e-86fd683d3050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
79958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2647679958
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1776826289
Short name T242
Test name
Test status
Simulation time 19310678411 ps
CPU time 2202.91 seconds
Started May 09 03:14:25 PM PDT 24
Finished May 09 03:51:10 PM PDT 24
Peak memory 289796 kb
Host smart-e1a33b88-7609-44be-8c40-637ad765cd71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776826289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1776826289
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1451392719
Short name T224
Test name
Test status
Simulation time 22194525 ps
CPU time 3.41 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 03:14:47 PM PDT 24
Peak memory 248928 kb
Host smart-b4d12693-e9c4-47c6-b238-6dce851b49d9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1451392719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1451392719
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1635557908
Short name T664
Test name
Test status
Simulation time 164699037027 ps
CPU time 841.97 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:28:29 PM PDT 24
Peak memory 273428 kb
Host smart-13c4b631-8fff-43f1-8375-51298e473414
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635557908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1635557908
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.269920625
Short name T236
Test name
Test status
Simulation time 701466067 ps
CPU time 11.1 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:14:56 PM PDT 24
Peak memory 252472 kb
Host smart-13784c32-f5dc-41da-9f7a-2c4af7347f18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=269920625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.269920625
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2728903628
Short name T579
Test name
Test status
Simulation time 1302063905 ps
CPU time 110.52 seconds
Started May 09 03:14:29 PM PDT 24
Finished May 09 03:16:21 PM PDT 24
Peak memory 256944 kb
Host smart-13bba66a-a436-4c3e-9a52-f289d935ff54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27289
03628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2728903628
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2094191945
Short name T68
Test name
Test status
Simulation time 716185141 ps
CPU time 22.45 seconds
Started May 09 03:14:29 PM PDT 24
Finished May 09 03:14:53 PM PDT 24
Peak memory 248808 kb
Host smart-799c20f2-ae72-48e0-a7a9-6ce3c514215f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20941
91945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2094191945
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.158454437
Short name T352
Test name
Test status
Simulation time 17129305315 ps
CPU time 1663.81 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:42:12 PM PDT 24
Peak memory 288384 kb
Host smart-4c88848a-3118-4b66-8f58-df4666f258cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158454437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.158454437
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2159800506
Short name T406
Test name
Test status
Simulation time 18104449873 ps
CPU time 824.26 seconds
Started May 09 03:14:30 PM PDT 24
Finished May 09 03:28:15 PM PDT 24
Peak memory 273428 kb
Host smart-57f4de79-88a4-49a0-a120-611457f49bad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159800506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2159800506
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.316878031
Short name T595
Test name
Test status
Simulation time 5030044889 ps
CPU time 200.56 seconds
Started May 09 03:14:28 PM PDT 24
Finished May 09 03:17:50 PM PDT 24
Peak memory 248052 kb
Host smart-4c5039c1-3db5-4120-8313-9bb9bea76613
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316878031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.316878031
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.57696518
Short name T683
Test name
Test status
Simulation time 81675445 ps
CPU time 8.92 seconds
Started May 09 03:14:28 PM PDT 24
Finished May 09 03:14:39 PM PDT 24
Peak memory 248772 kb
Host smart-f352e145-51b7-4099-877f-62b23bc6c98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57696
518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.57696518
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2579649168
Short name T116
Test name
Test status
Simulation time 219314183 ps
CPU time 25.79 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:14:53 PM PDT 24
Peak memory 248820 kb
Host smart-97786f16-eb60-4c19-a066-e2d95a9b3221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
49168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2579649168
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3150752682
Short name T455
Test name
Test status
Simulation time 142509158 ps
CPU time 6.19 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:14:34 PM PDT 24
Peak memory 248772 kb
Host smart-be442bc2-4233-4df5-98e6-47e06d366862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
52682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3150752682
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2266843499
Short name T534
Test name
Test status
Simulation time 5379018794 ps
CPU time 52.15 seconds
Started May 09 03:14:30 PM PDT 24
Finished May 09 03:15:24 PM PDT 24
Peak memory 256100 kb
Host smart-af3d5068-f52e-456f-8b0a-d60937261549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22668
43499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2266843499
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1039332751
Short name T687
Test name
Test status
Simulation time 51145644682 ps
CPU time 2599.49 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:58:02 PM PDT 24
Peak memory 289728 kb
Host smart-8880cebf-f519-4f08-bd47-a5f1a557ed1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039332751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1039332751
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1105977524
Short name T227
Test name
Test status
Simulation time 135736808 ps
CPU time 2.97 seconds
Started May 09 03:14:39 PM PDT 24
Finished May 09 03:14:43 PM PDT 24
Peak memory 248908 kb
Host smart-31619392-15a5-4bf0-a4fd-54501b20d4c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1105977524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1105977524
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.863422374
Short name T656
Test name
Test status
Simulation time 405599404 ps
CPU time 7.64 seconds
Started May 09 03:14:44 PM PDT 24
Finished May 09 03:14:53 PM PDT 24
Peak memory 248784 kb
Host smart-9129dab3-2baf-4143-a750-9da4ee7dd3e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=863422374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.863422374
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1717401865
Short name T588
Test name
Test status
Simulation time 4212508878 ps
CPU time 131.79 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 03:16:56 PM PDT 24
Peak memory 257028 kb
Host smart-a6362ecb-3705-4adc-899e-7352ac9f4833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17174
01865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1717401865
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3245742383
Short name T435
Test name
Test status
Simulation time 120101375 ps
CPU time 5.23 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:14:47 PM PDT 24
Peak memory 240572 kb
Host smart-3f67daa1-7a76-40b9-9cb4-21c6cb1e67b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
42383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3245742383
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.298408633
Short name T554
Test name
Test status
Simulation time 27654591256 ps
CPU time 1174.64 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:34:18 PM PDT 24
Peak memory 272780 kb
Host smart-796dce11-e4d5-4f4e-81e0-619deeb08a6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298408633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.298408633
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1124404731
Short name T505
Test name
Test status
Simulation time 61009654965 ps
CPU time 1512.16 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:39:57 PM PDT 24
Peak memory 283928 kb
Host smart-62c0748b-4a0b-4e0c-91ce-1aa2df9c88c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124404731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1124404731
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.4276481308
Short name T535
Test name
Test status
Simulation time 10152836839 ps
CPU time 423.63 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 03:21:47 PM PDT 24
Peak memory 248228 kb
Host smart-0ae7c853-3230-4474-b56a-0053e31ed8bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276481308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.4276481308
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1203689455
Short name T24
Test name
Test status
Simulation time 8146440888 ps
CPU time 79.99 seconds
Started May 09 03:14:39 PM PDT 24
Finished May 09 03:16:01 PM PDT 24
Peak memory 248916 kb
Host smart-d0556715-60b6-473f-941b-2438c24ee639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12036
89455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1203689455
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4042138559
Short name T580
Test name
Test status
Simulation time 488116675 ps
CPU time 27.7 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:15:11 PM PDT 24
Peak memory 248816 kb
Host smart-85d8874a-3059-410e-9eaa-3c3060e9e360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40421
38559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4042138559
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1143408496
Short name T498
Test name
Test status
Simulation time 1580867494 ps
CPU time 30.04 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:15:12 PM PDT 24
Peak memory 256080 kb
Host smart-30989778-7b2e-4875-9373-bc37d4f9e399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434
08496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1143408496
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2485700472
Short name T499
Test name
Test status
Simulation time 1247067876 ps
CPU time 32.58 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:15:14 PM PDT 24
Peak memory 248788 kb
Host smart-2d87a79e-2dd0-4383-90e9-44b07b195d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
00472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2485700472
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.312177301
Short name T606
Test name
Test status
Simulation time 119549767040 ps
CPU time 3672.91 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 04:15:56 PM PDT 24
Peak memory 289036 kb
Host smart-b80ebc4f-7ae6-4313-9314-3093a2254075
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312177301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.312177301
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2885044872
Short name T201
Test name
Test status
Simulation time 221468845431 ps
CPU time 10423.4 seconds
Started May 09 03:14:46 PM PDT 24
Finished May 09 06:08:32 PM PDT 24
Peak memory 388780 kb
Host smart-878ca17e-747d-42de-a99e-3e71c7471d93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885044872 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2885044872
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3892053067
Short name T488
Test name
Test status
Simulation time 41488384269 ps
CPU time 2325.49 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:53:27 PM PDT 24
Peak memory 289844 kb
Host smart-6ad2c4b4-8c71-4af9-92b6-6b9af022086c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892053067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3892053067
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.4101585848
Short name T628
Test name
Test status
Simulation time 1774938741 ps
CPU time 19.58 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:15:02 PM PDT 24
Peak memory 248800 kb
Host smart-c920abec-7077-47ac-9707-6262a885622b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4101585848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4101585848
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.883251685
Short name T246
Test name
Test status
Simulation time 6002335945 ps
CPU time 207.93 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:18:13 PM PDT 24
Peak memory 249848 kb
Host smart-b2328f43-d5b0-4cc9-a59d-58f09ce429f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88325
1685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.883251685
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2670875384
Short name T646
Test name
Test status
Simulation time 1012977053 ps
CPU time 32.89 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:15:15 PM PDT 24
Peak memory 248800 kb
Host smart-76cec1d3-0da2-4a96-a228-aee6666e00a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26708
75384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2670875384
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2814469153
Short name T473
Test name
Test status
Simulation time 56376248861 ps
CPU time 3583.76 seconds
Started May 09 03:14:46 PM PDT 24
Finished May 09 04:14:31 PM PDT 24
Peak memory 289328 kb
Host smart-caa86df9-5cb7-4960-bdee-80ecb7b59345
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814469153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2814469153
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3943897985
Short name T660
Test name
Test status
Simulation time 1281430963 ps
CPU time 35.78 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:15:20 PM PDT 24
Peak memory 248800 kb
Host smart-409250d4-6023-4a58-abcc-219e233cf45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438
97985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3943897985
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3636618364
Short name T511
Test name
Test status
Simulation time 679976715 ps
CPU time 41.98 seconds
Started May 09 03:14:41 PM PDT 24
Finished May 09 03:15:25 PM PDT 24
Peak memory 248452 kb
Host smart-6d6f3795-68d9-4265-abd9-d1950831ea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
18364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3636618364
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.16739114
Short name T553
Test name
Test status
Simulation time 1114055214 ps
CPU time 20.45 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:15:02 PM PDT 24
Peak memory 249180 kb
Host smart-832eae5d-d0b5-4e6d-b755-e407ecfad2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16739
114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.16739114
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3548644639
Short name T390
Test name
Test status
Simulation time 106749828 ps
CPU time 5.16 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:14:50 PM PDT 24
Peak memory 248768 kb
Host smart-29f8a339-3074-4704-8019-7aff1ad3ff88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35486
44639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3548644639
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2905789747
Short name T64
Test name
Test status
Simulation time 122340117850 ps
CPU time 2929.91 seconds
Started May 09 03:14:39 PM PDT 24
Finished May 09 04:03:31 PM PDT 24
Peak memory 319636 kb
Host smart-dccf3d9d-74be-4909-8885-2aebd7a10297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905789747 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2905789747
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1327303689
Short name T210
Test name
Test status
Simulation time 44848635 ps
CPU time 4.26 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:14:58 PM PDT 24
Peak memory 248960 kb
Host smart-ab7c1edb-0d80-4cf1-be24-6ac9d8daae51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1327303689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1327303689
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3014149994
Short name T676
Test name
Test status
Simulation time 338583023458 ps
CPU time 3333.6 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 04:10:18 PM PDT 24
Peak memory 281664 kb
Host smart-757191ac-1bff-409c-b8b3-0efb3023fd81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014149994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3014149994
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.128871490
Short name T452
Test name
Test status
Simulation time 984869181 ps
CPU time 44.25 seconds
Started May 09 03:14:53 PM PDT 24
Finished May 09 03:15:40 PM PDT 24
Peak memory 248748 kb
Host smart-554bcd66-b2ff-4dca-be9f-f93453464124
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=128871490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.128871490
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3490374399
Short name T610
Test name
Test status
Simulation time 3309379384 ps
CPU time 67.4 seconds
Started May 09 03:14:47 PM PDT 24
Finished May 09 03:15:55 PM PDT 24
Peak memory 256904 kb
Host smart-96bda495-8cb0-49bc-b61d-ea0de7a0f6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34903
74399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3490374399
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2606842910
Short name T701
Test name
Test status
Simulation time 757949291 ps
CPU time 44.02 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 03:15:28 PM PDT 24
Peak memory 248768 kb
Host smart-77be5f4f-3084-4491-b59d-1a3e48501419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
42910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2606842910
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2702184813
Short name T331
Test name
Test status
Simulation time 15499790453 ps
CPU time 990.68 seconds
Started May 09 03:14:57 PM PDT 24
Finished May 09 03:31:30 PM PDT 24
Peak memory 272668 kb
Host smart-0f567c9e-9b78-4bd7-80ef-906947b184bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702184813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2702184813
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.4001986877
Short name T383
Test name
Test status
Simulation time 10836957646 ps
CPU time 951.95 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:30:47 PM PDT 24
Peak memory 268588 kb
Host smart-a04412a2-1fda-459e-bc30-a5942aaba4dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001986877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.4001986877
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3312947590
Short name T312
Test name
Test status
Simulation time 43768043885 ps
CPU time 311.78 seconds
Started May 09 03:14:40 PM PDT 24
Finished May 09 03:19:54 PM PDT 24
Peak memory 254492 kb
Host smart-5f864255-d71e-4348-ab1d-e312ef7cede6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312947590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3312947590
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2651047177
Short name T366
Test name
Test status
Simulation time 846639985 ps
CPU time 53.39 seconds
Started May 09 03:14:42 PM PDT 24
Finished May 09 03:15:37 PM PDT 24
Peak memory 248828 kb
Host smart-baa64fd4-caf3-40db-a82b-bf1029bc14be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
47177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2651047177
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3973118269
Short name T62
Test name
Test status
Simulation time 3839378426 ps
CPU time 55.49 seconds
Started May 09 03:14:43 PM PDT 24
Finished May 09 03:15:40 PM PDT 24
Peak memory 256152 kb
Host smart-1c861de5-5722-41f0-aa70-d4746a6f07f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39731
18269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3973118269
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1323696783
Short name T449
Test name
Test status
Simulation time 49036523 ps
CPU time 5.72 seconds
Started May 09 03:14:39 PM PDT 24
Finished May 09 03:14:47 PM PDT 24
Peak memory 248776 kb
Host smart-c4bc9b2a-3581-4d43-9c9a-61acefc68a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13236
96783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1323696783
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3023812880
Short name T633
Test name
Test status
Simulation time 101906507878 ps
CPU time 2157.51 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:50:53 PM PDT 24
Peak memory 305964 kb
Host smart-3f347d72-2990-43ad-a8d6-37d590ac7344
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023812880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3023812880
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.22606923
Short name T58
Test name
Test status
Simulation time 17066091889 ps
CPU time 2072.78 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:49:26 PM PDT 24
Peak memory 289160 kb
Host smart-bb56a2bb-5936-4dd0-a38d-9e3a301abd2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22606923 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.22606923
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1447255958
Short name T213
Test name
Test status
Simulation time 48919563 ps
CPU time 3.87 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:14:57 PM PDT 24
Peak memory 248944 kb
Host smart-0ab0ca56-dfe0-4abd-8aab-01f9560799e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1447255958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1447255958
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2125299797
Short name T123
Test name
Test status
Simulation time 37285057311 ps
CPU time 1631.61 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:42:07 PM PDT 24
Peak memory 289380 kb
Host smart-b0ac5642-05fc-4768-940a-a28b26b33497
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125299797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2125299797
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1348640869
Short name T233
Test name
Test status
Simulation time 336997336 ps
CPU time 11.1 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:04 PM PDT 24
Peak memory 248760 kb
Host smart-cb508af7-2c9e-4639-bdc2-9bccd7b18ec4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1348640869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1348640869
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2277750015
Short name T385
Test name
Test status
Simulation time 5554307655 ps
CPU time 140.24 seconds
Started May 09 03:14:50 PM PDT 24
Finished May 09 03:17:11 PM PDT 24
Peak memory 257008 kb
Host smart-0ac84dae-0d6f-4e65-87ad-9aeb35fc7b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
50015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2277750015
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2723522762
Short name T559
Test name
Test status
Simulation time 7319843006 ps
CPU time 58.58 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:53 PM PDT 24
Peak memory 256992 kb
Host smart-130a3c3b-6a1c-4151-9ce9-8677aff9603c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
22762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2723522762
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3371649980
Short name T349
Test name
Test status
Simulation time 59548791656 ps
CPU time 1652.38 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:42:28 PM PDT 24
Peak memory 288156 kb
Host smart-c4fdeb3b-3559-4ccc-b286-c426c17d56ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371649980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3371649980
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2809275053
Short name T384
Test name
Test status
Simulation time 46985678388 ps
CPU time 1124.78 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:33:39 PM PDT 24
Peak memory 289288 kb
Host smart-b74d6ee7-10b8-44b3-8c99-18615803a770
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809275053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2809275053
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3087404593
Short name T320
Test name
Test status
Simulation time 11636758728 ps
CPU time 249.05 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:19:04 PM PDT 24
Peak memory 247876 kb
Host smart-c4d73a55-713d-4ab1-9ed2-6ff7470625af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087404593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3087404593
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2014852505
Short name T532
Test name
Test status
Simulation time 347067997 ps
CPU time 6.64 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:00 PM PDT 24
Peak memory 248800 kb
Host smart-526dcba7-4534-491e-aa9a-85680a4f5572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20148
52505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2014852505
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.38254636
Short name T677
Test name
Test status
Simulation time 2555800646 ps
CPU time 21.68 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:15:17 PM PDT 24
Peak memory 248860 kb
Host smart-24cda86b-5382-4ee6-b969-81e884cc3e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38254
636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.38254636
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.917265328
Short name T271
Test name
Test status
Simulation time 236169595 ps
CPU time 21.19 seconds
Started May 09 03:14:57 PM PDT 24
Finished May 09 03:15:21 PM PDT 24
Peak memory 254220 kb
Host smart-1b1289fc-c7f2-42db-a650-ce5549a9a6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91726
5328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.917265328
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.981343886
Short name T381
Test name
Test status
Simulation time 56133106 ps
CPU time 5.56 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:00 PM PDT 24
Peak memory 254440 kb
Host smart-3f888e64-f83a-463f-ab18-ed854f108367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98134
3886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.981343886
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1593485195
Short name T36
Test name
Test status
Simulation time 27381865229 ps
CPU time 943.96 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:30:38 PM PDT 24
Peak memory 272444 kb
Host smart-cbe8aaec-1e6a-4ed4-ab1b-1e806ee7856a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593485195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1593485195
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2832729510
Short name T550
Test name
Test status
Simulation time 30598068702 ps
CPU time 1033.83 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:32:08 PM PDT 24
Peak memory 272468 kb
Host smart-6803ddb8-10d8-4d3e-ae86-f8f203af37bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832729510 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2832729510
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.807031408
Short name T217
Test name
Test status
Simulation time 127479135 ps
CPU time 2.99 seconds
Started May 09 03:14:53 PM PDT 24
Finished May 09 03:14:59 PM PDT 24
Peak memory 249012 kb
Host smart-566a59dc-051c-4e4b-9ad4-b0e4e05ee94c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=807031408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.807031408
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4004266138
Short name T514
Test name
Test status
Simulation time 24150608218 ps
CPU time 1308.29 seconds
Started May 09 03:14:50 PM PDT 24
Finished May 09 03:36:41 PM PDT 24
Peak memory 289324 kb
Host smart-8105e5fc-1991-49b5-991f-cf305814948d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004266138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4004266138
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2114413829
Short name T468
Test name
Test status
Simulation time 3181315923 ps
CPU time 120.42 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:16:54 PM PDT 24
Peak memory 250016 kb
Host smart-80149f30-66ae-4e95-b596-f187778b18de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21144
13829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2114413829
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3321184808
Short name T544
Test name
Test status
Simulation time 1683408683 ps
CPU time 23.37 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:15:18 PM PDT 24
Peak memory 253964 kb
Host smart-06257e6b-f32c-47a7-a823-e6f420ce53c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33211
84808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3321184808
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2378552391
Short name T464
Test name
Test status
Simulation time 42457101186 ps
CPU time 852.81 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:29:06 PM PDT 24
Peak memory 265248 kb
Host smart-bb5bc6b2-946a-4aed-b9be-59f24b990b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378552391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2378552391
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.201483427
Short name T443
Test name
Test status
Simulation time 129547989754 ps
CPU time 1860.19 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:45:54 PM PDT 24
Peak memory 269332 kb
Host smart-873ae04d-5207-4439-8c73-931980d371c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201483427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.201483427
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2671024028
Short name T600
Test name
Test status
Simulation time 3314916733 ps
CPU time 139.56 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:17:14 PM PDT 24
Peak memory 247468 kb
Host smart-41d68512-5b4a-43c2-8dd9-2fd33c2b261f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671024028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2671024028
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4175944118
Short name T675
Test name
Test status
Simulation time 185619857 ps
CPU time 23.53 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:17 PM PDT 24
Peak memory 248764 kb
Host smart-afaf53da-3caa-45dd-b3ae-319070ac232a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41759
44118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4175944118
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2634261197
Short name T369
Test name
Test status
Simulation time 49025905 ps
CPU time 6.26 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:15:01 PM PDT 24
Peak memory 249912 kb
Host smart-2e23a663-c691-45ea-b1a7-3ca81d2ee11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26342
61197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2634261197
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4227336988
Short name T516
Test name
Test status
Simulation time 1574309137 ps
CPU time 48.5 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:41 PM PDT 24
Peak memory 249164 kb
Host smart-869d7513-2484-4b59-92f7-6fb211c16f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
36988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4227336988
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3981091170
Short name T114
Test name
Test status
Simulation time 12648449636 ps
CPU time 173.19 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:17:48 PM PDT 24
Peak memory 257008 kb
Host smart-c65f3089-8fdb-4041-89ad-dff76651bf1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981091170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3981091170
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1561235591
Short name T275
Test name
Test status
Simulation time 488300650504 ps
CPU time 5179.6 seconds
Started May 09 03:14:53 PM PDT 24
Finished May 09 04:41:16 PM PDT 24
Peak memory 305900 kb
Host smart-31dd9292-87d4-4db2-a6d0-d998b2bc184e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561235591 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1561235591
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2865720955
Short name T219
Test name
Test status
Simulation time 13405309 ps
CPU time 2.54 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:15:07 PM PDT 24
Peak memory 248932 kb
Host smart-0e08212d-20c7-4bab-8db5-391f537ce49f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2865720955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2865720955
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1942430233
Short name T85
Test name
Test status
Simulation time 95251113414 ps
CPU time 1422.61 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:38:48 PM PDT 24
Peak memory 267404 kb
Host smart-7c498078-4472-4b33-b772-9cc8bdf043aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942430233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1942430233
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2774368576
Short name T548
Test name
Test status
Simulation time 1220061492 ps
CPU time 26.81 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:15:32 PM PDT 24
Peak memory 248784 kb
Host smart-e58ae669-a951-4d8b-a940-fa117109598b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2774368576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2774368576
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2510989767
Short name T509
Test name
Test status
Simulation time 563679449 ps
CPU time 16.36 seconds
Started May 09 03:14:57 PM PDT 24
Finished May 09 03:15:16 PM PDT 24
Peak memory 255844 kb
Host smart-85595091-758c-4555-ab85-027114d3d9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
89767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2510989767
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2572199044
Short name T581
Test name
Test status
Simulation time 414882703 ps
CPU time 26.82 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:15:22 PM PDT 24
Peak memory 255496 kb
Host smart-f3809d7f-04dd-4e94-9377-d2186c469b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721
99044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2572199044
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3290132434
Short name T696
Test name
Test status
Simulation time 46617473013 ps
CPU time 1087.94 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:33:12 PM PDT 24
Peak memory 269380 kb
Host smart-c4f05b46-6c14-4512-a013-4409349c57b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290132434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3290132434
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3663473953
Short name T115
Test name
Test status
Simulation time 75590456338 ps
CPU time 2676.34 seconds
Started May 09 03:15:03 PM PDT 24
Finished May 09 03:59:42 PM PDT 24
Peak memory 289376 kb
Host smart-1833fe7f-b5db-49e8-8e07-7dd1b67d081f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663473953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3663473953
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1328832786
Short name T307
Test name
Test status
Simulation time 13286870076 ps
CPU time 316.3 seconds
Started May 09 03:15:04 PM PDT 24
Finished May 09 03:20:22 PM PDT 24
Peak memory 248280 kb
Host smart-2324f04d-ac2f-4eca-a3b4-ee83ccf5f124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328832786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1328832786
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1354990630
Short name T478
Test name
Test status
Simulation time 647014003 ps
CPU time 39.78 seconds
Started May 09 03:14:57 PM PDT 24
Finished May 09 03:15:39 PM PDT 24
Peak memory 248780 kb
Host smart-9ea9aaaf-67d3-4bcd-958a-5b8a90f8681e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13549
90630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1354990630
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2029745220
Short name T388
Test name
Test status
Simulation time 751163908 ps
CPU time 33.11 seconds
Started May 09 03:14:52 PM PDT 24
Finished May 09 03:15:28 PM PDT 24
Peak memory 247560 kb
Host smart-4597a8ee-7fca-4139-a020-d3296b570247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20297
45220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2029745220
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4009536105
Short name T620
Test name
Test status
Simulation time 2293147991 ps
CPU time 47.47 seconds
Started May 09 03:14:51 PM PDT 24
Finished May 09 03:15:41 PM PDT 24
Peak memory 256200 kb
Host smart-bb4b68ed-8f5f-445a-bd12-a517ef191d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
36105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4009536105
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.390890689
Short name T367
Test name
Test status
Simulation time 132343503 ps
CPU time 9.25 seconds
Started May 09 03:14:56 PM PDT 24
Finished May 09 03:15:08 PM PDT 24
Peak memory 251972 kb
Host smart-c2e519bd-e449-455c-ab8b-8c856eb5fd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39089
0689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.390890689
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3795379842
Short name T510
Test name
Test status
Simulation time 15122621505 ps
CPU time 163.91 seconds
Started May 09 03:15:05 PM PDT 24
Finished May 09 03:17:51 PM PDT 24
Peak memory 256968 kb
Host smart-02309fe5-7b3b-46be-b85f-dfd6b9e338a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795379842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3795379842
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.108593122
Short name T216
Test name
Test status
Simulation time 84408414 ps
CPU time 3.32 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:15:09 PM PDT 24
Peak memory 248968 kb
Host smart-a4c24ece-107a-4548-8b96-96359a2bc9f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=108593122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.108593122
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3379732746
Short name T57
Test name
Test status
Simulation time 55255462720 ps
CPU time 3241.28 seconds
Started May 09 03:15:03 PM PDT 24
Finished May 09 04:09:07 PM PDT 24
Peak memory 288676 kb
Host smart-2261d73a-4097-4e05-919d-77d0639296c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379732746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3379732746
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1782177565
Short name T200
Test name
Test status
Simulation time 461259770 ps
CPU time 23.14 seconds
Started May 09 03:15:04 PM PDT 24
Finished May 09 03:15:29 PM PDT 24
Peak memory 248816 kb
Host smart-4e443550-7312-4134-9c00-b1cb58645f84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1782177565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1782177565
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1830499621
Short name T518
Test name
Test status
Simulation time 2800062609 ps
CPU time 44.54 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:15:50 PM PDT 24
Peak memory 248972 kb
Host smart-9f3e1027-e7b4-439d-be93-4118dc936c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18304
99621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1830499621
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2663698262
Short name T613
Test name
Test status
Simulation time 1620448453 ps
CPU time 21.31 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:15:26 PM PDT 24
Peak memory 248784 kb
Host smart-68c389bd-9628-48bf-8e75-878b1da36415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26636
98262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2663698262
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3402457272
Short name T336
Test name
Test status
Simulation time 168360863872 ps
CPU time 2683.36 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:59:47 PM PDT 24
Peak memory 289340 kb
Host smart-fd38c6c9-3e1c-4cfb-ae44-1e572c9436c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402457272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3402457272
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2676334237
Short name T37
Test name
Test status
Simulation time 6567539505 ps
CPU time 222.31 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:18:47 PM PDT 24
Peak memory 248032 kb
Host smart-27ef4d42-e855-4834-b6ab-09be5b2d4e06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676334237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2676334237
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2255039378
Short name T599
Test name
Test status
Simulation time 866066218 ps
CPU time 15.69 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:15:21 PM PDT 24
Peak memory 248776 kb
Host smart-f01de0f7-4cf7-4418-9d3f-948a1b0b01b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22550
39378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2255039378
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3101504962
Short name T378
Test name
Test status
Simulation time 1104695191 ps
CPU time 20.56 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:15:26 PM PDT 24
Peak memory 248616 kb
Host smart-36a41b5f-6ece-4331-9c54-45ad35c6e28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015
04962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3101504962
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2087398791
Short name T279
Test name
Test status
Simulation time 103640160 ps
CPU time 10.97 seconds
Started May 09 03:15:01 PM PDT 24
Finished May 09 03:15:15 PM PDT 24
Peak memory 254480 kb
Host smart-7116f767-696b-4680-bfcf-833faf0bebde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20873
98791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2087398791
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.41642490
Short name T506
Test name
Test status
Simulation time 1959362297 ps
CPU time 60.08 seconds
Started May 09 03:15:02 PM PDT 24
Finished May 09 03:16:05 PM PDT 24
Peak memory 249076 kb
Host smart-44c7be57-1957-408f-a09f-b943b9703ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41642
490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.41642490
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2187605854
Short name T220
Test name
Test status
Simulation time 158601755 ps
CPU time 3.42 seconds
Started May 09 03:15:12 PM PDT 24
Finished May 09 03:15:17 PM PDT 24
Peak memory 248944 kb
Host smart-524d1cba-a476-4199-86b1-0e972bfd5145
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2187605854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2187605854
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3460312446
Short name T503
Test name
Test status
Simulation time 23389140011 ps
CPU time 841.41 seconds
Started May 09 03:15:15 PM PDT 24
Finished May 09 03:29:18 PM PDT 24
Peak memory 272860 kb
Host smart-f19da93a-c473-4d10-8287-480d09bb8202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460312446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3460312446
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2318141596
Short name T520
Test name
Test status
Simulation time 1468103718 ps
CPU time 20.33 seconds
Started May 09 03:15:13 PM PDT 24
Finished May 09 03:15:35 PM PDT 24
Peak memory 248824 kb
Host smart-903bf39f-b5a3-47ef-b204-ca6446b4f30c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2318141596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2318141596
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3930624668
Short name T126
Test name
Test status
Simulation time 17567149230 ps
CPU time 256.8 seconds
Started May 09 03:15:13 PM PDT 24
Finished May 09 03:19:32 PM PDT 24
Peak memory 257044 kb
Host smart-6b1a9c1c-e9d5-4883-9a62-f52203efedc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39306
24668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3930624668
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4159213933
Short name T404
Test name
Test status
Simulation time 868438363 ps
CPU time 67.08 seconds
Started May 09 03:15:14 PM PDT 24
Finished May 09 03:16:23 PM PDT 24
Peak memory 248868 kb
Host smart-805ad31d-6179-4c3b-b0f6-449bdbd96a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592
13933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4159213933
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.340650904
Short name T243
Test name
Test status
Simulation time 102897564297 ps
CPU time 3032.42 seconds
Started May 09 03:15:14 PM PDT 24
Finished May 09 04:05:48 PM PDT 24
Peak memory 289220 kb
Host smart-fadf46e4-4e6e-47ed-a05c-63bf18b89d63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340650904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.340650904
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2158675101
Short name T235
Test name
Test status
Simulation time 3480915682 ps
CPU time 153.22 seconds
Started May 09 03:15:13 PM PDT 24
Finished May 09 03:17:48 PM PDT 24
Peak memory 248256 kb
Host smart-0c6ae409-a3b6-4ee4-8b68-701b5e266524
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158675101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2158675101
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2102112899
Short name T409
Test name
Test status
Simulation time 173515498 ps
CPU time 12.32 seconds
Started May 09 03:15:05 PM PDT 24
Finished May 09 03:15:19 PM PDT 24
Peak memory 254308 kb
Host smart-4bb6e0ff-b8a2-4605-ab1d-6646a54956a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21021
12899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2102112899
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.689133951
Short name T650
Test name
Test status
Simulation time 1064149406 ps
CPU time 36.31 seconds
Started May 09 03:15:03 PM PDT 24
Finished May 09 03:15:42 PM PDT 24
Peak memory 255956 kb
Host smart-bce5e803-0771-4f3d-ad2c-bfba24f35c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68913
3951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.689133951
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3628927279
Short name T471
Test name
Test status
Simulation time 2468777931 ps
CPU time 14.8 seconds
Started May 09 03:15:14 PM PDT 24
Finished May 09 03:15:31 PM PDT 24
Peak memory 255604 kb
Host smart-7057aa51-83e4-4617-bfc7-31a82f3a8df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
27279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3628927279
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4167361179
Short name T457
Test name
Test status
Simulation time 1266284804 ps
CPU time 35.62 seconds
Started May 09 03:15:03 PM PDT 24
Finished May 09 03:15:41 PM PDT 24
Peak memory 248928 kb
Host smart-66f4a602-8641-440d-a43b-a4273eed00fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
61179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4167361179
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2440148307
Short name T35
Test name
Test status
Simulation time 23507928 ps
CPU time 2.41 seconds
Started May 09 03:13:56 PM PDT 24
Finished May 09 03:14:01 PM PDT 24
Peak memory 248912 kb
Host smart-adb391b3-f473-4451-adf0-edc83498b9f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2440148307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2440148307
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3853214182
Short name T662
Test name
Test status
Simulation time 144608468377 ps
CPU time 2188.87 seconds
Started May 09 03:13:56 PM PDT 24
Finished May 09 03:50:27 PM PDT 24
Peak memory 281564 kb
Host smart-42127944-8d9b-4dca-9645-3a5263c459c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853214182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3853214182
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2215537456
Short name T555
Test name
Test status
Simulation time 850257865 ps
CPU time 11.02 seconds
Started May 09 03:13:53 PM PDT 24
Finished May 09 03:14:06 PM PDT 24
Peak memory 248796 kb
Host smart-ec7fed68-89f8-4392-94ca-bbd6969474f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2215537456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2215537456
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1560351553
Short name T645
Test name
Test status
Simulation time 287786573 ps
CPU time 31 seconds
Started May 09 03:13:42 PM PDT 24
Finished May 09 03:14:16 PM PDT 24
Peak memory 248912 kb
Host smart-ba390953-9e7c-430e-beeb-90bde25d89f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
51553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1560351553
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3921442260
Short name T703
Test name
Test status
Simulation time 173771480 ps
CPU time 4.15 seconds
Started May 09 03:13:56 PM PDT 24
Finished May 09 03:14:01 PM PDT 24
Peak memory 240540 kb
Host smart-a5c90770-9235-4e16-a29a-6f462cb7d880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39214
42260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3921442260
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3439967496
Short name T672
Test name
Test status
Simulation time 92671366546 ps
CPU time 686.74 seconds
Started May 09 03:13:45 PM PDT 24
Finished May 09 03:25:13 PM PDT 24
Peak memory 273412 kb
Host smart-e64f1b30-5303-4e2f-8a31-bc4a0ef47ca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439967496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3439967496
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3444645269
Short name T129
Test name
Test status
Simulation time 60480673447 ps
CPU time 2020.18 seconds
Started May 09 03:13:54 PM PDT 24
Finished May 09 03:47:36 PM PDT 24
Peak memory 285148 kb
Host smart-16b6dd63-e8d7-4415-ba13-435463b03b91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444645269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3444645269
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1910390461
Short name T531
Test name
Test status
Simulation time 32562177179 ps
CPU time 352.68 seconds
Started May 09 03:13:45 PM PDT 24
Finished May 09 03:19:39 PM PDT 24
Peak memory 248324 kb
Host smart-409a82bc-ff8c-49b4-8947-d59e373ed9f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910390461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1910390461
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2429488397
Short name T603
Test name
Test status
Simulation time 270540268 ps
CPU time 8.27 seconds
Started May 09 03:13:44 PM PDT 24
Finished May 09 03:13:54 PM PDT 24
Peak memory 248796 kb
Host smart-11aa2013-f685-44ab-8cfe-223a993cfea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24294
88397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2429488397
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3656536930
Short name T591
Test name
Test status
Simulation time 228948342 ps
CPU time 9.04 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:14:06 PM PDT 24
Peak memory 248764 kb
Host smart-3fe80f08-69d1-4bbf-be6b-8c8f94dd4120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36565
36930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3656536930
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4068267033
Short name T33
Test name
Test status
Simulation time 755462692 ps
CPU time 32.2 seconds
Started May 09 03:13:54 PM PDT 24
Finished May 09 03:14:28 PM PDT 24
Peak memory 271428 kb
Host smart-7e858145-e6da-4733-86c7-ae5312f6679b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4068267033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4068267033
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1937953772
Short name T280
Test name
Test status
Simulation time 238935466 ps
CPU time 26.51 seconds
Started May 09 03:13:54 PM PDT 24
Finished May 09 03:14:22 PM PDT 24
Peak memory 248752 kb
Host smart-763d00ce-4a89-4832-aa30-e28b7095d73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
53772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1937953772
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2340901560
Short name T451
Test name
Test status
Simulation time 222290509 ps
CPU time 24.23 seconds
Started May 09 03:13:43 PM PDT 24
Finished May 09 03:14:09 PM PDT 24
Peak memory 248772 kb
Host smart-9930ee67-61ed-4444-985a-233f252ac32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
01560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2340901560
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.972344329
Short name T587
Test name
Test status
Simulation time 17221244025 ps
CPU time 158.38 seconds
Started May 09 03:15:13 PM PDT 24
Finished May 09 03:17:54 PM PDT 24
Peak memory 248924 kb
Host smart-d10b367b-279f-4fea-addc-441f2c002ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97234
4329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.972344329
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1018885464
Short name T432
Test name
Test status
Simulation time 46295308 ps
CPU time 5.94 seconds
Started May 09 03:15:12 PM PDT 24
Finished May 09 03:15:19 PM PDT 24
Peak memory 252012 kb
Host smart-ac6a0819-a562-452b-a05a-c52d6736b2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
85464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1018885464
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.674385076
Short name T556
Test name
Test status
Simulation time 782827941904 ps
CPU time 2954.44 seconds
Started May 09 03:15:14 PM PDT 24
Finished May 09 04:04:31 PM PDT 24
Peak memory 288876 kb
Host smart-ad632a7c-4a50-49d3-80bf-af02b2b14885
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674385076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.674385076
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.968503077
Short name T629
Test name
Test status
Simulation time 16631118088 ps
CPU time 202.4 seconds
Started May 09 03:15:14 PM PDT 24
Finished May 09 03:18:38 PM PDT 24
Peak memory 248256 kb
Host smart-c7061c44-c0b9-42a2-bca4-3707f7ea0afb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968503077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.968503077
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2172188407
Short name T15
Test name
Test status
Simulation time 595354116 ps
CPU time 40.79 seconds
Started May 09 03:15:15 PM PDT 24
Finished May 09 03:15:58 PM PDT 24
Peak memory 248756 kb
Host smart-4aa3681c-3ec2-4a42-bd29-56242f3870ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
88407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2172188407
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2536445157
Short name T401
Test name
Test status
Simulation time 899274963 ps
CPU time 17.32 seconds
Started May 09 03:15:10 PM PDT 24
Finished May 09 03:15:28 PM PDT 24
Peak memory 255632 kb
Host smart-7da6deb5-66e8-425d-a880-7971b537dd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25364
45157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2536445157
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4289580995
Short name T708
Test name
Test status
Simulation time 1901264840 ps
CPU time 21.77 seconds
Started May 09 03:15:14 PM PDT 24
Finished May 09 03:15:38 PM PDT 24
Peak memory 256296 kb
Host smart-d391c9e4-4b2b-44b2-9591-5fbe25183584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42895
80995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4289580995
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1117582781
Short name T524
Test name
Test status
Simulation time 1880452737 ps
CPU time 28.83 seconds
Started May 09 03:15:18 PM PDT 24
Finished May 09 03:15:48 PM PDT 24
Peak memory 248772 kb
Host smart-d6ea6a09-a08c-4098-a829-48171c8d9389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11175
82781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1117582781
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.4129746916
Short name T467
Test name
Test status
Simulation time 14751529379 ps
CPU time 1434.47 seconds
Started May 09 03:15:23 PM PDT 24
Finished May 09 03:39:19 PM PDT 24
Peak memory 284692 kb
Host smart-ec3d623d-3ab7-47d2-8e01-0c5c923de8a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129746916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4129746916
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3610225392
Short name T465
Test name
Test status
Simulation time 3258392209 ps
CPU time 155.01 seconds
Started May 09 03:15:23 PM PDT 24
Finished May 09 03:17:59 PM PDT 24
Peak memory 250216 kb
Host smart-7355ba87-989e-434c-96fb-9e567ff36ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102
25392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3610225392
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3145131144
Short name T436
Test name
Test status
Simulation time 530707414 ps
CPU time 9.93 seconds
Started May 09 03:15:23 PM PDT 24
Finished May 09 03:15:34 PM PDT 24
Peak memory 251036 kb
Host smart-1bddb938-dd4e-4d11-9330-e3723d48bf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31451
31144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3145131144
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1630451490
Short name T289
Test name
Test status
Simulation time 155480470945 ps
CPU time 1800.06 seconds
Started May 09 03:15:24 PM PDT 24
Finished May 09 03:45:26 PM PDT 24
Peak memory 272548 kb
Host smart-eed1dc51-19c4-4d10-8764-83b30becf822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630451490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1630451490
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1651935604
Short name T611
Test name
Test status
Simulation time 10412758444 ps
CPU time 1084.34 seconds
Started May 09 03:15:24 PM PDT 24
Finished May 09 03:33:30 PM PDT 24
Peak memory 288964 kb
Host smart-d4fdb2c3-f958-4a1c-b5e6-7255d54f2098
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651935604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1651935604
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3990375196
Short name T530
Test name
Test status
Simulation time 467113122 ps
CPU time 21.43 seconds
Started May 09 03:15:17 PM PDT 24
Finished May 09 03:15:39 PM PDT 24
Peak memory 248792 kb
Host smart-913ca06a-92f9-4d9c-b8b2-5f2cb5f3a08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
75196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3990375196
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2299407487
Short name T28
Test name
Test status
Simulation time 885974074 ps
CPU time 20.23 seconds
Started May 09 03:15:24 PM PDT 24
Finished May 09 03:15:46 PM PDT 24
Peak memory 248784 kb
Host smart-f91fb0c7-f5cd-419e-91f8-ab57ed9f7c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22994
07487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2299407487
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3294577482
Short name T642
Test name
Test status
Simulation time 577127653 ps
CPU time 16.87 seconds
Started May 09 03:15:22 PM PDT 24
Finished May 09 03:15:40 PM PDT 24
Peak memory 247584 kb
Host smart-80cda4cd-ceac-48d3-8233-908f6e4e36ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32945
77482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3294577482
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2407012980
Short name T96
Test name
Test status
Simulation time 4442442918 ps
CPU time 48.18 seconds
Started May 09 03:15:15 PM PDT 24
Finished May 09 03:16:05 PM PDT 24
Peak memory 255856 kb
Host smart-6ca722c8-c3f0-47de-b410-13ef0cdeb0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24070
12980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2407012980
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1886741403
Short name T615
Test name
Test status
Simulation time 23593870764 ps
CPU time 596.65 seconds
Started May 09 03:15:24 PM PDT 24
Finished May 09 03:25:23 PM PDT 24
Peak memory 273524 kb
Host smart-3b85d271-4fbd-46f2-a34d-278762b3fdb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886741403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1886741403
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3051114195
Short name T255
Test name
Test status
Simulation time 4035413432 ps
CPU time 161.64 seconds
Started May 09 03:15:36 PM PDT 24
Finished May 09 03:18:20 PM PDT 24
Peak memory 256784 kb
Host smart-69ec0c84-e178-4a5e-91f3-04433821b2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30511
14195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3051114195
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3799199154
Short name T453
Test name
Test status
Simulation time 1490277177 ps
CPU time 31.21 seconds
Started May 09 03:15:37 PM PDT 24
Finished May 09 03:16:10 PM PDT 24
Peak memory 255928 kb
Host smart-42b44c17-437a-41a4-ae78-9543f985c044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37991
99154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3799199154
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.964405440
Short name T196
Test name
Test status
Simulation time 149654412844 ps
CPU time 1672.19 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:43:30 PM PDT 24
Peak memory 288896 kb
Host smart-47e14456-889e-4a89-abd5-099e0cc7fae6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964405440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.964405440
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.636254462
Short name T494
Test name
Test status
Simulation time 137958119455 ps
CPU time 2179.89 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:51:57 PM PDT 24
Peak memory 285132 kb
Host smart-4d9af903-75aa-4102-9c40-8f889ef3549b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636254462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.636254462
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.560800834
Short name T670
Test name
Test status
Simulation time 17884299929 ps
CPU time 376.59 seconds
Started May 09 03:15:36 PM PDT 24
Finished May 09 03:21:55 PM PDT 24
Peak memory 248112 kb
Host smart-85edb156-0e01-418b-a14b-4df9622304bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560800834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.560800834
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4037389959
Short name T608
Test name
Test status
Simulation time 679934548 ps
CPU time 27.56 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:16:04 PM PDT 24
Peak memory 248800 kb
Host smart-67851832-f4a4-448f-8f0a-172d3ad7bedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
89959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4037389959
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1516882254
Short name T439
Test name
Test status
Simulation time 3041304812 ps
CPU time 33.25 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:16:09 PM PDT 24
Peak memory 248880 kb
Host smart-bd99243d-5c64-47e7-8569-e79b69c96c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15168
82254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1516882254
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1181861296
Short name T198
Test name
Test status
Simulation time 681674206 ps
CPU time 45.41 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:16:23 PM PDT 24
Peak memory 256192 kb
Host smart-47d061af-04e0-47ab-bfe0-a154fecf0717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11818
61296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1181861296
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1161865295
Short name T43
Test name
Test status
Simulation time 451922120 ps
CPU time 40.03 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:16:16 PM PDT 24
Peak memory 256024 kb
Host smart-83bd4839-8bc3-4064-874d-7512473d5201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11618
65295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1161865295
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1640713664
Short name T622
Test name
Test status
Simulation time 32317878657 ps
CPU time 2085.26 seconds
Started May 09 03:15:39 PM PDT 24
Finished May 09 03:50:25 PM PDT 24
Peak memory 284756 kb
Host smart-d75a41f0-212f-439b-8743-0521cf2af17f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640713664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1640713664
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2442498755
Short name T400
Test name
Test status
Simulation time 48129215600 ps
CPU time 1770.03 seconds
Started May 09 03:15:36 PM PDT 24
Finished May 09 03:45:08 PM PDT 24
Peak memory 281604 kb
Host smart-ecc0e173-ee8f-4809-80af-332672c8bf56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442498755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2442498755
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1895638476
Short name T281
Test name
Test status
Simulation time 23676814474 ps
CPU time 204.13 seconds
Started May 09 03:15:37 PM PDT 24
Finished May 09 03:19:03 PM PDT 24
Peak memory 250208 kb
Host smart-4e2c40a4-f783-4898-b4a9-5f124b8039db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18956
38476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1895638476
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.491528530
Short name T132
Test name
Test status
Simulation time 936044845 ps
CPU time 60.81 seconds
Started May 09 03:15:36 PM PDT 24
Finished May 09 03:16:39 PM PDT 24
Peak memory 256084 kb
Host smart-79c3df93-994c-4cd8-88fb-0f798a1ab1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49152
8530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.491528530
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3317894468
Short name T4
Test name
Test status
Simulation time 21459035742 ps
CPU time 1312.85 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:37:30 PM PDT 24
Peak memory 273412 kb
Host smart-d9ec7b02-bfe5-4ae8-a0a2-a78717ae7119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317894468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3317894468
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.994940600
Short name T377
Test name
Test status
Simulation time 63214266339 ps
CPU time 1096.9 seconds
Started May 09 03:15:47 PM PDT 24
Finished May 09 03:34:05 PM PDT 24
Peak memory 281656 kb
Host smart-8afc02dc-35eb-49e1-b5cc-6b82a2cb2041
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994940600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.994940600
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2159127580
Short name T525
Test name
Test status
Simulation time 364429044 ps
CPU time 37.03 seconds
Started May 09 03:15:33 PM PDT 24
Finished May 09 03:16:11 PM PDT 24
Peak memory 248756 kb
Host smart-896e807d-540f-4372-b185-dd095cf9116f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21591
27580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2159127580
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4030775405
Short name T287
Test name
Test status
Simulation time 2604600610 ps
CPU time 33.61 seconds
Started May 09 03:15:35 PM PDT 24
Finished May 09 03:16:10 PM PDT 24
Peak memory 256444 kb
Host smart-e0f06726-a7eb-458a-82dd-62119c7c64d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40307
75405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4030775405
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1248167193
Short name T655
Test name
Test status
Simulation time 33021632 ps
CPU time 5.08 seconds
Started May 09 03:15:38 PM PDT 24
Finished May 09 03:15:45 PM PDT 24
Peak memory 251008 kb
Host smart-8a533df6-d48e-4d09-ad13-16dfb53e58e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
67193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1248167193
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2771523487
Short name T486
Test name
Test status
Simulation time 980327780 ps
CPU time 32.4 seconds
Started May 09 03:15:36 PM PDT 24
Finished May 09 03:16:10 PM PDT 24
Peak memory 248720 kb
Host smart-2c46c764-22c8-41f8-a8df-e00762ddde9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
23487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2771523487
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2919997149
Short name T569
Test name
Test status
Simulation time 47844713413 ps
CPU time 2708.83 seconds
Started May 09 03:15:49 PM PDT 24
Finished May 09 04:00:58 PM PDT 24
Peak memory 288856 kb
Host smart-f141836b-9723-4ff1-966f-b16f618fe845
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919997149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2919997149
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2142467929
Short name T247
Test name
Test status
Simulation time 75150266694 ps
CPU time 2068.73 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:50:16 PM PDT 24
Peak memory 306340 kb
Host smart-c2adfc86-9082-478c-881d-aa1d686b4918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142467929 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2142467929
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2684835774
Short name T414
Test name
Test status
Simulation time 75818920817 ps
CPU time 712.71 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:27:40 PM PDT 24
Peak memory 265244 kb
Host smart-e2f4cab6-53a3-4276-b99c-daf1e92987c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684835774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2684835774
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2253136850
Short name T484
Test name
Test status
Simulation time 3331549934 ps
CPU time 97.03 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:17:24 PM PDT 24
Peak memory 256848 kb
Host smart-50e57fc2-18a0-4a78-ae1f-94648b71d1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
36850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2253136850
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1529639960
Short name T573
Test name
Test status
Simulation time 1637814515 ps
CPU time 52.79 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:16:40 PM PDT 24
Peak memory 255956 kb
Host smart-2e1cd5ab-18e1-4de4-9baf-f2c266171f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15296
39960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1529639960
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.4175058304
Short name T341
Test name
Test status
Simulation time 31357015309 ps
CPU time 1179.53 seconds
Started May 09 03:15:49 PM PDT 24
Finished May 09 03:35:29 PM PDT 24
Peak memory 272080 kb
Host smart-9d75a84f-58b2-4a87-a57a-bee76ae41f04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175058304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.4175058304
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3859642647
Short name T38
Test name
Test status
Simulation time 104243548395 ps
CPU time 3330.22 seconds
Started May 09 03:15:45 PM PDT 24
Finished May 09 04:11:17 PM PDT 24
Peak memory 289368 kb
Host smart-757beb5f-78c4-4882-ac39-4320bd692229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859642647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3859642647
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2881385434
Short name T416
Test name
Test status
Simulation time 116427999 ps
CPU time 8.73 seconds
Started May 09 03:15:52 PM PDT 24
Finished May 09 03:16:02 PM PDT 24
Peak memory 248752 kb
Host smart-fbc64109-8e84-4bb4-a6e4-9be292a40c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28813
85434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2881385434
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3272878951
Short name T440
Test name
Test status
Simulation time 1845253786 ps
CPU time 28.22 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:16:15 PM PDT 24
Peak memory 255656 kb
Host smart-d6d1a416-058a-4571-802c-f51878c77b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
78951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3272878951
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1890682048
Short name T448
Test name
Test status
Simulation time 123872868 ps
CPU time 5.42 seconds
Started May 09 03:15:52 PM PDT 24
Finished May 09 03:15:58 PM PDT 24
Peak memory 240536 kb
Host smart-a8c6a5d3-0549-43bf-ad8b-625cf57fc308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18906
82048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1890682048
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.550658519
Short name T507
Test name
Test status
Simulation time 3499546588 ps
CPU time 50.57 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:16:38 PM PDT 24
Peak memory 256996 kb
Host smart-90d18fb5-fe5e-4481-95b5-89f09cf82340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55065
8519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.550658519
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3769957519
Short name T260
Test name
Test status
Simulation time 73669676775 ps
CPU time 4207.38 seconds
Started May 09 03:15:47 PM PDT 24
Finished May 09 04:25:56 PM PDT 24
Peak memory 298024 kb
Host smart-b6503d81-a4d0-4309-b540-8386d34a2731
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769957519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3769957519
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.455798885
Short name T81
Test name
Test status
Simulation time 32548923062 ps
CPU time 1953.75 seconds
Started May 09 03:15:49 PM PDT 24
Finished May 09 03:48:23 PM PDT 24
Peak memory 281644 kb
Host smart-2720e6e8-a238-4865-83a0-766c5dede1fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455798885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.455798885
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3826269094
Short name T458
Test name
Test status
Simulation time 33775943120 ps
CPU time 233.34 seconds
Started May 09 03:15:44 PM PDT 24
Finished May 09 03:19:39 PM PDT 24
Peak memory 251948 kb
Host smart-c44701a2-708f-4f50-a186-0799d89a9874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262
69094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3826269094
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1106949060
Short name T625
Test name
Test status
Simulation time 114735686 ps
CPU time 11.23 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:15:59 PM PDT 24
Peak memory 255348 kb
Host smart-e7162e57-2431-4cd6-860a-70106f3b9465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11069
49060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1106949060
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1590507238
Short name T485
Test name
Test status
Simulation time 125577209463 ps
CPU time 1936.61 seconds
Started May 09 03:15:55 PM PDT 24
Finished May 09 03:48:13 PM PDT 24
Peak memory 286004 kb
Host smart-3dda7096-d040-41ea-b1e3-5ba1bd8995f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590507238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1590507238
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2249611553
Short name T370
Test name
Test status
Simulation time 2240404390 ps
CPU time 40.46 seconds
Started May 09 03:15:46 PM PDT 24
Finished May 09 03:16:28 PM PDT 24
Peak memory 248916 kb
Host smart-3c9ed9ec-2ffd-41bb-b920-17dfd422d807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22496
11553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2249611553
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2720299985
Short name T368
Test name
Test status
Simulation time 222665219 ps
CPU time 17.4 seconds
Started May 09 03:15:49 PM PDT 24
Finished May 09 03:16:07 PM PDT 24
Peak memory 248760 kb
Host smart-6ce9c264-4784-4edb-aede-d37bcb8ee5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
99985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2720299985
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2699725993
Short name T641
Test name
Test status
Simulation time 1597310341 ps
CPU time 36.85 seconds
Started May 09 03:15:44 PM PDT 24
Finished May 09 03:16:22 PM PDT 24
Peak memory 256160 kb
Host smart-c779752f-462e-496e-8358-2015f408234b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26997
25993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2699725993
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.505519884
Short name T286
Test name
Test status
Simulation time 29136821854 ps
CPU time 1657.64 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:43:35 PM PDT 24
Peak memory 289700 kb
Host smart-224edb5d-45f7-4e1c-9aa8-a5f8955797a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505519884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.505519884
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4051266818
Short name T117
Test name
Test status
Simulation time 51272182071 ps
CPU time 1226.11 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:36:23 PM PDT 24
Peak memory 281252 kb
Host smart-f76a35e0-19c7-4f72-9f21-dda3aee7dfc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051266818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4051266818
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3438437092
Short name T482
Test name
Test status
Simulation time 8024028719 ps
CPU time 253.84 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:20:12 PM PDT 24
Peak memory 256980 kb
Host smart-4300fd70-88b0-4f2d-aef1-6ab5d6768f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34384
37092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3438437092
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.126942662
Short name T481
Test name
Test status
Simulation time 467529076 ps
CPU time 13.86 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:16:11 PM PDT 24
Peak memory 248788 kb
Host smart-281bd336-8cb3-41de-8748-8aba69fe193d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
2662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.126942662
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1505961614
Short name T338
Test name
Test status
Simulation time 70900199808 ps
CPU time 2409.06 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:56:07 PM PDT 24
Peak memory 288800 kb
Host smart-79820e31-9b92-4845-b090-1134ea5164f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505961614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1505961614
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1007746842
Short name T119
Test name
Test status
Simulation time 95093544656 ps
CPU time 1554.45 seconds
Started May 09 03:15:57 PM PDT 24
Finished May 09 03:41:53 PM PDT 24
Peak memory 273388 kb
Host smart-fee8625d-d5e1-4b90-a3a4-88fe0cc9c5ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007746842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1007746842
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2673144083
Short name T42
Test name
Test status
Simulation time 1005796573 ps
CPU time 73.56 seconds
Started May 09 03:15:58 PM PDT 24
Finished May 09 03:17:13 PM PDT 24
Peak memory 256132 kb
Host smart-077d2a5b-c0a7-4efa-ad6c-a9700756b1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
44083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2673144083
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1993163894
Short name T605
Test name
Test status
Simulation time 840575235 ps
CPU time 15.88 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:16:13 PM PDT 24
Peak memory 248760 kb
Host smart-033a54a6-9372-464f-b2d9-3532f97e5223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19931
63894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1993163894
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1523180979
Short name T519
Test name
Test status
Simulation time 524477884 ps
CPU time 8.12 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 03:16:05 PM PDT 24
Peak memory 250812 kb
Host smart-a8063a7e-3700-4997-a087-0e1b62ec06bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15231
80979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1523180979
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2444854991
Short name T375
Test name
Test status
Simulation time 312265633 ps
CPU time 28.82 seconds
Started May 09 03:15:58 PM PDT 24
Finished May 09 03:16:28 PM PDT 24
Peak memory 248772 kb
Host smart-30ad28f9-2f22-4138-8791-dbe3f2fa821c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24448
54991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2444854991
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3432339878
Short name T74
Test name
Test status
Simulation time 9237577390 ps
CPU time 188.25 seconds
Started May 09 03:15:58 PM PDT 24
Finished May 09 03:19:07 PM PDT 24
Peak memory 256984 kb
Host smart-e541184c-91d6-472e-9e80-a50d68a27804
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432339878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3432339878
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1505043797
Short name T192
Test name
Test status
Simulation time 136814515902 ps
CPU time 3019.92 seconds
Started May 09 03:15:56 PM PDT 24
Finished May 09 04:06:17 PM PDT 24
Peak memory 298524 kb
Host smart-a623ef58-047b-4503-838f-944afc75f428
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505043797 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1505043797
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3300672985
Short name T648
Test name
Test status
Simulation time 22148590914 ps
CPU time 1656.5 seconds
Started May 09 03:16:07 PM PDT 24
Finished May 09 03:43:45 PM PDT 24
Peak memory 273408 kb
Host smart-ab95503a-e4b2-47eb-95c6-4cdd5b38898c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300672985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3300672985
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.380519075
Short name T208
Test name
Test status
Simulation time 48113088 ps
CPU time 4.29 seconds
Started May 09 03:16:08 PM PDT 24
Finished May 09 03:16:14 PM PDT 24
Peak memory 239276 kb
Host smart-20bea89f-2eba-4b0e-b5e4-e91b1b4120de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38051
9075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.380519075
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.309839391
Short name T394
Test name
Test status
Simulation time 161236013 ps
CPU time 25.15 seconds
Started May 09 03:16:12 PM PDT 24
Finished May 09 03:16:38 PM PDT 24
Peak memory 248688 kb
Host smart-f0a9fb6b-0b72-499f-8ac7-5daa74d1417d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
9391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.309839391
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3693617779
Short name T351
Test name
Test status
Simulation time 71209300234 ps
CPU time 2226.22 seconds
Started May 09 03:16:07 PM PDT 24
Finished May 09 03:53:15 PM PDT 24
Peak memory 281652 kb
Host smart-02ca9f1d-309d-49e9-8af4-e5997ced0db4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693617779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3693617779
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2038587853
Short name T428
Test name
Test status
Simulation time 21952904986 ps
CPU time 1248.75 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:37:00 PM PDT 24
Peak memory 284652 kb
Host smart-78d67b02-610c-43a9-a7eb-9c0c451fb212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038587853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2038587853
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.32608056
Short name T310
Test name
Test status
Simulation time 91013179864 ps
CPU time 197.19 seconds
Started May 09 03:16:09 PM PDT 24
Finished May 09 03:19:27 PM PDT 24
Peak memory 248112 kb
Host smart-ef568ea8-f5aa-4e0b-9f80-872ba3194c73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32608056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.32608056
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.17240338
Short name T492
Test name
Test status
Simulation time 883393790 ps
CPU time 50.03 seconds
Started May 09 03:15:58 PM PDT 24
Finished May 09 03:16:49 PM PDT 24
Peak memory 248844 kb
Host smart-2eecff02-c431-4971-ba0c-6bfa971db71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240
338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.17240338
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1662550241
Short name T391
Test name
Test status
Simulation time 1893701585 ps
CPU time 35.38 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:16:47 PM PDT 24
Peak memory 254640 kb
Host smart-1c51f6a3-d2b1-4d9f-849b-b41f765d9d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16625
50241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1662550241
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.693300669
Short name T22
Test name
Test status
Simulation time 1349642438 ps
CPU time 26.2 seconds
Started May 09 03:16:07 PM PDT 24
Finished May 09 03:16:35 PM PDT 24
Peak memory 253908 kb
Host smart-eb46fa4b-b101-45d8-8089-ea118c11ad53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69330
0669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.693300669
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3261028531
Short name T95
Test name
Test status
Simulation time 772575764 ps
CPU time 51.5 seconds
Started May 09 03:15:57 PM PDT 24
Finished May 09 03:16:50 PM PDT 24
Peak memory 248760 kb
Host smart-027559f9-c9e6-46e0-a765-1611dd79d220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32610
28531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3261028531
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2768803136
Short name T120
Test name
Test status
Simulation time 38345059185 ps
CPU time 2464.39 seconds
Started May 09 03:16:12 PM PDT 24
Finished May 09 03:57:18 PM PDT 24
Peak memory 289236 kb
Host smart-786e5431-66ab-4963-8a85-f56c2c55bb00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768803136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2768803136
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3141211930
Short name T575
Test name
Test status
Simulation time 1470270909 ps
CPU time 87.63 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:17:39 PM PDT 24
Peak memory 256936 kb
Host smart-fc2d93a9-fdc8-4846-943f-ba5be08d0ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31412
11930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3141211930
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2479413260
Short name T710
Test name
Test status
Simulation time 1341077261 ps
CPU time 30.38 seconds
Started May 09 03:16:12 PM PDT 24
Finished May 09 03:16:43 PM PDT 24
Peak memory 256020 kb
Host smart-519bf93d-16ba-400b-863a-7ca0af4e9aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794
13260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2479413260
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2953603612
Short name T339
Test name
Test status
Simulation time 10808806872 ps
CPU time 992.52 seconds
Started May 09 03:16:09 PM PDT 24
Finished May 09 03:32:43 PM PDT 24
Peak memory 272772 kb
Host smart-34035b0d-0dbc-4f3d-a231-9440ddb7ec0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953603612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2953603612
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2837971263
Short name T11
Test name
Test status
Simulation time 24744702973 ps
CPU time 1586.72 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:42:38 PM PDT 24
Peak memory 273352 kb
Host smart-09ba4451-8c88-448f-8fc2-e42b97bcb57c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837971263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2837971263
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2796761269
Short name T228
Test name
Test status
Simulation time 4316209243 ps
CPU time 157.83 seconds
Started May 09 03:16:07 PM PDT 24
Finished May 09 03:18:46 PM PDT 24
Peak memory 247000 kb
Host smart-3066b5ff-87fd-4d35-bcad-5f2261996f92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796761269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2796761269
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3627031656
Short name T651
Test name
Test status
Simulation time 2504334131 ps
CPU time 42.93 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:16:54 PM PDT 24
Peak memory 248800 kb
Host smart-85747388-38f7-4830-9109-f7cb2243313d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36270
31656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3627031656
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1962175601
Short name T21
Test name
Test status
Simulation time 669593719 ps
CPU time 44.56 seconds
Started May 09 03:16:07 PM PDT 24
Finished May 09 03:16:53 PM PDT 24
Peak memory 247556 kb
Host smart-3b2ddadc-2c21-4e18-b724-eb2974fc3d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621
75601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1962175601
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1550155466
Short name T424
Test name
Test status
Simulation time 1384971935 ps
CPU time 12.07 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:16:23 PM PDT 24
Peak memory 249092 kb
Host smart-34fd0a82-576e-45a8-89d7-9d93f7dd8dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
55466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1550155466
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4245682941
Short name T441
Test name
Test status
Simulation time 960718367 ps
CPU time 31.41 seconds
Started May 09 03:16:10 PM PDT 24
Finished May 09 03:16:43 PM PDT 24
Peak memory 248772 kb
Host smart-3b6ec66c-caa2-44b4-a04f-e7cc0a5edbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456
82941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4245682941
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2445552648
Short name T513
Test name
Test status
Simulation time 19170365593 ps
CPU time 1470.25 seconds
Started May 09 03:16:19 PM PDT 24
Finished May 09 03:40:50 PM PDT 24
Peak memory 265216 kb
Host smart-11c0d8af-0246-4731-8b2d-bd3613045329
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445552648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2445552648
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3216818478
Short name T450
Test name
Test status
Simulation time 6294696336 ps
CPU time 81.36 seconds
Started May 09 03:16:19 PM PDT 24
Finished May 09 03:17:41 PM PDT 24
Peak memory 248884 kb
Host smart-bf388ddb-a45c-45fd-bc9a-6feab991dc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32168
18478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3216818478
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2204545661
Short name T589
Test name
Test status
Simulation time 500403026 ps
CPU time 8.23 seconds
Started May 09 03:16:17 PM PDT 24
Finished May 09 03:16:26 PM PDT 24
Peak memory 250896 kb
Host smart-db8c90af-de35-493c-a689-ed177d09e39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22045
45661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2204545661
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1106589088
Short name T118
Test name
Test status
Simulation time 6644579001 ps
CPU time 707.75 seconds
Started May 09 03:16:18 PM PDT 24
Finished May 09 03:28:07 PM PDT 24
Peak memory 273332 kb
Host smart-06e4d6da-88b6-44e8-9834-8ee35789addb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106589088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1106589088
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.308403163
Short name T317
Test name
Test status
Simulation time 25602236736 ps
CPU time 442.83 seconds
Started May 09 03:16:18 PM PDT 24
Finished May 09 03:23:42 PM PDT 24
Peak memory 247992 kb
Host smart-5ea1c69c-6564-4272-a028-cc1e35de0d37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308403163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.308403163
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2678778083
Short name T690
Test name
Test status
Simulation time 4132144088 ps
CPU time 55.3 seconds
Started May 09 03:16:19 PM PDT 24
Finished May 09 03:17:15 PM PDT 24
Peak memory 257056 kb
Host smart-52bff7be-42bf-45a3-8877-084d165636d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26787
78083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2678778083
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2889243978
Short name T694
Test name
Test status
Simulation time 965232510 ps
CPU time 32.79 seconds
Started May 09 03:16:18 PM PDT 24
Finished May 09 03:16:51 PM PDT 24
Peak memory 248772 kb
Host smart-ba29db82-ffd6-4790-a678-750a5734dc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28892
43978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2889243978
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1563225902
Short name T73
Test name
Test status
Simulation time 2296212261 ps
CPU time 43.41 seconds
Started May 09 03:16:18 PM PDT 24
Finished May 09 03:17:02 PM PDT 24
Peak memory 248872 kb
Host smart-17506e58-20dc-4385-a2e2-8e39c6245fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15632
25902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1563225902
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1330844216
Short name T371
Test name
Test status
Simulation time 1153715674 ps
CPU time 22.72 seconds
Started May 09 03:16:19 PM PDT 24
Finished May 09 03:16:42 PM PDT 24
Peak memory 248800 kb
Host smart-d47ebf18-8f07-48d4-a609-4ac50473805d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13308
44216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1330844216
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.508041337
Short name T106
Test name
Test status
Simulation time 9482079928 ps
CPU time 143.85 seconds
Started May 09 03:16:19 PM PDT 24
Finished May 09 03:18:44 PM PDT 24
Peak memory 251040 kb
Host smart-ae6b1b6d-68cf-48a3-9adb-03517ab18005
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508041337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.508041337
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4212862398
Short name T212
Test name
Test status
Simulation time 130922699 ps
CPU time 3.6 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 03:14:13 PM PDT 24
Peak memory 248908 kb
Host smart-9d2248ac-2799-4ee2-becf-f077eea4d99c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4212862398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4212862398
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2040049765
Short name T637
Test name
Test status
Simulation time 11064249243 ps
CPU time 986.91 seconds
Started May 09 03:13:53 PM PDT 24
Finished May 09 03:30:21 PM PDT 24
Peak memory 273420 kb
Host smart-63476b16-4fce-4b5d-aba4-eadda3597a5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040049765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2040049765
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3869523466
Short name T469
Test name
Test status
Simulation time 1115102036 ps
CPU time 8.06 seconds
Started May 09 03:14:12 PM PDT 24
Finished May 09 03:14:21 PM PDT 24
Peak memory 248824 kb
Host smart-e0ea6078-9149-4a43-a156-08b5465c5488
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3869523466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3869523466
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1672606844
Short name T502
Test name
Test status
Simulation time 12949179465 ps
CPU time 225.57 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:17:42 PM PDT 24
Peak memory 256520 kb
Host smart-744343e2-7049-4f84-a5bd-128bbd5c7740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16726
06844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1672606844
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3795827785
Short name T437
Test name
Test status
Simulation time 1083721224 ps
CPU time 20 seconds
Started May 09 03:13:54 PM PDT 24
Finished May 09 03:14:15 PM PDT 24
Peak memory 255144 kb
Host smart-4a480c6f-0cef-46d2-bf61-12589137454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37958
27785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3795827785
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.981173570
Short name T397
Test name
Test status
Simulation time 214719202816 ps
CPU time 2322.12 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:52:40 PM PDT 24
Peak memory 289292 kb
Host smart-fa34d7db-ae93-43cb-a707-c1f088481183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981173570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.981173570
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3241934769
Short name T6
Test name
Test status
Simulation time 118718944103 ps
CPU time 339.52 seconds
Started May 09 03:13:53 PM PDT 24
Finished May 09 03:19:34 PM PDT 24
Peak memory 248132 kb
Host smart-3d8cf9dd-9b3b-4121-b0ae-915cecc6b765
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241934769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3241934769
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3770135428
Short name T487
Test name
Test status
Simulation time 125317327 ps
CPU time 12.22 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:14:09 PM PDT 24
Peak memory 248800 kb
Host smart-9349c72e-754b-4ac1-a81c-1c0a656c902d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37701
35428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3770135428
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1854767555
Short name T647
Test name
Test status
Simulation time 231599628 ps
CPU time 22.81 seconds
Started May 09 03:13:54 PM PDT 24
Finished May 09 03:14:19 PM PDT 24
Peak memory 248776 kb
Host smart-98c750e0-16b8-46f2-a8e5-d3ae8b12ecf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
67555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1854767555
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.4008094731
Short name T10
Test name
Test status
Simulation time 2438619434 ps
CPU time 24.98 seconds
Started May 09 03:14:06 PM PDT 24
Finished May 09 03:14:33 PM PDT 24
Peak memory 266564 kb
Host smart-872b36a6-4d43-4870-bc98-7cdde094e6fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4008094731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.4008094731
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.669632529
Short name T446
Test name
Test status
Simulation time 127045339 ps
CPU time 11.03 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:14:08 PM PDT 24
Peak memory 251832 kb
Host smart-aa443647-edbd-4eb3-a350-1127eea42b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66963
2529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.669632529
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3834366023
Short name T638
Test name
Test status
Simulation time 1149082759 ps
CPU time 39.97 seconds
Started May 09 03:13:55 PM PDT 24
Finished May 09 03:14:37 PM PDT 24
Peak memory 256116 kb
Host smart-b0282a38-ec22-4b53-98b5-4569449d1288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343
66023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3834366023
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3386892075
Short name T698
Test name
Test status
Simulation time 407555665938 ps
CPU time 2663.93 seconds
Started May 09 03:14:05 PM PDT 24
Finished May 09 03:58:32 PM PDT 24
Peak memory 289052 kb
Host smart-0a8a0e9e-22e5-472f-be7c-36f0afa6cd11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386892075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3386892075
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2471463832
Short name T688
Test name
Test status
Simulation time 31312321978 ps
CPU time 3935.8 seconds
Started May 09 03:14:05 PM PDT 24
Finished May 09 04:19:43 PM PDT 24
Peak memory 322020 kb
Host smart-da26e3e8-2836-4fdb-b64b-10018f95d9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471463832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2471463832
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1686613074
Short name T695
Test name
Test status
Simulation time 152864045406 ps
CPU time 2470.11 seconds
Started May 09 03:16:37 PM PDT 24
Finished May 09 03:57:48 PM PDT 24
Peak memory 289764 kb
Host smart-cf842e32-f86f-4e03-b346-016f0e481d31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686613074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1686613074
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4250649659
Short name T19
Test name
Test status
Simulation time 847504870 ps
CPU time 44.59 seconds
Started May 09 03:16:36 PM PDT 24
Finished May 09 03:17:22 PM PDT 24
Peak memory 248840 kb
Host smart-56032fb5-5a37-4355-8835-d6f09bdfe4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506
49659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4250649659
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2431205663
Short name T429
Test name
Test status
Simulation time 186574804 ps
CPU time 13.04 seconds
Started May 09 03:16:31 PM PDT 24
Finished May 09 03:16:44 PM PDT 24
Peak memory 253048 kb
Host smart-e922a450-7f37-4775-a547-20d22362c57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24312
05663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2431205663
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1962303604
Short name T346
Test name
Test status
Simulation time 28177852252 ps
CPU time 1423.54 seconds
Started May 09 03:16:36 PM PDT 24
Finished May 09 03:40:21 PM PDT 24
Peak memory 289708 kb
Host smart-cf7ead13-34d4-4a6d-a842-8a407e93dfa1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962303604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1962303604
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.37002897
Short name T547
Test name
Test status
Simulation time 8740185851 ps
CPU time 1255.47 seconds
Started May 09 03:16:28 PM PDT 24
Finished May 09 03:37:25 PM PDT 24
Peak memory 287280 kb
Host smart-aa501e12-8c2a-47a3-8f7d-bfa1d886a14e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37002897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.37002897
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.175781588
Short name T445
Test name
Test status
Simulation time 4569322796 ps
CPU time 191.8 seconds
Started May 09 03:16:37 PM PDT 24
Finished May 09 03:19:49 PM PDT 24
Peak memory 248180 kb
Host smart-f0333afb-8e24-447d-9ce2-b688dc635687
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175781588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.175781588
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2940499312
Short name T562
Test name
Test status
Simulation time 629537256 ps
CPU time 18.48 seconds
Started May 09 03:16:36 PM PDT 24
Finished May 09 03:16:55 PM PDT 24
Peak memory 248948 kb
Host smart-73ca024f-bb5e-410d-8d6e-7f08e221a1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29404
99312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2940499312
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.199836360
Short name T707
Test name
Test status
Simulation time 80561082 ps
CPU time 5.22 seconds
Started May 09 03:16:39 PM PDT 24
Finished May 09 03:16:45 PM PDT 24
Peak memory 239304 kb
Host smart-8745095a-62ba-4392-b3b6-99de268efec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983
6360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.199836360
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.185471367
Short name T54
Test name
Test status
Simulation time 1246073800 ps
CPU time 33.9 seconds
Started May 09 03:16:37 PM PDT 24
Finished May 09 03:17:12 PM PDT 24
Peak memory 255912 kb
Host smart-888f05c1-9e92-46df-836b-e264667d02c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
1367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.185471367
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3624451076
Short name T632
Test name
Test status
Simulation time 2106769344 ps
CPU time 32.26 seconds
Started May 09 03:16:28 PM PDT 24
Finished May 09 03:17:01 PM PDT 24
Peak memory 248800 kb
Host smart-cef06137-cf89-4bcd-9914-f0d4e04f3d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36244
51076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3624451076
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2223233748
Short name T292
Test name
Test status
Simulation time 152377492506 ps
CPU time 2761.34 seconds
Started May 09 03:16:38 PM PDT 24
Finished May 09 04:02:40 PM PDT 24
Peak memory 305964 kb
Host smart-1415d90e-7127-4dd7-b9ed-5689276aaac6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223233748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2223233748
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1185111108
Short name T413
Test name
Test status
Simulation time 18161845398 ps
CPU time 1164.22 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 03:36:08 PM PDT 24
Peak memory 273480 kb
Host smart-cbef6457-d631-4e70-9ac7-fea08eb2e700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185111108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1185111108
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.459182600
Short name T704
Test name
Test status
Simulation time 1722353970 ps
CPU time 39.91 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 03:17:24 PM PDT 24
Peak memory 256716 kb
Host smart-7f46e186-4c59-4fae-9726-7930a23ea7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45918
2600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.459182600
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2103974344
Short name T490
Test name
Test status
Simulation time 528443882 ps
CPU time 16.68 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 03:17:01 PM PDT 24
Peak memory 248780 kb
Host smart-f5679fec-32a7-4841-882d-d1e7592dcee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
74344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2103974344
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1471301034
Short name T624
Test name
Test status
Simulation time 51921322105 ps
CPU time 2627.37 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 04:00:32 PM PDT 24
Peak memory 288948 kb
Host smart-5905c75e-0c97-4c6e-a819-18ba1b67b42c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471301034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1471301034
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3260695152
Short name T652
Test name
Test status
Simulation time 191419936986 ps
CPU time 2990.35 seconds
Started May 09 03:16:55 PM PDT 24
Finished May 09 04:06:48 PM PDT 24
Peak memory 289576 kb
Host smart-bea8806b-ea3e-4a05-b796-1e3e0e309e0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260695152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3260695152
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1525466882
Short name T709
Test name
Test status
Simulation time 15568089389 ps
CPU time 520.76 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 03:25:24 PM PDT 24
Peak memory 247880 kb
Host smart-b84c94d0-e1b3-48c8-a395-a419904eb837
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525466882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1525466882
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3971692723
Short name T393
Test name
Test status
Simulation time 8751374203 ps
CPU time 58.92 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 03:17:43 PM PDT 24
Peak memory 256996 kb
Host smart-515f3966-c429-498d-acd2-1374c7a246b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39716
92723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3971692723
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3355806836
Short name T669
Test name
Test status
Simulation time 1000516292 ps
CPU time 15.47 seconds
Started May 09 03:16:43 PM PDT 24
Finished May 09 03:17:00 PM PDT 24
Peak memory 254292 kb
Host smart-83c05af2-a7d1-4ab3-9c42-b2b26e72e8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33558
06836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3355806836
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.392344956
Short name T94
Test name
Test status
Simulation time 110074494 ps
CPU time 4.4 seconds
Started May 09 03:16:42 PM PDT 24
Finished May 09 03:16:48 PM PDT 24
Peak memory 239300 kb
Host smart-824f5fd8-c8d6-4f56-9ebc-cc2912b112ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
4956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.392344956
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2784973123
Short name T277
Test name
Test status
Simulation time 3608305655 ps
CPU time 61.7 seconds
Started May 09 03:16:40 PM PDT 24
Finished May 09 03:17:42 PM PDT 24
Peak memory 248780 kb
Host smart-43244bb6-aa5f-4686-be0a-93003db27cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
73123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2784973123
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.950535432
Short name T131
Test name
Test status
Simulation time 84040727283 ps
CPU time 2898.24 seconds
Started May 09 03:17:00 PM PDT 24
Finished May 09 04:05:20 PM PDT 24
Peak memory 288276 kb
Host smart-f262538c-2bb2-4bae-a879-d938e57d0ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950535432 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.950535432
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1465610854
Short name T442
Test name
Test status
Simulation time 10241590258 ps
CPU time 920.03 seconds
Started May 09 03:16:54 PM PDT 24
Finished May 09 03:32:16 PM PDT 24
Peak memory 269572 kb
Host smart-d792a7ab-ad1d-43f8-9978-78324e3b54fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465610854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1465610854
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1724782116
Short name T508
Test name
Test status
Simulation time 624787674 ps
CPU time 38.54 seconds
Started May 09 03:16:55 PM PDT 24
Finished May 09 03:17:35 PM PDT 24
Peak memory 248560 kb
Host smart-35122575-369a-4662-901f-d31e1a6f430c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17247
82116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1724782116
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2830066995
Short name T69
Test name
Test status
Simulation time 642108928 ps
CPU time 39.42 seconds
Started May 09 03:16:59 PM PDT 24
Finished May 09 03:17:40 PM PDT 24
Peak memory 255340 kb
Host smart-1f80a26f-4a24-4046-8eec-5e2125866b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28300
66995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2830066995
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.821340078
Short name T207
Test name
Test status
Simulation time 10920461620 ps
CPU time 1070 seconds
Started May 09 03:16:55 PM PDT 24
Finished May 09 03:34:47 PM PDT 24
Peak memory 272780 kb
Host smart-56a7c123-0425-487f-962d-ff3ab035c792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821340078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.821340078
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.373320681
Short name T392
Test name
Test status
Simulation time 71368017472 ps
CPU time 1382.22 seconds
Started May 09 03:16:54 PM PDT 24
Finished May 09 03:39:58 PM PDT 24
Peak memory 289340 kb
Host smart-679220d2-f5a6-4e90-92ab-5e58a6abede7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373320681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.373320681
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2241574947
Short name T99
Test name
Test status
Simulation time 24641390532 ps
CPU time 237.8 seconds
Started May 09 03:16:53 PM PDT 24
Finished May 09 03:20:52 PM PDT 24
Peak memory 248204 kb
Host smart-9e5ef52e-9d08-4842-a3e2-12adc3efd5d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241574947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2241574947
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2342072294
Short name T699
Test name
Test status
Simulation time 58352062 ps
CPU time 6.34 seconds
Started May 09 03:16:53 PM PDT 24
Finished May 09 03:17:01 PM PDT 24
Peak memory 240584 kb
Host smart-c55dd1f8-0b92-476c-a6a2-1f2449e2373a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23420
72294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2342072294
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2226810931
Short name T566
Test name
Test status
Simulation time 2438276408 ps
CPU time 36.86 seconds
Started May 09 03:16:53 PM PDT 24
Finished May 09 03:17:32 PM PDT 24
Peak memory 248816 kb
Host smart-1d470874-5139-4d2a-bdb0-fdc9be3a0422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22268
10931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2226810931
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3377082481
Short name T577
Test name
Test status
Simulation time 170301560 ps
CPU time 13.36 seconds
Started May 09 03:16:54 PM PDT 24
Finished May 09 03:17:08 PM PDT 24
Peak memory 247436 kb
Host smart-6d811cb6-19dd-46f9-9b93-01f7f47ca4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33770
82481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3377082481
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3020977781
Short name T431
Test name
Test status
Simulation time 254726594 ps
CPU time 27.23 seconds
Started May 09 03:16:55 PM PDT 24
Finished May 09 03:17:24 PM PDT 24
Peak memory 248812 kb
Host smart-3298c68c-dd01-4a64-a103-5f48224438e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30209
77781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3020977781
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.806737596
Short name T609
Test name
Test status
Simulation time 2746550693 ps
CPU time 95.46 seconds
Started May 09 03:16:54 PM PDT 24
Finished May 09 03:18:31 PM PDT 24
Peak memory 256944 kb
Host smart-b60d8449-599b-48c1-b81a-04a6675bd17b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806737596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.806737596
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2697326731
Short name T291
Test name
Test status
Simulation time 77851056934 ps
CPU time 6810.67 seconds
Started May 09 03:16:54 PM PDT 24
Finished May 09 05:10:26 PM PDT 24
Peak memory 322520 kb
Host smart-1cf2d36f-eded-4457-b6f9-735fbac4f610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697326731 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2697326731
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1802820681
Short name T711
Test name
Test status
Simulation time 371027760088 ps
CPU time 2791.46 seconds
Started May 09 03:17:08 PM PDT 24
Finished May 09 04:03:41 PM PDT 24
Peak memory 281668 kb
Host smart-2ebf7fc7-0a95-4e7f-adf4-295b80851f7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802820681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1802820681
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3938043334
Short name T258
Test name
Test status
Simulation time 6930877716 ps
CPU time 96 seconds
Started May 09 03:16:53 PM PDT 24
Finished May 09 03:18:31 PM PDT 24
Peak memory 256752 kb
Host smart-11e7d613-30d4-4b0e-b26f-673b99f41eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39380
43334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3938043334
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2231994298
Short name T405
Test name
Test status
Simulation time 336758115 ps
CPU time 11.61 seconds
Started May 09 03:16:56 PM PDT 24
Finished May 09 03:17:09 PM PDT 24
Peak memory 248780 kb
Host smart-f8e58f46-ff9b-49c6-9b23-2457e2f15dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22319
94298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2231994298
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2705032496
Short name T332
Test name
Test status
Simulation time 203974994234 ps
CPU time 3000.92 seconds
Started May 09 03:17:04 PM PDT 24
Finished May 09 04:07:06 PM PDT 24
Peak memory 287028 kb
Host smart-9a09b4a5-d358-44b8-86b0-2c3ae39f5741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705032496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2705032496
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.4249095782
Short name T438
Test name
Test status
Simulation time 51675836634 ps
CPU time 1170.76 seconds
Started May 09 03:17:05 PM PDT 24
Finished May 09 03:36:37 PM PDT 24
Peak memory 288732 kb
Host smart-9498fc18-33f5-4b86-8589-6b669299cbf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249095782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4249095782
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4162281549
Short name T614
Test name
Test status
Simulation time 27684187202 ps
CPU time 294.08 seconds
Started May 09 03:17:03 PM PDT 24
Finished May 09 03:21:58 PM PDT 24
Peak memory 248372 kb
Host smart-0c9821bb-65a0-487f-9cf0-960df1380def
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162281549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4162281549
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1710297021
Short name T598
Test name
Test status
Simulation time 616295903 ps
CPU time 27.33 seconds
Started May 09 03:16:55 PM PDT 24
Finished May 09 03:17:25 PM PDT 24
Peak memory 256468 kb
Host smart-4d0b3d81-0b85-453e-bb32-6395ac23a0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17102
97021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1710297021
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1280980565
Short name T627
Test name
Test status
Simulation time 3937610838 ps
CPU time 56.85 seconds
Started May 09 03:16:56 PM PDT 24
Finished May 09 03:17:55 PM PDT 24
Peak memory 248712 kb
Host smart-c4d766d4-9264-4f05-b74f-fe6504191c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809
80565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1280980565
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.699830977
Short name T639
Test name
Test status
Simulation time 207658625 ps
CPU time 27.63 seconds
Started May 09 03:16:53 PM PDT 24
Finished May 09 03:17:22 PM PDT 24
Peak memory 256212 kb
Host smart-d686caa2-04ff-4911-ba17-0c7fc0b54d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69983
0977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.699830977
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3202564403
Short name T125
Test name
Test status
Simulation time 2792829605 ps
CPU time 38.8 seconds
Started May 09 03:17:00 PM PDT 24
Finished May 09 03:17:40 PM PDT 24
Peak memory 248820 kb
Host smart-609e8ad9-a71a-4f9f-9910-465640632d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32025
64403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3202564403
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1408642864
Short name T545
Test name
Test status
Simulation time 84672553758 ps
CPU time 4804.27 seconds
Started May 09 03:17:03 PM PDT 24
Finished May 09 04:37:09 PM PDT 24
Peak memory 305572 kb
Host smart-79d4b8f4-18fe-41d8-8ffe-3e39ada0cf4b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408642864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1408642864
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1721210585
Short name T103
Test name
Test status
Simulation time 38223781058 ps
CPU time 3977.72 seconds
Started May 09 03:17:04 PM PDT 24
Finished May 09 04:23:23 PM PDT 24
Peak memory 318912 kb
Host smart-cf64fbc0-0f83-4a71-aee8-cc22564d9870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721210585 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1721210585
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3798801251
Short name T419
Test name
Test status
Simulation time 95457874301 ps
CPU time 1653.7 seconds
Started May 09 03:17:05 PM PDT 24
Finished May 09 03:44:40 PM PDT 24
Peak memory 273632 kb
Host smart-2cf1da46-7576-4e04-b2a9-4306571ed7ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798801251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3798801251
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3483607856
Short name T617
Test name
Test status
Simulation time 2038178479 ps
CPU time 134.44 seconds
Started May 09 03:17:03 PM PDT 24
Finished May 09 03:19:19 PM PDT 24
Peak memory 256816 kb
Host smart-a33c410f-a18a-4f15-90d0-6b016447b159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
07856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3483607856
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.183338573
Short name T20
Test name
Test status
Simulation time 132543129 ps
CPU time 13.77 seconds
Started May 09 03:17:06 PM PDT 24
Finished May 09 03:17:21 PM PDT 24
Peak memory 249380 kb
Host smart-361d7dae-da9e-42b9-b274-2a303d6431eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
8573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.183338573
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1424614473
Short name T3
Test name
Test status
Simulation time 16935066088 ps
CPU time 1048.27 seconds
Started May 09 03:17:15 PM PDT 24
Finished May 09 03:34:45 PM PDT 24
Peak memory 265188 kb
Host smart-dcb4ca37-2646-47df-8fdc-57278e3cdb4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424614473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1424614473
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2472033172
Short name T584
Test name
Test status
Simulation time 30809184599 ps
CPU time 2249.08 seconds
Started May 09 03:17:15 PM PDT 24
Finished May 09 03:54:46 PM PDT 24
Peak memory 288532 kb
Host smart-68d2225b-89ce-4439-b186-2728862efbab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472033172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2472033172
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2016296490
Short name T324
Test name
Test status
Simulation time 11822880343 ps
CPU time 469.84 seconds
Started May 09 03:17:15 PM PDT 24
Finished May 09 03:25:06 PM PDT 24
Peak memory 247160 kb
Host smart-d2774df6-e91a-48e8-a5b5-c06acb817795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016296490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2016296490
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1529055921
Short name T686
Test name
Test status
Simulation time 938946600 ps
CPU time 48.17 seconds
Started May 09 03:17:04 PM PDT 24
Finished May 09 03:17:53 PM PDT 24
Peak memory 256028 kb
Host smart-35831ac2-4f3e-4ff7-a565-e345b3cfc8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15290
55921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1529055921
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3072339872
Short name T705
Test name
Test status
Simulation time 44533601 ps
CPU time 7.04 seconds
Started May 09 03:17:06 PM PDT 24
Finished May 09 03:17:13 PM PDT 24
Peak memory 239304 kb
Host smart-41c9f4dc-bd6c-4ecc-8ccf-dcf6a974b4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723
39872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3072339872
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.298743292
Short name T267
Test name
Test status
Simulation time 4120960868 ps
CPU time 33.78 seconds
Started May 09 03:17:05 PM PDT 24
Finished May 09 03:17:40 PM PDT 24
Peak memory 247920 kb
Host smart-f08b08c7-0faa-4e16-878a-d2760bccf83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29874
3292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.298743292
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.203204451
Short name T379
Test name
Test status
Simulation time 182211130 ps
CPU time 14.89 seconds
Started May 09 03:17:04 PM PDT 24
Finished May 09 03:17:19 PM PDT 24
Peak memory 254160 kb
Host smart-68ba357f-d4d5-4f4d-b3d2-66a3752f909b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20320
4451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.203204451
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2951454123
Short name T50
Test name
Test status
Simulation time 39940938151 ps
CPU time 2866.07 seconds
Started May 09 03:17:16 PM PDT 24
Finished May 09 04:05:03 PM PDT 24
Peak memory 289736 kb
Host smart-8d2abc37-a070-44b5-9ddc-3d0a300c8c83
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951454123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2951454123
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.297332427
Short name T461
Test name
Test status
Simulation time 310081103119 ps
CPU time 1934.85 seconds
Started May 09 03:17:25 PM PDT 24
Finished May 09 03:49:41 PM PDT 24
Peak memory 269896 kb
Host smart-19a57164-0536-4d04-9d16-d913e6aa4d69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297332427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.297332427
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2450860092
Short name T244
Test name
Test status
Simulation time 13082603994 ps
CPU time 211.95 seconds
Started May 09 03:17:14 PM PDT 24
Finished May 09 03:20:47 PM PDT 24
Peak memory 256980 kb
Host smart-205498db-3170-4473-8cba-f889d1dd526e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
60092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2450860092
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2507449662
Short name T500
Test name
Test status
Simulation time 504109505 ps
CPU time 12.31 seconds
Started May 09 03:17:19 PM PDT 24
Finished May 09 03:17:32 PM PDT 24
Peak memory 254740 kb
Host smart-e3f7ee62-ff4f-43a7-84e9-d422bbca08fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
49662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2507449662
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1456728736
Short name T560
Test name
Test status
Simulation time 187156523646 ps
CPU time 2253.53 seconds
Started May 09 03:17:24 PM PDT 24
Finished May 09 03:54:59 PM PDT 24
Peak memory 286296 kb
Host smart-e88fefab-a238-4a07-80ef-271194a06396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456728736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1456728736
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3183396421
Short name T314
Test name
Test status
Simulation time 3093200747 ps
CPU time 125.53 seconds
Started May 09 03:17:25 PM PDT 24
Finished May 09 03:19:32 PM PDT 24
Peak memory 248096 kb
Host smart-386d6865-1296-4386-aefb-c4370ade1ef3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183396421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3183396421
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.202338026
Short name T417
Test name
Test status
Simulation time 405518264 ps
CPU time 23.89 seconds
Started May 09 03:17:14 PM PDT 24
Finished May 09 03:17:39 PM PDT 24
Peak memory 255996 kb
Host smart-9f66836a-d17b-4ccf-bc62-da60228baa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20233
8026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.202338026
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1174508992
Short name T557
Test name
Test status
Simulation time 4871406473 ps
CPU time 69.13 seconds
Started May 09 03:17:15 PM PDT 24
Finished May 09 03:18:25 PM PDT 24
Peak memory 248696 kb
Host smart-223542b6-b2f8-4670-9daf-75bdf083ddd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11745
08992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1174508992
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.810354809
Short name T423
Test name
Test status
Simulation time 3697059742 ps
CPU time 57.9 seconds
Started May 09 03:17:15 PM PDT 24
Finished May 09 03:18:14 PM PDT 24
Peak memory 248820 kb
Host smart-7b07ec15-d195-4036-8c10-b31f852be13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81035
4809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.810354809
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1633807351
Short name T266
Test name
Test status
Simulation time 43681064672 ps
CPU time 840.12 seconds
Started May 09 03:17:26 PM PDT 24
Finished May 09 03:31:27 PM PDT 24
Peak memory 273356 kb
Host smart-62fc5f94-f437-44e2-bd74-c1bd5cd5ed92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633807351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1633807351
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2081875025
Short name T558
Test name
Test status
Simulation time 40929839939 ps
CPU time 2459.31 seconds
Started May 09 03:17:36 PM PDT 24
Finished May 09 03:58:37 PM PDT 24
Peak memory 289412 kb
Host smart-c59f22f3-f69e-4021-bba2-4c1d763d681f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081875025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2081875025
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.499339820
Short name T444
Test name
Test status
Simulation time 17765603428 ps
CPU time 237.91 seconds
Started May 09 03:17:26 PM PDT 24
Finished May 09 03:21:25 PM PDT 24
Peak memory 250892 kb
Host smart-dac77e39-f9d5-462d-a425-f5ddf30daa51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49933
9820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.499339820
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1814380162
Short name T420
Test name
Test status
Simulation time 27726332 ps
CPU time 3.18 seconds
Started May 09 03:17:26 PM PDT 24
Finished May 09 03:17:30 PM PDT 24
Peak memory 240588 kb
Host smart-c5b5f0a1-56c7-416a-8102-1ee01ae41312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18143
80162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1814380162
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.510758727
Short name T303
Test name
Test status
Simulation time 19956112830 ps
CPU time 1346.86 seconds
Started May 09 03:17:36 PM PDT 24
Finished May 09 03:40:05 PM PDT 24
Peak memory 267264 kb
Host smart-4aba08e6-4c4c-47aa-88f8-b91b7ed38738
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510758727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.510758727
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1065198229
Short name T109
Test name
Test status
Simulation time 59425121699 ps
CPU time 1196.23 seconds
Started May 09 03:17:36 PM PDT 24
Finished May 09 03:37:34 PM PDT 24
Peak memory 272052 kb
Host smart-2dfb025c-86cb-47ca-9f1a-194a811a9938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065198229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1065198229
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.652047291
Short name T309
Test name
Test status
Simulation time 15667695421 ps
CPU time 663.65 seconds
Started May 09 03:17:35 PM PDT 24
Finished May 09 03:28:41 PM PDT 24
Peak memory 254876 kb
Host smart-a0b78797-67d7-4fc8-9995-55b6c79a5926
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652047291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.652047291
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1076254873
Short name T653
Test name
Test status
Simulation time 893227538 ps
CPU time 63.88 seconds
Started May 09 03:17:25 PM PDT 24
Finished May 09 03:18:30 PM PDT 24
Peak memory 248768 kb
Host smart-d900bf5e-06f9-40ee-be26-b84a67add08e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10762
54873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1076254873
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3238349051
Short name T90
Test name
Test status
Simulation time 118716367 ps
CPU time 10.45 seconds
Started May 09 03:17:26 PM PDT 24
Finished May 09 03:17:38 PM PDT 24
Peak memory 255660 kb
Host smart-3ae03cc0-54fb-45ad-8555-e9f3534c4056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32383
49051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3238349051
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1608452012
Short name T585
Test name
Test status
Simulation time 317506188 ps
CPU time 20.62 seconds
Started May 09 03:17:25 PM PDT 24
Finished May 09 03:17:47 PM PDT 24
Peak memory 248816 kb
Host smart-675110d4-ee1c-487a-bfdb-315f5c6d9336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
52012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1608452012
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1770369914
Short name T466
Test name
Test status
Simulation time 87893495430 ps
CPU time 1069.28 seconds
Started May 09 03:17:34 PM PDT 24
Finished May 09 03:35:25 PM PDT 24
Peak memory 273356 kb
Host smart-361fb8e6-eef1-4d8f-a94d-1fe65f7fe80e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770369914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1770369914
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.407856521
Short name T522
Test name
Test status
Simulation time 118470717640 ps
CPU time 1998.88 seconds
Started May 09 03:17:37 PM PDT 24
Finished May 09 03:50:57 PM PDT 24
Peak memory 288836 kb
Host smart-4cf86a97-5ae8-41d6-a9a1-6414f2283cc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407856521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.407856521
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2889222725
Short name T491
Test name
Test status
Simulation time 643152963 ps
CPU time 10.43 seconds
Started May 09 03:17:34 PM PDT 24
Finished May 09 03:17:46 PM PDT 24
Peak memory 248820 kb
Host smart-4fbb641c-a4ce-4ca7-8150-8682a0b52cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28892
22725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2889222725
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3163800514
Short name T607
Test name
Test status
Simulation time 3784386264 ps
CPU time 27.65 seconds
Started May 09 03:17:35 PM PDT 24
Finished May 09 03:18:04 PM PDT 24
Peak memory 248820 kb
Host smart-fb0798a9-3aad-42a9-a451-a44270ff7a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638
00514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3163800514
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1070525524
Short name T302
Test name
Test status
Simulation time 15246717201 ps
CPU time 1606.16 seconds
Started May 09 03:17:47 PM PDT 24
Finished May 09 03:44:38 PM PDT 24
Peak memory 286844 kb
Host smart-c05bb2f9-c916-4acc-b7fb-7b6e040a8df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070525524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1070525524
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1119180315
Short name T529
Test name
Test status
Simulation time 84863528829 ps
CPU time 1508.49 seconds
Started May 09 03:17:47 PM PDT 24
Finished May 09 03:43:00 PM PDT 24
Peak memory 281608 kb
Host smart-4d76a637-d212-4229-9478-e98c2c7ca437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119180315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1119180315
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.701525291
Short name T644
Test name
Test status
Simulation time 44061776209 ps
CPU time 457.31 seconds
Started May 09 03:17:47 PM PDT 24
Finished May 09 03:25:28 PM PDT 24
Peak memory 255344 kb
Host smart-8d340e92-d8f5-4385-9e72-f3cc071f8d66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701525291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.701525291
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3210681463
Short name T597
Test name
Test status
Simulation time 1693105788 ps
CPU time 53.51 seconds
Started May 09 03:17:36 PM PDT 24
Finished May 09 03:18:32 PM PDT 24
Peak memory 248756 kb
Host smart-fd15095a-3954-4f90-9a0c-7bb76214c492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32106
81463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3210681463
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4285111610
Short name T427
Test name
Test status
Simulation time 800478524 ps
CPU time 15.51 seconds
Started May 09 03:17:34 PM PDT 24
Finished May 09 03:17:52 PM PDT 24
Peak memory 248756 kb
Host smart-11bfb314-31b6-49e9-a951-52bb081243f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
11610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4285111610
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.540648009
Short name T412
Test name
Test status
Simulation time 113694698 ps
CPU time 17.4 seconds
Started May 09 03:17:34 PM PDT 24
Finished May 09 03:17:53 PM PDT 24
Peak memory 248868 kb
Host smart-e43cc3a2-a7de-437c-b531-42d2a4ce083c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54064
8009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.540648009
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1937196988
Short name T634
Test name
Test status
Simulation time 493284218 ps
CPU time 17.23 seconds
Started May 09 03:17:36 PM PDT 24
Finished May 09 03:17:55 PM PDT 24
Peak memory 248796 kb
Host smart-fc645d91-ecf1-403a-bcb1-25b65e757f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19371
96988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1937196988
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4137116727
Short name T60
Test name
Test status
Simulation time 36571479267 ps
CPU time 2345.61 seconds
Started May 09 03:17:47 PM PDT 24
Finished May 09 03:56:57 PM PDT 24
Peak memory 289192 kb
Host smart-25209d58-9c61-48ea-a32f-0b22ffdc88cd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137116727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4137116727
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.372531655
Short name T263
Test name
Test status
Simulation time 73426424451 ps
CPU time 5008.91 seconds
Started May 09 03:17:46 PM PDT 24
Finished May 09 04:41:19 PM PDT 24
Peak memory 305940 kb
Host smart-935be9d9-9a27-4333-a39e-c0c4176621da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372531655 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.372531655
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1502419047
Short name T533
Test name
Test status
Simulation time 31510929471 ps
CPU time 868.83 seconds
Started May 09 03:17:58 PM PDT 24
Finished May 09 03:32:29 PM PDT 24
Peak memory 268280 kb
Host smart-8adb283c-19d5-4dd6-8754-eda322b6ee83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502419047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1502419047
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3536735072
Short name T44
Test name
Test status
Simulation time 2294356695 ps
CPU time 184.21 seconds
Started May 09 03:17:57 PM PDT 24
Finished May 09 03:21:03 PM PDT 24
Peak memory 257208 kb
Host smart-4c061b35-9359-4f0f-9857-382bc6cda247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35367
35072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3536735072
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2538397317
Short name T713
Test name
Test status
Simulation time 1801023953 ps
CPU time 29.31 seconds
Started May 09 03:17:58 PM PDT 24
Finished May 09 03:18:30 PM PDT 24
Peak memory 248804 kb
Host smart-8b6029bd-1578-42b2-8c88-e54f11c43bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25383
97317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2538397317
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1201250395
Short name T330
Test name
Test status
Simulation time 20656925385 ps
CPU time 756.75 seconds
Started May 09 03:17:57 PM PDT 24
Finished May 09 03:30:35 PM PDT 24
Peak memory 267332 kb
Host smart-44ab8a48-8401-4c05-b1af-b371ed02e6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201250395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1201250395
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3909916332
Short name T583
Test name
Test status
Simulation time 76706183827 ps
CPU time 2118.52 seconds
Started May 09 03:17:59 PM PDT 24
Finished May 09 03:53:20 PM PDT 24
Peak memory 289348 kb
Host smart-e127ead1-dc0e-47a2-bd2d-c883002d4926
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909916332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3909916332
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1531200104
Short name T308
Test name
Test status
Simulation time 29401253838 ps
CPU time 244.41 seconds
Started May 09 03:17:59 PM PDT 24
Finished May 09 03:22:06 PM PDT 24
Peak memory 248256 kb
Host smart-bb7956b9-4440-470b-84b3-37d92492c168
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531200104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1531200104
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3744358843
Short name T365
Test name
Test status
Simulation time 2251172105 ps
CPU time 59.68 seconds
Started May 09 03:17:46 PM PDT 24
Finished May 09 03:18:49 PM PDT 24
Peak memory 248828 kb
Host smart-73ff28de-a602-4e23-8caf-737f471824e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37443
58843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3744358843
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4261739255
Short name T568
Test name
Test status
Simulation time 79083194 ps
CPU time 8.94 seconds
Started May 09 03:17:47 PM PDT 24
Finished May 09 03:18:00 PM PDT 24
Peak memory 249248 kb
Host smart-d0263a9c-b308-4e18-ab03-1da380a2b8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42617
39255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4261739255
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3292672335
Short name T92
Test name
Test status
Simulation time 2559783544 ps
CPU time 51.61 seconds
Started May 09 03:17:57 PM PDT 24
Finished May 09 03:18:50 PM PDT 24
Peak memory 256296 kb
Host smart-23649697-9eae-43fe-82de-6c7c303b7862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32926
72335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3292672335
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2814921101
Short name T415
Test name
Test status
Simulation time 1339408703 ps
CPU time 19.3 seconds
Started May 09 03:17:47 PM PDT 24
Finished May 09 03:18:10 PM PDT 24
Peak memory 248784 kb
Host smart-345ed42e-c62b-4deb-80bf-e2e389b1c3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28149
21101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2814921101
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1525726404
Short name T41
Test name
Test status
Simulation time 90722445791 ps
CPU time 1678.17 seconds
Started May 09 03:18:08 PM PDT 24
Finished May 09 03:46:07 PM PDT 24
Peak memory 273420 kb
Host smart-03d4c876-8d8b-4008-978c-a58b407cf403
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525726404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1525726404
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2251181283
Short name T402
Test name
Test status
Simulation time 26598174538 ps
CPU time 221.79 seconds
Started May 09 03:18:08 PM PDT 24
Finished May 09 03:21:51 PM PDT 24
Peak memory 256948 kb
Host smart-55ee005a-37e5-44ce-bf17-516fd5135efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22511
81283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2251181283
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1683439843
Short name T462
Test name
Test status
Simulation time 2056943398 ps
CPU time 31.16 seconds
Started May 09 03:18:09 PM PDT 24
Finished May 09 03:18:42 PM PDT 24
Peak memory 247664 kb
Host smart-36374448-24dd-4676-b38c-4236bb8422d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16834
39843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1683439843
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1036302861
Short name T340
Test name
Test status
Simulation time 105489935096 ps
CPU time 1646.12 seconds
Started May 09 03:18:07 PM PDT 24
Finished May 09 03:45:34 PM PDT 24
Peak memory 265252 kb
Host smart-3a0caa64-218c-4369-9a5c-a5c30d0f9752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036302861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1036302861
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1351548991
Short name T234
Test name
Test status
Simulation time 147288276163 ps
CPU time 2253.7 seconds
Started May 09 03:18:09 PM PDT 24
Finished May 09 03:55:44 PM PDT 24
Peak memory 273356 kb
Host smart-bad85970-052a-4cdb-b4b8-78e56a3a98f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351548991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1351548991
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1103416712
Short name T305
Test name
Test status
Simulation time 77560216579 ps
CPU time 254.09 seconds
Started May 09 03:18:08 PM PDT 24
Finished May 09 03:22:23 PM PDT 24
Peak memory 247864 kb
Host smart-7b221512-a746-401f-8738-5dbcef4df225
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103416712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1103416712
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.250151313
Short name T623
Test name
Test status
Simulation time 1185314496 ps
CPU time 26.48 seconds
Started May 09 03:17:58 PM PDT 24
Finished May 09 03:18:27 PM PDT 24
Peak memory 248824 kb
Host smart-9c4b0cdd-b020-4a38-86e2-4d2e4cd967a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25015
1313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.250151313
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1647522121
Short name T636
Test name
Test status
Simulation time 3044581634 ps
CPU time 49.05 seconds
Started May 09 03:17:59 PM PDT 24
Finished May 09 03:18:50 PM PDT 24
Peak memory 248972 kb
Host smart-6052f2df-4bb1-4e4e-9c47-c56537acb1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16475
22121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1647522121
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1301873482
Short name T52
Test name
Test status
Simulation time 505233686 ps
CPU time 27.11 seconds
Started May 09 03:18:09 PM PDT 24
Finished May 09 03:18:37 PM PDT 24
Peak memory 248804 kb
Host smart-d49b7f44-16c7-4e8f-9411-89d598ffa98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13018
73482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1301873482
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3316791913
Short name T666
Test name
Test status
Simulation time 831287134 ps
CPU time 50.84 seconds
Started May 09 03:17:58 PM PDT 24
Finished May 09 03:18:50 PM PDT 24
Peak memory 256292 kb
Host smart-6294c014-3eea-4058-8529-34958c821bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
91913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3316791913
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2699349781
Short name T640
Test name
Test status
Simulation time 53784559068 ps
CPU time 2697.01 seconds
Started May 09 03:18:08 PM PDT 24
Finished May 09 04:03:06 PM PDT 24
Peak memory 289572 kb
Host smart-ce248f76-66f8-41fc-bbc5-aa955e6da6ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699349781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2699349781
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2968676590
Short name T218
Test name
Test status
Simulation time 70076640 ps
CPU time 3.79 seconds
Started May 09 03:14:12 PM PDT 24
Finished May 09 03:14:17 PM PDT 24
Peak memory 249008 kb
Host smart-50180164-da87-4d56-81cf-f6c810cbd22d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2968676590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2968676590
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2331098251
Short name T46
Test name
Test status
Simulation time 19346961137 ps
CPU time 1263.22 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 03:35:12 PM PDT 24
Peak memory 265220 kb
Host smart-094b43da-a30f-4943-a88a-9cfebd6b49fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331098251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2331098251
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.378944654
Short name T667
Test name
Test status
Simulation time 158443919 ps
CPU time 8.86 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 03:14:18 PM PDT 24
Peak memory 248792 kb
Host smart-87154826-c750-4eb8-a89f-9c2167f44b23
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=378944654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.378944654
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2795341932
Short name T578
Test name
Test status
Simulation time 7979389330 ps
CPU time 115.92 seconds
Started May 09 03:14:09 PM PDT 24
Finished May 09 03:16:07 PM PDT 24
Peak memory 257028 kb
Host smart-5182180f-2f8a-43cc-9593-15fc74b9039f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953
41932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2795341932
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2212599373
Short name T268
Test name
Test status
Simulation time 1216430195 ps
CPU time 36.69 seconds
Started May 09 03:14:09 PM PDT 24
Finished May 09 03:14:47 PM PDT 24
Peak memory 255444 kb
Host smart-234f28eb-aa86-452b-953d-a6e67a08aaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
99373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2212599373
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.741733146
Short name T347
Test name
Test status
Simulation time 10865529710 ps
CPU time 1115.66 seconds
Started May 09 03:14:06 PM PDT 24
Finished May 09 03:32:43 PM PDT 24
Peak memory 282552 kb
Host smart-511083d3-acee-4e81-84cb-8b0132c8748f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741733146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.741733146
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2971682629
Short name T230
Test name
Test status
Simulation time 9435576586 ps
CPU time 1002.45 seconds
Started May 09 03:14:09 PM PDT 24
Finished May 09 03:30:53 PM PDT 24
Peak memory 282468 kb
Host smart-c33ab2dc-a2e0-4def-8b8e-95dae4dee97f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971682629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2971682629
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2302724743
Short name T321
Test name
Test status
Simulation time 17271865370 ps
CPU time 182.07 seconds
Started May 09 03:14:06 PM PDT 24
Finished May 09 03:17:10 PM PDT 24
Peak memory 247232 kb
Host smart-079a3bdc-748f-4687-86d9-5a95dc572fe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302724743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2302724743
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3988185425
Short name T635
Test name
Test status
Simulation time 718094492 ps
CPU time 13.55 seconds
Started May 09 03:14:09 PM PDT 24
Finished May 09 03:14:24 PM PDT 24
Peak memory 255180 kb
Host smart-ceac6054-4089-4952-84c7-1985488f7f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39881
85425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3988185425
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3250043892
Short name T373
Test name
Test status
Simulation time 59327075 ps
CPU time 2.98 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 03:14:13 PM PDT 24
Peak memory 239260 kb
Host smart-2d45c4ac-4ba7-4255-97d7-17878a2e49e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500
43892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3250043892
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1271965555
Short name T34
Test name
Test status
Simulation time 1254107879 ps
CPU time 53.88 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 03:15:04 PM PDT 24
Peak memory 265476 kb
Host smart-131926c2-4576-49eb-ae3e-e829932fa302
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1271965555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1271965555
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2915351937
Short name T89
Test name
Test status
Simulation time 1043334322 ps
CPU time 30.24 seconds
Started May 09 03:14:04 PM PDT 24
Finished May 09 03:14:36 PM PDT 24
Peak memory 255588 kb
Host smart-85b11d41-f87c-4fdc-ba0a-196441d76efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29153
51937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2915351937
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.245784875
Short name T470
Test name
Test status
Simulation time 184663883 ps
CPU time 21.78 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 03:14:30 PM PDT 24
Peak memory 248772 kb
Host smart-2d17ed40-a634-412b-986c-dcfd4048582e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
4875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.245784875
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2739098205
Short name T659
Test name
Test status
Simulation time 49748921964 ps
CPU time 3120.06 seconds
Started May 09 03:18:20 PM PDT 24
Finished May 09 04:10:21 PM PDT 24
Peak memory 287464 kb
Host smart-2aef6fbe-ac8e-411b-97c8-c8687eb521c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739098205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2739098205
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1908759124
Short name T372
Test name
Test status
Simulation time 46933830888 ps
CPU time 367.99 seconds
Started May 09 03:18:08 PM PDT 24
Finished May 09 03:24:18 PM PDT 24
Peak memory 250948 kb
Host smart-0d945f90-fa57-47fc-96ac-f66ff15a618d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19087
59124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1908759124
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3467369145
Short name T539
Test name
Test status
Simulation time 225326262 ps
CPU time 17.12 seconds
Started May 09 03:18:07 PM PDT 24
Finished May 09 03:18:26 PM PDT 24
Peak memory 253580 kb
Host smart-ab208b1c-b4bc-4ab0-8fcb-300e759d3c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34673
69145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3467369145
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4253954177
Short name T328
Test name
Test status
Simulation time 14680387319 ps
CPU time 1012.43 seconds
Started May 09 03:18:19 PM PDT 24
Finished May 09 03:35:13 PM PDT 24
Peak memory 272544 kb
Host smart-cb049d1e-31c4-417b-ae69-f77ac0af8518
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253954177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4253954177
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.637120291
Short name T396
Test name
Test status
Simulation time 44377750141 ps
CPU time 2797.34 seconds
Started May 09 03:18:19 PM PDT 24
Finished May 09 04:04:58 PM PDT 24
Peak memory 282888 kb
Host smart-023c08f9-f3df-46ec-ae0c-2456a7a83639
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637120291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.637120291
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3168317651
Short name T319
Test name
Test status
Simulation time 30645747918 ps
CPU time 242.56 seconds
Started May 09 03:18:22 PM PDT 24
Finished May 09 03:22:25 PM PDT 24
Peak memory 248024 kb
Host smart-50c62682-bfba-4863-811a-ada3f92276bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168317651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3168317651
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1055059232
Short name T40
Test name
Test status
Simulation time 821526734 ps
CPU time 47.61 seconds
Started May 09 03:18:09 PM PDT 24
Finished May 09 03:18:58 PM PDT 24
Peak memory 248824 kb
Host smart-f2605066-afa6-4c11-abbc-8885e47ef878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
59232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1055059232
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1555347297
Short name T128
Test name
Test status
Simulation time 567525634 ps
CPU time 29.67 seconds
Started May 09 03:18:09 PM PDT 24
Finished May 09 03:18:40 PM PDT 24
Peak memory 255684 kb
Host smart-6ea7262e-e206-4e69-9bda-21f71b96bcfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553
47297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1555347297
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.345500467
Short name T122
Test name
Test status
Simulation time 2440793333 ps
CPU time 40.28 seconds
Started May 09 03:18:08 PM PDT 24
Finished May 09 03:18:49 PM PDT 24
Peak memory 248836 kb
Host smart-bef31990-d3ce-44bc-9588-96095933bbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34550
0467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.345500467
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1665747168
Short name T546
Test name
Test status
Simulation time 5035542621 ps
CPU time 49.7 seconds
Started May 09 03:18:07 PM PDT 24
Finished May 09 03:18:58 PM PDT 24
Peak memory 256388 kb
Host smart-94111b65-5e00-4733-b11b-01df55630769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
47168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1665747168
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2560808163
Short name T630
Test name
Test status
Simulation time 65871206281 ps
CPU time 474.32 seconds
Started May 09 03:18:35 PM PDT 24
Finished May 09 03:26:31 PM PDT 24
Peak memory 256960 kb
Host smart-45a582ee-5ffd-46df-9ac0-4b9340a3041f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560808163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2560808163
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.544126188
Short name T483
Test name
Test status
Simulation time 8676674001 ps
CPU time 625.47 seconds
Started May 09 03:18:35 PM PDT 24
Finished May 09 03:29:02 PM PDT 24
Peak memory 272244 kb
Host smart-e95c68e9-8ec1-4bb6-aa69-50d768065bda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544126188 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.544126188
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2663442936
Short name T515
Test name
Test status
Simulation time 14112378234 ps
CPU time 1200.85 seconds
Started May 09 03:18:36 PM PDT 24
Finished May 09 03:38:39 PM PDT 24
Peak memory 285668 kb
Host smart-3e9c390b-2e34-4016-830f-25cd2cc8fa44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663442936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2663442936
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2130408095
Short name T567
Test name
Test status
Simulation time 15036157936 ps
CPU time 206.49 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 03:22:00 PM PDT 24
Peak memory 257040 kb
Host smart-e3748826-2f64-4a7d-b04c-dc6767c0b6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304
08095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2130408095
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.494964780
Short name T501
Test name
Test status
Simulation time 364509484 ps
CPU time 31.84 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 03:19:06 PM PDT 24
Peak memory 255696 kb
Host smart-c0d133ac-14df-4589-b822-b89c49b2c4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49496
4780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.494964780
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.21611660
Short name T337
Test name
Test status
Simulation time 39393265025 ps
CPU time 963.64 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 03:34:38 PM PDT 24
Peak memory 265228 kb
Host smart-328a6241-876c-4158-b648-c33018fa6838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21611660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.21611660
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3213529761
Short name T101
Test name
Test status
Simulation time 21696785831 ps
CPU time 1200.58 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 03:38:34 PM PDT 24
Peak memory 281608 kb
Host smart-2b13b9cf-1c08-449c-a870-c7e1b622b054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213529761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3213529761
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2315314867
Short name T110
Test name
Test status
Simulation time 18212634299 ps
CPU time 374.85 seconds
Started May 09 03:18:34 PM PDT 24
Finished May 09 03:24:50 PM PDT 24
Peak memory 247160 kb
Host smart-254ad14b-2f7a-4693-b0ef-987c703ef74c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315314867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2315314867
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1704005137
Short name T47
Test name
Test status
Simulation time 1091025446 ps
CPU time 43.08 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 03:19:17 PM PDT 24
Peak memory 256088 kb
Host smart-0ab8ac58-db65-4231-9a47-381af3667f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17040
05137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1704005137
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.176538394
Short name T447
Test name
Test status
Simulation time 124933540 ps
CPU time 8.93 seconds
Started May 09 03:18:33 PM PDT 24
Finished May 09 03:18:43 PM PDT 24
Peak memory 249996 kb
Host smart-6f3380f0-cb03-4a04-90af-bdf22be24d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17653
8394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.176538394
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4178645184
Short name T127
Test name
Test status
Simulation time 307231577 ps
CPU time 21.88 seconds
Started May 09 03:18:37 PM PDT 24
Finished May 09 03:19:00 PM PDT 24
Peak memory 255288 kb
Host smart-a44af5bf-a46d-4daa-b314-5f508ee19772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41786
45184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4178645184
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1223514828
Short name T674
Test name
Test status
Simulation time 1607874982 ps
CPU time 34.44 seconds
Started May 09 03:18:32 PM PDT 24
Finished May 09 03:19:07 PM PDT 24
Peak memory 248800 kb
Host smart-e0c15c62-a9ea-4038-bc10-c0d1f5b59cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
14828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1223514828
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3651760044
Short name T616
Test name
Test status
Simulation time 105249091509 ps
CPU time 714.08 seconds
Started May 09 03:18:48 PM PDT 24
Finished May 09 03:30:43 PM PDT 24
Peak memory 265192 kb
Host smart-8c277782-742a-4550-bab5-d5ba255a4808
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651760044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3651760044
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.630068066
Short name T374
Test name
Test status
Simulation time 1097795557 ps
CPU time 71.74 seconds
Started May 09 03:18:46 PM PDT 24
Finished May 09 03:19:59 PM PDT 24
Peak memory 256768 kb
Host smart-f7d7edee-a666-41a2-be3a-ac1c2f60b650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63006
8066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.630068066
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3923109167
Short name T454
Test name
Test status
Simulation time 350505052 ps
CPU time 26.94 seconds
Started May 09 03:18:45 PM PDT 24
Finished May 09 03:19:13 PM PDT 24
Peak memory 256452 kb
Host smart-bd0b6187-8000-4e06-9f47-89486dbd7973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39231
09167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3923109167
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.250646502
Short name T326
Test name
Test status
Simulation time 82424309201 ps
CPU time 2254.68 seconds
Started May 09 03:18:46 PM PDT 24
Finished May 09 03:56:23 PM PDT 24
Peak memory 285592 kb
Host smart-6afdacb7-509b-4b23-8c22-37d8c1d5efbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250646502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.250646502
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3772677337
Short name T382
Test name
Test status
Simulation time 74730934811 ps
CPU time 2598.49 seconds
Started May 09 03:18:55 PM PDT 24
Finished May 09 04:02:14 PM PDT 24
Peak memory 281584 kb
Host smart-3b64e223-d742-42d3-8193-0a5060b63d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772677337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3772677337
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1881393745
Short name T325
Test name
Test status
Simulation time 89889160217 ps
CPU time 499.89 seconds
Started May 09 03:18:46 PM PDT 24
Finished May 09 03:27:07 PM PDT 24
Peak memory 254988 kb
Host smart-7cecc8b9-ab0b-4558-8911-2d4065d61fee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881393745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1881393745
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2535671583
Short name T692
Test name
Test status
Simulation time 413514297 ps
CPU time 40.37 seconds
Started May 09 03:18:45 PM PDT 24
Finished May 09 03:19:27 PM PDT 24
Peak memory 256100 kb
Host smart-6d8da35d-33d3-474c-9ab7-d800fa2a122a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25356
71583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2535671583
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3139075556
Short name T691
Test name
Test status
Simulation time 583101812 ps
CPU time 26.92 seconds
Started May 09 03:18:46 PM PDT 24
Finished May 09 03:19:15 PM PDT 24
Peak memory 247808 kb
Host smart-2e3fade0-bfcd-49d6-ab42-04e363903c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
75556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3139075556
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3979615292
Short name T45
Test name
Test status
Simulation time 519899710 ps
CPU time 35.78 seconds
Started May 09 03:18:45 PM PDT 24
Finished May 09 03:19:22 PM PDT 24
Peak memory 254076 kb
Host smart-fab30984-c2b9-4dfe-8e8b-598a1951a6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39796
15292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3979615292
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3418878449
Short name T79
Test name
Test status
Simulation time 692637856 ps
CPU time 13.85 seconds
Started May 09 03:18:36 PM PDT 24
Finished May 09 03:18:51 PM PDT 24
Peak memory 248744 kb
Host smart-fbc29526-f872-4a6e-989e-d80ba25fa227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188
78449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3418878449
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2039650701
Short name T253
Test name
Test status
Simulation time 10888583774 ps
CPU time 315.14 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 03:24:13 PM PDT 24
Peak memory 257048 kb
Host smart-d4e6b1c0-9958-447c-a69d-031459f9d14d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039650701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2039650701
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.309281933
Short name T612
Test name
Test status
Simulation time 61595183798 ps
CPU time 2672.56 seconds
Started May 09 03:18:59 PM PDT 24
Finished May 09 04:03:33 PM PDT 24
Peak memory 281672 kb
Host smart-2252d51e-f117-4eb8-8771-9480a0259ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309281933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.309281933
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2707782948
Short name T681
Test name
Test status
Simulation time 14215043874 ps
CPU time 113.73 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 03:20:52 PM PDT 24
Peak memory 256948 kb
Host smart-e04273b7-fc40-4a8f-8d53-030bca3d0dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
82948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2707782948
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.492970689
Short name T512
Test name
Test status
Simulation time 1128262346 ps
CPU time 37.68 seconds
Started May 09 03:18:58 PM PDT 24
Finished May 09 03:19:37 PM PDT 24
Peak memory 249244 kb
Host smart-e9e7f93d-1aae-46e3-a818-0b4468c33610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49297
0689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.492970689
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1776703241
Short name T301
Test name
Test status
Simulation time 23447656660 ps
CPU time 1364.66 seconds
Started May 09 03:21:35 PM PDT 24
Finished May 09 03:44:21 PM PDT 24
Peak memory 281600 kb
Host smart-c0ab6d72-22f4-4715-b0f8-eac1b7a61927
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776703241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1776703241
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1716564845
Short name T604
Test name
Test status
Simulation time 8237456880 ps
CPU time 759.73 seconds
Started May 09 03:20:27 PM PDT 24
Finished May 09 03:33:07 PM PDT 24
Peak memory 265216 kb
Host smart-f60b8021-7fa7-4767-a694-aa406afd257a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716564845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1716564845
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.718214763
Short name T313
Test name
Test status
Simulation time 5220434127 ps
CPU time 221.09 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:28:52 PM PDT 24
Peak memory 248368 kb
Host smart-58982e7f-806e-4d94-b8b9-72605214ffd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718214763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.718214763
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.53031759
Short name T552
Test name
Test status
Simulation time 69562001 ps
CPU time 4.76 seconds
Started May 09 03:18:58 PM PDT 24
Finished May 09 03:19:04 PM PDT 24
Peak memory 240584 kb
Host smart-60266b00-ad99-4abe-934d-0b24f083c376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53031
759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.53031759
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3426968889
Short name T195
Test name
Test status
Simulation time 1146009007 ps
CPU time 78.2 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 03:20:16 PM PDT 24
Peak memory 248764 kb
Host smart-4769a7e3-a535-43e2-bb9f-ffff7f45b81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34269
68889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3426968889
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1542000724
Short name T574
Test name
Test status
Simulation time 131962408 ps
CPU time 9.81 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 03:19:08 PM PDT 24
Peak memory 247384 kb
Host smart-f1cecfdc-ffac-4b49-b57f-b52e8bfab98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15420
00724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1542000724
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1427649122
Short name T496
Test name
Test status
Simulation time 390814692 ps
CPU time 23.53 seconds
Started May 09 03:18:57 PM PDT 24
Finished May 09 03:19:22 PM PDT 24
Peak memory 248800 kb
Host smart-41b43c4c-917f-4738-99da-5443e85307f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14276
49122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1427649122
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3313720272
Short name T18
Test name
Test status
Simulation time 33940745099 ps
CPU time 2564.77 seconds
Started May 09 03:20:38 PM PDT 24
Finished May 09 04:03:24 PM PDT 24
Peak memory 289576 kb
Host smart-5b1bd13a-edd4-4b25-b334-81409dba9d36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313720272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3313720272
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3636367967
Short name T238
Test name
Test status
Simulation time 39621951650 ps
CPU time 2519.47 seconds
Started May 09 03:21:16 PM PDT 24
Finished May 09 04:03:17 PM PDT 24
Peak memory 289968 kb
Host smart-a0a55097-5fc2-4aea-93db-08f943e71b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636367967 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3636367967
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2329718812
Short name T540
Test name
Test status
Simulation time 53826236193 ps
CPU time 2953.29 seconds
Started May 09 03:21:04 PM PDT 24
Finished May 09 04:10:19 PM PDT 24
Peak memory 288168 kb
Host smart-ffa2a337-63ba-43dc-b616-badb9778adfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329718812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2329718812
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3899754173
Short name T39
Test name
Test status
Simulation time 22207568840 ps
CPU time 332.83 seconds
Started May 09 03:20:40 PM PDT 24
Finished May 09 03:26:14 PM PDT 24
Peak memory 257040 kb
Host smart-418f0b1b-e8b5-47c7-9fc1-2e02d94f5fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38997
54173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3899754173
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3201614177
Short name T541
Test name
Test status
Simulation time 2471360816 ps
CPU time 79.47 seconds
Started May 09 03:24:42 PM PDT 24
Finished May 09 03:26:32 PM PDT 24
Peak memory 249220 kb
Host smart-4f28eab1-ed9c-48cb-8476-cb8726ad0364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016
14177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3201614177
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1610117652
Short name T364
Test name
Test status
Simulation time 17885426231 ps
CPU time 700.7 seconds
Started May 09 03:21:08 PM PDT 24
Finished May 09 03:32:50 PM PDT 24
Peak memory 272260 kb
Host smart-fb94c95d-262a-44ac-b6d6-0cabfce5b3a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610117652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1610117652
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1813230595
Short name T551
Test name
Test status
Simulation time 37345042846 ps
CPU time 1434.07 seconds
Started May 09 03:21:24 PM PDT 24
Finished May 09 03:45:20 PM PDT 24
Peak memory 273024 kb
Host smart-63f44904-934f-42e9-92b1-c0b914b2f7ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813230595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1813230595
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3832824291
Short name T673
Test name
Test status
Simulation time 4202656990 ps
CPU time 95.1 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:26:47 PM PDT 24
Peak memory 248212 kb
Host smart-05f97877-0efc-4371-899d-673bcb96f371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832824291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3832824291
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3378953534
Short name T663
Test name
Test status
Simulation time 1797673385 ps
CPU time 30.57 seconds
Started May 09 03:21:30 PM PDT 24
Finished May 09 03:22:02 PM PDT 24
Peak memory 256280 kb
Host smart-60e1f2fe-444c-4d1e-b189-e42ca6fc83e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33789
53534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3378953534
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.569743138
Short name T479
Test name
Test status
Simulation time 1546013104 ps
CPU time 56.19 seconds
Started May 09 03:24:40 PM PDT 24
Finished May 09 03:26:04 PM PDT 24
Peak memory 256028 kb
Host smart-8faadaaf-61a8-4438-be12-985b92a2a499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56974
3138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.569743138
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.177370064
Short name T536
Test name
Test status
Simulation time 39172309 ps
CPU time 5.81 seconds
Started May 09 03:21:24 PM PDT 24
Finished May 09 03:21:31 PM PDT 24
Peak memory 240580 kb
Host smart-7336d495-5a95-4b18-b25f-bd2f4f82ea9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17737
0064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.177370064
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.4240956317
Short name T476
Test name
Test status
Simulation time 233633360 ps
CPU time 7.42 seconds
Started May 09 03:21:50 PM PDT 24
Finished May 09 03:21:59 PM PDT 24
Peak memory 248816 kb
Host smart-caad6765-8dcf-4eda-8bd3-784457b0a975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
56317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.4240956317
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1653810536
Short name T254
Test name
Test status
Simulation time 156123300893 ps
CPU time 4399.34 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 04:38:33 PM PDT 24
Peak memory 338232 kb
Host smart-7d172b7c-fb7b-4928-91b1-431abc097381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653810536 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1653810536
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1272802794
Short name T593
Test name
Test status
Simulation time 9507734253 ps
CPU time 968.37 seconds
Started May 09 03:21:33 PM PDT 24
Finished May 09 03:37:43 PM PDT 24
Peak memory 270548 kb
Host smart-706bae28-eed4-4894-a25d-ce7beb138e9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272802794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1272802794
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1801638929
Short name T475
Test name
Test status
Simulation time 245178894 ps
CPU time 24.5 seconds
Started May 09 03:24:42 PM PDT 24
Finished May 09 03:25:39 PM PDT 24
Peak memory 248836 kb
Host smart-68813c63-eee1-4f2c-a3d0-0b7bafe1ec82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18016
38929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1801638929
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.997888848
Short name T84
Test name
Test status
Simulation time 305781378 ps
CPU time 26.55 seconds
Started May 09 03:21:23 PM PDT 24
Finished May 09 03:21:51 PM PDT 24
Peak memory 248964 kb
Host smart-d27ea029-9c41-4989-819d-b96e1421790f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99788
8848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.997888848
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2856224253
Short name T712
Test name
Test status
Simulation time 32152435033 ps
CPU time 2280.7 seconds
Started May 09 03:21:36 PM PDT 24
Finished May 09 03:59:38 PM PDT 24
Peak memory 281188 kb
Host smart-f05446c0-77be-4cc9-b6c5-7283c48057ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856224253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2856224253
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1435774194
Short name T389
Test name
Test status
Simulation time 1819008673 ps
CPU time 19.32 seconds
Started May 09 03:24:46 PM PDT 24
Finished May 09 03:25:39 PM PDT 24
Peak memory 248768 kb
Host smart-9a911719-07b5-469e-88dc-c1349592109f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14357
74194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1435774194
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1840987724
Short name T245
Test name
Test status
Simulation time 1712447044 ps
CPU time 36.03 seconds
Started May 09 03:21:07 PM PDT 24
Finished May 09 03:21:44 PM PDT 24
Peak memory 249156 kb
Host smart-e503520c-ab0e-4426-b307-99cb8c3b1e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18409
87724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1840987724
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2584504056
Short name T65
Test name
Test status
Simulation time 5547622938 ps
CPU time 47.23 seconds
Started May 09 03:21:25 PM PDT 24
Finished May 09 03:22:15 PM PDT 24
Peak memory 247924 kb
Host smart-8b43f317-8be7-412b-8501-2527fb6a8f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25845
04056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2584504056
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3502650365
Short name T88
Test name
Test status
Simulation time 479011946 ps
CPU time 12.55 seconds
Started May 09 03:21:29 PM PDT 24
Finished May 09 03:21:43 PM PDT 24
Peak memory 248804 kb
Host smart-dc733866-e7de-4632-8400-b933cdf9cbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
50365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3502650365
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.12106385
Short name T269
Test name
Test status
Simulation time 44745671638 ps
CPU time 1012.86 seconds
Started May 09 03:20:49 PM PDT 24
Finished May 09 03:37:42 PM PDT 24
Peak memory 271068 kb
Host smart-9f46ee1c-fc5a-4dbc-8a22-69620ab62a31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12106385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_hand
ler_stress_all.12106385
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.277291550
Short name T542
Test name
Test status
Simulation time 36313120960 ps
CPU time 1125.67 seconds
Started May 09 03:21:07 PM PDT 24
Finished May 09 03:39:54 PM PDT 24
Peak memory 265268 kb
Host smart-ee124529-3e53-4319-91c3-df2aaed23a51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277291550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.277291550
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2693448126
Short name T586
Test name
Test status
Simulation time 25037125254 ps
CPU time 147.44 seconds
Started May 09 03:24:46 PM PDT 24
Finished May 09 03:27:47 PM PDT 24
Peak memory 256960 kb
Host smart-4969a5a7-d44b-4378-b797-1f7077c8ece0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26934
48126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2693448126
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1417349136
Short name T527
Test name
Test status
Simulation time 120081496 ps
CPU time 20.75 seconds
Started May 09 03:22:19 PM PDT 24
Finished May 09 03:22:41 PM PDT 24
Peak memory 255896 kb
Host smart-bac318f1-815d-4823-a389-44e54a29a0e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14173
49136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1417349136
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3288495764
Short name T248
Test name
Test status
Simulation time 38453820950 ps
CPU time 1114.7 seconds
Started May 09 03:24:46 PM PDT 24
Finished May 09 03:43:54 PM PDT 24
Peak memory 265192 kb
Host smart-27a68b50-26a9-44d4-8729-715ab761b59d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288495764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3288495764
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1588262655
Short name T463
Test name
Test status
Simulation time 120657001647 ps
CPU time 2179.84 seconds
Started May 09 03:24:40 PM PDT 24
Finished May 09 04:01:30 PM PDT 24
Peak memory 288836 kb
Host smart-795a69a6-2304-4da6-b44b-8140422608cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588262655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1588262655
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2072889277
Short name T311
Test name
Test status
Simulation time 8167923464 ps
CPU time 348.91 seconds
Started May 09 03:24:46 PM PDT 24
Finished May 09 03:31:08 PM PDT 24
Peak memory 247152 kb
Host smart-404d1caf-b586-47e7-92d6-58680dd39989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072889277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2072889277
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3258839504
Short name T561
Test name
Test status
Simulation time 99380690 ps
CPU time 13.39 seconds
Started May 09 03:21:51 PM PDT 24
Finished May 09 03:22:06 PM PDT 24
Peak memory 248772 kb
Host smart-af797e24-dfca-43aa-b56c-63c886004df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32588
39504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3258839504
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4102957784
Short name T407
Test name
Test status
Simulation time 1241507878 ps
CPU time 27.74 seconds
Started May 09 03:21:54 PM PDT 24
Finished May 09 03:22:23 PM PDT 24
Peak memory 247712 kb
Host smart-9505899b-561e-4874-b010-d8ed504d7736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
57784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4102957784
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4212233627
Short name T538
Test name
Test status
Simulation time 580721664 ps
CPU time 36.82 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:25:48 PM PDT 24
Peak memory 255424 kb
Host smart-c614bc55-e241-4e97-8030-66d0e72d1fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
33627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4212233627
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.725309553
Short name T684
Test name
Test status
Simulation time 3317587209 ps
CPU time 36.45 seconds
Started May 09 03:21:19 PM PDT 24
Finished May 09 03:21:56 PM PDT 24
Peak memory 255620 kb
Host smart-63d859c8-dbcc-4deb-92d2-2f0103a87a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72530
9553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.725309553
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.55889480
Short name T257
Test name
Test status
Simulation time 3753666372 ps
CPU time 300.81 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:30:11 PM PDT 24
Peak memory 257064 kb
Host smart-a9a4d17a-8844-406f-852a-6d6ad0606c13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55889480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_hand
ler_stress_all.55889480
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2479626184
Short name T680
Test name
Test status
Simulation time 163366709469 ps
CPU time 2102.87 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 04:00:13 PM PDT 24
Peak memory 301228 kb
Host smart-c0faed9e-b6db-4f39-819d-fddd7ac97a14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479626184 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2479626184
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2026512692
Short name T474
Test name
Test status
Simulation time 35769271156 ps
CPU time 978.63 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:41:31 PM PDT 24
Peak memory 273412 kb
Host smart-926282ba-e3aa-44c4-9729-7a658c4d99da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026512692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2026512692
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2357294895
Short name T689
Test name
Test status
Simulation time 19093528024 ps
CPU time 114.82 seconds
Started May 09 03:24:40 PM PDT 24
Finished May 09 03:27:05 PM PDT 24
Peak memory 257024 kb
Host smart-3234ba13-522f-4c97-aa4f-3ab659498119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23572
94895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2357294895
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1368442621
Short name T80
Test name
Test status
Simulation time 353760534 ps
CPU time 25.83 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:25:36 PM PDT 24
Peak memory 249052 kb
Host smart-a9e54cf6-ed31-4842-9645-50b682348958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
42621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1368442621
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.380571858
Short name T345
Test name
Test status
Simulation time 9360917451 ps
CPU time 907.88 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:40:23 PM PDT 24
Peak memory 267300 kb
Host smart-6da8a57e-e981-4a17-a58c-d480bb9b4884
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380571858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.380571858
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1272784838
Short name T658
Test name
Test status
Simulation time 10346266225 ps
CPU time 1141.06 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:44:14 PM PDT 24
Peak memory 289300 kb
Host smart-f8bb2289-7dd7-46e9-8902-eedf3032c7fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272784838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1272784838
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.684453675
Short name T523
Test name
Test status
Simulation time 2214092431 ps
CPU time 66.73 seconds
Started May 09 03:24:40 PM PDT 24
Finished May 09 03:26:17 PM PDT 24
Peak memory 256180 kb
Host smart-2da9044b-917e-41c2-a4cf-31e3b3a7a4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68445
3675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.684453675
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1628681608
Short name T105
Test name
Test status
Simulation time 803214736 ps
CPU time 43.44 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:25:58 PM PDT 24
Peak memory 255336 kb
Host smart-1e7a3bc7-5626-4355-b3fd-568b506c339f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16286
81608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1628681608
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.442180439
Short name T380
Test name
Test status
Simulation time 710233382 ps
CPU time 22.74 seconds
Started May 09 03:22:10 PM PDT 24
Finished May 09 03:22:34 PM PDT 24
Peak memory 254912 kb
Host smart-42af4c66-a89f-46c9-9684-75b66a3d1794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44218
0439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.442180439
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3887896373
Short name T576
Test name
Test status
Simulation time 453115240 ps
CPU time 27.74 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:25:42 PM PDT 24
Peak memory 256920 kb
Host smart-fe5e2206-5e6a-4117-bfa1-2ea97e4f7c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38878
96373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3887896373
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1812398925
Short name T51
Test name
Test status
Simulation time 106187130686 ps
CPU time 3414.43 seconds
Started May 09 03:24:42 PM PDT 24
Finished May 09 04:22:08 PM PDT 24
Peak memory 305364 kb
Host smart-508ed1cd-cbfc-4e1a-aab1-345747d54af5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812398925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1812398925
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.278182194
Short name T53
Test name
Test status
Simulation time 30466269210 ps
CPU time 1611.33 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:52:06 PM PDT 24
Peak memory 289936 kb
Host smart-5b41f412-659b-41a6-8a34-af7e7cc4b7f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278182194 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.278182194
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.305039378
Short name T643
Test name
Test status
Simulation time 52560407467 ps
CPU time 3169.95 seconds
Started May 09 03:20:48 PM PDT 24
Finished May 09 04:13:39 PM PDT 24
Peak memory 289288 kb
Host smart-fcf69677-22fc-473e-b487-27a74f0e3be7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305039378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.305039378
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.881400697
Short name T596
Test name
Test status
Simulation time 7422723940 ps
CPU time 219.76 seconds
Started May 09 03:24:44 PM PDT 24
Finished May 09 03:28:56 PM PDT 24
Peak memory 256860 kb
Host smart-4180a628-3ea3-48b7-9147-61180a9f2be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88140
0697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.881400697
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2924450838
Short name T82
Test name
Test status
Simulation time 195216065 ps
CPU time 14.74 seconds
Started May 09 03:24:44 PM PDT 24
Finished May 09 03:25:30 PM PDT 24
Peak memory 252912 kb
Host smart-6711f2a8-dba5-40f6-8541-193e3634f77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244
50838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2924450838
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2434364877
Short name T288
Test name
Test status
Simulation time 141576274585 ps
CPU time 2086.09 seconds
Started May 09 03:20:48 PM PDT 24
Finished May 09 03:55:35 PM PDT 24
Peak memory 283036 kb
Host smart-a7b98466-eddf-40e5-b444-f4a2f4131ab4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434364877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2434364877
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1787229220
Short name T543
Test name
Test status
Simulation time 177285730581 ps
CPU time 2733.76 seconds
Started May 09 03:20:50 PM PDT 24
Finished May 09 04:06:25 PM PDT 24
Peak memory 283952 kb
Host smart-79cedced-06b7-42d1-811d-c4386bd0bbf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787229220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1787229220
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4227326685
Short name T306
Test name
Test status
Simulation time 7370053724 ps
CPU time 308.61 seconds
Started May 09 03:20:52 PM PDT 24
Finished May 09 03:26:01 PM PDT 24
Peak memory 248200 kb
Host smart-6e2e8ebe-415d-4ecd-8be2-58be2b492bd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227326685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4227326685
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3498014576
Short name T75
Test name
Test status
Simulation time 796055612 ps
CPU time 54.07 seconds
Started May 09 03:24:42 PM PDT 24
Finished May 09 03:26:08 PM PDT 24
Peak memory 248764 kb
Host smart-e23b42ed-97bd-4463-9dac-c74a3c48131c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980
14576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3498014576
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3006247680
Short name T282
Test name
Test status
Simulation time 569969781 ps
CPU time 35.52 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:25:48 PM PDT 24
Peak memory 255648 kb
Host smart-dabf46a9-383a-49eb-8dc5-0f54f2a3e724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30062
47680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3006247680
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.647918228
Short name T130
Test name
Test status
Simulation time 3768464879 ps
CPU time 59.48 seconds
Started May 09 03:20:49 PM PDT 24
Finished May 09 03:21:49 PM PDT 24
Peak memory 256344 kb
Host smart-c7705dfc-153e-4b7d-8bab-a3df08b139ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64791
8228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.647918228
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2980679564
Short name T678
Test name
Test status
Simulation time 709336997 ps
CPU time 43.05 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:25:56 PM PDT 24
Peak memory 248780 kb
Host smart-bd39f395-f3d2-46e9-880b-4915e7dc8d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
79564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2980679564
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.78907255
Short name T631
Test name
Test status
Simulation time 110876940413 ps
CPU time 1801.2 seconds
Started May 09 03:20:48 PM PDT 24
Finished May 09 03:50:50 PM PDT 24
Peak memory 283656 kb
Host smart-24614d50-936d-4ca7-adbf-b92c4a7ea408
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78907255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_hand
ler_stress_all.78907255
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.50468925
Short name T495
Test name
Test status
Simulation time 106167562537 ps
CPU time 3167.64 seconds
Started May 09 03:24:44 PM PDT 24
Finished May 09 04:18:05 PM PDT 24
Peak memory 281620 kb
Host smart-8e87a5a3-792f-4d5a-aad3-442c7d3d0cb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50468925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.50468925
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4171225019
Short name T661
Test name
Test status
Simulation time 2382225864 ps
CPU time 155.06 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:27:50 PM PDT 24
Peak memory 250956 kb
Host smart-8b26a49b-c62f-497d-9c29-86167770bb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41712
25019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4171225019
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3183516672
Short name T528
Test name
Test status
Simulation time 1163362730 ps
CPU time 41.41 seconds
Started May 09 03:21:20 PM PDT 24
Finished May 09 03:22:02 PM PDT 24
Peak memory 249012 kb
Host smart-8ef40047-692e-4cab-89da-540806ebf717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31835
16672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3183516672
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1615180236
Short name T300
Test name
Test status
Simulation time 19106881669 ps
CPU time 1690.05 seconds
Started May 09 03:24:46 PM PDT 24
Finished May 09 03:53:29 PM PDT 24
Peak memory 288776 kb
Host smart-4f3f1099-c7d1-4132-9bc9-02c363984725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615180236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1615180236
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2048658854
Short name T697
Test name
Test status
Simulation time 170043836230 ps
CPU time 2745.68 seconds
Started May 09 03:24:44 PM PDT 24
Finished May 09 04:11:02 PM PDT 24
Peak memory 289264 kb
Host smart-a1973241-ba85-4845-bbea-c179f29763ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048658854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2048658854
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.4292277803
Short name T570
Test name
Test status
Simulation time 140085611337 ps
CPU time 329.75 seconds
Started May 09 03:24:45 PM PDT 24
Finished May 09 03:30:48 PM PDT 24
Peak memory 248004 kb
Host smart-e9ebcb10-7262-415e-af67-5f369609b49a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292277803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4292277803
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3203755483
Short name T649
Test name
Test status
Simulation time 46325978 ps
CPU time 5.8 seconds
Started May 09 03:24:49 PM PDT 24
Finished May 09 03:25:28 PM PDT 24
Peak memory 248764 kb
Host smart-a7902b8c-f34d-40a1-ae05-e1ad77edd67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32037
55483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3203755483
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2436414697
Short name T693
Test name
Test status
Simulation time 1573113837 ps
CPU time 26.09 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:25:41 PM PDT 24
Peak memory 256072 kb
Host smart-eebe481b-ff34-4eb7-9bab-f12e25901264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24364
14697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2436414697
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3387801537
Short name T270
Test name
Test status
Simulation time 468740576 ps
CPU time 30.99 seconds
Started May 09 03:24:43 PM PDT 24
Finished May 09 03:25:46 PM PDT 24
Peak memory 248772 kb
Host smart-fb72d9a2-e36d-4151-a5a3-4537f1be5ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33878
01537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3387801537
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.260059288
Short name T665
Test name
Test status
Simulation time 1851682218 ps
CPU time 30.05 seconds
Started May 09 03:24:19 PM PDT 24
Finished May 09 03:24:49 PM PDT 24
Peak memory 248780 kb
Host smart-a07d2aab-8290-4e1c-b91f-ff12b2b39f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005
9288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.260059288
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3892037440
Short name T222
Test name
Test status
Simulation time 62845740 ps
CPU time 3.27 seconds
Started May 09 03:14:06 PM PDT 24
Finished May 09 03:14:11 PM PDT 24
Peak memory 248952 kb
Host smart-382db6f1-a2f7-46fa-a61b-328ef561696f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3892037440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3892037440
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2557731187
Short name T100
Test name
Test status
Simulation time 8928853521 ps
CPU time 890.33 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 03:29:00 PM PDT 24
Peak memory 270612 kb
Host smart-e6477463-daf8-444a-ae7e-b26b12b25a15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557731187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2557731187
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2944181357
Short name T386
Test name
Test status
Simulation time 473412439 ps
CPU time 11.51 seconds
Started May 09 03:14:05 PM PDT 24
Finished May 09 03:14:18 PM PDT 24
Peak memory 248788 kb
Host smart-854f24e9-4c64-4abb-b084-4769887bfbd6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2944181357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2944181357
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2471863743
Short name T124
Test name
Test status
Simulation time 4447986354 ps
CPU time 97.12 seconds
Started May 09 03:14:05 PM PDT 24
Finished May 09 03:15:44 PM PDT 24
Peak memory 257232 kb
Host smart-8b71b608-f5c7-4150-92c4-cad61da2f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24718
63743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2471863743
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3788942230
Short name T410
Test name
Test status
Simulation time 1843868478 ps
CPU time 68.7 seconds
Started May 09 03:14:05 PM PDT 24
Finished May 09 03:15:16 PM PDT 24
Peak memory 248784 kb
Host smart-62582ee7-d5ab-4460-b63a-290b316f2ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
42230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3788942230
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3918440230
Short name T298
Test name
Test status
Simulation time 43508934318 ps
CPU time 1255.97 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 03:35:06 PM PDT 24
Peak memory 267256 kb
Host smart-8b83edc3-2931-44b1-80a6-34fdd807245b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918440230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3918440230
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.951252862
Short name T403
Test name
Test status
Simulation time 228600046385 ps
CPU time 2937.88 seconds
Started May 09 03:14:11 PM PDT 24
Finished May 09 04:03:10 PM PDT 24
Peak memory 289204 kb
Host smart-474e633e-7031-4ee6-b1be-12a4fe33c396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951252862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.951252862
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.579169729
Short name T668
Test name
Test status
Simulation time 7889698659 ps
CPU time 310.01 seconds
Started May 09 03:14:09 PM PDT 24
Finished May 09 03:19:21 PM PDT 24
Peak memory 248388 kb
Host smart-dba7871a-a994-4622-b0ea-bceea22ee0f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579169729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.579169729
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3306549096
Short name T706
Test name
Test status
Simulation time 247949017 ps
CPU time 4.81 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 03:14:14 PM PDT 24
Peak memory 240588 kb
Host smart-101419b4-8085-4924-8121-854761413d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33065
49096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3306549096
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3414797442
Short name T297
Test name
Test status
Simulation time 3024443213 ps
CPU time 81.06 seconds
Started May 09 03:14:10 PM PDT 24
Finished May 09 03:15:32 PM PDT 24
Peak memory 256284 kb
Host smart-e14fabb8-05de-4f1a-b29b-9b28ec866445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34147
97442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3414797442
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3310904896
Short name T411
Test name
Test status
Simulation time 18240360 ps
CPU time 3.61 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 03:14:13 PM PDT 24
Peak memory 240560 kb
Host smart-f368c536-93f3-444e-b963-ee1f15309660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33109
04896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3310904896
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1812801443
Short name T193
Test name
Test status
Simulation time 120281025829 ps
CPU time 3511.47 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 04:12:42 PM PDT 24
Peak memory 289348 kb
Host smart-a6dc2232-997a-48e2-806c-a55a86f1d012
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812801443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1812801443
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2539735339
Short name T194
Test name
Test status
Simulation time 106693304811 ps
CPU time 4196.49 seconds
Started May 09 03:14:07 PM PDT 24
Finished May 09 04:24:07 PM PDT 24
Peak memory 305728 kb
Host smart-145c66cf-eaf4-49f4-b9a7-8efa12dedbf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539735339 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2539735339
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2384985317
Short name T226
Test name
Test status
Simulation time 50061549 ps
CPU time 3.91 seconds
Started May 09 03:14:14 PM PDT 24
Finished May 09 03:14:19 PM PDT 24
Peak memory 248956 kb
Host smart-6c5b2d88-5781-4eaa-ad0f-845ecc0dff46
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2384985317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2384985317
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1529468698
Short name T398
Test name
Test status
Simulation time 141028927709 ps
CPU time 2402.34 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:54:19 PM PDT 24
Peak memory 281640 kb
Host smart-5bf51b5e-0036-4822-bb33-db70fb6a1d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529468698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1529468698
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.4265142971
Short name T571
Test name
Test status
Simulation time 187711137 ps
CPU time 10.63 seconds
Started May 09 03:14:14 PM PDT 24
Finished May 09 03:14:26 PM PDT 24
Peak memory 240520 kb
Host smart-4dcf35e7-a2cb-41d2-bf4f-fc083415edaa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4265142971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.4265142971
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1414807182
Short name T72
Test name
Test status
Simulation time 4233075807 ps
CPU time 248.05 seconds
Started May 09 03:14:11 PM PDT 24
Finished May 09 03:18:20 PM PDT 24
Peak memory 255748 kb
Host smart-c4785f3a-bb7a-40cb-a553-b2039e56524b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14148
07182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1414807182
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3957538439
Short name T590
Test name
Test status
Simulation time 3423809693 ps
CPU time 62.45 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 03:15:13 PM PDT 24
Peak memory 248876 kb
Host smart-fd5ebc29-1b32-461d-98a1-6fbe44adc497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39575
38439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3957538439
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.93285838
Short name T343
Test name
Test status
Simulation time 201547700556 ps
CPU time 1810.03 seconds
Started May 09 03:14:23 PM PDT 24
Finished May 09 03:44:35 PM PDT 24
Peak memory 271848 kb
Host smart-904dd3d2-36e4-44dd-a46b-5c637ce9a3e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93285838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.93285838
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2168073299
Short name T70
Test name
Test status
Simulation time 46410830025 ps
CPU time 2693.7 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 03:59:11 PM PDT 24
Peak memory 289380 kb
Host smart-3217bdd0-c0fd-43d2-a90c-424de8251787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168073299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2168073299
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3486221904
Short name T283
Test name
Test status
Simulation time 31907679315 ps
CPU time 334.16 seconds
Started May 09 03:14:17 PM PDT 24
Finished May 09 03:19:53 PM PDT 24
Peak memory 254796 kb
Host smart-8678818a-fb94-4daa-8d15-df42215a43fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486221904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3486221904
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1714654282
Short name T229
Test name
Test status
Simulation time 1078851470 ps
CPU time 50.57 seconds
Started May 09 03:14:09 PM PDT 24
Finished May 09 03:15:01 PM PDT 24
Peak memory 248856 kb
Host smart-2a6cc60b-6400-49f0-a5ae-a1e81072c86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17146
54282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1714654282
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4278267171
Short name T489
Test name
Test status
Simulation time 325479754 ps
CPU time 20.49 seconds
Started May 09 03:14:04 PM PDT 24
Finished May 09 03:14:27 PM PDT 24
Peak memory 255680 kb
Host smart-de77dbac-c586-4e83-82af-4120f7056d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42782
67171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4278267171
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3986989962
Short name T425
Test name
Test status
Simulation time 256364280 ps
CPU time 30.29 seconds
Started May 09 03:14:08 PM PDT 24
Finished May 09 03:14:40 PM PDT 24
Peak memory 248832 kb
Host smart-3405f7d5-fda1-4c21-a9b3-e4c1b24180c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39869
89962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3986989962
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2965233949
Short name T565
Test name
Test status
Simulation time 511752441 ps
CPU time 27.92 seconds
Started May 09 03:14:06 PM PDT 24
Finished May 09 03:14:36 PM PDT 24
Peak memory 248816 kb
Host smart-b211f7f5-ee56-4188-bacc-9aa9e41900ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652
33949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2965233949
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1193285331
Short name T563
Test name
Test status
Simulation time 23474556706 ps
CPU time 1223.21 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:34:51 PM PDT 24
Peak memory 285852 kb
Host smart-b9feb21c-920e-4df5-9303-e3747bdb6c4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193285331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1193285331
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.989274460
Short name T526
Test name
Test status
Simulation time 53813008739 ps
CPU time 6045.28 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 04:55:04 PM PDT 24
Peak memory 338528 kb
Host smart-a9861394-7888-43f4-b091-0cce9b0c92cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989274460 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.989274460
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.966287731
Short name T223
Test name
Test status
Simulation time 14633070 ps
CPU time 2.8 seconds
Started May 09 03:14:24 PM PDT 24
Finished May 09 03:14:28 PM PDT 24
Peak memory 248964 kb
Host smart-9f7649dc-53ea-4022-ae0f-c7271df9dc80
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=966287731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.966287731
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2168723377
Short name T78
Test name
Test status
Simulation time 54793522728 ps
CPU time 1448.79 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 03:38:26 PM PDT 24
Peak memory 282436 kb
Host smart-4f3f1787-44bd-4412-922a-a82ad0124059
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168723377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2168723377
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4165321798
Short name T376
Test name
Test status
Simulation time 416923975 ps
CPU time 8.82 seconds
Started May 09 03:14:19 PM PDT 24
Finished May 09 03:14:29 PM PDT 24
Peak memory 240616 kb
Host smart-fdd79871-218a-40d5-ac28-01f3b1db4d7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4165321798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4165321798
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3042338190
Short name T284
Test name
Test status
Simulation time 1049180577 ps
CPU time 52.27 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:15:09 PM PDT 24
Peak memory 248748 kb
Host smart-4c73d9fe-8dfa-4d85-92d8-f7abeceafab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30423
38190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3042338190
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2027309050
Short name T295
Test name
Test status
Simulation time 502282769 ps
CPU time 18.18 seconds
Started May 09 03:14:14 PM PDT 24
Finished May 09 03:14:33 PM PDT 24
Peak memory 248784 kb
Host smart-a16d6cd6-1318-46e7-8fa8-de3ddd734a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
09050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2027309050
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3763252784
Short name T335
Test name
Test status
Simulation time 34306868823 ps
CPU time 2402.53 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:54:20 PM PDT 24
Peak memory 281596 kb
Host smart-6a8b561e-a7e7-4f8b-9c51-0a843dc0a8ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763252784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3763252784
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1430064393
Short name T549
Test name
Test status
Simulation time 14814996100 ps
CPU time 1119.42 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 03:32:58 PM PDT 24
Peak memory 265180 kb
Host smart-b6bade8c-5039-4482-90aa-87129d7be57b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430064393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1430064393
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.4133076710
Short name T657
Test name
Test status
Simulation time 20629035660 ps
CPU time 403.54 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:21:11 PM PDT 24
Peak memory 247076 kb
Host smart-ad0dd4b9-bd86-4e6f-92ed-d4552070e8b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133076710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4133076710
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2842339027
Short name T30
Test name
Test status
Simulation time 1461429086 ps
CPU time 12.46 seconds
Started May 09 03:14:18 PM PDT 24
Finished May 09 03:14:32 PM PDT 24
Peak memory 248816 kb
Host smart-eb54cb4e-a74b-43f3-9f7d-6c94198f2d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28423
39027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2842339027
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2885049444
Short name T459
Test name
Test status
Simulation time 100912994 ps
CPU time 8.18 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 03:14:26 PM PDT 24
Peak memory 252108 kb
Host smart-e17312b5-32ef-447c-a712-c779e951630a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28850
49444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2885049444
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2301949388
Short name T421
Test name
Test status
Simulation time 1229043992 ps
CPU time 39.08 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:14:55 PM PDT 24
Peak memory 248768 kb
Host smart-74b2bf7e-be94-4a76-a9f5-6e654b3c15ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23019
49388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2301949388
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1301986473
Short name T256
Test name
Test status
Simulation time 43375348580 ps
CPU time 2307.78 seconds
Started May 09 03:14:17 PM PDT 24
Finished May 09 03:52:47 PM PDT 24
Peak memory 283904 kb
Host smart-854f6eaa-2534-4ace-ba5d-463f975206fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301986473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1301986473
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.4206638730
Short name T214
Test name
Test status
Simulation time 17662507 ps
CPU time 2.82 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:14:30 PM PDT 24
Peak memory 248772 kb
Host smart-5e715308-527f-46be-8f3a-d85a1933ec94
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4206638730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.4206638730
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.224940705
Short name T564
Test name
Test status
Simulation time 49772414011 ps
CPU time 3082.31 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 04:05:50 PM PDT 24
Peak memory 281596 kb
Host smart-00ed0c42-ec27-4ed8-b15b-fd64911ddc21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224940705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.224940705
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2637819607
Short name T387
Test name
Test status
Simulation time 109493480 ps
CPU time 7.8 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:14:24 PM PDT 24
Peak memory 248752 kb
Host smart-2290e091-b9e8-4e14-8210-4a48894f56b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2637819607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2637819607
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2934782952
Short name T112
Test name
Test status
Simulation time 3112895255 ps
CPU time 184.47 seconds
Started May 09 03:14:23 PM PDT 24
Finished May 09 03:17:28 PM PDT 24
Peak memory 249900 kb
Host smart-2628af08-1523-492b-b579-5f2da747dbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
82952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2934782952
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3037183054
Short name T621
Test name
Test status
Simulation time 2556568056 ps
CPU time 35.84 seconds
Started May 09 03:14:19 PM PDT 24
Finished May 09 03:14:56 PM PDT 24
Peak memory 256244 kb
Host smart-3b2440c2-02cc-4069-b1e8-0ceb5d88444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30371
83054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3037183054
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3030449424
Short name T399
Test name
Test status
Simulation time 82994487655 ps
CPU time 1392.77 seconds
Started May 09 03:14:17 PM PDT 24
Finished May 09 03:37:32 PM PDT 24
Peak memory 273424 kb
Host smart-e2328c69-c155-4411-9ef2-7c258d1caa67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030449424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3030449424
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1342433787
Short name T322
Test name
Test status
Simulation time 10663049109 ps
CPU time 454.31 seconds
Started May 09 03:14:16 PM PDT 24
Finished May 09 03:21:52 PM PDT 24
Peak memory 254504 kb
Host smart-9a08310d-3617-44c9-b8f7-38568f74f2fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342433787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1342433787
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4199933299
Short name T111
Test name
Test status
Simulation time 698263541 ps
CPU time 37.24 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:14:54 PM PDT 24
Peak memory 248788 kb
Host smart-2b1d91c3-365a-4f94-8591-4ef8f3545888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41999
33299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4199933299
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3607588121
Short name T456
Test name
Test status
Simulation time 860338858 ps
CPU time 29.83 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:14:46 PM PDT 24
Peak memory 255668 kb
Host smart-cc0aa894-cc18-419d-9e82-bab33747bd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075
88121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3607588121
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2341794024
Short name T671
Test name
Test status
Simulation time 626064813 ps
CPU time 21.33 seconds
Started May 09 03:14:24 PM PDT 24
Finished May 09 03:14:47 PM PDT 24
Peak memory 255612 kb
Host smart-b0dc1587-cabf-4975-aedb-d048797be760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23417
94024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2341794024
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2242380660
Short name T71
Test name
Test status
Simulation time 1201920971 ps
CPU time 69.45 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:15:26 PM PDT 24
Peak memory 248800 kb
Host smart-9298c571-76b9-4161-9e95-d1a1cadabadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
80660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2242380660
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3785852290
Short name T293
Test name
Test status
Simulation time 85464286747 ps
CPU time 1646.62 seconds
Started May 09 03:14:14 PM PDT 24
Finished May 09 03:41:41 PM PDT 24
Peak memory 289724 kb
Host smart-7cabc2ee-fdeb-48ad-b351-275709d59212
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785852290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3785852290
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2460400773
Short name T98
Test name
Test status
Simulation time 32096474 ps
CPU time 3.61 seconds
Started May 09 03:14:30 PM PDT 24
Finished May 09 03:14:35 PM PDT 24
Peak memory 248880 kb
Host smart-2399fda5-cb98-4eba-ba77-0a85c7f29e59
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2460400773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2460400773
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1817010080
Short name T682
Test name
Test status
Simulation time 55865819087 ps
CPU time 1472.31 seconds
Started May 09 03:14:14 PM PDT 24
Finished May 09 03:38:48 PM PDT 24
Peak memory 288540 kb
Host smart-7f7a06ac-7418-425d-a7fe-96bc56381e29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817010080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1817010080
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2990252764
Short name T395
Test name
Test status
Simulation time 2136437045 ps
CPU time 48.22 seconds
Started May 09 03:14:30 PM PDT 24
Finished May 09 03:15:19 PM PDT 24
Peak memory 248724 kb
Host smart-98c995b1-afd5-4adf-a2ee-2468f0409ef7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2990252764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2990252764
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.846169306
Short name T572
Test name
Test status
Simulation time 847281348 ps
CPU time 94.62 seconds
Started May 09 03:14:23 PM PDT 24
Finished May 09 03:15:58 PM PDT 24
Peak memory 256968 kb
Host smart-1dd44056-8406-4bf6-9263-314812addd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84616
9306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.846169306
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2305207607
Short name T17
Test name
Test status
Simulation time 260226935 ps
CPU time 22.1 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:14:49 PM PDT 24
Peak memory 255820 kb
Host smart-2ce028c6-1108-4739-a43f-6e5d2140b3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
07607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2305207607
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1750279532
Short name T13
Test name
Test status
Simulation time 7828154965 ps
CPU time 846.16 seconds
Started May 09 03:14:27 PM PDT 24
Finished May 09 03:28:35 PM PDT 24
Peak memory 272832 kb
Host smart-4c2fbef2-20e2-4b16-8a28-dbb2f4ea7f58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750279532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1750279532
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.4025248018
Short name T430
Test name
Test status
Simulation time 15069458486 ps
CPU time 1592.32 seconds
Started May 09 03:14:26 PM PDT 24
Finished May 09 03:41:01 PM PDT 24
Peak memory 288696 kb
Host smart-9a92c6dd-bab3-4e4f-858c-b7ae8784d6fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025248018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.4025248018
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.716859134
Short name T594
Test name
Test status
Simulation time 1372729095 ps
CPU time 42.48 seconds
Started May 09 03:14:24 PM PDT 24
Finished May 09 03:15:08 PM PDT 24
Peak memory 248820 kb
Host smart-4b92252a-f736-4263-9157-b8bcfbb4e28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71685
9134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.716859134
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2112253930
Short name T477
Test name
Test status
Simulation time 285212224 ps
CPU time 32.52 seconds
Started May 09 03:14:14 PM PDT 24
Finished May 09 03:14:48 PM PDT 24
Peak memory 248776 kb
Host smart-284ef4ee-129a-4d9e-9afb-970384dededd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21122
53930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2112253930
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3805079271
Short name T272
Test name
Test status
Simulation time 230178351 ps
CPU time 15.21 seconds
Started May 09 03:14:19 PM PDT 24
Finished May 09 03:14:35 PM PDT 24
Peak memory 248820 kb
Host smart-803e8fc1-9ac8-4bd3-a0f1-dfb9561d2bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
79271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3805079271
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.671220674
Short name T685
Test name
Test status
Simulation time 2389214275 ps
CPU time 42.33 seconds
Started May 09 03:14:15 PM PDT 24
Finished May 09 03:14:59 PM PDT 24
Peak memory 256248 kb
Host smart-a22758bf-be31-4e94-bb24-494794155caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67122
0674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.671220674
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2857387274
Short name T460
Test name
Test status
Simulation time 35727594206 ps
CPU time 1989.99 seconds
Started May 09 03:14:28 PM PDT 24
Finished May 09 03:47:39 PM PDT 24
Peak memory 273448 kb
Host smart-1a0be93b-376b-4590-a032-d2dddb4b449b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857387274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2857387274
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3977654164
Short name T86
Test name
Test status
Simulation time 76154078622 ps
CPU time 7329.19 seconds
Started May 09 03:14:27 PM PDT 24
Finished May 09 05:16:39 PM PDT 24
Peak memory 404480 kb
Host smart-f8438228-569d-4cad-95a2-e27b9eb4d397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977654164 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3977654164
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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