Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	75813	1			T5	442		T13	2241		T14	81
class_i[0x1]	66852	1			T5	145		T14	4162		T43	2
class_i[0x2]	51931	1			T18	2		T4	1		T5	15
class_i[0x3]	71050	1			T18	7		T4	25		T5	2322

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	66166	1			T4	4		T5	561		T13	557
alert[0x1]	66507	1			T18	1		T4	3		T5	1107
alert[0x2]	67046	1			T18	3		T4	9		T5	697
alert[0x3]	65927	1			T18	5		T4	10		T5	559

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

265384

1

T18

9

T4

26

T5

2924

esc_ping_fail

262

1

T7

3

T8

3

T9

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	66089	1			T4	4		T5	561		T13	557
esc_integrity_fail	alert[0x1]	66433	1			T18	1		T4	3		T5	1107
esc_integrity_fail	alert[0x2]	66986	1			T18	3		T4	9		T5	697
esc_integrity_fail	alert[0x3]	65876	1			T18	5		T4	10		T5	559
esc_ping_fail	alert[0x0]	77	1			T8	1		T9	1		T196	4
esc_ping_fail	alert[0x1]	74	1			T7	1		T8	1		T9	2
esc_ping_fail	alert[0x2]	60	1			T7	1		T8	1		T9	2
esc_ping_fail	alert[0x3]	51	1			T7	1		T9	2		T196	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	75757	1			T5	442		T13	2241		T14	81
esc_integrity_fail	class_i[0x1]	66784	1			T5	145		T14	4162		T43	2
esc_integrity_fail	class_i[0x2]	51853	1			T18	2		T4	1		T5	15
esc_integrity_fail	class_i[0x3]	70990	1			T18	7		T4	25		T5	2322
esc_ping_fail	class_i[0x0]	56	1			T7	1		T9	4		T296	1
esc_ping_fail	class_i[0x1]	68	1			T8	2		T9	1		T196	11
esc_ping_fail	class_i[0x2]	78	1			T7	1		T199	4		T318	1
esc_ping_fail	class_i[0x3]	60	1			T7	1		T8	1		T9	2