Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	88	1			T20	1		T13	1		T14	2
class_index[0x1]	68	1			T20	1		T74	1		T76	1
class_index[0x2]	71	1			T13	1		T70	3		T74	1
class_index[0x3]	66	1			T13	1		T14	2		T74	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	105	1			T74	1		T79	1		T26	2
intr_timeout_cnt[1]	65	1			T13	2		T70	3		T39	1
intr_timeout_cnt[2]	24	1			T77	1		T26	1		T83	1
intr_timeout_cnt[3]	21	1			T20	2		T13	1		T14	1
intr_timeout_cnt[4]	19	1			T81	1		T30	1		T254	1
intr_timeout_cnt[5]	8	1			T14	1		T83	1		T114	1
intr_timeout_cnt[6]	20	1			T74	1		T73	2		T53	1
intr_timeout_cnt[7]	10	1			T14	1		T26	1		T31	1
intr_timeout_cnt[8]	15	1			T14	1		T74	1		T43	1
intr_timeout_cnt[9]	6	1			T74	1		T26	1		T255	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T79	1		T33	1		T256	4
class_index[0x0]	intr_timeout_cnt[1]	19	1			T13	1		T39	1		T82	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T26	1		T31	1		T254	1
class_index[0x0]	intr_timeout_cnt[3]	7	1			T20	1		T57	1		T257	1
class_index[0x0]	intr_timeout_cnt[4]	7	1			T81	1		T254	1		T114	2
class_index[0x0]	intr_timeout_cnt[5]	5	1			T14	1		T114	1		T103	1
class_index[0x0]	intr_timeout_cnt[6]	5	1			T73	1		T258	1		T23	1
class_index[0x0]	intr_timeout_cnt[7]	5	1			T31	1		T96	1		T23	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T14	1		T43	1		T22	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T74	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	27	1			T26	1		T84	1		T30	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T76	1		T78	1		T86	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T57	1		T259	3		-	-
class_index[0x1]	intr_timeout_cnt[3]	3	1			T20	1		T85	1		T260	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T261	1		T182	2		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T83	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T74	1		T262	1		T263	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T96	1		T264	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	6	1			T26	1		T23	1		T265	1
class_index[0x1]	intr_timeout_cnt[9]	4	1			T255	1		T266	1		T267	1
class_index[0x2]	intr_timeout_cnt[0]	26	1			T27	1		T91	2		T32	4
class_index[0x2]	intr_timeout_cnt[1]	19	1			T13	1		T70	3		T26	2
class_index[0x2]	intr_timeout_cnt[2]	5	1			T53	1		T254	1		T257	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T31	2		T96	1		T268	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T264	1		T181	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T103	1		T252	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	7	1			T31	1		T22	1		T269	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T270	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	5	1			T74	1		T30	3		T271	1
class_index[0x3]	intr_timeout_cnt[0]	25	1			T74	1		T26	1		T57	4
class_index[0x3]	intr_timeout_cnt[1]	14	1			T53	1		T60	1		T61	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T77	1		T83	1		T261	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T13	1		T14	1		T56	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T30	1		T22	1		T262	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T73	1		T53	1		T272	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T14	1		T26	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T31	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T26	1		-	-		-	-