Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	354115	1			T1	143		T2	1681		T3	1385
all_values[1]	354115	1			T1	143		T2	1681		T3	1385
all_values[2]	354115	1			T1	143		T2	1681		T3	1385
all_values[3]	354115	1			T1	143		T2	1681		T3	1385

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

706112

1

T1

298

T2

3339

T3

2768

auto[1]

710348

1

T1

274

T2

3385

T3

2772

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

840106

1

T1

290

T2

5496

T3

2822

auto[1]

576354

1

T1

282

T2

1228

T3

2718

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100059	1			T1	37		T2	617		T3	335
all_values[0]	auto[0]	auto[1]	76588	1			T1	36		T2	213		T3	335
all_values[0]	auto[1]	auto[0]	101094	1			T1	35		T2	655		T3	358
all_values[0]	auto[1]	auto[1]	76374	1			T1	35		T2	196		T3	357
all_values[1]	auto[0]	auto[0]	105237	1			T1	41		T2	822		T3	357
all_values[1]	auto[0]	auto[1]	71228	1			T1	41		T3	334		T18	10
all_values[1]	auto[1]	auto[0]	106628	1			T1	31		T2	859		T3	359
all_values[1]	auto[1]	auto[1]	71022	1			T1	30		T3	335		T18	8
all_values[2]	auto[0]	auto[0]	107212	1			T1	34		T2	654		T3	368
all_values[2]	auto[0]	auto[1]	68981	1			T1	33		T2	202		T3	343
all_values[2]	auto[1]	auto[0]	108822	1			T1	38		T2	627		T3	350
all_values[2]	auto[1]	auto[1]	69100	1			T1	38		T2	198		T3	324
all_values[3]	auto[0]	auto[0]	105008	1			T1	39		T2	627		T3	350
all_values[3]	auto[0]	auto[1]	71799	1			T1	37		T2	204		T3	346
all_values[3]	auto[1]	auto[0]	106046	1			T1	35		T2	635		T3	345
all_values[3]	auto[1]	auto[1]	71262	1			T1	32		T2	215		T3	344