Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	354115	1			T1	143		T2	1681		T3	1385
all_pins[1]	354115	1			T1	143		T2	1681		T3	1385
all_pins[2]	354115	1			T1	143		T2	1681		T3	1385
all_pins[3]	354115	1			T1	143		T2	1681		T3	1385

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1128702	1			T1	437		T2	6115		T3	4180
values[0x1]	287758	1			T1	135		T2	609		T3	1360
transitions[0x0=>0x1]	191417	1			T1	88		T2	552		T3	876
transitions[0x1=>0x0]	191690	1			T1	88		T2	552		T3	877

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	277741	1			T1	108		T2	1485		T3	1028
all_pins[0]	values[0x1]	76374	1			T1	35		T2	196		T3	357
all_pins[0]	transitions[0x0=>0x1]	75690	1			T1	35		T2	196		T3	356
all_pins[0]	transitions[0x1=>0x0]	70851	1			T1	32		T2	215		T3	344
all_pins[1]	values[0x0]	283093	1			T1	113		T2	1681		T3	1050
all_pins[1]	values[0x1]	71022	1			T1	30		T3	335		T18	8
all_pins[1]	transitions[0x0=>0x1]	38441	1			T1	16		T3	162		T18	5
all_pins[1]	transitions[0x1=>0x0]	43793	1			T1	21		T2	196		T3	184
all_pins[2]	values[0x0]	285015	1			T1	105		T2	1483		T3	1061
all_pins[2]	values[0x1]	69100	1			T1	38		T2	198		T3	324
all_pins[2]	transitions[0x0=>0x1]	37573	1			T1	22		T2	198		T3	164
all_pins[2]	transitions[0x1=>0x0]	39495	1			T1	14		T3	175		T18	8
all_pins[3]	values[0x0]	282853	1			T1	111		T2	1466		T3	1041
all_pins[3]	values[0x1]	71262	1			T1	32		T2	215		T3	344
all_pins[3]	transitions[0x0=>0x1]	39713	1			T1	15		T2	158		T3	194
all_pins[3]	transitions[0x1=>0x0]	37551	1			T1	21		T2	141		T3	174