Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	92603	1			T3	593		T5	328		T13	370
accum_cnt_1000	232308	1			T1	55		T2	1883		T3	1341
accum_cnt_100	29338	1			T1	41		T2	296		T3	79
accum_cnt_50	62929	1			T1	31		T2	233		T3	51
accum_cnt_10	166751	1			T1	10		T2	70		T3	14
accum_cnt_0	418746	1			T1	147		T2	2506		T3	2082

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262122	1			T1	71		T2	1247		T3	1040
class_index[0x1]	262122	1			T1	71		T2	1247		T3	1040
class_index[0x2]	262122	1			T1	71		T2	1247		T3	1040
class_index[0x3]	262122	1			T1	71		T2	1247		T3	1040

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25951	1			T13	75		T15	401		T17	113
class_index[0x0]	accum_cnt_1000	65222	1			T1	37		T5	86		T13	270
class_index[0x0]	accum_cnt_100	10358	1			T1	15		T5	25		T13	44
class_index[0x0]	accum_cnt_50	18255	1			T1	13		T18	24		T5	20
class_index[0x0]	accum_cnt_10	40337	1			T1	3		T18	7		T4	7
class_index[0x0]	accum_cnt_0	85828	1			T1	3		T2	1247		T3	1040
class_index[0x1]	accum_cnt_2000	23796	1			T13	132		T14	274		T48	474
class_index[0x1]	accum_cnt_1000	55230	1			T13	400		T14	1177		T46	46
class_index[0x1]	accum_cnt_100	6349	1			T13	104		T14	123		T46	28
class_index[0x1]	accum_cnt_50	15259	1			T5	130		T13	102		T14	146
class_index[0x1]	accum_cnt_10	44318	1			T18	30		T4	7		T19	1
class_index[0x1]	accum_cnt_0	107347	1			T1	71		T2	1247		T3	1040
class_index[0x2]	accum_cnt_2000	24052	1			T3	239		T5	101		T14	115
class_index[0x2]	accum_cnt_1000	55476	1			T2	929		T3	725		T19	2
class_index[0x2]	accum_cnt_100	5963	1			T2	149		T3	39		T19	15
class_index[0x2]	accum_cnt_50	18431	1			T2	124		T3	29		T19	16
class_index[0x2]	accum_cnt_10	41590	1			T2	38		T3	7		T4	10
class_index[0x2]	accum_cnt_0	108006	1			T1	71		T2	7		T3	1
class_index[0x3]	accum_cnt_2000	18804	1			T3	354		T5	227		T13	163
class_index[0x3]	accum_cnt_1000	56380	1			T1	18		T2	954		T3	616
class_index[0x3]	accum_cnt_100	6668	1			T1	26		T2	147		T3	40
class_index[0x3]	accum_cnt_50	10984	1			T1	18		T2	109		T3	22
class_index[0x3]	accum_cnt_10	40506	1			T1	7		T2	32		T3	7
class_index[0x3]	accum_cnt_0	117565	1			T1	2		T2	5		T3	1