Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3375	1			T4	3		T13	67		T25	21
alert[0x1]	7068	1			T13	42		T14	55		T17	621
alert[0x2]	13103	1			T14	22		T17	4313		T71	466
alert[0x3]	7132	1			T14	32		T17	34		T47	26
alert[0x4]	5578	1			T5	17		T14	40		T71	3
alert[0x5]	6238	1			T5	5		T13	30		T14	1727
alert[0x6]	3838	1			T47	17		T26	13		T199	1
alert[0x7]	6326	1			T5	2		T14	1473		T7	1
alert[0x8]	8555	1			T2	1		T14	8		T25	13
alert[0x9]	10949	1			T5	25		T14	483		T76	12
alert[0xa]	7014	1			T47	2216		T71	19		T25	2
alert[0xb]	4903	1			T13	27		T17	122		T47	24
alert[0xc]	5596	1			T13	36		T47	9		T76	272
alert[0xd]	17560	1			T14	218		T7	1		T71	580
alert[0xe]	3698	1			T5	15		T17	266		T76	49
alert[0xf]	6677	1			T5	4		T13	12		T17	6
alert[0x10]	6877	1			T47	19		T71	26		T25	3
alert[0x11]	5596	1			T18	26		T5	17		T13	47
alert[0x12]	3795	1			T5	20		T71	7		T76	8
alert[0x13]	8131	1			T5	10		T13	57		T14	248
alert[0x14]	6098	1			T6	1		T14	246		T17	37
alert[0x15]	21193	1			T13	3336		T14	2368		T7	1
alert[0x16]	7095	1			T13	31		T17	5		T47	492
alert[0x17]	6745	1			T13	21		T14	8		T47	3
alert[0x18]	8243	1			T14	23		T71	7		T26	116
alert[0x19]	16423	1			T13	96		T14	1648		T71	297
alert[0x1a]	4126	1			T13	52		T47	174		T25	34
alert[0x1b]	9406	1			T18	1		T5	2		T17	17
alert[0x1c]	1174	1			T13	60		T17	257		T76	10
alert[0x1d]	9271	1			T5	12		T6	2		T13	8
alert[0x1e]	5452	1			T13	313		T17	1		T47	49
alert[0x1f]	4899	1			T18	19		T14	456		T74	1
alert[0x20]	5261	1			T17	29		T71	15		T76	36
alert[0x21]	6838	1			T13	43		T81	1		T84	504
alert[0x22]	7218	1			T14	100		T47	503		T71	103
alert[0x23]	6893	1			T5	13		T13	24		T47	55
alert[0x24]	6074	1			T13	36		T47	507		T76	241
alert[0x25]	5698	1			T14	1		T71	26		T196	1
alert[0x26]	13340	1			T4	3		T71	592		T76	59
alert[0x27]	9984	1			T13	671		T47	24		T71	242
alert[0x28]	5887	1			T2	1		T13	27		T17	38
alert[0x29]	6147	1			T17	42		T74	1		T26	1744
alert[0x2a]	7746	1			T14	716		T43	6		T71	7
alert[0x2b]	5238	1			T5	12		T13	191		T17	43
alert[0x2c]	2803	1			T18	3		T5	94		T14	15
alert[0x2d]	6100	1			T14	40		T17	420		T47	17
alert[0x2e]	5655	1			T14	65		T76	682		T245	95
alert[0x2f]	5756	1			T5	2		T13	122		T14	190
alert[0x30]	11699	1			T4	2		T13	58		T14	335
alert[0x31]	4886	1			T5	11		T13	27		T14	145
alert[0x32]	8477	1			T14	11		T47	111		T71	25
alert[0x33]	7420	1			T5	23		T14	17		T17	257
alert[0x34]	3370	1			T5	1		T13	21		T14	36
alert[0x35]	5336	1			T13	8		T14	1		T7	1
alert[0x36]	4885	1			T13	226		T14	71		T71	1036
alert[0x37]	5276	1			T13	43		T14	1809		T47	75
alert[0x38]	13079	1			T18	1		T5	6		T14	2149
alert[0x39]	3814	1			T14	15		T17	5		T47	60
alert[0x3a]	10585	1			T47	191		T71	300		T76	302
alert[0x3b]	8531	1			T13	869		T17	281		T76	28
alert[0x3c]	11759	1			T14	684		T76	46		T26	17
alert[0x3d]	8628	1			T4	1		T25	1		T81	1
alert[0x3e]	11611	1			T14	88		T17	75		T47	423
alert[0x3f]	4873	1			T13	6		T7	1		T17	1965
alert[0x40]	11606	1			T5	1		T13	447		T74	4

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	135577	1			T18	50		T4	1		T5	223
class_i[0x1]	101126	1			T5	24		T13	2167		T14	85
class_i[0x2]	103394	1			T4	8		T5	9		T6	3
class_i[0x3]	144510	1			T2	2		T5	36		T13	3373

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

483972

1

T18

50

T4

9

T5

292

alert_ping_fail

635

1

T2

2

T6

3

T7

6

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3368	1			T4	3		T13	67		T25	21
alert_integrity_fail	alert[0x1]	7060	1			T13	42		T14	55		T17	621
alert_integrity_fail	alert[0x2]	13088	1			T14	22		T17	4313		T71	466
alert_integrity_fail	alert[0x3]	7124	1			T14	32		T17	34		T47	26
alert_integrity_fail	alert[0x4]	5571	1			T5	17		T14	40		T71	3
alert_integrity_fail	alert[0x5]	6224	1			T5	5		T13	30		T14	1727
alert_integrity_fail	alert[0x6]	3826	1			T47	17		T26	13		T245	748
alert_integrity_fail	alert[0x7]	6312	1			T5	2		T14	1473		T71	29
alert_integrity_fail	alert[0x8]	8543	1			T14	8		T25	13		T26	1586
alert_integrity_fail	alert[0x9]	10942	1			T5	25		T14	483		T76	12
alert_integrity_fail	alert[0xa]	7004	1			T47	2216		T71	19		T25	2
alert_integrity_fail	alert[0xb]	4896	1			T13	27		T17	122		T47	24
alert_integrity_fail	alert[0xc]	5586	1			T13	36		T47	9		T76	272
alert_integrity_fail	alert[0xd]	17555	1			T14	218		T71	580		T76	16
alert_integrity_fail	alert[0xe]	3692	1			T5	15		T17	266		T76	49
alert_integrity_fail	alert[0xf]	6668	1			T5	4		T13	12		T17	6
alert_integrity_fail	alert[0x10]	6873	1			T47	19		T71	26		T25	3
alert_integrity_fail	alert[0x11]	5590	1			T18	26		T5	17		T13	47
alert_integrity_fail	alert[0x12]	3787	1			T5	20		T71	7		T76	8
alert_integrity_fail	alert[0x13]	8116	1			T5	10		T13	57		T14	248
alert_integrity_fail	alert[0x14]	6077	1			T14	246		T17	37		T76	2
alert_integrity_fail	alert[0x15]	21176	1			T13	3336		T14	2368		T17	5
alert_integrity_fail	alert[0x16]	7080	1			T13	31		T17	5		T47	492
alert_integrity_fail	alert[0x17]	6732	1			T13	21		T14	8		T47	3
alert_integrity_fail	alert[0x18]	8236	1			T14	23		T71	7		T26	116
alert_integrity_fail	alert[0x19]	16410	1			T13	96		T14	1648		T71	297
alert_integrity_fail	alert[0x1a]	4120	1			T13	52		T47	174		T25	34
alert_integrity_fail	alert[0x1b]	9398	1			T18	1		T5	2		T17	17
alert_integrity_fail	alert[0x1c]	1162	1			T13	60		T17	257		T76	10
alert_integrity_fail	alert[0x1d]	9263	1			T5	12		T13	8		T47	1274
alert_integrity_fail	alert[0x1e]	5441	1			T13	313		T17	1		T47	49
alert_integrity_fail	alert[0x1f]	4888	1			T18	19		T14	456		T74	1
alert_integrity_fail	alert[0x20]	5249	1			T17	29		T71	15		T76	36
alert_integrity_fail	alert[0x21]	6829	1			T13	43		T81	1		T84	504
alert_integrity_fail	alert[0x22]	7213	1			T14	100		T47	503		T71	103
alert_integrity_fail	alert[0x23]	6888	1			T5	13		T13	24		T47	55
alert_integrity_fail	alert[0x24]	6062	1			T13	36		T47	507		T76	241
alert_integrity_fail	alert[0x25]	5688	1			T14	1		T71	26		T30	678
alert_integrity_fail	alert[0x26]	13332	1			T4	3		T71	592		T76	59
alert_integrity_fail	alert[0x27]	9978	1			T13	671		T47	24		T71	242
alert_integrity_fail	alert[0x28]	5873	1			T13	27		T17	38		T47	745
alert_integrity_fail	alert[0x29]	6137	1			T17	42		T74	1		T26	1744
alert_integrity_fail	alert[0x2a]	7737	1			T14	716		T43	6		T71	7
alert_integrity_fail	alert[0x2b]	5227	1			T5	12		T13	191		T17	43
alert_integrity_fail	alert[0x2c]	2786	1			T18	3		T5	94		T14	15
alert_integrity_fail	alert[0x2d]	6090	1			T14	40		T17	420		T47	17
alert_integrity_fail	alert[0x2e]	5644	1			T14	65		T76	682		T245	95
alert_integrity_fail	alert[0x2f]	5740	1			T5	2		T13	122		T14	190
alert_integrity_fail	alert[0x30]	11687	1			T4	2		T13	58		T14	335
alert_integrity_fail	alert[0x31]	4880	1			T5	11		T13	27		T14	145
alert_integrity_fail	alert[0x32]	8468	1			T14	11		T47	111		T71	25
alert_integrity_fail	alert[0x33]	7406	1			T5	23		T14	17		T17	257
alert_integrity_fail	alert[0x34]	3361	1			T5	1		T13	21		T14	36
alert_integrity_fail	alert[0x35]	5327	1			T13	8		T14	1		T17	41
alert_integrity_fail	alert[0x36]	4873	1			T13	226		T14	71		T71	1036
alert_integrity_fail	alert[0x37]	5269	1			T13	43		T14	1809		T47	75
alert_integrity_fail	alert[0x38]	13072	1			T18	1		T5	6		T14	2149
alert_integrity_fail	alert[0x39]	3810	1			T14	15		T17	5		T47	60
alert_integrity_fail	alert[0x3a]	10577	1			T47	191		T71	300		T76	302
alert_integrity_fail	alert[0x3b]	8522	1			T13	869		T17	281		T76	28
alert_integrity_fail	alert[0x3c]	11750	1			T14	684		T76	46		T26	17
alert_integrity_fail	alert[0x3d]	8623	1			T4	1		T25	1		T81	1
alert_integrity_fail	alert[0x3e]	11601	1			T14	88		T17	75		T47	423
alert_integrity_fail	alert[0x3f]	4866	1			T13	6		T17	1965		T47	9
alert_integrity_fail	alert[0x40]	11599	1			T5	1		T13	447		T74	4
alert_ping_fail	alert[0x0]	7	1			T225	1		T292	1		T293	1
alert_ping_fail	alert[0x1]	8	1			T9	1		T294	1		T295	2
alert_ping_fail	alert[0x2]	15	1			T9	1		T294	1		T95	1
alert_ping_fail	alert[0x3]	8	1			T199	1		T296	1		T297	1
alert_ping_fail	alert[0x4]	7	1			T8	1		T9	1		T196	1
alert_ping_fail	alert[0x5]	14	1			T9	1		T298	1		T299	1
alert_ping_fail	alert[0x6]	12	1			T199	1		T300	2		T301	1
alert_ping_fail	alert[0x7]	14	1			T7	1		T111	1		T302	1
alert_ping_fail	alert[0x8]	12	1			T2	1		T303	2		T290	1
alert_ping_fail	alert[0x9]	7	1			T294	1		T109	1		T293	1
alert_ping_fail	alert[0xa]	10	1			T9	1		T284	1		T111	1
alert_ping_fail	alert[0xb]	7	1			T8	1		T303	1		T225	2
alert_ping_fail	alert[0xc]	10	1			T304	1		T305	1		T295	1
alert_ping_fail	alert[0xd]	5	1			T7	1		T306	1		T307	1
alert_ping_fail	alert[0xe]	6	1			T298	1		T111	1		T308	1
alert_ping_fail	alert[0xf]	9	1			T309	1		T302	1		T310	1
alert_ping_fail	alert[0x10]	4	1			T310	2		T292	1		T311	1
alert_ping_fail	alert[0x11]	6	1			T8	2		T307	1		T308	1
alert_ping_fail	alert[0x12]	8	1			T196	1		T303	1		T306	2
alert_ping_fail	alert[0x13]	15	1			T294	1		T299	1		T312	2
alert_ping_fail	alert[0x14]	21	1			T6	1		T305	1		T313	1
alert_ping_fail	alert[0x15]	17	1			T7	1		T309	1		T305	1
alert_ping_fail	alert[0x16]	15	1			T196	2		T199	1		T309	1
alert_ping_fail	alert[0x17]	13	1			T9	1		T196	1		T199	2
alert_ping_fail	alert[0x18]	7	1			T314	1		T315	1		T316	1
alert_ping_fail	alert[0x19]	13	1			T303	1		T317	1		T305	1
alert_ping_fail	alert[0x1a]	6	1			T9	2		T318	1		T314	1
alert_ping_fail	alert[0x1b]	8	1			T196	1		T303	1		T310	1
alert_ping_fail	alert[0x1c]	12	1			T9	1		T299	1		T302	1
alert_ping_fail	alert[0x1d]	8	1			T6	2		T9	1		T319	1
alert_ping_fail	alert[0x1e]	11	1			T196	1		T298	1		T299	1
alert_ping_fail	alert[0x1f]	11	1			T8	1		T303	1		T320	1
alert_ping_fail	alert[0x20]	12	1			T8	1		T305	1		T302	1
alert_ping_fail	alert[0x21]	9	1			T304	1		T303	1		T302	1
alert_ping_fail	alert[0x22]	5	1			T297	1		T303	1		T321	1
alert_ping_fail	alert[0x23]	5	1			T9	1		T297	1		T292	1
alert_ping_fail	alert[0x24]	12	1			T294	1		T303	1		T299	1
alert_ping_fail	alert[0x25]	10	1			T196	1		T310	1		T321	1
alert_ping_fail	alert[0x26]	8	1			T9	1		T302	1		T306	1
alert_ping_fail	alert[0x27]	6	1			T296	1		T297	1		T306	1
alert_ping_fail	alert[0x28]	14	1			T2	1		T121	1		T9	1
alert_ping_fail	alert[0x29]	10	1			T196	1		T310	1		T315	2
alert_ping_fail	alert[0x2a]	9	1			T304	1		T310	1		T321	1
alert_ping_fail	alert[0x2b]	11	1			T121	1		T304	1		T303	1
alert_ping_fail	alert[0x2c]	17	1			T196	1		T322	1		T225	1
alert_ping_fail	alert[0x2d]	10	1			T290	1		T111	1		T323	1
alert_ping_fail	alert[0x2e]	11	1			T297	1		T310	1		T314	1
alert_ping_fail	alert[0x2f]	16	1			T196	2		T318	1		T305	3
alert_ping_fail	alert[0x30]	12	1			T7	1		T199	2		T298	1
alert_ping_fail	alert[0x31]	6	1			T296	1		T316	1		T292	2
alert_ping_fail	alert[0x32]	9	1			T9	1		T297	1		T317	1
alert_ping_fail	alert[0x33]	14	1			T9	2		T111	1		T225	2
alert_ping_fail	alert[0x34]	9	1			T196	1		T225	2		T310	1
alert_ping_fail	alert[0x35]	9	1			T7	1		T225	1		T310	1
alert_ping_fail	alert[0x36]	12	1			T196	1		T310	1		T295	1
alert_ping_fail	alert[0x37]	7	1			T310	2		T307	1		T311	1
alert_ping_fail	alert[0x38]	7	1			T196	1		T199	1		T315	1
alert_ping_fail	alert[0x39]	4	1			T8	1		T297	1		T303	1
alert_ping_fail	alert[0x3a]	8	1			T295	1		T321	2		T314	1
alert_ping_fail	alert[0x3b]	9	1			T298	1		T299	1		T109	2
alert_ping_fail	alert[0x3c]	9	1			T297	1		T305	1		T310	1
alert_ping_fail	alert[0x3d]	5	1			T317	1		T295	1		T324	1
alert_ping_fail	alert[0x3e]	10	1			T199	1		T298	1		T299	1
alert_ping_fail	alert[0x3f]	7	1			T7	1		T309	1		T111	1
alert_ping_fail	alert[0x40]	7	1			T9	1		T298	1		T310	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	135471	1			T18	50		T4	1		T5	223
alert_integrity_fail	class_i[0x1]	101026	1			T5	24		T13	2167		T14	85
alert_integrity_fail	class_i[0x2]	103181	1			T4	8		T5	9		T13	126
alert_integrity_fail	class_i[0x3]	144294	1			T5	36		T13	3373		T14	4629
alert_ping_fail	class_i[0x0]	106	1			T9	10		T196	1		T309	4
alert_ping_fail	class_i[0x1]	100	1			T9	2		T196	4		T199	8
alert_ping_fail	class_i[0x2]	213	1			T6	3		T121	2		T8	7
alert_ping_fail	class_i[0x3]	216	1			T2	2		T7	6		T9	4