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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.71 100.00 100.00 100.00 99.38 99.68


Total test records in report: 832
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T138 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3345088777 May 19 02:22:30 PM PDT 24 May 19 02:39:27 PM PDT 24 14677152553 ps
T776 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.590387218 May 19 02:21:41 PM PDT 24 May 19 02:21:43 PM PDT 24 7630759 ps
T180 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2124935826 May 19 02:21:39 PM PDT 24 May 19 02:21:42 PM PDT 24 60152414 ps
T777 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2822679065 May 19 02:22:49 PM PDT 24 May 19 02:22:53 PM PDT 24 48592974 ps
T778 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1478159928 May 19 02:22:15 PM PDT 24 May 19 02:22:16 PM PDT 24 17965843 ps
T779 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3363684036 May 19 02:22:20 PM PDT 24 May 19 02:22:22 PM PDT 24 10928781 ps
T780 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2099174293 May 19 02:22:35 PM PDT 24 May 19 02:22:37 PM PDT 24 9884866 ps
T130 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1919976853 May 19 02:21:54 PM PDT 24 May 19 02:26:51 PM PDT 24 4511356230 ps
T781 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1223883139 May 19 02:22:50 PM PDT 24 May 19 02:22:52 PM PDT 24 6620200 ps
T142 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3302822031 May 19 02:22:11 PM PDT 24 May 19 02:31:06 PM PDT 24 7906129512 ps
T782 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2517823339 May 19 02:22:35 PM PDT 24 May 19 02:22:37 PM PDT 24 11185069 ps
T783 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3801786376 May 19 02:21:17 PM PDT 24 May 19 02:21:24 PM PDT 24 273375327 ps
T148 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2586703244 May 19 02:20:58 PM PDT 24 May 19 02:22:49 PM PDT 24 820649917 ps
T784 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3417633329 May 19 02:22:50 PM PDT 24 May 19 02:22:52 PM PDT 24 9526969 ps
T785 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2858771930 May 19 02:22:14 PM PDT 24 May 19 02:22:27 PM PDT 24 92789085 ps
T786 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2881986109 May 19 02:21:50 PM PDT 24 May 19 02:21:56 PM PDT 24 264335193 ps
T787 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2306769355 May 19 02:22:51 PM PDT 24 May 19 02:22:53 PM PDT 24 10146303 ps
T788 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.214503747 May 19 02:20:16 PM PDT 24 May 19 02:20:23 PM PDT 24 183293043 ps
T789 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1016411799 May 19 02:20:57 PM PDT 24 May 19 02:20:59 PM PDT 24 9878232 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1484707512 May 19 02:22:09 PM PDT 24 May 19 02:22:11 PM PDT 24 30510421 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3017010227 May 19 02:22:03 PM PDT 24 May 19 02:22:09 PM PDT 24 54443762 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1578984525 May 19 02:20:39 PM PDT 24 May 19 02:21:47 PM PDT 24 580790787 ps
T793 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3397391120 May 19 02:22:56 PM PDT 24 May 19 02:22:58 PM PDT 24 18241620 ps
T794 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1361229347 May 19 02:20:28 PM PDT 24 May 19 02:20:49 PM PDT 24 293882587 ps
T132 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.92841197 May 19 02:20:44 PM PDT 24 May 19 02:22:30 PM PDT 24 6190381857 ps
T795 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.127562891 May 19 02:22:28 PM PDT 24 May 19 02:22:30 PM PDT 24 19523657 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3720223082 May 19 02:20:16 PM PDT 24 May 19 02:40:17 PM PDT 24 68185433513 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.948295389 May 19 02:21:39 PM PDT 24 May 19 02:21:45 PM PDT 24 262778688 ps
T797 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2540930596 May 19 02:22:40 PM PDT 24 May 19 02:22:42 PM PDT 24 9782777 ps
T133 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1472143561 May 19 02:21:53 PM PDT 24 May 19 02:25:04 PM PDT 24 1628283217 ps
T145 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3695671566 May 19 02:21:25 PM PDT 24 May 19 02:26:47 PM PDT 24 7917174631 ps
T798 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3137095515 May 19 02:20:57 PM PDT 24 May 19 02:21:03 PM PDT 24 128419424 ps
T152 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1637541547 May 19 02:20:49 PM PDT 24 May 19 02:37:00 PM PDT 24 235414432722 ps
T799 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2029717676 May 19 02:21:17 PM PDT 24 May 19 02:22:53 PM PDT 24 1289140211 ps
T800 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4005098187 May 19 02:21:43 PM PDT 24 May 19 02:22:07 PM PDT 24 679514897 ps
T801 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.788804158 May 19 02:21:11 PM PDT 24 May 19 02:21:37 PM PDT 24 273823518 ps
T131 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3832162308 May 19 02:21:38 PM PDT 24 May 19 02:27:55 PM PDT 24 23981812533 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1289977793 May 19 02:21:24 PM PDT 24 May 19 02:21:35 PM PDT 24 578219898 ps
T803 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4167423053 May 19 02:22:40 PM PDT 24 May 19 02:22:42 PM PDT 24 31858383 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3857443158 May 19 02:20:17 PM PDT 24 May 19 02:20:24 PM PDT 24 45250376 ps
T170 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1853682386 May 19 02:22:31 PM PDT 24 May 19 02:23:12 PM PDT 24 5214703108 ps
T153 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.562955641 May 19 02:22:28 PM PDT 24 May 19 02:39:01 PM PDT 24 58561516285 ps
T151 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.110937688 May 19 02:21:19 PM PDT 24 May 19 02:24:23 PM PDT 24 3488962046 ps
T805 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1617042536 May 19 02:22:55 PM PDT 24 May 19 02:22:57 PM PDT 24 13447689 ps
T806 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2478331492 May 19 02:21:35 PM PDT 24 May 19 02:26:54 PM PDT 24 9136804767 ps
T150 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4050336777 May 19 02:22:25 PM PDT 24 May 19 02:24:55 PM PDT 24 1985949064 ps
T807 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1289375704 May 19 02:21:54 PM PDT 24 May 19 02:22:04 PM PDT 24 133160234 ps
T808 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3933204401 May 19 02:21:35 PM PDT 24 May 19 02:21:39 PM PDT 24 34660162 ps
T809 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.528129796 May 19 02:20:37 PM PDT 24 May 19 02:20:39 PM PDT 24 7635212 ps
T810 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2477625534 May 19 02:22:19 PM PDT 24 May 19 02:22:30 PM PDT 24 266216066 ps
T811 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1004828224 May 19 02:21:43 PM PDT 24 May 19 02:21:49 PM PDT 24 36154371 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2814693188 May 19 02:20:46 PM PDT 24 May 19 02:21:06 PM PDT 24 264809445 ps
T155 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1934587175 May 19 02:22:15 PM PDT 24 May 19 02:45:12 PM PDT 24 126046609591 ps
T813 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1082807104 May 19 02:21:42 PM PDT 24 May 19 02:31:05 PM PDT 24 26541577623 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2873456282 May 19 02:20:56 PM PDT 24 May 19 02:27:57 PM PDT 24 5872763909 ps
T815 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2448193077 May 19 02:21:19 PM PDT 24 May 19 02:21:27 PM PDT 24 193725354 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1630554339 May 19 02:21:02 PM PDT 24 May 19 02:21:07 PM PDT 24 40391142 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4006583829 May 19 02:20:55 PM PDT 24 May 19 02:21:12 PM PDT 24 987904191 ps
T818 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.354516708 May 19 02:22:26 PM PDT 24 May 19 02:22:43 PM PDT 24 413744831 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3207896257 May 19 02:22:03 PM PDT 24 May 19 02:22:18 PM PDT 24 2020007134 ps
T820 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2102176609 May 19 02:21:35 PM PDT 24 May 19 02:24:02 PM PDT 24 3723175846 ps
T144 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3137531570 May 19 02:21:43 PM PDT 24 May 19 02:26:45 PM PDT 24 9024622800 ps
T821 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1254800738 May 19 02:22:52 PM PDT 24 May 19 02:22:54 PM PDT 24 6845852 ps
T158 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2184847715 May 19 02:22:20 PM PDT 24 May 19 02:27:34 PM PDT 24 28024845951 ps
T173 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2176091700 May 19 02:20:46 PM PDT 24 May 19 02:20:50 PM PDT 24 456093097 ps
T154 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3776593145 May 19 02:20:45 PM PDT 24 May 19 02:24:19 PM PDT 24 1663152817 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1914856161 May 19 02:20:27 PM PDT 24 May 19 02:20:39 PM PDT 24 360207364 ps
T165 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3937970059 May 19 02:21:25 PM PDT 24 May 19 02:22:43 PM PDT 24 1294624139 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1335067699 May 19 02:21:28 PM PDT 24 May 19 02:21:40 PM PDT 24 136320374 ps
T824 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3316572133 May 19 02:22:35 PM PDT 24 May 19 02:22:37 PM PDT 24 25672364 ps
T825 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2405204007 May 19 02:20:35 PM PDT 24 May 19 02:20:41 PM PDT 24 284300697 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.893275413 May 19 02:20:58 PM PDT 24 May 19 02:27:15 PM PDT 24 22822337736 ps
T827 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1980891845 May 19 02:21:20 PM PDT 24 May 19 02:21:25 PM PDT 24 62212874 ps
T156 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1058688619 May 19 02:20:31 PM PDT 24 May 19 02:23:55 PM PDT 24 12727085848 ps
T157 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2803428654 May 19 02:22:04 PM PDT 24 May 19 02:30:38 PM PDT 24 6443982208 ps
T172 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.64633973 May 19 02:21:24 PM PDT 24 May 19 02:21:59 PM PDT 24 5582561010 ps
T828 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.488389103 May 19 02:22:09 PM PDT 24 May 19 02:22:18 PM PDT 24 366587955 ps
T829 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.213915935 May 19 02:21:49 PM PDT 24 May 19 02:22:26 PM PDT 24 1036971539 ps
T141 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4052169472 May 19 02:21:33 PM PDT 24 May 19 02:26:14 PM PDT 24 3666210421 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3110597587 May 19 02:21:02 PM PDT 24 May 19 02:25:29 PM PDT 24 3326738889 ps
T831 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1353137960 May 19 02:22:34 PM PDT 24 May 19 02:22:43 PM PDT 24 496274162 ps
T832 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1942158296 May 19 02:20:46 PM PDT 24 May 19 02:23:58 PM PDT 24 7645308069 ps

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3559718483
Short name T13
Test name
Test status
Simulation time 279490780463 ps
CPU time 4829.66 seconds
Started May 19 02:32:26 PM PDT 24
Finished May 19 03:52:57 PM PDT 24
Peak memory 321536 kb
Host smart-b7453aea-f363-4dff-93fb-45e067fe77b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559718483 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3559718483
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2067186880
Short name T10
Test name
Test status
Simulation time 715930589 ps
CPU time 23.2 seconds
Started May 19 02:28:53 PM PDT 24
Finished May 19 02:29:17 PM PDT 24
Peak memory 271096 kb
Host smart-6771cdb2-ea55-4a36-981e-329dec727ab1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2067186880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2067186880
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.239803147
Short name T26
Test name
Test status
Simulation time 163145378246 ps
CPU time 5650.7 seconds
Started May 19 02:31:53 PM PDT 24
Finished May 19 04:06:06 PM PDT 24
Peak memory 322716 kb
Host smart-9ae7e35c-0a8f-4f1a-b804-5c71d8d4d1bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239803147 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.239803147
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2190128695
Short name T160
Test name
Test status
Simulation time 3318289782 ps
CPU time 42.25 seconds
Started May 19 02:20:15 PM PDT 24
Finished May 19 02:20:57 PM PDT 24
Peak memory 239560 kb
Host smart-4fdab4c6-c0c6-4820-a5c0-3722f19ff69b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2190128695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2190128695
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1781689464
Short name T92
Test name
Test status
Simulation time 50569264800 ps
CPU time 1212.84 seconds
Started May 19 02:28:53 PM PDT 24
Finished May 19 02:49:07 PM PDT 24
Peak memory 289896 kb
Host smart-917fdd6c-c004-4ad8-bd10-31738b5d3e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781689464 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1781689464
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.734095872
Short name T121
Test name
Test status
Simulation time 103172558475 ps
CPU time 1487.79 seconds
Started May 19 02:32:36 PM PDT 24
Finished May 19 02:57:25 PM PDT 24
Peak memory 267240 kb
Host smart-f900b20b-dade-4e5b-84b7-cafd5ee993d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734095872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.734095872
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3832162308
Short name T131
Test name
Test status
Simulation time 23981812533 ps
CPU time 377.3 seconds
Started May 19 02:21:38 PM PDT 24
Finished May 19 02:27:55 PM PDT 24
Peak memory 265084 kb
Host smart-4202d2ae-b2c6-45ae-ac68-aab906f0dc37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3832162308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3832162308
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.536640032
Short name T57
Test name
Test status
Simulation time 285661066239 ps
CPU time 4857.92 seconds
Started May 19 02:31:42 PM PDT 24
Finished May 19 03:52:42 PM PDT 24
Peak memory 306028 kb
Host smart-c9d49ad9-df08-4b1f-8c45-01fdf1586d09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536640032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.536640032
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2970545133
Short name T31
Test name
Test status
Simulation time 200929854973 ps
CPU time 3525.42 seconds
Started May 19 02:31:38 PM PDT 24
Finished May 19 03:30:25 PM PDT 24
Peak memory 300584 kb
Host smart-58ceaa88-53cf-41d3-b8ae-e22fbf63c365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970545133 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2970545133
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1268624205
Short name T124
Test name
Test status
Simulation time 12888685799 ps
CPU time 612.05 seconds
Started May 19 02:22:19 PM PDT 24
Finished May 19 02:32:32 PM PDT 24
Peak memory 265052 kb
Host smart-ce8a9a9a-db7d-4757-beac-c9c81fdb18c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268624205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1268624205
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4011610072
Short name T76
Test name
Test status
Simulation time 54670584858 ps
CPU time 3414.39 seconds
Started May 19 02:30:27 PM PDT 24
Finished May 19 03:27:22 PM PDT 24
Peak memory 289772 kb
Host smart-80645774-800e-4ebc-96e7-48da834f9595
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011610072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4011610072
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3502918340
Short name T139
Test name
Test status
Simulation time 5148237657 ps
CPU time 716.77 seconds
Started May 19 02:21:54 PM PDT 24
Finished May 19 02:33:52 PM PDT 24
Peak memory 265268 kb
Host smart-e3ad287e-3e18-4a73-b37e-57d460f8fa95
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502918340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3502918340
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3994075376
Short name T109
Test name
Test status
Simulation time 64822606035 ps
CPU time 525.02 seconds
Started May 19 02:29:46 PM PDT 24
Finished May 19 02:38:32 PM PDT 24
Peak memory 248204 kb
Host smart-313e6f68-fc77-4f4e-8c59-058104059c12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994075376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3994075376
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2070745064
Short name T2
Test name
Test status
Simulation time 139249995447 ps
CPU time 2511.54 seconds
Started May 19 02:31:16 PM PDT 24
Finished May 19 03:13:08 PM PDT 24
Peak memory 281560 kb
Host smart-76ec69bc-945d-48e9-adc8-e4e16d1d1cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070745064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2070745064
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1528288197
Short name T136
Test name
Test status
Simulation time 12054064904 ps
CPU time 862.92 seconds
Started May 19 02:20:55 PM PDT 24
Finished May 19 02:35:19 PM PDT 24
Peak memory 265124 kb
Host smart-535f2c34-eea4-4168-ac26-c37bf675817d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528288197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1528288197
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1368998922
Short name T345
Test name
Test status
Simulation time 8656485 ps
CPU time 1.47 seconds
Started May 19 02:21:19 PM PDT 24
Finished May 19 02:21:21 PM PDT 24
Peak memory 235660 kb
Host smart-215e5af9-7f81-4ce2-a3d3-005c59d749f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1368998922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1368998922
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1637541547
Short name T152
Test name
Test status
Simulation time 235414432722 ps
CPU time 970.18 seconds
Started May 19 02:20:49 PM PDT 24
Finished May 19 02:37:00 PM PDT 24
Peak memory 270652 kb
Host smart-5db4263c-77ea-443b-8488-248998dfb376
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637541547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1637541547
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2137097840
Short name T116
Test name
Test status
Simulation time 13203419459 ps
CPU time 1342.82 seconds
Started May 19 02:33:26 PM PDT 24
Finished May 19 02:55:50 PM PDT 24
Peak memory 282292 kb
Host smart-98725232-b4e4-45c8-90d3-7bd2c39d764f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137097840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2137097840
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2106111757
Short name T9
Test name
Test status
Simulation time 144906055328 ps
CPU time 416.99 seconds
Started May 19 02:31:15 PM PDT 24
Finished May 19 02:38:12 PM PDT 24
Peak memory 248752 kb
Host smart-aa03f93e-a367-4c65-987b-40e3b099c976
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106111757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2106111757
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.214732359
Short name T14
Test name
Test status
Simulation time 94095210107 ps
CPU time 4460.36 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 03:43:02 PM PDT 24
Peak memory 351932 kb
Host smart-2d488b5f-3ed7-4221-af4a-fafef6199ae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214732359 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.214732359
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3083512935
Short name T326
Test name
Test status
Simulation time 200648421260 ps
CPU time 3547.06 seconds
Started May 19 02:33:10 PM PDT 24
Finished May 19 03:32:18 PM PDT 24
Peak memory 289256 kb
Host smart-937c7c20-bc81-4973-9aa4-bb4ba0b923af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083512935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3083512935
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3695671566
Short name T145
Test name
Test status
Simulation time 7917174631 ps
CPU time 321.25 seconds
Started May 19 02:21:25 PM PDT 24
Finished May 19 02:26:47 PM PDT 24
Peak memory 270736 kb
Host smart-1fa1a26b-ff5f-4f1c-af52-0f18c55689dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3695671566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3695671566
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3918516457
Short name T316
Test name
Test status
Simulation time 23969947042 ps
CPU time 500.47 seconds
Started May 19 02:32:50 PM PDT 24
Finished May 19 02:41:11 PM PDT 24
Peak memory 248040 kb
Host smart-433a1695-148d-4f89-932c-21289d15cf93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918516457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3918516457
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.956403339
Short name T129
Test name
Test status
Simulation time 12718657328 ps
CPU time 1047.62 seconds
Started May 19 02:21:36 PM PDT 24
Finished May 19 02:39:04 PM PDT 24
Peak memory 265328 kb
Host smart-992d304f-ac50-4a29-99f8-90fe6172968b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956403339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.956403339
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.562955641
Short name T153
Test name
Test status
Simulation time 58561516285 ps
CPU time 992.27 seconds
Started May 19 02:22:28 PM PDT 24
Finished May 19 02:39:01 PM PDT 24
Peak memory 273040 kb
Host smart-9a6d81be-6c8c-4c06-8951-d86f157f1fe0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562955641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.562955641
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.328214588
Short name T310
Test name
Test status
Simulation time 14317764207 ps
CPU time 575.86 seconds
Started May 19 02:33:27 PM PDT 24
Finished May 19 02:43:03 PM PDT 24
Peak memory 248040 kb
Host smart-64071eda-ae2a-45f8-9080-1a8b6fd463dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328214588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.328214588
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.647077678
Short name T300
Test name
Test status
Simulation time 42448461862 ps
CPU time 2365.65 seconds
Started May 19 02:29:06 PM PDT 24
Finished May 19 03:08:33 PM PDT 24
Peak memory 272696 kb
Host smart-6bb7220a-884e-45c7-966d-462ff152d57d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647077678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.647077678
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.365259830
Short name T134
Test name
Test status
Simulation time 2379265515 ps
CPU time 223.98 seconds
Started May 19 02:21:07 PM PDT 24
Finished May 19 02:24:51 PM PDT 24
Peak memory 265156 kb
Host smart-8b11b220-af64-44b3-950f-15cb132ba304
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=365259830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.365259830
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2483612517
Short name T347
Test name
Test status
Simulation time 12143226 ps
CPU time 1.49 seconds
Started May 19 02:22:40 PM PDT 24
Finished May 19 02:22:42 PM PDT 24
Peak memory 236612 kb
Host smart-2ae05689-5a98-4083-93f3-41d2c96e649d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2483612517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2483612517
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2128186798
Short name T293
Test name
Test status
Simulation time 12712199360 ps
CPU time 481.75 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 02:36:43 PM PDT 24
Peak memory 248136 kb
Host smart-4b8f86d0-2380-4369-8d2e-039d2aa93b51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128186798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2128186798
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4136548512
Short name T53
Test name
Test status
Simulation time 32422388181 ps
CPU time 1129.04 seconds
Started May 19 02:33:32 PM PDT 24
Finished May 19 02:52:22 PM PDT 24
Peak memory 272380 kb
Host smart-5b845e44-e3f9-4a18-885b-35ad3c287e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136548512 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4136548512
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2356804755
Short name T295
Test name
Test status
Simulation time 6462942888 ps
CPU time 256.72 seconds
Started May 19 02:34:39 PM PDT 24
Finished May 19 02:38:57 PM PDT 24
Peak memory 254680 kb
Host smart-ec21df66-9374-44f3-92c8-9e616f92cc90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356804755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2356804755
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.92996710
Short name T312
Test name
Test status
Simulation time 156973477496 ps
CPU time 1152.66 seconds
Started May 19 02:30:17 PM PDT 24
Finished May 19 02:49:30 PM PDT 24
Peak memory 271392 kb
Host smart-4815ecfd-c858-4e0c-b5b0-e39a44dbf2e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92996710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.92996710
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2049664127
Short name T6
Test name
Test status
Simulation time 741147496504 ps
CPU time 2632.88 seconds
Started May 19 02:31:25 PM PDT 24
Finished May 19 03:15:19 PM PDT 24
Peak memory 288220 kb
Host smart-e20875a2-87e2-407f-8504-6475ac11aaf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049664127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2049664127
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1782426841
Short name T252
Test name
Test status
Simulation time 406543556764 ps
CPU time 5329.88 seconds
Started May 19 02:31:25 PM PDT 24
Finished May 19 04:00:16 PM PDT 24
Peak memory 315512 kb
Host smart-30dde69e-b579-4785-8470-99711c6bb105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782426841 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1782426841
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1749415297
Short name T22
Test name
Test status
Simulation time 34219088819 ps
CPU time 876.61 seconds
Started May 19 02:30:44 PM PDT 24
Finished May 19 02:45:21 PM PDT 24
Peak memory 265204 kb
Host smart-07f2338b-3ff5-419d-a851-fc047fbbb86a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749415297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1749415297
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.843798806
Short name T74
Test name
Test status
Simulation time 413249080 ps
CPU time 30.71 seconds
Started May 19 02:31:29 PM PDT 24
Finished May 19 02:32:01 PM PDT 24
Peak memory 247420 kb
Host smart-87ffd178-fcd2-44ae-8d52-8d3805993afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84379
8806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.843798806
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.543499786
Short name T135
Test name
Test status
Simulation time 7555001646 ps
CPU time 314.75 seconds
Started May 19 02:22:08 PM PDT 24
Finished May 19 02:27:23 PM PDT 24
Peak memory 265140 kb
Host smart-be38835e-e800-485f-ac4d-bdf6125c8819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=543499786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.543499786
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1018729441
Short name T203
Test name
Test status
Simulation time 92906312 ps
CPU time 5.67 seconds
Started May 19 02:22:21 PM PDT 24
Finished May 19 02:22:27 PM PDT 24
Peak memory 235864 kb
Host smart-d364d1bf-c36f-496a-b90c-128a64513aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1018729441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1018729441
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1409768481
Short name T111
Test name
Test status
Simulation time 15654207470 ps
CPU time 244.71 seconds
Started May 19 02:29:04 PM PDT 24
Finished May 19 02:33:10 PM PDT 24
Peak memory 248216 kb
Host smart-e6f43240-92aa-4b91-8a60-0c00b57aa139
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409768481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1409768481
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1448574812
Short name T266
Test name
Test status
Simulation time 59740520690 ps
CPU time 3440.2 seconds
Started May 19 02:29:21 PM PDT 24
Finished May 19 03:26:42 PM PDT 24
Peak memory 289232 kb
Host smart-19496d3e-ce66-446c-9b8c-5a22175728a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448574812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1448574812
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.230794115
Short name T329
Test name
Test status
Simulation time 76484346898 ps
CPU time 1186.2 seconds
Started May 19 02:31:53 PM PDT 24
Finished May 19 02:51:41 PM PDT 24
Peak memory 266264 kb
Host smart-8203cdc4-23a8-47cc-8f0f-e504f03b6be3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230794115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.230794115
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4052169472
Short name T141
Test name
Test status
Simulation time 3666210421 ps
CPU time 280.79 seconds
Started May 19 02:21:33 PM PDT 24
Finished May 19 02:26:14 PM PDT 24
Peak memory 272948 kb
Host smart-a7e19ba8-dc36-48d7-a7ac-3fcf09e56c8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4052169472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4052169472
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2880717000
Short name T23
Test name
Test status
Simulation time 53355185158 ps
CPU time 3554.56 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 03:28:17 PM PDT 24
Peak memory 305420 kb
Host smart-6b6d2db2-6402-4dc8-a494-2748c85302c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880717000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2880717000
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2740150940
Short name T215
Test name
Test status
Simulation time 77371007 ps
CPU time 3.23 seconds
Started May 19 02:28:37 PM PDT 24
Finished May 19 02:28:41 PM PDT 24
Peak memory 248920 kb
Host smart-4749f729-1d4a-4af2-9f9a-d8b12b2789e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2740150940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2740150940
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.51332263
Short name T206
Test name
Test status
Simulation time 107607560 ps
CPU time 2.84 seconds
Started May 19 02:29:13 PM PDT 24
Finished May 19 02:29:17 PM PDT 24
Peak memory 249128 kb
Host smart-847694d8-4f64-4cf1-b335-09f4097db1f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=51332263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.51332263
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3022794387
Short name T222
Test name
Test status
Simulation time 83495447 ps
CPU time 4.02 seconds
Started May 19 02:29:54 PM PDT 24
Finished May 19 02:29:59 PM PDT 24
Peak memory 248928 kb
Host smart-0d9ca1dd-4a29-45b4-a9f5-0739ce8d44b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3022794387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3022794387
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3080255954
Short name T208
Test name
Test status
Simulation time 29157505 ps
CPU time 3.09 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 02:29:06 PM PDT 24
Peak memory 248940 kb
Host smart-62c510c1-9a6f-4aee-8506-ce3812ef84a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3080255954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3080255954
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3472285691
Short name T249
Test name
Test status
Simulation time 179454396 ps
CPU time 13.49 seconds
Started May 19 02:20:26 PM PDT 24
Finished May 19 02:20:40 PM PDT 24
Peak memory 242172 kb
Host smart-362d3462-78be-4e18-b713-4ec83dc5ff3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472285691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3472285691
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3079483728
Short name T343
Test name
Test status
Simulation time 17653615 ps
CPU time 1.39 seconds
Started May 19 02:22:40 PM PDT 24
Finished May 19 02:22:42 PM PDT 24
Peak memory 236604 kb
Host smart-d6d609cf-5c0f-4e53-bb04-b7364898bc62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3079483728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3079483728
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1295389082
Short name T261
Test name
Test status
Simulation time 1341451824 ps
CPU time 35.89 seconds
Started May 19 02:29:15 PM PDT 24
Finished May 19 02:29:52 PM PDT 24
Peak memory 255620 kb
Host smart-8e764f68-528d-4b69-a0ac-1f3186e958ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12953
89082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1295389082
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1905552610
Short name T202
Test name
Test status
Simulation time 116818870370 ps
CPU time 2635.64 seconds
Started May 19 02:29:26 PM PDT 24
Finished May 19 03:13:22 PM PDT 24
Peak memory 322036 kb
Host smart-642e91c4-54d4-4344-9aed-0a0bbaadfc73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905552610 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1905552610
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.748456091
Short name T279
Test name
Test status
Simulation time 73065987895 ps
CPU time 4507.8 seconds
Started May 19 02:30:06 PM PDT 24
Finished May 19 03:45:14 PM PDT 24
Peak memory 306088 kb
Host smart-595e6c9d-faea-4ba9-889e-33d11dc61d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748456091 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.748456091
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1816533789
Short name T286
Test name
Test status
Simulation time 74172885391 ps
CPU time 405.7 seconds
Started May 19 02:30:16 PM PDT 24
Finished May 19 02:37:03 PM PDT 24
Peak memory 248180 kb
Host smart-edd1b9ab-f0c7-4297-b469-cb8dbc81c6fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816533789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1816533789
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2965092357
Short name T524
Test name
Test status
Simulation time 40449402129 ps
CPU time 401.77 seconds
Started May 19 02:32:08 PM PDT 24
Finished May 19 02:38:50 PM PDT 24
Peak memory 256396 kb
Host smart-c96ac6d8-7acc-468b-a01c-cb1679fac472
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965092357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2965092357
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3619338182
Short name T264
Test name
Test status
Simulation time 836349005 ps
CPU time 43.63 seconds
Started May 19 02:32:28 PM PDT 24
Finished May 19 02:33:13 PM PDT 24
Peak memory 248756 kb
Host smart-6e3d925a-a4fe-4e1c-aec4-39550f0ac561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193
38182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3619338182
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1860235549
Short name T108
Test name
Test status
Simulation time 14776330505 ps
CPU time 1470.9 seconds
Started May 19 02:30:30 PM PDT 24
Finished May 19 02:55:01 PM PDT 24
Peak memory 289728 kb
Host smart-6d9ea2a4-3afd-4a69-bc4b-37a58c4815cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860235549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1860235549
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.92841197
Short name T132
Test name
Test status
Simulation time 6190381857 ps
CPU time 105.17 seconds
Started May 19 02:20:44 PM PDT 24
Finished May 19 02:22:30 PM PDT 24
Peak memory 267572 kb
Host smart-57eaf6ec-f520-4210-a4e4-ec24b040a174
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=92841197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors
.92841197
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2884458227
Short name T338
Test name
Test status
Simulation time 125733054447 ps
CPU time 1930.87 seconds
Started May 19 02:28:42 PM PDT 24
Finished May 19 03:00:54 PM PDT 24
Peak memory 288720 kb
Host smart-65588e25-9afd-42d4-b9f9-cbd995705619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884458227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2884458227
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2491800323
Short name T50
Test name
Test status
Simulation time 135842608 ps
CPU time 7.3 seconds
Started May 19 02:29:23 PM PDT 24
Finished May 19 02:29:31 PM PDT 24
Peak memory 253328 kb
Host smart-267d1896-b57b-44f6-b665-5bb32bbbe9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24918
00323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2491800323
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2351364673
Short name T85
Test name
Test status
Simulation time 166041251 ps
CPU time 16.83 seconds
Started May 19 02:29:40 PM PDT 24
Finished May 19 02:29:58 PM PDT 24
Peak memory 255540 kb
Host smart-30313ec5-e263-4688-97fe-cfd81330f9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23513
64673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2351364673
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.580708229
Short name T274
Test name
Test status
Simulation time 306905228468 ps
CPU time 8210.29 seconds
Started May 19 02:29:51 PM PDT 24
Finished May 19 04:46:43 PM PDT 24
Peak memory 394452 kb
Host smart-c5d219ec-1d4c-4712-a3b3-eae2c0e00f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580708229 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.580708229
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1827511748
Short name T270
Test name
Test status
Simulation time 6608788904 ps
CPU time 49.02 seconds
Started May 19 02:30:13 PM PDT 24
Finished May 19 02:31:02 PM PDT 24
Peak memory 256404 kb
Host smart-ff0cc562-3a47-4aed-a413-a8e686059d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18275
11748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1827511748
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2252030434
Short name T520
Test name
Test status
Simulation time 7278900042 ps
CPU time 288.12 seconds
Started May 19 02:30:32 PM PDT 24
Finished May 19 02:35:21 PM PDT 24
Peak memory 248196 kb
Host smart-f7d7c994-e95f-4078-bca4-ee804d078d7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252030434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2252030434
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1382512785
Short name T335
Test name
Test status
Simulation time 19102377980 ps
CPU time 1662.75 seconds
Started May 19 02:30:59 PM PDT 24
Finished May 19 02:58:43 PM PDT 24
Peak memory 289752 kb
Host smart-bb25b1b2-bc46-4816-8323-351f3d6121e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382512785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1382512785
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1673822362
Short name T258
Test name
Test status
Simulation time 116990403087 ps
CPU time 1885.28 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 03:02:26 PM PDT 24
Peak memory 289060 kb
Host smart-c7824862-8346-4ce8-91be-9362ece31936
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673822362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1673822362
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3437503262
Short name T280
Test name
Test status
Simulation time 93466295 ps
CPU time 10.49 seconds
Started May 19 02:31:22 PM PDT 24
Finished May 19 02:31:33 PM PDT 24
Peak memory 248876 kb
Host smart-8ef61d1a-eb88-4383-83f4-a7993aa60e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34375
03262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3437503262
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.404855911
Short name T83
Test name
Test status
Simulation time 435129869 ps
CPU time 31.62 seconds
Started May 19 02:28:51 PM PDT 24
Finished May 19 02:29:23 PM PDT 24
Peak memory 248704 kb
Host smart-d3b1b334-220b-45fb-bcfe-b0829ab018e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
5911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.404855911
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2550837212
Short name T113
Test name
Test status
Simulation time 50706651203 ps
CPU time 1310.91 seconds
Started May 19 02:29:04 PM PDT 24
Finished May 19 02:50:57 PM PDT 24
Peak memory 289568 kb
Host smart-edcbee9d-7201-428d-a9f9-024d0bc548eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550837212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2550837212
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3720223082
Short name T147
Test name
Test status
Simulation time 68185433513 ps
CPU time 1200.48 seconds
Started May 19 02:20:16 PM PDT 24
Finished May 19 02:40:17 PM PDT 24
Peak memory 265168 kb
Host smart-6abdad01-3337-48e1-a359-48cbd93fc6b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720223082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3720223082
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1295616486
Short name T168
Test name
Test status
Simulation time 603923206 ps
CPU time 59.8 seconds
Started May 19 02:21:43 PM PDT 24
Finished May 19 02:22:43 PM PDT 24
Peak memory 240112 kb
Host smart-f7e8f322-f9d4-4ff2-9246-51692e07f62c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1295616486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1295616486
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3435669920
Short name T167
Test name
Test status
Simulation time 38254592 ps
CPU time 3.22 seconds
Started May 19 02:21:19 PM PDT 24
Finished May 19 02:21:22 PM PDT 24
Peak memory 236548 kb
Host smart-a9574278-d445-4aed-9df9-a0f084689ca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3435669920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3435669920
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3937970059
Short name T165
Test name
Test status
Simulation time 1294624139 ps
CPU time 77.7 seconds
Started May 19 02:21:25 PM PDT 24
Finished May 19 02:22:43 PM PDT 24
Peak memory 240044 kb
Host smart-c2df3573-621f-46a6-ae53-72c698812828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3937970059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3937970059
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2861800484
Short name T166
Test name
Test status
Simulation time 218375505 ps
CPU time 3.99 seconds
Started May 19 02:20:35 PM PDT 24
Finished May 19 02:20:40 PM PDT 24
Peak memory 236896 kb
Host smart-80c29b57-12c8-4db4-b367-a6852d24c191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2861800484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2861800484
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2746267902
Short name T169
Test name
Test status
Simulation time 4764462624 ps
CPU time 69.59 seconds
Started May 19 02:22:16 PM PDT 24
Finished May 19 02:23:26 PM PDT 24
Peak memory 239380 kb
Host smart-75cd8e9e-ddfc-432f-8ab5-8cae42a8bbec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2746267902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2746267902
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.494926231
Short name T122
Test name
Test status
Simulation time 1627691550 ps
CPU time 93.95 seconds
Started May 19 02:20:14 PM PDT 24
Finished May 19 02:21:48 PM PDT 24
Peak memory 256884 kb
Host smart-eb96464d-495e-4af0-96e9-6c0a52a4cf4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=494926231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.494926231
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3467769736
Short name T176
Test name
Test status
Simulation time 295607796 ps
CPU time 21.52 seconds
Started May 19 02:22:07 PM PDT 24
Finished May 19 02:22:28 PM PDT 24
Peak memory 236796 kb
Host smart-e098bb6e-d2e3-46f7-86ae-8ee74655dbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3467769736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3467769736
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3922401067
Short name T128
Test name
Test status
Simulation time 13780603529 ps
CPU time 275.59 seconds
Started May 19 02:22:10 PM PDT 24
Finished May 19 02:26:46 PM PDT 24
Peak memory 265136 kb
Host smart-0c3e4dff-b6ce-4e1e-8494-45738595f001
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3922401067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3922401067
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3439308087
Short name T174
Test name
Test status
Simulation time 3473775825 ps
CPU time 47.49 seconds
Started May 19 02:22:16 PM PDT 24
Finished May 19 02:23:04 PM PDT 24
Peak memory 240132 kb
Host smart-3a12e60f-03cc-4fd2-bef1-ff46073662e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3439308087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3439308087
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.161722773
Short name T123
Test name
Test status
Simulation time 3872801884 ps
CPU time 136.26 seconds
Started May 19 02:22:14 PM PDT 24
Finished May 19 02:24:30 PM PDT 24
Peak memory 265672 kb
Host smart-111c39d0-b19d-4ee7-b6b2-3634194ed3dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=161722773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.161722773
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2661914853
Short name T179
Test name
Test status
Simulation time 182851448 ps
CPU time 22.28 seconds
Started May 19 02:21:33 PM PDT 24
Finished May 19 02:21:56 PM PDT 24
Peak memory 236632 kb
Host smart-1a3ceec3-d486-46b9-9d52-1f7fe2868b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2661914853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2661914853
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2124935826
Short name T180
Test name
Test status
Simulation time 60152414 ps
CPU time 2.9 seconds
Started May 19 02:21:39 PM PDT 24
Finished May 19 02:21:42 PM PDT 24
Peak memory 236560 kb
Host smart-ddf0a345-e394-4d8d-8782-7c129d6fc746
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2124935826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2124935826
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2579680218
Short name T171
Test name
Test status
Simulation time 99489344 ps
CPU time 4.08 seconds
Started May 19 02:21:54 PM PDT 24
Finished May 19 02:21:59 PM PDT 24
Peak memory 237208 kb
Host smart-b0c607ed-1406-4e18-99bf-86395e90ee1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2579680218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2579680218
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1853682386
Short name T170
Test name
Test status
Simulation time 5214703108 ps
CPU time 40.7 seconds
Started May 19 02:22:31 PM PDT 24
Finished May 19 02:23:12 PM PDT 24
Peak memory 248376 kb
Host smart-1596c991-6772-4d73-862b-a3b16d355d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1853682386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1853682386
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3832670210
Short name T175
Test name
Test status
Simulation time 99706416 ps
CPU time 2.51 seconds
Started May 19 02:20:44 PM PDT 24
Finished May 19 02:20:47 PM PDT 24
Peak memory 236872 kb
Host smart-a9a383f3-2400-4ff8-854e-fcee3e7a7e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3832670210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3832670210
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2176091700
Short name T173
Test name
Test status
Simulation time 456093097 ps
CPU time 3.51 seconds
Started May 19 02:20:46 PM PDT 24
Finished May 19 02:20:50 PM PDT 24
Peak memory 236904 kb
Host smart-6ab73c50-b646-4462-b19f-82b2e3dfa1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2176091700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2176091700
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.297361662
Short name T161
Test name
Test status
Simulation time 207468150 ps
CPU time 22.41 seconds
Started May 19 02:20:57 PM PDT 24
Finished May 19 02:21:20 PM PDT 24
Peak memory 245148 kb
Host smart-55b8de88-d2ce-479c-b865-f32b483f22b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=297361662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.297361662
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.64633973
Short name T172
Test name
Test status
Simulation time 5582561010 ps
CPU time 34.86 seconds
Started May 19 02:21:24 PM PDT 24
Finished May 19 02:21:59 PM PDT 24
Peak memory 244904 kb
Host smart-fe6cd24a-e1dc-48bf-8512-096dbcf837af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=64633973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.64633973
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2947606215
Short name T711
Test name
Test status
Simulation time 2414614341 ps
CPU time 127.5 seconds
Started May 19 02:20:19 PM PDT 24
Finished May 19 02:22:27 PM PDT 24
Peak memory 236788 kb
Host smart-aa1bdfdd-4729-42ee-882a-33f6e9714ee8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2947606215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2947606215
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1151526532
Short name T762
Test name
Test status
Simulation time 3476814417 ps
CPU time 201.91 seconds
Started May 19 02:20:20 PM PDT 24
Finished May 19 02:23:42 PM PDT 24
Peak memory 235680 kb
Host smart-4a8aae8a-54da-4882-889c-c51001e65807
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1151526532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1151526532
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3857443158
Short name T804
Test name
Test status
Simulation time 45250376 ps
CPU time 6.35 seconds
Started May 19 02:20:17 PM PDT 24
Finished May 19 02:20:24 PM PDT 24
Peak memory 240340 kb
Host smart-3e1aa023-1de3-41fa-a24b-f2c130758a0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3857443158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3857443158
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.921860935
Short name T735
Test name
Test status
Simulation time 116833590 ps
CPU time 5.24 seconds
Started May 19 02:20:20 PM PDT 24
Finished May 19 02:20:25 PM PDT 24
Peak memory 239424 kb
Host smart-d4fe0e76-f653-4cf3-b5d4-32899d5d4a2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=921860935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.921860935
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3998762818
Short name T162
Test name
Test status
Simulation time 16906548 ps
CPU time 1.25 seconds
Started May 19 02:20:21 PM PDT 24
Finished May 19 02:20:23 PM PDT 24
Peak memory 235616 kb
Host smart-5d8cb23c-759d-4ebb-98a2-c6cd0018070c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3998762818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3998762818
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1914856161
Short name T822
Test name
Test status
Simulation time 360207364 ps
CPU time 12.3 seconds
Started May 19 02:20:27 PM PDT 24
Finished May 19 02:20:39 PM PDT 24
Peak memory 248268 kb
Host smart-8961681b-b3ca-495a-999d-b9d96bff2628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1914856161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1914856161
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.214503747
Short name T788
Test name
Test status
Simulation time 183293043 ps
CPU time 7.07 seconds
Started May 19 02:20:16 PM PDT 24
Finished May 19 02:20:23 PM PDT 24
Peak memory 246692 kb
Host smart-00783eed-8d8b-4aaf-a631-834b458f0d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=214503747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.214503747
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1578984525
Short name T792
Test name
Test status
Simulation time 580790787 ps
CPU time 67.93 seconds
Started May 19 02:20:39 PM PDT 24
Finished May 19 02:21:47 PM PDT 24
Peak memory 236672 kb
Host smart-e92d7437-03bd-439c-a934-59509774c54f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1578984525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1578984525
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3424868147
Short name T754
Test name
Test status
Simulation time 8163905484 ps
CPU time 91.4 seconds
Started May 19 02:20:38 PM PDT 24
Finished May 19 02:22:10 PM PDT 24
Peak memory 240140 kb
Host smart-a6a9ea62-e80f-4cce-9c99-b6a23cfe640f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3424868147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3424868147
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2405204007
Short name T825
Test name
Test status
Simulation time 284300697 ps
CPU time 5.84 seconds
Started May 19 02:20:35 PM PDT 24
Finished May 19 02:20:41 PM PDT 24
Peak memory 240100 kb
Host smart-dafcaa4e-5e06-40e8-a4b1-77a516eabc27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2405204007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2405204007
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3671386442
Short name T737
Test name
Test status
Simulation time 182098212 ps
CPU time 5.56 seconds
Started May 19 02:20:40 PM PDT 24
Finished May 19 02:20:46 PM PDT 24
Peak memory 256256 kb
Host smart-30d0be7b-5b3d-4dbc-829e-6cdfff70fd1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671386442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3671386442
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2204948627
Short name T752
Test name
Test status
Simulation time 238972866 ps
CPU time 9.84 seconds
Started May 19 02:20:38 PM PDT 24
Finished May 19 02:20:48 PM PDT 24
Peak memory 240048 kb
Host smart-4f36a3ab-7476-4da7-b3ec-6bb8179c9aad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2204948627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2204948627
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.528129796
Short name T809
Test name
Test status
Simulation time 7635212 ps
CPU time 1.38 seconds
Started May 19 02:20:37 PM PDT 24
Finished May 19 02:20:39 PM PDT 24
Peak memory 236584 kb
Host smart-ce987e29-5616-4e29-a828-61bbe3bfdb33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=528129796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.528129796
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.106036316
Short name T194
Test name
Test status
Simulation time 682071091 ps
CPU time 49.28 seconds
Started May 19 02:20:43 PM PDT 24
Finished May 19 02:21:33 PM PDT 24
Peak memory 244724 kb
Host smart-497b0761-8dd2-436e-ba5b-30767fa97609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=106036316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.106036316
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1058688619
Short name T156
Test name
Test status
Simulation time 12727085848 ps
CPU time 202.51 seconds
Started May 19 02:20:31 PM PDT 24
Finished May 19 02:23:55 PM PDT 24
Peak memory 268940 kb
Host smart-fd1655b2-988e-400e-9aa9-1c68a5fc5110
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1058688619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1058688619
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3615574244
Short name T143
Test name
Test status
Simulation time 8507750484 ps
CPU time 588.35 seconds
Started May 19 02:20:26 PM PDT 24
Finished May 19 02:30:15 PM PDT 24
Peak memory 265108 kb
Host smart-fec716a9-0ff0-484a-9833-1ca369283b22
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615574244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3615574244
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1361229347
Short name T794
Test name
Test status
Simulation time 293882587 ps
CPU time 20.5 seconds
Started May 19 02:20:28 PM PDT 24
Finished May 19 02:20:49 PM PDT 24
Peak memory 247156 kb
Host smart-5c31f331-981b-493e-bbbf-b7a9009767ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1361229347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1361229347
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1004828224
Short name T811
Test name
Test status
Simulation time 36154371 ps
CPU time 5.19 seconds
Started May 19 02:21:43 PM PDT 24
Finished May 19 02:21:49 PM PDT 24
Peak memory 256760 kb
Host smart-090f310a-6e29-41c9-bdd9-7f038654ffb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004828224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1004828224
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.948295389
Short name T796
Test name
Test status
Simulation time 262778688 ps
CPU time 5.86 seconds
Started May 19 02:21:39 PM PDT 24
Finished May 19 02:21:45 PM PDT 24
Peak memory 239800 kb
Host smart-41e33e25-9644-4670-aea0-1c67f73cfafe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=948295389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.948295389
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.590387218
Short name T776
Test name
Test status
Simulation time 7630759 ps
CPU time 1.47 seconds
Started May 19 02:21:41 PM PDT 24
Finished May 19 02:21:43 PM PDT 24
Peak memory 235632 kb
Host smart-d36fee2f-b50f-4c67-bb97-5555cf1a78eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=590387218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.590387218
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4005098187
Short name T800
Test name
Test status
Simulation time 679514897 ps
CPU time 24 seconds
Started May 19 02:21:43 PM PDT 24
Finished May 19 02:22:07 PM PDT 24
Peak memory 248232 kb
Host smart-dde4a7a6-ec5a-48cc-963b-eb733df96997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4005098187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4005098187
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2863324690
Short name T125
Test name
Test status
Simulation time 51232932055 ps
CPU time 977.47 seconds
Started May 19 02:21:38 PM PDT 24
Finished May 19 02:37:56 PM PDT 24
Peak memory 265112 kb
Host smart-0262f5d6-b612-4c8c-a2a6-a48e9dc1035e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863324690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2863324690
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3551971385
Short name T733
Test name
Test status
Simulation time 184472098 ps
CPU time 11.88 seconds
Started May 19 02:21:38 PM PDT 24
Finished May 19 02:21:50 PM PDT 24
Peak memory 252392 kb
Host smart-37421c67-7a00-483b-8451-a19ea776b9e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3551971385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3551971385
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2881986109
Short name T786
Test name
Test status
Simulation time 264335193 ps
CPU time 5.5 seconds
Started May 19 02:21:50 PM PDT 24
Finished May 19 02:21:56 PM PDT 24
Peak memory 248372 kb
Host smart-9be962bd-b9a5-459f-b61a-396721e7ad0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881986109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2881986109
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2314565738
Short name T738
Test name
Test status
Simulation time 120887862 ps
CPU time 5.28 seconds
Started May 19 02:21:45 PM PDT 24
Finished May 19 02:21:50 PM PDT 24
Peak memory 239992 kb
Host smart-8f53fbae-c576-46d4-acbe-6e5bb0ea3a40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2314565738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2314565738
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1525595917
Short name T744
Test name
Test status
Simulation time 15159625 ps
CPU time 1.82 seconds
Started May 19 02:21:44 PM PDT 24
Finished May 19 02:21:46 PM PDT 24
Peak memory 236604 kb
Host smart-ec7b7aec-7f5c-4aa2-9235-3c302db4668b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1525595917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1525595917
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.213915935
Short name T829
Test name
Test status
Simulation time 1036971539 ps
CPU time 35.84 seconds
Started May 19 02:21:49 PM PDT 24
Finished May 19 02:22:26 PM PDT 24
Peak memory 244764 kb
Host smart-54fc9a79-7609-4e16-aa48-82b8608a977e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=213915935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.213915935
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3137531570
Short name T144
Test name
Test status
Simulation time 9024622800 ps
CPU time 301.71 seconds
Started May 19 02:21:43 PM PDT 24
Finished May 19 02:26:45 PM PDT 24
Peak memory 265100 kb
Host smart-601f00b1-d7d9-4626-912e-71ac2316c214
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3137531570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3137531570
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1082807104
Short name T813
Test name
Test status
Simulation time 26541577623 ps
CPU time 562.44 seconds
Started May 19 02:21:42 PM PDT 24
Finished May 19 02:31:05 PM PDT 24
Peak memory 265248 kb
Host smart-b118b8ab-7523-4b53-a622-e6f2b250af35
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082807104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1082807104
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.496481407
Short name T722
Test name
Test status
Simulation time 79530566 ps
CPU time 9.45 seconds
Started May 19 02:21:42 PM PDT 24
Finished May 19 02:21:52 PM PDT 24
Peak memory 248388 kb
Host smart-5d65451b-b4a8-45c9-a4b3-a3704ea724b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=496481407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.496481407
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1289375704
Short name T807
Test name
Test status
Simulation time 133160234 ps
CPU time 9.36 seconds
Started May 19 02:21:54 PM PDT 24
Finished May 19 02:22:04 PM PDT 24
Peak memory 236960 kb
Host smart-6aa6d76d-ca4d-42f3-8121-11d626693e0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289375704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1289375704
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.725821100
Short name T714
Test name
Test status
Simulation time 62696554 ps
CPU time 3.37 seconds
Started May 19 02:21:54 PM PDT 24
Finished May 19 02:21:57 PM PDT 24
Peak memory 239224 kb
Host smart-3188c113-1d50-45c3-a9e9-bbfcd5b60bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=725821100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.725821100
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3563663416
Short name T750
Test name
Test status
Simulation time 12934067 ps
CPU time 1.33 seconds
Started May 19 02:21:52 PM PDT 24
Finished May 19 02:21:54 PM PDT 24
Peak memory 236436 kb
Host smart-4951c703-9401-4a80-973a-4d8a7271833f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3563663416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3563663416
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.241332802
Short name T728
Test name
Test status
Simulation time 2053846727 ps
CPU time 24.19 seconds
Started May 19 02:21:53 PM PDT 24
Finished May 19 02:22:18 PM PDT 24
Peak memory 245880 kb
Host smart-8d3fd912-bf04-4a21-9db1-6071f71d46e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=241332802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.241332802
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1472143561
Short name T133
Test name
Test status
Simulation time 1628283217 ps
CPU time 191.43 seconds
Started May 19 02:21:53 PM PDT 24
Finished May 19 02:25:04 PM PDT 24
Peak memory 265060 kb
Host smart-ae1e39ac-27b0-4742-b013-5e172f3e477a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1472143561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1472143561
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1919976853
Short name T130
Test name
Test status
Simulation time 4511356230 ps
CPU time 296.5 seconds
Started May 19 02:21:54 PM PDT 24
Finished May 19 02:26:51 PM PDT 24
Peak memory 265172 kb
Host smart-0b1fc87f-5604-4a0b-8eba-befdf1c1bb92
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919976853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1919976853
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.810489484
Short name T727
Test name
Test status
Simulation time 38449016 ps
CPU time 6.56 seconds
Started May 19 02:21:53 PM PDT 24
Finished May 19 02:22:00 PM PDT 24
Peak memory 250848 kb
Host smart-1644ab62-5e74-4af8-9426-3a04f613e741
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=810489484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.810489484
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3207896257
Short name T819
Test name
Test status
Simulation time 2020007134 ps
CPU time 14.38 seconds
Started May 19 02:22:03 PM PDT 24
Finished May 19 02:22:18 PM PDT 24
Peak memory 251408 kb
Host smart-e873f982-e002-433f-b58a-8f90618d6a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207896257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3207896257
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3017010227
Short name T791
Test name
Test status
Simulation time 54443762 ps
CPU time 5.8 seconds
Started May 19 02:22:03 PM PDT 24
Finished May 19 02:22:09 PM PDT 24
Peak memory 236544 kb
Host smart-daf3ad9a-e381-4012-b8be-e4d3b749c24e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3017010227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3017010227
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2074985335
Short name T740
Test name
Test status
Simulation time 6683065 ps
CPU time 1.47 seconds
Started May 19 02:22:03 PM PDT 24
Finished May 19 02:22:05 PM PDT 24
Peak memory 235632 kb
Host smart-88ee660e-b72f-415f-b53d-d7e767b9275d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074985335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2074985335
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2969139405
Short name T723
Test name
Test status
Simulation time 86988965 ps
CPU time 13.87 seconds
Started May 19 02:22:03 PM PDT 24
Finished May 19 02:22:18 PM PDT 24
Peak memory 244716 kb
Host smart-541aa34e-4bae-4fde-bdc5-cc87623be7eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2969139405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2969139405
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2468241841
Short name T126
Test name
Test status
Simulation time 4817199344 ps
CPU time 92.53 seconds
Started May 19 02:22:03 PM PDT 24
Finished May 19 02:23:36 PM PDT 24
Peak memory 256880 kb
Host smart-82e429f5-12a9-45c7-a4e2-0ef3648e5f28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2468241841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2468241841
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.694599727
Short name T710
Test name
Test status
Simulation time 2744610425 ps
CPU time 25.85 seconds
Started May 19 02:22:04 PM PDT 24
Finished May 19 02:22:30 PM PDT 24
Peak memory 248340 kb
Host smart-7c05ee8c-e2f3-4c17-844e-d02a74434a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=694599727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.694599727
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1769547761
Short name T159
Test name
Test status
Simulation time 191855654 ps
CPU time 3.86 seconds
Started May 19 02:22:04 PM PDT 24
Finished May 19 02:22:08 PM PDT 24
Peak memory 236544 kb
Host smart-3b8772d5-6289-4e9c-93ea-30cd14d1c42b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1769547761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1769547761
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1054505233
Short name T353
Test name
Test status
Simulation time 1468380374 ps
CPU time 7.64 seconds
Started May 19 02:22:11 PM PDT 24
Finished May 19 02:22:19 PM PDT 24
Peak memory 240332 kb
Host smart-c522c8ff-3ad5-4408-bcba-9ecf67fd63d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054505233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1054505233
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.488389103
Short name T828
Test name
Test status
Simulation time 366587955 ps
CPU time 8.32 seconds
Started May 19 02:22:09 PM PDT 24
Finished May 19 02:22:18 PM PDT 24
Peak memory 235612 kb
Host smart-210ee822-c661-4a19-b2b7-b93cf8238bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=488389103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.488389103
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1484707512
Short name T790
Test name
Test status
Simulation time 30510421 ps
CPU time 1.6 seconds
Started May 19 02:22:09 PM PDT 24
Finished May 19 02:22:11 PM PDT 24
Peak memory 236824 kb
Host smart-5c8548f2-c126-42f4-9158-7bdabb64fde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1484707512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1484707512
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1259458721
Short name T177
Test name
Test status
Simulation time 839090626 ps
CPU time 37.12 seconds
Started May 19 02:22:10 PM PDT 24
Finished May 19 02:22:48 PM PDT 24
Peak memory 244732 kb
Host smart-6cf51320-bb30-4f35-a31c-bd526890b5f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1259458721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1259458721
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2803428654
Short name T157
Test name
Test status
Simulation time 6443982208 ps
CPU time 513.82 seconds
Started May 19 02:22:04 PM PDT 24
Finished May 19 02:30:38 PM PDT 24
Peak memory 265188 kb
Host smart-15cc6b7b-b1b3-4f6c-9485-fe508e4fc002
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803428654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2803428654
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4068771819
Short name T250
Test name
Test status
Simulation time 453675477 ps
CPU time 23.01 seconds
Started May 19 02:22:07 PM PDT 24
Finished May 19 02:22:30 PM PDT 24
Peak memory 247900 kb
Host smart-eb875d1c-0e5b-4e11-b8b1-a2dfbc429fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4068771819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4068771819
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2501972975
Short name T719
Test name
Test status
Simulation time 470266644 ps
CPU time 9.48 seconds
Started May 19 02:22:14 PM PDT 24
Finished May 19 02:22:24 PM PDT 24
Peak memory 239568 kb
Host smart-4bf9a78e-d926-489c-81d1-ccaff8d14a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501972975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2501972975
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3521431491
Short name T716
Test name
Test status
Simulation time 21768175 ps
CPU time 3.4 seconds
Started May 19 02:22:14 PM PDT 24
Finished May 19 02:22:17 PM PDT 24
Peak memory 236504 kb
Host smart-4330da03-6ecb-45b4-8e39-50144f101241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3521431491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3521431491
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1478159928
Short name T778
Test name
Test status
Simulation time 17965843 ps
CPU time 1.2 seconds
Started May 19 02:22:15 PM PDT 24
Finished May 19 02:22:16 PM PDT 24
Peak memory 236544 kb
Host smart-f44e3df3-26e6-4187-93e5-e7ec41b6894e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1478159928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1478159928
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2858771930
Short name T785
Test name
Test status
Simulation time 92789085 ps
CPU time 12.11 seconds
Started May 19 02:22:14 PM PDT 24
Finished May 19 02:22:27 PM PDT 24
Peak memory 244712 kb
Host smart-dc027950-90b0-4efd-bd27-8b1acfc1fdcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2858771930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2858771930
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3302822031
Short name T142
Test name
Test status
Simulation time 7906129512 ps
CPU time 534.53 seconds
Started May 19 02:22:11 PM PDT 24
Finished May 19 02:31:06 PM PDT 24
Peak memory 265116 kb
Host smart-d53aa29d-ce03-4c4c-8dfa-171b86d83c09
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302822031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3302822031
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.610679207
Short name T743
Test name
Test status
Simulation time 51507425 ps
CPU time 8.1 seconds
Started May 19 02:22:11 PM PDT 24
Finished May 19 02:22:19 PM PDT 24
Peak memory 252388 kb
Host smart-9ec4b664-8cdd-4072-a66b-64868fcae0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=610679207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.610679207
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2370668965
Short name T766
Test name
Test status
Simulation time 633932192 ps
CPU time 12.01 seconds
Started May 19 02:22:20 PM PDT 24
Finished May 19 02:22:33 PM PDT 24
Peak memory 250816 kb
Host smart-dd20c738-26ed-4768-90b1-cb8130967df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370668965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2370668965
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2863421237
Short name T775
Test name
Test status
Simulation time 180158969 ps
CPU time 8.22 seconds
Started May 19 02:22:19 PM PDT 24
Finished May 19 02:22:28 PM PDT 24
Peak memory 235620 kb
Host smart-c7ad0023-02c3-494e-bb31-63a617378f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2863421237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2863421237
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3363684036
Short name T779
Test name
Test status
Simulation time 10928781 ps
CPU time 1.67 seconds
Started May 19 02:22:20 PM PDT 24
Finished May 19 02:22:22 PM PDT 24
Peak memory 235572 kb
Host smart-fe5a49dc-2029-4f4f-a39f-73a567404c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363684036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3363684036
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3994841332
Short name T178
Test name
Test status
Simulation time 604183277 ps
CPU time 37.8 seconds
Started May 19 02:22:23 PM PDT 24
Finished May 19 02:23:02 PM PDT 24
Peak memory 243824 kb
Host smart-62ed980d-4f78-455f-8a0f-016cff0a2940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3994841332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3994841332
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1934587175
Short name T155
Test name
Test status
Simulation time 126046609591 ps
CPU time 1375.77 seconds
Started May 19 02:22:15 PM PDT 24
Finished May 19 02:45:12 PM PDT 24
Peak memory 272624 kb
Host smart-de4ef507-f2db-4cde-9e72-f680075247b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934587175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1934587175
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.577761772
Short name T708
Test name
Test status
Simulation time 63553650 ps
CPU time 9.44 seconds
Started May 19 02:22:15 PM PDT 24
Finished May 19 02:22:25 PM PDT 24
Peak memory 247860 kb
Host smart-c5e6596b-e0c7-4457-aed8-d809367e9aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=577761772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.577761772
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.76508590
Short name T352
Test name
Test status
Simulation time 31319826 ps
CPU time 4.89 seconds
Started May 19 02:22:23 PM PDT 24
Finished May 19 02:22:29 PM PDT 24
Peak memory 240180 kb
Host smart-3aa87c24-7c42-48a4-ac9f-78ebf955fb05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76508590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.alert_handler_csr_mem_rw_with_rand_reset.76508590
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3212487262
Short name T715
Test name
Test status
Simulation time 125026780 ps
CPU time 6.07 seconds
Started May 19 02:22:20 PM PDT 24
Finished May 19 02:22:26 PM PDT 24
Peak memory 236504 kb
Host smart-d3d0896d-3efe-4fc0-9511-7f32813cf79c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3212487262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3212487262
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3686961601
Short name T764
Test name
Test status
Simulation time 7299638 ps
CPU time 1.5 seconds
Started May 19 02:22:19 PM PDT 24
Finished May 19 02:22:21 PM PDT 24
Peak memory 234624 kb
Host smart-49fcbebd-c98a-4ca4-a5e8-17bf995caf98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3686961601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3686961601
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1909070371
Short name T774
Test name
Test status
Simulation time 176052523 ps
CPU time 24.95 seconds
Started May 19 02:22:21 PM PDT 24
Finished May 19 02:22:47 PM PDT 24
Peak memory 245004 kb
Host smart-c5d60c18-2f66-416f-837f-8ae9fbfa9ee4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1909070371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1909070371
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2184847715
Short name T158
Test name
Test status
Simulation time 28024845951 ps
CPU time 313.05 seconds
Started May 19 02:22:20 PM PDT 24
Finished May 19 02:27:34 PM PDT 24
Peak memory 265088 kb
Host smart-2b691bea-0225-4c18-b55d-5902277e2804
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2184847715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2184847715
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2477625534
Short name T810
Test name
Test status
Simulation time 266216066 ps
CPU time 10.49 seconds
Started May 19 02:22:19 PM PDT 24
Finished May 19 02:22:30 PM PDT 24
Peak memory 254712 kb
Host smart-7bb0817b-ad95-48b3-8dad-81a7b702fd92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2477625534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2477625534
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.518635637
Short name T765
Test name
Test status
Simulation time 45869100 ps
CPU time 5.09 seconds
Started May 19 02:22:25 PM PDT 24
Finished May 19 02:22:31 PM PDT 24
Peak memory 241272 kb
Host smart-70aed8f6-8cda-44d9-979e-fe45419b949b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518635637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.518635637
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2104979780
Short name T759
Test name
Test status
Simulation time 75947314 ps
CPU time 3.61 seconds
Started May 19 02:22:23 PM PDT 24
Finished May 19 02:22:28 PM PDT 24
Peak memory 236548 kb
Host smart-bc57af2b-84f4-4ab2-9e41-2791d8af9ebc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2104979780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2104979780
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.127562891
Short name T795
Test name
Test status
Simulation time 19523657 ps
CPU time 1.23 seconds
Started May 19 02:22:28 PM PDT 24
Finished May 19 02:22:30 PM PDT 24
Peak memory 235668 kb
Host smart-9d97549c-b289-4cdf-ad8f-0f3fd08d0848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127562891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.127562891
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.154225125
Short name T758
Test name
Test status
Simulation time 1916011734 ps
CPU time 37.91 seconds
Started May 19 02:22:28 PM PDT 24
Finished May 19 02:23:06 PM PDT 24
Peak memory 244788 kb
Host smart-97c4aeed-7107-4fce-bc2a-3b252d2d0f0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=154225125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.154225125
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4050336777
Short name T150
Test name
Test status
Simulation time 1985949064 ps
CPU time 149.16 seconds
Started May 19 02:22:25 PM PDT 24
Finished May 19 02:24:55 PM PDT 24
Peak memory 256852 kb
Host smart-6f459d23-fb01-4e33-bc43-cf4f97f2449a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4050336777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4050336777
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.354516708
Short name T818
Test name
Test status
Simulation time 413744831 ps
CPU time 16.9 seconds
Started May 19 02:22:26 PM PDT 24
Finished May 19 02:22:43 PM PDT 24
Peak memory 247300 kb
Host smart-eecb6baf-96d5-4064-b54d-6ebb8bfc1320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=354516708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.354516708
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1110421314
Short name T730
Test name
Test status
Simulation time 61488122 ps
CPU time 2.02 seconds
Started May 19 02:22:23 PM PDT 24
Finished May 19 02:22:26 PM PDT 24
Peak memory 237048 kb
Host smart-137284c8-cf00-4cb7-a0b9-69f9628a045e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1110421314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1110421314
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1353137960
Short name T831
Test name
Test status
Simulation time 496274162 ps
CPU time 8.97 seconds
Started May 19 02:22:34 PM PDT 24
Finished May 19 02:22:43 PM PDT 24
Peak memory 252408 kb
Host smart-1644b16f-a7e4-41f2-b931-1306504d0953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353137960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1353137960
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3285648553
Short name T748
Test name
Test status
Simulation time 65138667 ps
CPU time 3.34 seconds
Started May 19 02:22:31 PM PDT 24
Finished May 19 02:22:34 PM PDT 24
Peak memory 235452 kb
Host smart-54f9f0fa-3570-4b1a-945a-bd3ebe1d0ade
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3285648553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3285648553
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1041488553
Short name T773
Test name
Test status
Simulation time 11931335 ps
CPU time 1.37 seconds
Started May 19 02:22:30 PM PDT 24
Finished May 19 02:22:32 PM PDT 24
Peak memory 236592 kb
Host smart-30a29842-1dc8-410b-9115-77fe668d8b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1041488553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1041488553
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3332424395
Short name T767
Test name
Test status
Simulation time 222916265 ps
CPU time 11.74 seconds
Started May 19 02:22:30 PM PDT 24
Finished May 19 02:22:42 PM PDT 24
Peak memory 244764 kb
Host smart-5bcf493b-f3d4-4308-b0e4-795d53e4651a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3332424395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3332424395
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3215334681
Short name T149
Test name
Test status
Simulation time 7123367015 ps
CPU time 145.73 seconds
Started May 19 02:22:31 PM PDT 24
Finished May 19 02:24:57 PM PDT 24
Peak memory 265068 kb
Host smart-0b0db332-8392-464c-bc26-d9a743387fea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3215334681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3215334681
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3345088777
Short name T138
Test name
Test status
Simulation time 14677152553 ps
CPU time 1016.58 seconds
Started May 19 02:22:30 PM PDT 24
Finished May 19 02:39:27 PM PDT 24
Peak memory 273308 kb
Host smart-13847fb0-6371-4d63-b564-0c14cbf739b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345088777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3345088777
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.565712228
Short name T768
Test name
Test status
Simulation time 57440002 ps
CPU time 7.4 seconds
Started May 19 02:22:30 PM PDT 24
Finished May 19 02:22:38 PM PDT 24
Peak memory 246720 kb
Host smart-79340cb2-1617-42ed-a43f-07c201da9067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=565712228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.565712228
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1942158296
Short name T832
Test name
Test status
Simulation time 7645308069 ps
CPU time 190.82 seconds
Started May 19 02:20:46 PM PDT 24
Finished May 19 02:23:58 PM PDT 24
Peak memory 240964 kb
Host smart-bf57599e-db0e-4a64-9eda-599b1e931910
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1942158296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1942158296
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1339441617
Short name T746
Test name
Test status
Simulation time 170985271379 ps
CPU time 464.96 seconds
Started May 19 02:20:43 PM PDT 24
Finished May 19 02:28:28 PM PDT 24
Peak memory 236472 kb
Host smart-b0f27f2a-46f9-41af-9588-24c2718867de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1339441617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1339441617
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.392581295
Short name T193
Test name
Test status
Simulation time 102908522 ps
CPU time 9.01 seconds
Started May 19 02:20:41 PM PDT 24
Finished May 19 02:20:51 PM PDT 24
Peak memory 240064 kb
Host smart-2944384c-b956-4614-b736-53c3315e34b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=392581295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.392581295
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2148521931
Short name T736
Test name
Test status
Simulation time 265665646 ps
CPU time 9.57 seconds
Started May 19 02:20:46 PM PDT 24
Finished May 19 02:20:56 PM PDT 24
Peak memory 255952 kb
Host smart-d19b5f5d-9376-4c4c-945e-0e0c1e6c2c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148521931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2148521931
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.534152242
Short name T351
Test name
Test status
Simulation time 54930498 ps
CPU time 4.97 seconds
Started May 19 02:20:45 PM PDT 24
Finished May 19 02:20:50 PM PDT 24
Peak memory 236552 kb
Host smart-9e24182e-54e7-4f05-b4e0-90d9a37c6dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=534152242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.534152242
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3386458164
Short name T734
Test name
Test status
Simulation time 8643256 ps
CPU time 1.53 seconds
Started May 19 02:20:44 PM PDT 24
Finished May 19 02:20:45 PM PDT 24
Peak memory 236568 kb
Host smart-f470f0f7-b5b8-47dc-a940-1dda3bbe4107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3386458164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3386458164
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2814693188
Short name T812
Test name
Test status
Simulation time 264809445 ps
CPU time 20.08 seconds
Started May 19 02:20:46 PM PDT 24
Finished May 19 02:21:06 PM PDT 24
Peak memory 244784 kb
Host smart-36651657-73b6-4ad0-88a9-a251f6b5a8f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2814693188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2814693188
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2965630879
Short name T137
Test name
Test status
Simulation time 9265291876 ps
CPU time 559.37 seconds
Started May 19 02:20:43 PM PDT 24
Finished May 19 02:30:03 PM PDT 24
Peak memory 265136 kb
Host smart-6fb6378b-278f-4c7c-a2d9-2d3bd7c69675
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965630879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2965630879
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2289323988
Short name T761
Test name
Test status
Simulation time 93929712 ps
CPU time 9.17 seconds
Started May 19 02:20:45 PM PDT 24
Finished May 19 02:20:55 PM PDT 24
Peak memory 254404 kb
Host smart-2711dd02-fd7e-4296-91d4-f53888871387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2289323988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2289323988
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2513994122
Short name T346
Test name
Test status
Simulation time 67634139 ps
CPU time 1.52 seconds
Started May 19 02:22:35 PM PDT 24
Finished May 19 02:22:37 PM PDT 24
Peak memory 236424 kb
Host smart-aa20fed0-6582-413e-b231-a54028919260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2513994122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2513994122
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3316572133
Short name T824
Test name
Test status
Simulation time 25672364 ps
CPU time 1.3 seconds
Started May 19 02:22:35 PM PDT 24
Finished May 19 02:22:37 PM PDT 24
Peak memory 236656 kb
Host smart-ee338f25-2bed-470e-8ada-8d00cba133ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3316572133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3316572133
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2099174293
Short name T780
Test name
Test status
Simulation time 9884866 ps
CPU time 1.59 seconds
Started May 19 02:22:35 PM PDT 24
Finished May 19 02:22:37 PM PDT 24
Peak memory 236560 kb
Host smart-7c8ebb7c-7928-4559-b503-1beb4bb18d16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2099174293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2099174293
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.885154035
Short name T749
Test name
Test status
Simulation time 7204235 ps
CPU time 1.5 seconds
Started May 19 02:22:34 PM PDT 24
Finished May 19 02:22:36 PM PDT 24
Peak memory 234640 kb
Host smart-3948e61a-733b-423e-ada6-e7c1a47c782f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=885154035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.885154035
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2517823339
Short name T782
Test name
Test status
Simulation time 11185069 ps
CPU time 1.44 seconds
Started May 19 02:22:35 PM PDT 24
Finished May 19 02:22:37 PM PDT 24
Peak memory 234748 kb
Host smart-aa34621c-4284-48d4-bc44-9082fc1f7ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2517823339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2517823339
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1750083168
Short name T760
Test name
Test status
Simulation time 11017328 ps
CPU time 1.43 seconds
Started May 19 02:22:40 PM PDT 24
Finished May 19 02:22:43 PM PDT 24
Peak memory 236568 kb
Host smart-5922f379-13b5-4197-8093-ab38e0f72595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1750083168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1750083168
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.914107409
Short name T771
Test name
Test status
Simulation time 15194923 ps
CPU time 1.5 seconds
Started May 19 02:22:41 PM PDT 24
Finished May 19 02:22:44 PM PDT 24
Peak memory 236592 kb
Host smart-306b8e6e-6c57-4492-bd7d-2eff85f2dc2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914107409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.914107409
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2314364947
Short name T732
Test name
Test status
Simulation time 9211404 ps
CPU time 1.5 seconds
Started May 19 02:22:39 PM PDT 24
Finished May 19 02:22:41 PM PDT 24
Peak memory 235644 kb
Host smart-b67c95b3-4c6b-4f3b-aebe-538a1e3ee91b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2314364947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2314364947
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4167423053
Short name T803
Test name
Test status
Simulation time 31858383 ps
CPU time 1.33 seconds
Started May 19 02:22:40 PM PDT 24
Finished May 19 02:22:42 PM PDT 24
Peak memory 235536 kb
Host smart-20ca205f-aa01-4b14-a26f-94ee0dbfeb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4167423053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4167423053
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4277968996
Short name T755
Test name
Test status
Simulation time 3420662601 ps
CPU time 255.32 seconds
Started May 19 02:20:57 PM PDT 24
Finished May 19 02:25:12 PM PDT 24
Peak memory 238432 kb
Host smart-d254a283-9bab-4ae8-bc1f-bf56d7db9d9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4277968996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4277968996
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2873456282
Short name T814
Test name
Test status
Simulation time 5872763909 ps
CPU time 421.34 seconds
Started May 19 02:20:56 PM PDT 24
Finished May 19 02:27:57 PM PDT 24
Peak memory 236596 kb
Host smart-7f883eb7-f6a8-4de5-8ff8-6454f46f9cd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2873456282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2873456282
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2286491923
Short name T751
Test name
Test status
Simulation time 81435636 ps
CPU time 3.63 seconds
Started May 19 02:20:55 PM PDT 24
Finished May 19 02:20:59 PM PDT 24
Peak memory 240036 kb
Host smart-e4a0e490-8c3f-4cbb-853a-a48e2e11ebaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2286491923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2286491923
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3137095515
Short name T798
Test name
Test status
Simulation time 128419424 ps
CPU time 6.03 seconds
Started May 19 02:20:57 PM PDT 24
Finished May 19 02:21:03 PM PDT 24
Peak memory 238808 kb
Host smart-dfdda9fc-0ec4-4125-9bf9-035a8d103c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137095515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3137095515
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4150767706
Short name T747
Test name
Test status
Simulation time 61311727 ps
CPU time 5.67 seconds
Started May 19 02:20:55 PM PDT 24
Finished May 19 02:21:02 PM PDT 24
Peak memory 236528 kb
Host smart-b937865c-8b37-47ee-9d7a-331e676b5ddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4150767706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4150767706
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1001399154
Short name T763
Test name
Test status
Simulation time 10431371 ps
CPU time 1.61 seconds
Started May 19 02:20:46 PM PDT 24
Finished May 19 02:20:48 PM PDT 24
Peak memory 235672 kb
Host smart-6b71faca-1ab0-4822-b4ff-76b5b99a4fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1001399154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1001399154
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4006583829
Short name T817
Test name
Test status
Simulation time 987904191 ps
CPU time 16.69 seconds
Started May 19 02:20:55 PM PDT 24
Finished May 19 02:21:12 PM PDT 24
Peak memory 243840 kb
Host smart-6f5479d4-2d08-492d-9127-245e4cc74136
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4006583829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.4006583829
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3776593145
Short name T154
Test name
Test status
Simulation time 1663152817 ps
CPU time 213.73 seconds
Started May 19 02:20:45 PM PDT 24
Finished May 19 02:24:19 PM PDT 24
Peak memory 265092 kb
Host smart-0f6fb268-2e36-4e3f-a8dd-958c6090a39e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3776593145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3776593145
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2178486461
Short name T713
Test name
Test status
Simulation time 569229813 ps
CPU time 14.67 seconds
Started May 19 02:20:49 PM PDT 24
Finished May 19 02:21:04 PM PDT 24
Peak memory 248348 kb
Host smart-bb938e79-800a-4f43-9156-652c44464550
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2178486461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2178486461
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2540930596
Short name T797
Test name
Test status
Simulation time 9782777 ps
CPU time 1.64 seconds
Started May 19 02:22:40 PM PDT 24
Finished May 19 02:22:42 PM PDT 24
Peak memory 236572 kb
Host smart-ad33f672-407e-4059-a615-7d0dd84e1760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2540930596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2540930596
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4287611324
Short name T741
Test name
Test status
Simulation time 17467672 ps
CPU time 1.38 seconds
Started May 19 02:22:41 PM PDT 24
Finished May 19 02:22:44 PM PDT 24
Peak memory 236580 kb
Host smart-45e4fa52-5ff8-457b-bb56-2ef9ac48c239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4287611324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4287611324
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.508144711
Short name T344
Test name
Test status
Simulation time 6282881 ps
CPU time 1.45 seconds
Started May 19 02:22:40 PM PDT 24
Finished May 19 02:22:42 PM PDT 24
Peak memory 235680 kb
Host smart-2e38e272-2e55-4335-a32b-16e20b5028c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508144711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.508144711
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2822679065
Short name T777
Test name
Test status
Simulation time 48592974 ps
CPU time 2.98 seconds
Started May 19 02:22:49 PM PDT 24
Finished May 19 02:22:53 PM PDT 24
Peak memory 234616 kb
Host smart-27dc195f-7a73-4637-8f54-071f618e1163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2822679065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2822679065
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2306769355
Short name T787
Test name
Test status
Simulation time 10146303 ps
CPU time 1.57 seconds
Started May 19 02:22:51 PM PDT 24
Finished May 19 02:22:53 PM PDT 24
Peak memory 235588 kb
Host smart-f5ca3d62-a182-4e7a-bcac-d9ed04885416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306769355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2306769355
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2000188348
Short name T725
Test name
Test status
Simulation time 10152911 ps
CPU time 1.35 seconds
Started May 19 02:22:47 PM PDT 24
Finished May 19 02:22:49 PM PDT 24
Peak memory 234616 kb
Host smart-3322a5be-916f-4aa6-9a2f-2624b0ea7f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000188348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2000188348
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1206580166
Short name T349
Test name
Test status
Simulation time 32301216 ps
CPU time 1.43 seconds
Started May 19 02:22:45 PM PDT 24
Finished May 19 02:22:47 PM PDT 24
Peak memory 235852 kb
Host smart-881a94bd-e52b-4b53-8786-ef61c29636ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1206580166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1206580166
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1254800738
Short name T821
Test name
Test status
Simulation time 6845852 ps
CPU time 1.53 seconds
Started May 19 02:22:52 PM PDT 24
Finished May 19 02:22:54 PM PDT 24
Peak memory 235576 kb
Host smart-09a2e5de-9fa2-4eb7-ae06-14e50e12ed6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1254800738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1254800738
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3996952426
Short name T164
Test name
Test status
Simulation time 24874216 ps
CPU time 1.46 seconds
Started May 19 02:22:52 PM PDT 24
Finished May 19 02:22:53 PM PDT 24
Peak memory 236584 kb
Host smart-36d2618b-0c53-4bc8-8e85-2c4035151a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3996952426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3996952426
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3110597587
Short name T830
Test name
Test status
Simulation time 3326738889 ps
CPU time 266.95 seconds
Started May 19 02:21:02 PM PDT 24
Finished May 19 02:25:29 PM PDT 24
Peak memory 238620 kb
Host smart-15ffa060-80d8-422d-a0dc-43432b4ba3e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3110597587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3110597587
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.893275413
Short name T826
Test name
Test status
Simulation time 22822337736 ps
CPU time 376.41 seconds
Started May 19 02:20:58 PM PDT 24
Finished May 19 02:27:15 PM PDT 24
Peak memory 240152 kb
Host smart-52c59d4a-195a-4fe4-a9e1-43a5f2b38ac9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=893275413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.893275413
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1630554339
Short name T816
Test name
Test status
Simulation time 40391142 ps
CPU time 4.18 seconds
Started May 19 02:21:02 PM PDT 24
Finished May 19 02:21:07 PM PDT 24
Peak memory 240112 kb
Host smart-ce0222ba-2d42-4b7d-9ab6-544f38a3cc82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1630554339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1630554339
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2393760431
Short name T724
Test name
Test status
Simulation time 302201376 ps
CPU time 13.22 seconds
Started May 19 02:21:06 PM PDT 24
Finished May 19 02:21:20 PM PDT 24
Peak memory 251392 kb
Host smart-0a1aa0a0-bde5-46cb-9635-df9634335db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393760431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2393760431
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3541248174
Short name T769
Test name
Test status
Simulation time 132530939 ps
CPU time 9.15 seconds
Started May 19 02:21:02 PM PDT 24
Finished May 19 02:21:12 PM PDT 24
Peak memory 236556 kb
Host smart-e5137d54-d410-49c1-af23-c8073f680998
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3541248174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3541248174
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1016411799
Short name T789
Test name
Test status
Simulation time 9878232 ps
CPU time 1.58 seconds
Started May 19 02:20:57 PM PDT 24
Finished May 19 02:20:59 PM PDT 24
Peak memory 236548 kb
Host smart-ed23114a-9fe3-4247-84ec-878cacb28b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016411799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1016411799
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1583751223
Short name T726
Test name
Test status
Simulation time 351646117 ps
CPU time 25.37 seconds
Started May 19 02:21:08 PM PDT 24
Finished May 19 02:21:33 PM PDT 24
Peak memory 244756 kb
Host smart-e381df36-9d5a-4917-8a03-1b9ce4ee2fe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1583751223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1583751223
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2586703244
Short name T148
Test name
Test status
Simulation time 820649917 ps
CPU time 111.28 seconds
Started May 19 02:20:58 PM PDT 24
Finished May 19 02:22:49 PM PDT 24
Peak memory 265036 kb
Host smart-07177916-7027-49d0-9b29-570601b8c6e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2586703244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2586703244
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2435817013
Short name T709
Test name
Test status
Simulation time 113496175 ps
CPU time 8.56 seconds
Started May 19 02:21:03 PM PDT 24
Finished May 19 02:21:12 PM PDT 24
Peak memory 248376 kb
Host smart-63190e11-1d59-4c60-a632-3389211f424d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2435817013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2435817013
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1508530988
Short name T718
Test name
Test status
Simulation time 7940179 ps
CPU time 1.33 seconds
Started May 19 02:22:53 PM PDT 24
Finished May 19 02:22:55 PM PDT 24
Peak memory 236552 kb
Host smart-f4a5529f-7926-4f95-bd98-5ffe7114a796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1508530988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1508530988
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3221383015
Short name T745
Test name
Test status
Simulation time 8122265 ps
CPU time 1.51 seconds
Started May 19 02:22:49 PM PDT 24
Finished May 19 02:22:51 PM PDT 24
Peak memory 236556 kb
Host smart-217d74ae-f8d5-461e-a0ab-f763891097c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3221383015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3221383015
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3397391120
Short name T793
Test name
Test status
Simulation time 18241620 ps
CPU time 1.39 seconds
Started May 19 02:22:56 PM PDT 24
Finished May 19 02:22:58 PM PDT 24
Peak memory 234652 kb
Host smart-ce7c1cf6-4b74-4a0a-be85-b4727307f3e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3397391120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3397391120
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1223883139
Short name T781
Test name
Test status
Simulation time 6620200 ps
CPU time 1.4 seconds
Started May 19 02:22:50 PM PDT 24
Finished May 19 02:22:52 PM PDT 24
Peak memory 235632 kb
Host smart-1e0d858d-cc61-4ae7-b3fd-7f0bfb3ec28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1223883139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1223883139
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.748319111
Short name T163
Test name
Test status
Simulation time 11559953 ps
CPU time 1.26 seconds
Started May 19 02:22:49 PM PDT 24
Finished May 19 02:22:51 PM PDT 24
Peak memory 236588 kb
Host smart-76f5c26f-0b7f-4f53-a563-1a71ed02b2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=748319111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.748319111
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3417633329
Short name T784
Test name
Test status
Simulation time 9526969 ps
CPU time 1.55 seconds
Started May 19 02:22:50 PM PDT 24
Finished May 19 02:22:52 PM PDT 24
Peak memory 234564 kb
Host smart-14a395ac-dadb-49b5-8505-c1706ada985e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3417633329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3417633329
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3783275739
Short name T251
Test name
Test status
Simulation time 18271364 ps
CPU time 1.41 seconds
Started May 19 02:22:52 PM PDT 24
Finished May 19 02:22:54 PM PDT 24
Peak memory 236592 kb
Host smart-5359b5f3-d92c-4c02-944d-4f239d2641cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783275739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3783275739
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1846009689
Short name T772
Test name
Test status
Simulation time 6658539 ps
CPU time 1.58 seconds
Started May 19 02:22:55 PM PDT 24
Finished May 19 02:22:57 PM PDT 24
Peak memory 235652 kb
Host smart-28ecd1e6-1430-4430-84f9-ceeffb14093f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1846009689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1846009689
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1617042536
Short name T805
Test name
Test status
Simulation time 13447689 ps
CPU time 1.49 seconds
Started May 19 02:22:55 PM PDT 24
Finished May 19 02:22:57 PM PDT 24
Peak memory 236548 kb
Host smart-a46e3d16-98ba-4b62-91cd-271ebf25dd41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1617042536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1617042536
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.852991884
Short name T739
Test name
Test status
Simulation time 8501358 ps
CPU time 1.4 seconds
Started May 19 02:22:54 PM PDT 24
Finished May 19 02:22:56 PM PDT 24
Peak memory 236584 kb
Host smart-274708bc-3c97-442a-84e9-b9be8e21ab61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=852991884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.852991884
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3801786376
Short name T783
Test name
Test status
Simulation time 273375327 ps
CPU time 6.87 seconds
Started May 19 02:21:17 PM PDT 24
Finished May 19 02:21:24 PM PDT 24
Peak memory 243344 kb
Host smart-68e0a826-9ad1-422c-991e-8956ec548978
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801786376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3801786376
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1092417301
Short name T742
Test name
Test status
Simulation time 65711039 ps
CPU time 3.44 seconds
Started May 19 02:21:13 PM PDT 24
Finished May 19 02:21:17 PM PDT 24
Peak memory 235604 kb
Host smart-84f5c2a0-3e3b-429e-a001-f7e95e589641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1092417301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1092417301
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3213499428
Short name T348
Test name
Test status
Simulation time 13546667 ps
CPU time 1.75 seconds
Started May 19 02:21:13 PM PDT 24
Finished May 19 02:21:15 PM PDT 24
Peak memory 236604 kb
Host smart-ca38e48d-b5fe-4d56-a051-39ea082c5114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3213499428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3213499428
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.788804158
Short name T801
Test name
Test status
Simulation time 273823518 ps
CPU time 25.11 seconds
Started May 19 02:21:11 PM PDT 24
Finished May 19 02:21:37 PM PDT 24
Peak memory 240008 kb
Host smart-6eb8a56c-901a-4f18-a78f-f1f1d49e25d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=788804158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.788804158
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4181485899
Short name T127
Test name
Test status
Simulation time 18056573398 ps
CPU time 628.93 seconds
Started May 19 02:21:07 PM PDT 24
Finished May 19 02:31:36 PM PDT 24
Peak memory 265328 kb
Host smart-a1b09cb1-df2a-4c51-94f6-91a1a9eea024
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181485899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4181485899
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2008995303
Short name T729
Test name
Test status
Simulation time 1085950033 ps
CPU time 22.41 seconds
Started May 19 02:21:07 PM PDT 24
Finished May 19 02:21:29 PM PDT 24
Peak memory 253452 kb
Host smart-fea3c746-d14d-40f4-b66d-d4297e21bf61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2008995303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2008995303
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2029717676
Short name T799
Test name
Test status
Simulation time 1289140211 ps
CPU time 95.33 seconds
Started May 19 02:21:17 PM PDT 24
Finished May 19 02:22:53 PM PDT 24
Peak memory 239352 kb
Host smart-5e74b7ae-e75b-4a39-815c-5377b68f2787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2029717676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2029717676
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4141120112
Short name T720
Test name
Test status
Simulation time 116223126 ps
CPU time 10.05 seconds
Started May 19 02:21:36 PM PDT 24
Finished May 19 02:21:46 PM PDT 24
Peak memory 251888 kb
Host smart-17679313-2267-43d9-936d-7286f1270ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141120112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4141120112
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1980891845
Short name T827
Test name
Test status
Simulation time 62212874 ps
CPU time 4.68 seconds
Started May 19 02:21:20 PM PDT 24
Finished May 19 02:21:25 PM PDT 24
Peak memory 235628 kb
Host smart-686f8c22-0606-4c89-870b-00bc2edf4da3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1980891845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1980891845
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.4285473176
Short name T192
Test name
Test status
Simulation time 498501733 ps
CPU time 35.65 seconds
Started May 19 02:21:20 PM PDT 24
Finished May 19 02:21:56 PM PDT 24
Peak memory 243796 kb
Host smart-33a8f4c0-4365-4e70-a156-17e881224565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4285473176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.4285473176
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.110937688
Short name T151
Test name
Test status
Simulation time 3488962046 ps
CPU time 183.32 seconds
Started May 19 02:21:19 PM PDT 24
Finished May 19 02:24:23 PM PDT 24
Peak memory 256936 kb
Host smart-e9d8beb2-120e-4d55-afdd-ff641799a7fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=110937688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.110937688
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.240998659
Short name T140
Test name
Test status
Simulation time 13549680935 ps
CPU time 503.78 seconds
Started May 19 02:21:18 PM PDT 24
Finished May 19 02:29:42 PM PDT 24
Peak memory 265292 kb
Host smart-3d67dc56-8b69-4fc3-9bb3-6d6a1badd267
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240998659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.240998659
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2448193077
Short name T815
Test name
Test status
Simulation time 193725354 ps
CPU time 7.77 seconds
Started May 19 02:21:19 PM PDT 24
Finished May 19 02:21:27 PM PDT 24
Peak memory 251760 kb
Host smart-077b56e5-7d89-4294-8847-f9d7251fb13c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448193077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2448193077
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1065040566
Short name T712
Test name
Test status
Simulation time 127399844 ps
CPU time 7.64 seconds
Started May 19 02:21:25 PM PDT 24
Finished May 19 02:21:33 PM PDT 24
Peak memory 240132 kb
Host smart-4424d6f8-0ff5-46bd-af20-094695b9c570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065040566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1065040566
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3933204401
Short name T808
Test name
Test status
Simulation time 34660162 ps
CPU time 3.51 seconds
Started May 19 02:21:35 PM PDT 24
Finished May 19 02:21:39 PM PDT 24
Peak memory 236524 kb
Host smart-09a5dc19-9380-4203-917f-dbca7edcf89e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3933204401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3933204401
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2560123208
Short name T342
Test name
Test status
Simulation time 12169219 ps
CPU time 1.3 seconds
Started May 19 02:21:24 PM PDT 24
Finished May 19 02:21:25 PM PDT 24
Peak memory 236600 kb
Host smart-63f15312-7953-4e87-8dc7-47ffbaff855c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2560123208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2560123208
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2409043124
Short name T195
Test name
Test status
Simulation time 176027466 ps
CPU time 11.67 seconds
Started May 19 02:21:35 PM PDT 24
Finished May 19 02:21:48 PM PDT 24
Peak memory 248272 kb
Host smart-19545052-7cbb-4270-9369-dcaae2056368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2409043124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2409043124
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1521650096
Short name T770
Test name
Test status
Simulation time 267101680 ps
CPU time 16.74 seconds
Started May 19 02:21:23 PM PDT 24
Finished May 19 02:21:40 PM PDT 24
Peak memory 248180 kb
Host smart-9009b032-80ef-44e7-be30-33d2e345b23d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1521650096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1521650096
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4192936202
Short name T756
Test name
Test status
Simulation time 1073703241 ps
CPU time 12.57 seconds
Started May 19 02:21:28 PM PDT 24
Finished May 19 02:21:41 PM PDT 24
Peak memory 254100 kb
Host smart-01a21421-45dd-4c6d-b134-6da9b80df580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192936202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4192936202
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1335067699
Short name T823
Test name
Test status
Simulation time 136320374 ps
CPU time 11.5 seconds
Started May 19 02:21:28 PM PDT 24
Finished May 19 02:21:40 PM PDT 24
Peak memory 236532 kb
Host smart-f0f3f38f-ec3f-4a8d-a1c4-1773608949c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1335067699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1335067699
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1132824681
Short name T753
Test name
Test status
Simulation time 7364677 ps
CPU time 1.51 seconds
Started May 19 02:21:30 PM PDT 24
Finished May 19 02:21:31 PM PDT 24
Peak memory 235684 kb
Host smart-5e4d945a-396e-4b6e-aa4c-5752ed3b8017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1132824681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1132824681
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2587268699
Short name T721
Test name
Test status
Simulation time 1675432062 ps
CPU time 24.97 seconds
Started May 19 02:21:28 PM PDT 24
Finished May 19 02:21:53 PM PDT 24
Peak memory 248264 kb
Host smart-bf83d9a5-173c-46dc-9ae5-ce82b8074d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2587268699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2587268699
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2102176609
Short name T820
Test name
Test status
Simulation time 3723175846 ps
CPU time 146.11 seconds
Started May 19 02:21:35 PM PDT 24
Finished May 19 02:24:02 PM PDT 24
Peak memory 265092 kb
Host smart-c6151164-c426-4e56-8fb0-f40600813716
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2102176609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2102176609
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2478331492
Short name T806
Test name
Test status
Simulation time 9136804767 ps
CPU time 317.51 seconds
Started May 19 02:21:35 PM PDT 24
Finished May 19 02:26:54 PM PDT 24
Peak memory 269464 kb
Host smart-12d1f267-2775-4833-bbd1-c659377ec8ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478331492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2478331492
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1289977793
Short name T802
Test name
Test status
Simulation time 578219898 ps
CPU time 10.11 seconds
Started May 19 02:21:24 PM PDT 24
Finished May 19 02:21:35 PM PDT 24
Peak memory 248440 kb
Host smart-81c6b515-de79-4a75-bb52-fbe4f36b64a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1289977793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1289977793
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3485696311
Short name T204
Test name
Test status
Simulation time 133526799 ps
CPU time 6.53 seconds
Started May 19 02:21:39 PM PDT 24
Finished May 19 02:21:46 PM PDT 24
Peak memory 256456 kb
Host smart-ab5f3366-1d55-47ed-ba14-a6f6eb517007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485696311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3485696311
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3605846402
Short name T757
Test name
Test status
Simulation time 122012404 ps
CPU time 6.13 seconds
Started May 19 02:21:34 PM PDT 24
Finished May 19 02:21:41 PM PDT 24
Peak memory 236496 kb
Host smart-e844a8d2-e072-4de9-ac69-aaae8072511f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3605846402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3605846402
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1390048446
Short name T731
Test name
Test status
Simulation time 8310045 ps
CPU time 1.41 seconds
Started May 19 02:21:33 PM PDT 24
Finished May 19 02:21:35 PM PDT 24
Peak memory 235660 kb
Host smart-19261b04-2193-4f9e-bc60-b2b532ffbcba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1390048446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1390048446
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4154919537
Short name T191
Test name
Test status
Simulation time 681242006 ps
CPU time 21.9 seconds
Started May 19 02:21:39 PM PDT 24
Finished May 19 02:22:01 PM PDT 24
Peak memory 248292 kb
Host smart-17b74462-2bf0-4764-bd26-bb80e41621c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4154919537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4154919537
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2203832720
Short name T146
Test name
Test status
Simulation time 8327026152 ps
CPU time 583.19 seconds
Started May 19 02:21:30 PM PDT 24
Finished May 19 02:31:14 PM PDT 24
Peak memory 267888 kb
Host smart-4d9c354e-dcbd-4e2d-8d1a-007fbbe729e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203832720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2203832720
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1620682013
Short name T717
Test name
Test status
Simulation time 496635983 ps
CPU time 18.89 seconds
Started May 19 02:21:34 PM PDT 24
Finished May 19 02:21:54 PM PDT 24
Peak memory 248156 kb
Host smart-b0484f5a-f3c7-4f02-b0dd-ec7739a0bdae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1620682013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1620682013
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3877966052
Short name T681
Test name
Test status
Simulation time 55771677371 ps
CPU time 3097.61 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 03:20:18 PM PDT 24
Peak memory 289268 kb
Host smart-a3fee028-14ca-4725-a993-76efe64476c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877966052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3877966052
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4257195762
Short name T583
Test name
Test status
Simulation time 1515726029 ps
CPU time 34.11 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:29:14 PM PDT 24
Peak memory 248752 kb
Host smart-28a34268-ca85-43d9-b43f-fc6c591f812d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4257195762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4257195762
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4180805968
Short name T680
Test name
Test status
Simulation time 7442016048 ps
CPU time 182.78 seconds
Started May 19 02:28:30 PM PDT 24
Finished May 19 02:31:33 PM PDT 24
Peak memory 257000 kb
Host smart-f871f964-d075-4be1-a00e-177a786901af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41808
05968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4180805968
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1426186885
Short name T401
Test name
Test status
Simulation time 429157866 ps
CPU time 29.96 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:29:04 PM PDT 24
Peak memory 248784 kb
Host smart-4f52f508-7a69-444f-a379-bb501cde079e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
86885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1426186885
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.427361856
Short name T453
Test name
Test status
Simulation time 745570524477 ps
CPU time 1900.66 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 03:00:22 PM PDT 24
Peak memory 273412 kb
Host smart-b73bba0e-9e4d-4781-a4fe-01f15969829b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427361856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.427361856
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1137814406
Short name T196
Test name
Test status
Simulation time 23494324241 ps
CPU time 469.85 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:36:30 PM PDT 24
Peak memory 248036 kb
Host smart-5eba43ea-93ff-455e-be40-a33cffa0c35d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137814406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1137814406
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2808874593
Short name T408
Test name
Test status
Simulation time 817565913 ps
CPU time 13.14 seconds
Started May 19 02:28:34 PM PDT 24
Finished May 19 02:28:48 PM PDT 24
Peak memory 256972 kb
Host smart-e08341bb-fedd-4e00-b669-221360243f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28088
74593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2808874593
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3360326819
Short name T63
Test name
Test status
Simulation time 1515781390 ps
CPU time 53.34 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:29:28 PM PDT 24
Peak memory 248736 kb
Host smart-6cd632d3-3467-4b12-875e-ab801bb4829b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33603
26819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3360326819
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4038598266
Short name T12
Test name
Test status
Simulation time 451706735 ps
CPU time 22.87 seconds
Started May 19 02:28:38 PM PDT 24
Finished May 19 02:29:02 PM PDT 24
Peak memory 277572 kb
Host smart-7e856d6a-06a7-4e1c-875c-7e5ae5d75beb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4038598266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4038598266
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3899007152
Short name T693
Test name
Test status
Simulation time 747920924 ps
CPU time 50.77 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:29:24 PM PDT 24
Peak memory 255584 kb
Host smart-4e461d0c-1857-4c35-a404-8ee5e90eb337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38990
07152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3899007152
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.4074768515
Short name T615
Test name
Test status
Simulation time 123404435 ps
CPU time 9.78 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:50 PM PDT 24
Peak memory 248768 kb
Host smart-2f183367-29ae-4732-ba2a-3c94344381aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40747
68515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.4074768515
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.631062161
Short name T73
Test name
Test status
Simulation time 38166540923 ps
CPU time 2425.81 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 03:09:07 PM PDT 24
Peak memory 289404 kb
Host smart-e7af0ad4-770c-4fcd-889c-9dec94105d41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631062161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.631062161
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1675719294
Short name T218
Test name
Test status
Simulation time 123773224 ps
CPU time 3.06 seconds
Started May 19 02:28:43 PM PDT 24
Finished May 19 02:28:47 PM PDT 24
Peak memory 248888 kb
Host smart-1bd2ca3c-9f3b-479e-9c8d-2bc7bd912030
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1675719294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1675719294
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1762641978
Short name T410
Test name
Test status
Simulation time 145526851883 ps
CPU time 1548.43 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 02:54:30 PM PDT 24
Peak memory 273476 kb
Host smart-87b8f9ee-f514-4633-88f9-7eac3e98169d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762641978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1762641978
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3415319320
Short name T562
Test name
Test status
Simulation time 2920902840 ps
CPU time 54.14 seconds
Started May 19 02:28:42 PM PDT 24
Finished May 19 02:29:37 PM PDT 24
Peak memory 240624 kb
Host smart-18a559b4-199d-4939-b67c-6b27f4417f0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3415319320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3415319320
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1145904315
Short name T564
Test name
Test status
Simulation time 6809996139 ps
CPU time 140.71 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 02:31:02 PM PDT 24
Peak memory 250900 kb
Host smart-78031375-65d9-43bc-8fba-2047942fc5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459
04315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1145904315
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3744800895
Short name T584
Test name
Test status
Simulation time 570394584 ps
CPU time 17.63 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:58 PM PDT 24
Peak memory 248836 kb
Host smart-cc45a368-322a-443b-9edf-e20c5a17d55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37448
00895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3744800895
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3026429320
Short name T337
Test name
Test status
Simulation time 27279587094 ps
CPU time 1630.57 seconds
Started May 19 02:28:38 PM PDT 24
Finished May 19 02:55:49 PM PDT 24
Peak memory 289800 kb
Host smart-91b2da36-2804-4307-ad61-216605a79ff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026429320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3026429320
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.932920927
Short name T443
Test name
Test status
Simulation time 576467575 ps
CPU time 40.83 seconds
Started May 19 02:28:42 PM PDT 24
Finished May 19 02:29:23 PM PDT 24
Peak memory 248732 kb
Host smart-ff938d52-e008-414e-a2e7-d3cd930ab9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93292
0927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.932920927
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3806070108
Short name T117
Test name
Test status
Simulation time 2499462077 ps
CPU time 42.7 seconds
Started May 19 02:28:40 PM PDT 24
Finished May 19 02:29:24 PM PDT 24
Peak memory 256224 kb
Host smart-1c886842-e77c-4871-b2d6-5e38359e0712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38060
70108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3806070108
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2588154988
Short name T35
Test name
Test status
Simulation time 3475875372 ps
CPU time 19.97 seconds
Started May 19 02:28:43 PM PDT 24
Finished May 19 02:29:04 PM PDT 24
Peak memory 278716 kb
Host smart-002d2a8c-f84c-4596-8d53-2a3751b9da7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2588154988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2588154988
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2580896698
Short name T67
Test name
Test status
Simulation time 1042853383 ps
CPU time 32.3 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:29:13 PM PDT 24
Peak memory 248780 kb
Host smart-db286144-5a15-40f9-9911-3e1a40e0bff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25808
96698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2580896698
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4017384732
Short name T657
Test name
Test status
Simulation time 5540342781 ps
CPU time 57.89 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:29:37 PM PDT 24
Peak memory 256132 kb
Host smart-7bf9534b-48f9-47ff-86a2-1ebd449b025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40173
84732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4017384732
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1033625894
Short name T242
Test name
Test status
Simulation time 9542357804 ps
CPU time 267.84 seconds
Started May 19 02:28:46 PM PDT 24
Finished May 19 02:33:14 PM PDT 24
Peak memory 257028 kb
Host smart-582302c4-39d8-404d-99a6-71696fb270d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033625894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1033625894
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.515981230
Short name T528
Test name
Test status
Simulation time 82768775666 ps
CPU time 3031.92 seconds
Started May 19 02:28:43 PM PDT 24
Finished May 19 03:19:17 PM PDT 24
Peak memory 301088 kb
Host smart-3fc3a522-26c4-485c-b31f-3009fcda6957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515981230 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.515981230
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3841856178
Short name T209
Test name
Test status
Simulation time 37490873 ps
CPU time 4.11 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 02:29:08 PM PDT 24
Peak memory 248892 kb
Host smart-f99daf9f-876a-4ed7-972d-1f10a5f35b96
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3841856178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3841856178
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1384002498
Short name T110
Test name
Test status
Simulation time 7827668863 ps
CPU time 817.83 seconds
Started May 19 02:29:04 PM PDT 24
Finished May 19 02:42:43 PM PDT 24
Peak memory 273364 kb
Host smart-0a838fed-0180-481a-bc11-fabb9d9e9c3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384002498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1384002498
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2386804975
Short name T398
Test name
Test status
Simulation time 1418860862 ps
CPU time 22.25 seconds
Started May 19 02:29:06 PM PDT 24
Finished May 19 02:29:29 PM PDT 24
Peak memory 248756 kb
Host smart-b5cf9b99-1d94-46cb-9d24-830d35b0e737
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2386804975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2386804975
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2363326463
Short name T384
Test name
Test status
Simulation time 4163130911 ps
CPU time 242.14 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:33:13 PM PDT 24
Peak memory 256968 kb
Host smart-eebd7cc7-4aac-4f6a-a599-bd36f699a0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23633
26463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2363326463
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2229776445
Short name T531
Test name
Test status
Simulation time 1775291210 ps
CPU time 37.25 seconds
Started May 19 02:29:05 PM PDT 24
Finished May 19 02:29:43 PM PDT 24
Peak memory 248752 kb
Host smart-1004fc80-f672-4b68-9c18-df40997ac494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22297
76445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2229776445
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1629151527
Short name T695
Test name
Test status
Simulation time 182908815257 ps
CPU time 2341.39 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 03:08:06 PM PDT 24
Peak memory 273456 kb
Host smart-bf2652f8-b5f0-424d-844c-127376445b6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629151527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1629151527
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2224799407
Short name T226
Test name
Test status
Simulation time 22645058440 ps
CPU time 906.19 seconds
Started May 19 02:29:10 PM PDT 24
Finished May 19 02:44:17 PM PDT 24
Peak memory 272872 kb
Host smart-1993e62d-78a7-48bd-a5e7-91ee157c1fc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224799407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2224799407
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3096139486
Short name T455
Test name
Test status
Simulation time 986787626 ps
CPU time 11.28 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 02:29:16 PM PDT 24
Peak memory 248792 kb
Host smart-8ef133dd-49e6-4796-b062-2ffd4db8d0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
39486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3096139486
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.965804893
Short name T421
Test name
Test status
Simulation time 718013396 ps
CPU time 45.13 seconds
Started May 19 02:29:05 PM PDT 24
Finished May 19 02:29:51 PM PDT 24
Peak memory 248908 kb
Host smart-50108dcc-c81d-41b5-9e8c-845bbcf8a08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96580
4893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.965804893
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1970109526
Short name T412
Test name
Test status
Simulation time 3442499253 ps
CPU time 53.4 seconds
Started May 19 02:29:05 PM PDT 24
Finished May 19 02:29:59 PM PDT 24
Peak memory 256440 kb
Host smart-32874450-f95a-47ee-8065-c0758031911c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
09526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1970109526
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1667810487
Short name T457
Test name
Test status
Simulation time 506428567 ps
CPU time 28.36 seconds
Started May 19 02:29:06 PM PDT 24
Finished May 19 02:29:35 PM PDT 24
Peak memory 248848 kb
Host smart-450e2d1c-9c4c-43bb-91e4-cb79502e7e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16678
10487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1667810487
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3758224777
Short name T97
Test name
Test status
Simulation time 11143127003 ps
CPU time 1021.26 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 02:46:06 PM PDT 24
Peak memory 281592 kb
Host smart-6e3e9ac0-bdc8-4439-900b-93d446336512
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758224777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3758224777
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.184718077
Short name T642
Test name
Test status
Simulation time 12003563133 ps
CPU time 802.36 seconds
Started May 19 02:29:11 PM PDT 24
Finished May 19 02:42:34 PM PDT 24
Peak memory 272876 kb
Host smart-91951bc1-f833-4a55-8d67-105b639ab59c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184718077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.184718077
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1179695327
Short name T469
Test name
Test status
Simulation time 418789549 ps
CPU time 11.03 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:29:21 PM PDT 24
Peak memory 248768 kb
Host smart-f07759b3-92f1-48b2-86ae-3e1d59bd62f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1179695327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1179695327
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3039698398
Short name T400
Test name
Test status
Simulation time 695472624 ps
CPU time 62.87 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:30:13 PM PDT 24
Peak memory 256836 kb
Host smart-97d7e876-2216-4806-a8c1-33f3cedf8379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30396
98398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3039698398
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1451456376
Short name T601
Test name
Test status
Simulation time 3218572230 ps
CPU time 55.7 seconds
Started May 19 02:29:10 PM PDT 24
Finished May 19 02:30:06 PM PDT 24
Peak memory 248792 kb
Host smart-bb87c206-8d5f-499a-a507-262be778bc0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
56376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1451456376
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2337081820
Short name T325
Test name
Test status
Simulation time 43801380689 ps
CPU time 1423.77 seconds
Started May 19 02:29:08 PM PDT 24
Finished May 19 02:52:53 PM PDT 24
Peak memory 266224 kb
Host smart-b3f0d63e-1b8c-4cb0-93fa-1ed5a8f8a697
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337081820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2337081820
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2348363540
Short name T550
Test name
Test status
Simulation time 29235248139 ps
CPU time 1937.28 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 03:01:28 PM PDT 24
Peak memory 272416 kb
Host smart-8d724c5e-c657-40a4-99ab-d5bd44b0d86f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348363540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2348363540
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.72585028
Short name T589
Test name
Test status
Simulation time 5572068498 ps
CPU time 241.74 seconds
Started May 19 02:29:15 PM PDT 24
Finished May 19 02:33:18 PM PDT 24
Peak memory 248096 kb
Host smart-4bd41961-1694-4ccf-a7be-fd36be97766a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72585028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.72585028
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2038744620
Short name T399
Test name
Test status
Simulation time 2719263046 ps
CPU time 42.94 seconds
Started May 19 02:29:07 PM PDT 24
Finished May 19 02:29:50 PM PDT 24
Peak memory 256960 kb
Host smart-f41aaedb-6059-4466-a391-0717618c8ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
44620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2038744620
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1436914733
Short name T361
Test name
Test status
Simulation time 533924886 ps
CPU time 10.81 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:29:21 PM PDT 24
Peak memory 248728 kb
Host smart-8b86ee81-c553-4c78-89ae-aeab562985ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14369
14733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1436914733
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2065891607
Short name T516
Test name
Test status
Simulation time 1272328202 ps
CPU time 34.51 seconds
Started May 19 02:29:15 PM PDT 24
Finished May 19 02:29:50 PM PDT 24
Peak memory 248756 kb
Host smart-23ca5f51-f8ee-45b7-9e72-fcad2969f7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
91607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2065891607
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.527580705
Short name T540
Test name
Test status
Simulation time 55300421187 ps
CPU time 1176.26 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:48:46 PM PDT 24
Peak memory 286144 kb
Host smart-0f827d4b-f108-41c1-a0cb-54097698e952
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527580705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.527580705
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3371948035
Short name T25
Test name
Test status
Simulation time 20978819906 ps
CPU time 1357.27 seconds
Started May 19 02:29:14 PM PDT 24
Finished May 19 02:51:53 PM PDT 24
Peak memory 281716 kb
Host smart-f9b0926b-b741-4ca6-9545-2a90f0a73e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371948035 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3371948035
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3315824798
Short name T210
Test name
Test status
Simulation time 17712725 ps
CPU time 2.48 seconds
Started May 19 02:29:22 PM PDT 24
Finished May 19 02:29:26 PM PDT 24
Peak memory 248904 kb
Host smart-228496b1-c6db-41f9-86ca-c971e7cd250b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3315824798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3315824798
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1581952065
Short name T473
Test name
Test status
Simulation time 197704930675 ps
CPU time 3075.22 seconds
Started May 19 02:29:14 PM PDT 24
Finished May 19 03:20:30 PM PDT 24
Peak memory 281608 kb
Host smart-c0aeff7a-0102-49e5-9d39-b02d815034c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581952065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1581952065
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1493463214
Short name T678
Test name
Test status
Simulation time 2836067208 ps
CPU time 33.44 seconds
Started May 19 02:29:22 PM PDT 24
Finished May 19 02:29:56 PM PDT 24
Peak memory 248816 kb
Host smart-8d55b523-00b6-4b52-b5cb-05ca61ee3c0c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1493463214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1493463214
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1012766262
Short name T460
Test name
Test status
Simulation time 8040106489 ps
CPU time 260.81 seconds
Started May 19 02:29:16 PM PDT 24
Finished May 19 02:33:38 PM PDT 24
Peak memory 250424 kb
Host smart-658fd13c-e4df-4240-be53-8bc20a768e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10127
66262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1012766262
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2552014126
Short name T200
Test name
Test status
Simulation time 1640066613 ps
CPU time 40.26 seconds
Started May 19 02:29:14 PM PDT 24
Finished May 19 02:29:55 PM PDT 24
Peak memory 249188 kb
Host smart-0e4bad3b-f249-49c0-a5b3-c5b0e8af3d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
14126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2552014126
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.441245142
Short name T235
Test name
Test status
Simulation time 29476478347 ps
CPU time 1621.71 seconds
Started May 19 02:29:19 PM PDT 24
Finished May 19 02:56:21 PM PDT 24
Peak memory 265272 kb
Host smart-50be61dc-4c4b-4495-bf82-37f01fcacde9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441245142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.441245142
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.356647723
Short name T228
Test name
Test status
Simulation time 37055940264 ps
CPU time 2107.68 seconds
Started May 19 02:29:22 PM PDT 24
Finished May 19 03:04:31 PM PDT 24
Peak memory 289144 kb
Host smart-ab9fdae1-b937-4a18-8d83-a9e557306db9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356647723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.356647723
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2778264327
Short name T7
Test name
Test status
Simulation time 33558230358 ps
CPU time 213.77 seconds
Started May 19 02:29:22 PM PDT 24
Finished May 19 02:32:56 PM PDT 24
Peak memory 248356 kb
Host smart-d2bec844-59ea-4c67-8691-3af4eb53fdbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778264327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2778264327
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1293490020
Short name T285
Test name
Test status
Simulation time 1557207775 ps
CPU time 47.38 seconds
Started May 19 02:29:16 PM PDT 24
Finished May 19 02:30:05 PM PDT 24
Peak memory 248936 kb
Host smart-0dedb801-816d-42ae-b81c-3982d79e84e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12934
90020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1293490020
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2072323524
Short name T626
Test name
Test status
Simulation time 129616663 ps
CPU time 9.35 seconds
Started May 19 02:29:16 PM PDT 24
Finished May 19 02:29:27 PM PDT 24
Peak memory 251068 kb
Host smart-2c9f3ea7-df11-4d9e-9d14-03060d6fe796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20723
23524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2072323524
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.903585185
Short name T515
Test name
Test status
Simulation time 662507763 ps
CPU time 44.07 seconds
Started May 19 02:29:15 PM PDT 24
Finished May 19 02:30:00 PM PDT 24
Peak memory 248780 kb
Host smart-42275384-8ea5-47b4-90a7-4ba6011720ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90358
5185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.903585185
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2934749255
Short name T428
Test name
Test status
Simulation time 1424292657 ps
CPU time 37.15 seconds
Started May 19 02:29:14 PM PDT 24
Finished May 19 02:29:52 PM PDT 24
Peak memory 248768 kb
Host smart-34dbdd08-d55c-459d-a61d-9a1d111e5ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
49255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2934749255
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1418963972
Short name T212
Test name
Test status
Simulation time 55632126 ps
CPU time 4.49 seconds
Started May 19 02:29:35 PM PDT 24
Finished May 19 02:29:41 PM PDT 24
Peak memory 248936 kb
Host smart-192934a6-0138-4e48-a0d3-3e3fec42ff10
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1418963972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1418963972
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.972822813
Short name T446
Test name
Test status
Simulation time 28496744606 ps
CPU time 733.18 seconds
Started May 19 02:29:30 PM PDT 24
Finished May 19 02:41:44 PM PDT 24
Peak memory 268764 kb
Host smart-5a14db24-2394-4f71-bf98-68f8e822a2c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972822813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.972822813
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2778242469
Short name T429
Test name
Test status
Simulation time 1985956736 ps
CPU time 39.48 seconds
Started May 19 02:29:35 PM PDT 24
Finished May 19 02:30:15 PM PDT 24
Peak memory 248788 kb
Host smart-f2707895-7fe3-4e95-ac00-be54a3e2ddc8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2778242469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2778242469
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.292395969
Short name T442
Test name
Test status
Simulation time 10966272656 ps
CPU time 155.02 seconds
Started May 19 02:29:31 PM PDT 24
Finished May 19 02:32:07 PM PDT 24
Peak memory 256908 kb
Host smart-07a8efa9-80c4-4a5d-b536-25936f4904ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
5969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.292395969
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2964411965
Short name T464
Test name
Test status
Simulation time 500712613 ps
CPU time 15.95 seconds
Started May 19 02:29:31 PM PDT 24
Finished May 19 02:29:48 PM PDT 24
Peak memory 248768 kb
Host smart-1cbea9e6-4169-48b7-aec1-d5a679ee1c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29644
11965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2964411965
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3164056823
Short name T694
Test name
Test status
Simulation time 23701125233 ps
CPU time 1448.17 seconds
Started May 19 02:29:32 PM PDT 24
Finished May 19 02:53:41 PM PDT 24
Peak memory 272536 kb
Host smart-ebbbe628-7dc5-4673-a014-e9691f6d3f57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164056823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3164056823
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3877582524
Short name T517
Test name
Test status
Simulation time 291667162669 ps
CPU time 1912.45 seconds
Started May 19 02:29:36 PM PDT 24
Finished May 19 03:01:29 PM PDT 24
Peak memory 268240 kb
Host smart-adf49191-09a0-4d15-acfc-f48a31505b7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877582524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3877582524
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2586408364
Short name T294
Test name
Test status
Simulation time 12525494970 ps
CPU time 148.8 seconds
Started May 19 02:29:33 PM PDT 24
Finished May 19 02:32:02 PM PDT 24
Peak memory 248252 kb
Host smart-256d3feb-9f78-4475-ba94-10c2e3d9eea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586408364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2586408364
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1985382528
Short name T435
Test name
Test status
Simulation time 382995475 ps
CPU time 25.86 seconds
Started May 19 02:29:23 PM PDT 24
Finished May 19 02:29:50 PM PDT 24
Peak memory 255932 kb
Host smart-356eacff-5df7-466b-9f3a-6201598b9b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19853
82528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1985382528
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3336361852
Short name T378
Test name
Test status
Simulation time 140176031 ps
CPU time 6.09 seconds
Started May 19 02:29:30 PM PDT 24
Finished May 19 02:29:37 PM PDT 24
Peak memory 248724 kb
Host smart-191ac007-d5e6-4a75-bd79-3202aaa0f9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33363
61852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3336361852
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3066250010
Short name T417
Test name
Test status
Simulation time 142849086 ps
CPU time 17.06 seconds
Started May 19 02:29:22 PM PDT 24
Finished May 19 02:29:40 PM PDT 24
Peak memory 256496 kb
Host smart-89df1836-a102-4e68-8a60-7e5bee3fec00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30662
50010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3066250010
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2404652638
Short name T288
Test name
Test status
Simulation time 21584572584 ps
CPU time 2084.41 seconds
Started May 19 02:29:36 PM PDT 24
Finished May 19 03:04:21 PM PDT 24
Peak memory 297832 kb
Host smart-def632c3-4f3c-4817-bdc4-bfffdb95a663
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404652638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2404652638
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3210390396
Short name T205
Test name
Test status
Simulation time 256965910 ps
CPU time 3.14 seconds
Started May 19 02:29:44 PM PDT 24
Finished May 19 02:29:48 PM PDT 24
Peak memory 248928 kb
Host smart-8a5d0197-fc47-43c9-aeb7-d3ae0b8b3022
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3210390396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3210390396
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2581740299
Short name T486
Test name
Test status
Simulation time 31507654077 ps
CPU time 1975.72 seconds
Started May 19 02:29:40 PM PDT 24
Finished May 19 03:02:37 PM PDT 24
Peak memory 281604 kb
Host smart-9f94d459-2c84-4c5a-9d4c-0c94d06e9f17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581740299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2581740299
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1051651020
Short name T426
Test name
Test status
Simulation time 95295585 ps
CPU time 6.81 seconds
Started May 19 02:29:47 PM PDT 24
Finished May 19 02:29:55 PM PDT 24
Peak memory 240516 kb
Host smart-e89ca6d7-8729-4133-99a9-067a371276a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1051651020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1051651020
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2675672081
Short name T391
Test name
Test status
Simulation time 58660708 ps
CPU time 4.29 seconds
Started May 19 02:29:40 PM PDT 24
Finished May 19 02:29:45 PM PDT 24
Peak memory 239256 kb
Host smart-50ec2085-ead3-44db-9db2-f35eae77b435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26756
72081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2675672081
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.458075697
Short name T79
Test name
Test status
Simulation time 413519831 ps
CPU time 32.54 seconds
Started May 19 02:29:35 PM PDT 24
Finished May 19 02:30:09 PM PDT 24
Peak memory 256944 kb
Host smart-8fc5935f-0253-4a60-9998-6ddee33ce095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45807
5697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.458075697
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3602498035
Short name T332
Test name
Test status
Simulation time 384529726317 ps
CPU time 2790.51 seconds
Started May 19 02:29:40 PM PDT 24
Finished May 19 03:16:12 PM PDT 24
Peak memory 289104 kb
Host smart-70bac28e-b616-446a-933e-638dccb4945a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602498035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3602498035
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3792394146
Short name T611
Test name
Test status
Simulation time 79352207848 ps
CPU time 1379.55 seconds
Started May 19 02:29:41 PM PDT 24
Finished May 19 02:52:41 PM PDT 24
Peak memory 273396 kb
Host smart-33d37c8c-ed8a-45b4-b9e9-0c270619b9b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792394146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3792394146
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2650447597
Short name T690
Test name
Test status
Simulation time 23261003337 ps
CPU time 233.58 seconds
Started May 19 02:29:41 PM PDT 24
Finished May 19 02:33:35 PM PDT 24
Peak memory 248100 kb
Host smart-37e05606-3be1-4870-abaf-1149ea73b7e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650447597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2650447597
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2580533374
Short name T437
Test name
Test status
Simulation time 772992384 ps
CPU time 12.01 seconds
Started May 19 02:29:34 PM PDT 24
Finished May 19 02:29:47 PM PDT 24
Peak memory 248748 kb
Host smart-0526a339-aca3-4e4a-afb5-5a2f2836b7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25805
33374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2580533374
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.104572437
Short name T52
Test name
Test status
Simulation time 269397844 ps
CPU time 9.22 seconds
Started May 19 02:29:34 PM PDT 24
Finished May 19 02:29:44 PM PDT 24
Peak memory 248712 kb
Host smart-58cc2fd0-bbf3-4572-82d2-82b54b7db626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
2437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.104572437
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.818600992
Short name T420
Test name
Test status
Simulation time 700112103 ps
CPU time 18.71 seconds
Started May 19 02:29:37 PM PDT 24
Finished May 19 02:29:56 PM PDT 24
Peak memory 248760 kb
Host smart-2d60f37c-ccf8-48bd-b2e9-eb8f92e8c67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81860
0992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.818600992
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1565257611
Short name T566
Test name
Test status
Simulation time 84902799960 ps
CPU time 1542.77 seconds
Started May 19 02:29:45 PM PDT 24
Finished May 19 02:55:29 PM PDT 24
Peak memory 297468 kb
Host smart-d3eb0e28-50f1-41ff-9d96-28a1eeed9cf1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565257611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1565257611
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2852152332
Short name T201
Test name
Test status
Simulation time 174862058528 ps
CPU time 5860.36 seconds
Started May 19 02:29:45 PM PDT 24
Finished May 19 04:07:27 PM PDT 24
Peak memory 348068 kb
Host smart-8b00cace-2307-4a98-a653-14b3df502792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852152332 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2852152332
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2049414941
Short name T214
Test name
Test status
Simulation time 12742528 ps
CPU time 2.8 seconds
Started May 19 02:29:50 PM PDT 24
Finished May 19 02:29:53 PM PDT 24
Peak memory 248916 kb
Host smart-a77573a3-9971-40ed-8f41-f1b4d7fc6146
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2049414941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2049414941
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3312199958
Short name T700
Test name
Test status
Simulation time 25968295384 ps
CPU time 1326.67 seconds
Started May 19 02:29:46 PM PDT 24
Finished May 19 02:51:54 PM PDT 24
Peak memory 273612 kb
Host smart-9a7f7b14-5d44-47a9-9515-38eda0633f78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312199958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3312199958
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1307623574
Short name T506
Test name
Test status
Simulation time 817458136 ps
CPU time 19.24 seconds
Started May 19 02:29:50 PM PDT 24
Finished May 19 02:30:10 PM PDT 24
Peak memory 248736 kb
Host smart-ed8f36af-f846-4771-935f-43a40eb78535
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1307623574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1307623574
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4096465559
Short name T592
Test name
Test status
Simulation time 2666514536 ps
CPU time 127.26 seconds
Started May 19 02:29:45 PM PDT 24
Finished May 19 02:31:53 PM PDT 24
Peak memory 256924 kb
Host smart-e5369f7d-8f21-4476-a8a3-a1fa68f96505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40964
65559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4096465559
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1594110888
Short name T649
Test name
Test status
Simulation time 429027296 ps
CPU time 20.61 seconds
Started May 19 02:29:45 PM PDT 24
Finished May 19 02:30:06 PM PDT 24
Peak memory 248784 kb
Host smart-444d3370-fd59-4b6a-8629-920e44af25ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15941
10888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1594110888
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1875231736
Short name T328
Test name
Test status
Simulation time 42683681421 ps
CPU time 1028.6 seconds
Started May 19 02:29:46 PM PDT 24
Finished May 19 02:46:55 PM PDT 24
Peak memory 269300 kb
Host smart-889e2a63-ba69-4800-991c-1e29633ce9c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875231736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1875231736
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2502013007
Short name T579
Test name
Test status
Simulation time 116551206651 ps
CPU time 3382.12 seconds
Started May 19 02:29:44 PM PDT 24
Finished May 19 03:26:08 PM PDT 24
Peak memory 289512 kb
Host smart-d8ea6c62-b5ff-4103-9c57-49fca66adc4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502013007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2502013007
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.664055587
Short name T37
Test name
Test status
Simulation time 858010843 ps
CPU time 39.28 seconds
Started May 19 02:29:46 PM PDT 24
Finished May 19 02:30:27 PM PDT 24
Peak memory 248752 kb
Host smart-ba64863b-7e25-469a-bc89-0016e0ac70e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66405
5587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.664055587
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2497018479
Short name T240
Test name
Test status
Simulation time 2042803949 ps
CPU time 35.19 seconds
Started May 19 02:29:45 PM PDT 24
Finished May 19 02:30:21 PM PDT 24
Peak memory 256340 kb
Host smart-ed031266-37e8-48af-8d21-555f6feb687f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24970
18479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2497018479
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.496542037
Short name T656
Test name
Test status
Simulation time 706508655 ps
CPU time 19.41 seconds
Started May 19 02:29:45 PM PDT 24
Finished May 19 02:30:05 PM PDT 24
Peak memory 248748 kb
Host smart-8706a657-12b8-42f6-860e-0586938e8f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49654
2037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.496542037
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1784904175
Short name T595
Test name
Test status
Simulation time 352463432 ps
CPU time 32.96 seconds
Started May 19 02:29:46 PM PDT 24
Finished May 19 02:30:20 PM PDT 24
Peak memory 248736 kb
Host smart-41d76cf4-c8df-472f-b8fc-ecff0b341e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17849
04175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1784904175
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.222482887
Short name T518
Test name
Test status
Simulation time 207990026 ps
CPU time 7.98 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 02:30:01 PM PDT 24
Peak memory 254216 kb
Host smart-8a7f2d3c-07e1-43dd-b39a-1f1c42fd2d4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222482887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.222482887
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.627006514
Short name T687
Test name
Test status
Simulation time 85766459126 ps
CPU time 2507.89 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 03:11:41 PM PDT 24
Peak memory 273532 kb
Host smart-69196b8e-fbba-4b9d-85bb-c356ae9d5bd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627006514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.627006514
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1544461899
Short name T350
Test name
Test status
Simulation time 3109499537 ps
CPU time 55.77 seconds
Started May 19 02:29:50 PM PDT 24
Finished May 19 02:30:47 PM PDT 24
Peak memory 240596 kb
Host smart-7bf5d6a5-90f3-4e96-b539-c52c87e6cfd2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1544461899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1544461899
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4039499554
Short name T41
Test name
Test status
Simulation time 12333076421 ps
CPU time 197.65 seconds
Started May 19 02:29:53 PM PDT 24
Finished May 19 02:33:11 PM PDT 24
Peak memory 256936 kb
Host smart-57188b9b-acfe-4c1b-b93f-c61d91e8dfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40394
99554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4039499554
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2119435129
Short name T368
Test name
Test status
Simulation time 142384151 ps
CPU time 12.11 seconds
Started May 19 02:30:01 PM PDT 24
Finished May 19 02:30:14 PM PDT 24
Peak memory 248732 kb
Host smart-50431f19-4217-4d0c-a498-8eab2692cf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21194
35129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2119435129
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1689127659
Short name T339
Test name
Test status
Simulation time 50287296079 ps
CPU time 2962.29 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 03:19:15 PM PDT 24
Peak memory 288696 kb
Host smart-146992d7-18ad-436f-bf85-f7d2aded7aee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689127659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1689127659
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2415598596
Short name T655
Test name
Test status
Simulation time 6334881556 ps
CPU time 721.09 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 02:41:54 PM PDT 24
Peak memory 273340 kb
Host smart-99275cef-3356-4de2-b962-c9bb9e8c8f42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415598596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2415598596
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3005127448
Short name T600
Test name
Test status
Simulation time 11092585565 ps
CPU time 105.29 seconds
Started May 19 02:29:51 PM PDT 24
Finished May 19 02:31:37 PM PDT 24
Peak memory 252788 kb
Host smart-06c4609e-56d3-406c-8b54-e841f21d17a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005127448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3005127448
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.34134352
Short name T525
Test name
Test status
Simulation time 2853952321 ps
CPU time 45.22 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 02:30:38 PM PDT 24
Peak memory 257024 kb
Host smart-23d1a1f4-d2ae-48a7-9ab6-5f4466c0914e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34134
352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.34134352
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3544067720
Short name T509
Test name
Test status
Simulation time 3575773327 ps
CPU time 50.14 seconds
Started May 19 02:29:50 PM PDT 24
Finished May 19 02:30:41 PM PDT 24
Peak memory 255584 kb
Host smart-8e495ff8-3c38-4135-abc9-ab590add3f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35440
67720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3544067720
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.766910229
Short name T253
Test name
Test status
Simulation time 2723096843 ps
CPU time 45.63 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 02:30:39 PM PDT 24
Peak memory 247932 kb
Host smart-d221e5c0-c457-40f4-9ae2-28657fa2136f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76691
0229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.766910229
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1612805256
Short name T418
Test name
Test status
Simulation time 2585360430 ps
CPU time 55.05 seconds
Started May 19 02:29:52 PM PDT 24
Finished May 19 02:30:48 PM PDT 24
Peak memory 255596 kb
Host smart-7a909ae6-3b53-48c4-ae84-551a834fdbf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128
05256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1612805256
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2307306071
Short name T662
Test name
Test status
Simulation time 146610799534 ps
CPU time 2309.42 seconds
Started May 19 02:29:51 PM PDT 24
Finished May 19 03:08:22 PM PDT 24
Peak memory 281720 kb
Host smart-a06d98d8-e2df-4b30-a58b-85d912ba7294
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307306071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2307306071
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3433418267
Short name T207
Test name
Test status
Simulation time 31089170 ps
CPU time 3.15 seconds
Started May 19 02:30:01 PM PDT 24
Finished May 19 02:30:05 PM PDT 24
Peak memory 248904 kb
Host smart-6f49d7ad-4904-4945-a410-51b1c94b27dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3433418267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3433418267
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2646147741
Short name T597
Test name
Test status
Simulation time 27784132662 ps
CPU time 1588.64 seconds
Started May 19 02:29:56 PM PDT 24
Finished May 19 02:56:26 PM PDT 24
Peak memory 273440 kb
Host smart-161a0c8d-4b62-4955-bca3-5b095883a79f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646147741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2646147741
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1996389127
Short name T698
Test name
Test status
Simulation time 946351525 ps
CPU time 13.48 seconds
Started May 19 02:29:55 PM PDT 24
Finished May 19 02:30:09 PM PDT 24
Peak memory 240568 kb
Host smart-0f480f25-a68b-4702-8898-9e1bf10f49cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1996389127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1996389127
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.972228320
Short name T467
Test name
Test status
Simulation time 648744523 ps
CPU time 40.85 seconds
Started May 19 02:29:57 PM PDT 24
Finished May 19 02:30:39 PM PDT 24
Peak memory 255680 kb
Host smart-df8ea680-d282-496d-a2f9-0091b93a0d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97222
8320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.972228320
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2976746269
Short name T532
Test name
Test status
Simulation time 853643563 ps
CPU time 21.06 seconds
Started May 19 02:30:01 PM PDT 24
Finished May 19 02:30:23 PM PDT 24
Peak memory 256184 kb
Host smart-911a8be6-5b5b-4900-a48c-288866240802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
46269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2976746269
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1452461360
Short name T277
Test name
Test status
Simulation time 46485912589 ps
CPU time 1554.71 seconds
Started May 19 02:29:55 PM PDT 24
Finished May 19 02:55:51 PM PDT 24
Peak memory 289048 kb
Host smart-f9881560-f573-44c9-9122-192604b797c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452461360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1452461360
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3503401977
Short name T456
Test name
Test status
Simulation time 6298681041 ps
CPU time 775.9 seconds
Started May 19 02:30:01 PM PDT 24
Finished May 19 02:42:57 PM PDT 24
Peak memory 273564 kb
Host smart-dda5aaeb-6fc6-40cc-8bc7-86d2ba424c1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503401977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3503401977
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4243603421
Short name T311
Test name
Test status
Simulation time 18307561977 ps
CPU time 194.62 seconds
Started May 19 02:29:56 PM PDT 24
Finished May 19 02:33:11 PM PDT 24
Peak memory 248076 kb
Host smart-228a5084-98f0-4fb5-81c9-fa1ae0dc6fd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243603421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4243603421
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.810998697
Short name T581
Test name
Test status
Simulation time 1751703407 ps
CPU time 29.92 seconds
Started May 19 02:29:57 PM PDT 24
Finished May 19 02:30:28 PM PDT 24
Peak memory 248764 kb
Host smart-805e27b8-ff7f-44cf-a47d-d4d7dd97cbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81099
8697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.810998697
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2559253534
Short name T80
Test name
Test status
Simulation time 8732965312 ps
CPU time 39.66 seconds
Started May 19 02:30:00 PM PDT 24
Finished May 19 02:30:40 PM PDT 24
Peak memory 256972 kb
Host smart-d786f731-423f-4548-80ce-c3d19e8d4714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25592
53534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2559253534
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1748918374
Short name T637
Test name
Test status
Simulation time 3832225702 ps
CPU time 56.58 seconds
Started May 19 02:29:57 PM PDT 24
Finished May 19 02:30:54 PM PDT 24
Peak memory 255720 kb
Host smart-ab19a64c-ae7c-4212-a32c-7c885028c4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489
18374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1748918374
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2023145369
Short name T356
Test name
Test status
Simulation time 210977218 ps
CPU time 21.39 seconds
Started May 19 02:29:56 PM PDT 24
Finished May 19 02:30:18 PM PDT 24
Peak memory 256920 kb
Host smart-a4eee719-dc9a-40fd-98d7-e41bfbb07afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20231
45369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2023145369
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2820495465
Short name T555
Test name
Test status
Simulation time 11901493859 ps
CPU time 678.76 seconds
Started May 19 02:30:01 PM PDT 24
Finished May 19 02:41:21 PM PDT 24
Peak memory 257168 kb
Host smart-b15f4acd-7bb6-4c45-9c5b-6bb675e8ca40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820495465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2820495465
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3626746946
Short name T267
Test name
Test status
Simulation time 21476043328 ps
CPU time 2493.61 seconds
Started May 19 02:30:03 PM PDT 24
Finished May 19 03:11:37 PM PDT 24
Peak memory 305240 kb
Host smart-4ea69f36-5a01-4937-a364-fcd6cf9b28c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626746946 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3626746946
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3557498198
Short name T220
Test name
Test status
Simulation time 88656316 ps
CPU time 3.88 seconds
Started May 19 02:30:05 PM PDT 24
Finished May 19 02:30:10 PM PDT 24
Peak memory 248916 kb
Host smart-f3ec14b3-0c7b-4c96-8ae5-111c1348e9e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3557498198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3557498198
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1228265729
Short name T559
Test name
Test status
Simulation time 40766223538 ps
CPU time 2632.6 seconds
Started May 19 02:30:03 PM PDT 24
Finished May 19 03:13:57 PM PDT 24
Peak memory 289728 kb
Host smart-675c4132-56a4-4a92-a043-faf378952677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228265729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1228265729
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3308555668
Short name T563
Test name
Test status
Simulation time 4769588492 ps
CPU time 55.93 seconds
Started May 19 02:30:05 PM PDT 24
Finished May 19 02:31:02 PM PDT 24
Peak memory 240548 kb
Host smart-991d6324-6000-4bcb-a5e5-dcecc1f7aa03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3308555668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3308555668
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3802083586
Short name T118
Test name
Test status
Simulation time 1702841484 ps
CPU time 127.81 seconds
Started May 19 02:30:02 PM PDT 24
Finished May 19 02:32:11 PM PDT 24
Peak memory 256772 kb
Host smart-f256de97-09b3-4a4f-884d-1f202f2f678d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
83586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3802083586
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1256869652
Short name T33
Test name
Test status
Simulation time 727422956 ps
CPU time 16.51 seconds
Started May 19 02:30:00 PM PDT 24
Finished May 19 02:30:17 PM PDT 24
Peak memory 248856 kb
Host smart-2ca12894-fa35-49f1-8267-711eb5129bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12568
69652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1256869652
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1575310303
Short name T301
Test name
Test status
Simulation time 21595282148 ps
CPU time 883.68 seconds
Started May 19 02:30:05 PM PDT 24
Finished May 19 02:44:49 PM PDT 24
Peak memory 272536 kb
Host smart-8ede39bc-7ae3-4169-8f0f-7adbf39cf0b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575310303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1575310303
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.418913305
Short name T29
Test name
Test status
Simulation time 35954855204 ps
CPU time 2553.19 seconds
Started May 19 02:30:06 PM PDT 24
Finished May 19 03:12:40 PM PDT 24
Peak memory 289232 kb
Host smart-b2c8acf7-b65d-46db-9ef9-1c1db3fec09a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418913305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.418913305
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2067827693
Short name T319
Test name
Test status
Simulation time 13607623718 ps
CPU time 553.62 seconds
Started May 19 02:30:03 PM PDT 24
Finished May 19 02:39:17 PM PDT 24
Peak memory 247296 kb
Host smart-08e2af30-43d9-455a-98b5-5f1cee8791d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067827693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2067827693
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1770139163
Short name T359
Test name
Test status
Simulation time 669616768 ps
CPU time 17.77 seconds
Started May 19 02:30:02 PM PDT 24
Finished May 19 02:30:20 PM PDT 24
Peak memory 248760 kb
Host smart-12311824-7c01-45c4-9e8f-abbacdea7a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17701
39163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1770139163
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3000572222
Short name T58
Test name
Test status
Simulation time 198350136 ps
CPU time 21.7 seconds
Started May 19 02:30:03 PM PDT 24
Finished May 19 02:30:25 PM PDT 24
Peak memory 247488 kb
Host smart-c8f5b459-c479-4682-9bff-bdebaeac25d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30005
72222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3000572222
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1825272466
Short name T20
Test name
Test status
Simulation time 479323739 ps
CPU time 28.55 seconds
Started May 19 02:30:03 PM PDT 24
Finished May 19 02:30:32 PM PDT 24
Peak memory 247596 kb
Host smart-4dbb084f-4a37-430d-9d98-aad5964ab5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18252
72466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1825272466
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3067487389
Short name T676
Test name
Test status
Simulation time 251984033 ps
CPU time 16.04 seconds
Started May 19 02:30:00 PM PDT 24
Finished May 19 02:30:17 PM PDT 24
Peak memory 248748 kb
Host smart-a0bd312d-438e-4576-af1a-cd26bbebaf5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30674
87389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3067487389
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1922150386
Short name T489
Test name
Test status
Simulation time 4330770785 ps
CPU time 289.56 seconds
Started May 19 02:30:09 PM PDT 24
Finished May 19 02:34:58 PM PDT 24
Peak memory 256600 kb
Host smart-9346becf-f653-42a5-aa45-b526a2c781a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922150386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1922150386
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4130209110
Short name T213
Test name
Test status
Simulation time 34877948 ps
CPU time 2.41 seconds
Started May 19 02:30:17 PM PDT 24
Finished May 19 02:30:20 PM PDT 24
Peak memory 248888 kb
Host smart-12f7735b-a245-4176-91c6-a6755d49dfba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4130209110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4130209110
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4028555011
Short name T27
Test name
Test status
Simulation time 154192969015 ps
CPU time 2600.31 seconds
Started May 19 02:30:13 PM PDT 24
Finished May 19 03:13:34 PM PDT 24
Peak memory 289720 kb
Host smart-9359e587-86c2-4e28-aec0-0797a1b225e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028555011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4028555011
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3564617569
Short name T468
Test name
Test status
Simulation time 227526832 ps
CPU time 7.9 seconds
Started May 19 02:30:15 PM PDT 24
Finished May 19 02:30:23 PM PDT 24
Peak memory 240568 kb
Host smart-3b2c0983-d659-4e67-bcc3-61cdcc29a37e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3564617569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3564617569
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1430632628
Short name T46
Test name
Test status
Simulation time 1630673899 ps
CPU time 140.27 seconds
Started May 19 02:30:13 PM PDT 24
Finished May 19 02:32:34 PM PDT 24
Peak memory 256936 kb
Host smart-cc445f45-5c8e-40f5-aa29-6b079c539b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14306
32628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1430632628
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1643475696
Short name T496
Test name
Test status
Simulation time 159009025 ps
CPU time 7.07 seconds
Started May 19 02:30:24 PM PDT 24
Finished May 19 02:30:31 PM PDT 24
Peak memory 254188 kb
Host smart-b7ecfad4-00a8-48bf-957b-cba373b7a400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16434
75696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1643475696
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4148604138
Short name T276
Test name
Test status
Simulation time 37897289407 ps
CPU time 1272.76 seconds
Started May 19 02:30:18 PM PDT 24
Finished May 19 02:51:31 PM PDT 24
Peak memory 273408 kb
Host smart-8189bf85-98b2-42fd-b9b4-adde16492e32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148604138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4148604138
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1503882769
Short name T575
Test name
Test status
Simulation time 678947695 ps
CPU time 14.84 seconds
Started May 19 02:30:11 PM PDT 24
Finished May 19 02:30:26 PM PDT 24
Peak memory 248736 kb
Host smart-de6a5136-aca7-402e-9cc1-efdbdc1d6dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15038
82769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1503882769
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.230204462
Short name T604
Test name
Test status
Simulation time 379880113 ps
CPU time 21.69 seconds
Started May 19 02:30:12 PM PDT 24
Finished May 19 02:30:34 PM PDT 24
Peak memory 255000 kb
Host smart-fb3286d9-695b-40ca-9c52-6765a2e6c8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
4462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.230204462
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.946001098
Short name T389
Test name
Test status
Simulation time 76491533 ps
CPU time 6.08 seconds
Started May 19 02:30:06 PM PDT 24
Finished May 19 02:30:13 PM PDT 24
Peak memory 248760 kb
Host smart-033625b3-8440-4e02-9182-476aaa71598f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94600
1098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.946001098
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3836614185
Short name T87
Test name
Test status
Simulation time 597329668 ps
CPU time 31.46 seconds
Started May 19 02:30:18 PM PDT 24
Finished May 19 02:30:50 PM PDT 24
Peak memory 256908 kb
Host smart-4aa77999-eaa0-4140-b6a0-0e064636b223
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836614185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3836614185
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3885299834
Short name T102
Test name
Test status
Simulation time 14297696031 ps
CPU time 1059.06 seconds
Started May 19 02:30:18 PM PDT 24
Finished May 19 02:47:58 PM PDT 24
Peak memory 270296 kb
Host smart-36c03b14-d78f-48fa-8a84-c77f56df97ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885299834 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3885299834
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3445092534
Short name T216
Test name
Test status
Simulation time 14978951 ps
CPU time 2.38 seconds
Started May 19 02:28:45 PM PDT 24
Finished May 19 02:28:48 PM PDT 24
Peak memory 248924 kb
Host smart-a0affcf2-a912-4649-b10b-16d54febc90a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3445092534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3445092534
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2098396631
Short name T487
Test name
Test status
Simulation time 25041876079 ps
CPU time 1601.5 seconds
Started May 19 02:28:54 PM PDT 24
Finished May 19 02:55:37 PM PDT 24
Peak memory 265252 kb
Host smart-456a707b-af7a-4aae-b49f-8069cff2a55c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098396631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2098396631
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1278576146
Short name T232
Test name
Test status
Simulation time 180951405 ps
CPU time 10.6 seconds
Started May 19 02:28:47 PM PDT 24
Finished May 19 02:28:58 PM PDT 24
Peak memory 248804 kb
Host smart-d65ad1a9-9c84-4778-8166-46951b2e4d34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1278576146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1278576146
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2784416645
Short name T69
Test name
Test status
Simulation time 5602714794 ps
CPU time 91.22 seconds
Started May 19 02:28:44 PM PDT 24
Finished May 19 02:30:16 PM PDT 24
Peak memory 256664 kb
Host smart-d044d11c-ad82-47e0-9f34-5504f63cddbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27844
16645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2784416645
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2344645816
Short name T406
Test name
Test status
Simulation time 1133590249 ps
CPU time 53.51 seconds
Started May 19 02:28:43 PM PDT 24
Finished May 19 02:29:38 PM PDT 24
Peak memory 255520 kb
Host smart-25d8720d-0187-425c-ba33-9bea6a3524a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23446
45816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2344645816
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.180044530
Short name T598
Test name
Test status
Simulation time 17695806551 ps
CPU time 1672.02 seconds
Started May 19 02:28:45 PM PDT 24
Finished May 19 02:56:38 PM PDT 24
Peak memory 289080 kb
Host smart-205079a8-995b-497f-af7f-a3efbdfaba10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180044530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.180044530
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3657773036
Short name T244
Test name
Test status
Simulation time 136419672870 ps
CPU time 2581.43 seconds
Started May 19 02:28:44 PM PDT 24
Finished May 19 03:11:46 PM PDT 24
Peak memory 289812 kb
Host smart-123f3704-0d51-4f6d-963a-2d515c6e04b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657773036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3657773036
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.806964690
Short name T315
Test name
Test status
Simulation time 9743102199 ps
CPU time 424.37 seconds
Started May 19 02:28:45 PM PDT 24
Finished May 19 02:35:50 PM PDT 24
Peak memory 248224 kb
Host smart-8cb520b8-63c1-4180-9536-c3832f82e407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806964690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.806964690
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2306079061
Short name T682
Test name
Test status
Simulation time 2715611596 ps
CPU time 25.59 seconds
Started May 19 02:28:44 PM PDT 24
Finished May 19 02:29:10 PM PDT 24
Peak memory 248892 kb
Host smart-4dfba742-c044-4041-874c-ff0f4201b891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23060
79061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2306079061
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1767826696
Short name T701
Test name
Test status
Simulation time 717015621 ps
CPU time 16.6 seconds
Started May 19 02:28:44 PM PDT 24
Finished May 19 02:29:01 PM PDT 24
Peak memory 255924 kb
Host smart-cf1766bc-5574-4d59-be50-a63e7309893d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17678
26696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1767826696
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.352835049
Short name T11
Test name
Test status
Simulation time 980398938 ps
CPU time 23.74 seconds
Started May 19 02:28:45 PM PDT 24
Finished May 19 02:29:09 PM PDT 24
Peak memory 278788 kb
Host smart-45bc12af-b7b1-485e-97a8-05953829204f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=352835049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.352835049
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1324537708
Short name T492
Test name
Test status
Simulation time 194721967 ps
CPU time 11.86 seconds
Started May 19 02:28:43 PM PDT 24
Finished May 19 02:28:55 PM PDT 24
Peak memory 252924 kb
Host smart-9578f70d-4b47-4baf-a66c-792c07baa6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13245
37708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1324537708
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1595679280
Short name T379
Test name
Test status
Simulation time 434141007 ps
CPU time 38.74 seconds
Started May 19 02:28:45 PM PDT 24
Finished May 19 02:29:25 PM PDT 24
Peak memory 248764 kb
Host smart-17734ba2-824c-4d1b-9edd-cbe6199382aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15956
79280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1595679280
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1761960556
Short name T5
Test name
Test status
Simulation time 26406488468 ps
CPU time 1932.89 seconds
Started May 19 02:28:46 PM PDT 24
Finished May 19 03:00:59 PM PDT 24
Peak memory 289320 kb
Host smart-67e261b4-b3b6-4711-86e7-a4afa8c6e764
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761960556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1761960556
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.338755795
Short name T248
Test name
Test status
Simulation time 1656163402 ps
CPU time 115.47 seconds
Started May 19 02:28:44 PM PDT 24
Finished May 19 02:30:40 PM PDT 24
Peak memory 268944 kb
Host smart-60b82eb1-a961-4bb2-8f00-fb340761da5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338755795 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.338755795
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2406927613
Short name T106
Test name
Test status
Simulation time 66521752071 ps
CPU time 2021.68 seconds
Started May 19 02:30:21 PM PDT 24
Finished May 19 03:04:04 PM PDT 24
Peak memory 273412 kb
Host smart-d368ae42-54e5-4cce-a94f-6982ea1437aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406927613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2406927613
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1712022829
Short name T511
Test name
Test status
Simulation time 4191314952 ps
CPU time 118.45 seconds
Started May 19 02:30:17 PM PDT 24
Finished May 19 02:32:16 PM PDT 24
Peak memory 248808 kb
Host smart-374f1ae7-afc7-427b-9ea9-6e7f17c4b4a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17120
22829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1712022829
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3950462959
Short name T397
Test name
Test status
Simulation time 3778865923 ps
CPU time 25.5 seconds
Started May 19 02:30:16 PM PDT 24
Finished May 19 02:30:43 PM PDT 24
Peak memory 248800 kb
Host smart-07cfb93c-cb8c-4ab1-82fb-1cc9560f41f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39504
62959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3950462959
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.684304964
Short name T188
Test name
Test status
Simulation time 99872046177 ps
CPU time 1410.43 seconds
Started May 19 02:30:23 PM PDT 24
Finished May 19 02:53:54 PM PDT 24
Peak memory 272720 kb
Host smart-3753dc17-498b-4a26-a43f-a65b3a8b70f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684304964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.684304964
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3946577501
Short name T48
Test name
Test status
Simulation time 31674298258 ps
CPU time 2378.69 seconds
Started May 19 02:30:24 PM PDT 24
Finished May 19 03:10:03 PM PDT 24
Peak memory 281084 kb
Host smart-e3f6f25e-19bf-4a54-9375-09c7c247ec98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946577501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3946577501
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4233322461
Short name T302
Test name
Test status
Simulation time 7138486374 ps
CPU time 290.27 seconds
Started May 19 02:30:21 PM PDT 24
Finished May 19 02:35:12 PM PDT 24
Peak memory 247152 kb
Host smart-ee1edcfb-8d42-40e3-b793-6ff84495380a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233322461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4233322461
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1120193867
Short name T430
Test name
Test status
Simulation time 4887589710 ps
CPU time 60.37 seconds
Started May 19 02:30:16 PM PDT 24
Finished May 19 02:31:18 PM PDT 24
Peak memory 248824 kb
Host smart-40a4b987-4e45-4b49-84e9-cac08d3056d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11201
93867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1120193867
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.675990489
Short name T472
Test name
Test status
Simulation time 267635538 ps
CPU time 6.26 seconds
Started May 19 02:30:15 PM PDT 24
Finished May 19 02:30:22 PM PDT 24
Peak memory 247648 kb
Host smart-ca3266b6-0c76-4767-8e0d-3a8ce52ff07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67599
0489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.675990489
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2415898240
Short name T652
Test name
Test status
Simulation time 418646290 ps
CPU time 26.71 seconds
Started May 19 02:30:23 PM PDT 24
Finished May 19 02:30:50 PM PDT 24
Peak memory 256424 kb
Host smart-b477ba71-1938-4e83-be45-0046f7763e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24158
98240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2415898240
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3906606740
Short name T667
Test name
Test status
Simulation time 539154256 ps
CPU time 39.73 seconds
Started May 19 02:30:17 PM PDT 24
Finished May 19 02:30:58 PM PDT 24
Peak memory 255952 kb
Host smart-c634dfb0-2e10-4675-873d-ef372abb17d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39066
06740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3906606740
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.200759769
Short name T91
Test name
Test status
Simulation time 35282886644 ps
CPU time 2133.61 seconds
Started May 19 02:30:22 PM PDT 24
Finished May 19 03:05:56 PM PDT 24
Peak memory 289808 kb
Host smart-33d9e0c1-1afd-4e78-837e-aa89741e60f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200759769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.200759769
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4008555133
Short name T224
Test name
Test status
Simulation time 4951789399 ps
CPU time 282.25 seconds
Started May 19 02:30:30 PM PDT 24
Finished May 19 02:35:13 PM PDT 24
Peak memory 250888 kb
Host smart-7473ad6e-b3b6-49a0-897c-862b25a7203c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40085
55133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4008555133
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3041620974
Short name T482
Test name
Test status
Simulation time 2463635236 ps
CPU time 35.62 seconds
Started May 19 02:30:26 PM PDT 24
Finished May 19 02:31:02 PM PDT 24
Peak memory 257004 kb
Host smart-ea6b88c6-bdef-4c46-922b-bc413e31a1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30416
20974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3041620974
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1316195483
Short name T289
Test name
Test status
Simulation time 20364073213 ps
CPU time 893.78 seconds
Started May 19 02:30:26 PM PDT 24
Finished May 19 02:45:21 PM PDT 24
Peak memory 269336 kb
Host smart-89099706-f7a3-409b-8afa-2e5b924b9bc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316195483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1316195483
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1893216455
Short name T588
Test name
Test status
Simulation time 18549076194 ps
CPU time 1817.51 seconds
Started May 19 02:30:30 PM PDT 24
Finished May 19 03:00:48 PM PDT 24
Peak memory 289408 kb
Host smart-8f53d2c4-0a75-4ab3-85ba-faec8693e075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893216455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1893216455
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3992763543
Short name T556
Test name
Test status
Simulation time 10093028395 ps
CPU time 186.24 seconds
Started May 19 02:30:30 PM PDT 24
Finished May 19 02:33:37 PM PDT 24
Peak memory 247092 kb
Host smart-cf7737b3-d320-4473-817b-6e5ab50df40e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992763543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3992763543
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3972383732
Short name T504
Test name
Test status
Simulation time 1184113483 ps
CPU time 47.07 seconds
Started May 19 02:30:22 PM PDT 24
Finished May 19 02:31:09 PM PDT 24
Peak memory 248760 kb
Host smart-f2478937-f14b-48e9-91c0-8b76d417c825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39723
83732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3972383732
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2343056751
Short name T521
Test name
Test status
Simulation time 834103434 ps
CPU time 8.5 seconds
Started May 19 02:30:24 PM PDT 24
Finished May 19 02:30:33 PM PDT 24
Peak memory 247316 kb
Host smart-671bdafa-39ec-4ae1-aad8-4b6293ad0901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
56751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2343056751
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2612734988
Short name T43
Test name
Test status
Simulation time 627808701 ps
CPU time 21.51 seconds
Started May 19 02:30:28 PM PDT 24
Finished May 19 02:30:50 PM PDT 24
Peak memory 247424 kb
Host smart-b3572a44-5311-44a2-991a-83894ec8f991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26127
34988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2612734988
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.552641986
Short name T684
Test name
Test status
Simulation time 242376333 ps
CPU time 26.89 seconds
Started May 19 02:30:22 PM PDT 24
Finished May 19 02:30:50 PM PDT 24
Peak memory 248748 kb
Host smart-05dc46f7-aed1-405a-8546-62fe2eba964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55264
1986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.552641986
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3663367661
Short name T631
Test name
Test status
Simulation time 48397815313 ps
CPU time 3145.57 seconds
Started May 19 02:30:26 PM PDT 24
Finished May 19 03:22:52 PM PDT 24
Peak memory 322684 kb
Host smart-644e8468-2556-43ae-817b-18bc5373b38b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663367661 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3663367661
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1343689572
Short name T703
Test name
Test status
Simulation time 26889897568 ps
CPU time 1404.81 seconds
Started May 19 02:30:33 PM PDT 24
Finished May 19 02:53:58 PM PDT 24
Peak memory 288004 kb
Host smart-54cebad1-62de-46eb-8667-c0225bc16f23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343689572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1343689572
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.4127181793
Short name T234
Test name
Test status
Simulation time 1550005690 ps
CPU time 89.48 seconds
Started May 19 02:30:33 PM PDT 24
Finished May 19 02:32:03 PM PDT 24
Peak memory 249760 kb
Host smart-4296c4ae-3e61-4c3c-9152-a3fbca51ad84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41271
81793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.4127181793
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.178750406
Short name T75
Test name
Test status
Simulation time 1090463151 ps
CPU time 58.69 seconds
Started May 19 02:30:33 PM PDT 24
Finished May 19 02:31:32 PM PDT 24
Peak memory 248912 kb
Host smart-6168d9bd-a1fa-40ac-9d8c-bad5d9837499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
0406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.178750406
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1643564355
Short name T333
Test name
Test status
Simulation time 54651556212 ps
CPU time 1401.23 seconds
Started May 19 02:30:32 PM PDT 24
Finished May 19 02:53:54 PM PDT 24
Peak memory 287780 kb
Host smart-a1b0ecd5-c4b9-484d-a22d-f341743b2d41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643564355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1643564355
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3254471733
Short name T369
Test name
Test status
Simulation time 723205417987 ps
CPU time 2200 seconds
Started May 19 02:30:36 PM PDT 24
Finished May 19 03:07:17 PM PDT 24
Peak memory 289160 kb
Host smart-b0bc0f76-3f40-4309-b6dd-e5d18daa77f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254471733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3254471733
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.436338724
Short name T609
Test name
Test status
Simulation time 997216217 ps
CPU time 32.84 seconds
Started May 19 02:30:31 PM PDT 24
Finished May 19 02:31:04 PM PDT 24
Peak memory 248752 kb
Host smart-3e06c7c7-5c57-42c9-9347-32d29bde60c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43633
8724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.436338724
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1357231359
Short name T362
Test name
Test status
Simulation time 3210537160 ps
CPU time 53.01 seconds
Started May 19 02:30:26 PM PDT 24
Finished May 19 02:31:20 PM PDT 24
Peak memory 256112 kb
Host smart-75e59266-455f-4a7d-8786-1c854822bf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
31359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1357231359
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4111811080
Short name T704
Test name
Test status
Simulation time 575219369 ps
CPU time 18.27 seconds
Started May 19 02:30:33 PM PDT 24
Finished May 19 02:30:52 PM PDT 24
Peak memory 247476 kb
Host smart-8e081315-3515-4bd5-98b5-743b1085e47e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41118
11080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4111811080
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3867933698
Short name T385
Test name
Test status
Simulation time 5089172095 ps
CPU time 47.3 seconds
Started May 19 02:30:30 PM PDT 24
Finished May 19 02:31:18 PM PDT 24
Peak memory 248840 kb
Host smart-4ff58063-298d-4ca6-9367-3dd3290fb38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38679
33698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3867933698
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.442996480
Short name T272
Test name
Test status
Simulation time 82655702551 ps
CPU time 2816.27 seconds
Started May 19 02:30:41 PM PDT 24
Finished May 19 03:17:38 PM PDT 24
Peak memory 298004 kb
Host smart-8ac4b717-f7ae-4f02-98d3-047f57a6cbd8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442996480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.442996480
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4131428429
Short name T458
Test name
Test status
Simulation time 149950056393 ps
CPU time 2836.24 seconds
Started May 19 02:30:36 PM PDT 24
Finished May 19 03:17:53 PM PDT 24
Peak memory 298080 kb
Host smart-f381db19-d3ea-4f2e-93bc-c98d76505ca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131428429 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4131428429
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1858742628
Short name T414
Test name
Test status
Simulation time 90036663427 ps
CPU time 2797.37 seconds
Started May 19 02:30:42 PM PDT 24
Finished May 19 03:17:21 PM PDT 24
Peak memory 289300 kb
Host smart-47e0b375-3813-4107-94da-fae0d7820bf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858742628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1858742628
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2059682294
Short name T187
Test name
Test status
Simulation time 16304191191 ps
CPU time 247.93 seconds
Started May 19 02:30:35 PM PDT 24
Finished May 19 02:34:44 PM PDT 24
Peak memory 256972 kb
Host smart-0d3cc283-0bb1-49f2-a1a0-0d06291e3725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596
82294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2059682294
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3518001053
Short name T78
Test name
Test status
Simulation time 148380185 ps
CPU time 8.39 seconds
Started May 19 02:30:37 PM PDT 24
Finished May 19 02:30:46 PM PDT 24
Peak memory 251528 kb
Host smart-a407d812-8170-46b3-8b20-6b652bcc8423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
01053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3518001053
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1387118401
Short name T331
Test name
Test status
Simulation time 19083378591 ps
CPU time 1504 seconds
Started May 19 02:30:42 PM PDT 24
Finished May 19 02:55:46 PM PDT 24
Peak memory 289140 kb
Host smart-a6658e16-2399-4de5-b8d8-19466195dbbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387118401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1387118401
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.751059084
Short name T541
Test name
Test status
Simulation time 19013398661 ps
CPU time 1055.38 seconds
Started May 19 02:30:44 PM PDT 24
Finished May 19 02:48:19 PM PDT 24
Peak memory 265188 kb
Host smart-555dab68-20fa-4bc1-a07e-495df25a802c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751059084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.751059084
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3017074164
Short name T533
Test name
Test status
Simulation time 20072098120 ps
CPU time 423.81 seconds
Started May 19 02:30:42 PM PDT 24
Finished May 19 02:37:46 PM PDT 24
Peak memory 248236 kb
Host smart-ffafeb72-954a-4764-a6a3-4a5a3df51c5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017074164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3017074164
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3277075805
Short name T594
Test name
Test status
Simulation time 136611084 ps
CPU time 5.33 seconds
Started May 19 02:30:37 PM PDT 24
Finished May 19 02:30:43 PM PDT 24
Peak memory 240564 kb
Host smart-da74ae16-cca3-4f19-9915-f9d71ff91e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770
75805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3277075805
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1055374475
Short name T648
Test name
Test status
Simulation time 2110712428 ps
CPU time 14.13 seconds
Started May 19 02:30:36 PM PDT 24
Finished May 19 02:30:51 PM PDT 24
Peak memory 248776 kb
Host smart-49c2c6f3-1c67-455b-9f98-c72d9d27c31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10553
74475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1055374475
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3755460699
Short name T254
Test name
Test status
Simulation time 1264198717 ps
CPU time 23.4 seconds
Started May 19 02:30:41 PM PDT 24
Finished May 19 02:31:05 PM PDT 24
Peak memory 255668 kb
Host smart-5bc6387d-f999-4935-9b4b-c2153357e40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37554
60699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3755460699
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2456044064
Short name T702
Test name
Test status
Simulation time 69856086 ps
CPU time 5.87 seconds
Started May 19 02:30:36 PM PDT 24
Finished May 19 02:30:43 PM PDT 24
Peak memory 248712 kb
Host smart-1242cd02-977c-4589-a42b-b622c908f242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24560
44064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2456044064
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3649537436
Short name T629
Test name
Test status
Simulation time 29254153853 ps
CPU time 955.12 seconds
Started May 19 02:30:43 PM PDT 24
Finished May 19 02:46:39 PM PDT 24
Peak memory 271216 kb
Host smart-b8dacb4c-3df6-470f-9a73-a227d99a117d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649537436 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3649537436
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1247531482
Short name T223
Test name
Test status
Simulation time 16769578523 ps
CPU time 1487.23 seconds
Started May 19 02:30:47 PM PDT 24
Finished May 19 02:55:35 PM PDT 24
Peak memory 287284 kb
Host smart-195e4d36-3bbb-41bb-88ef-6b7930a8dbd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247531482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1247531482
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3680090911
Short name T227
Test name
Test status
Simulation time 11325649093 ps
CPU time 317.89 seconds
Started May 19 02:30:48 PM PDT 24
Finished May 19 02:36:07 PM PDT 24
Peak memory 256944 kb
Host smart-670d71bf-08bc-43df-985d-0733355cfd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
90911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3680090911
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1118132860
Short name T561
Test name
Test status
Simulation time 881044395 ps
CPU time 52.2 seconds
Started May 19 02:30:46 PM PDT 24
Finished May 19 02:31:39 PM PDT 24
Peak memory 256944 kb
Host smart-a2766f77-d139-4ccc-8810-b2eb2dee4be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11181
32860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1118132860
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3058370549
Short name T247
Test name
Test status
Simulation time 110688498701 ps
CPU time 3132.53 seconds
Started May 19 02:30:52 PM PDT 24
Finished May 19 03:23:06 PM PDT 24
Peak memory 289704 kb
Host smart-79a02280-b606-4207-b43f-7c7968b4a8f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058370549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3058370549
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2193187199
Short name T296
Test name
Test status
Simulation time 8774101306 ps
CPU time 92.68 seconds
Started May 19 02:30:47 PM PDT 24
Finished May 19 02:32:20 PM PDT 24
Peak memory 252828 kb
Host smart-01da9e55-b491-480f-a61f-e3cd1ed2344c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193187199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2193187199
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1339524376
Short name T354
Test name
Test status
Simulation time 1012511182 ps
CPU time 23.78 seconds
Started May 19 02:30:48 PM PDT 24
Finished May 19 02:31:12 PM PDT 24
Peak memory 255432 kb
Host smart-5cf62f87-9022-40fc-b652-ea1a8d8421fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
24376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1339524376
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2352008461
Short name T586
Test name
Test status
Simulation time 1278525196 ps
CPU time 29.73 seconds
Started May 19 02:30:48 PM PDT 24
Finished May 19 02:31:18 PM PDT 24
Peak memory 255552 kb
Host smart-b2e46151-a6ab-4b0a-a7f0-69a686780507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23520
08461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2352008461
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1446847173
Short name T630
Test name
Test status
Simulation time 408313138 ps
CPU time 30.1 seconds
Started May 19 02:30:48 PM PDT 24
Finished May 19 02:31:18 PM PDT 24
Peak memory 249160 kb
Host smart-3f4e48fb-8111-41cb-be70-b0769ecfce1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14468
47173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1446847173
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.809943622
Short name T186
Test name
Test status
Simulation time 246045936 ps
CPU time 31.36 seconds
Started May 19 02:30:48 PM PDT 24
Finished May 19 02:31:20 PM PDT 24
Peak memory 256044 kb
Host smart-9ae46395-9fbf-475d-a8b8-a8e09c292545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80994
3622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.809943622
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4212960832
Short name T61
Test name
Test status
Simulation time 77417713345 ps
CPU time 2498.36 seconds
Started May 19 02:30:52 PM PDT 24
Finished May 19 03:12:32 PM PDT 24
Peak memory 281628 kb
Host smart-46ed0440-ae46-46ef-b681-38f22c1ffa75
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212960832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4212960832
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1831534980
Short name T546
Test name
Test status
Simulation time 10532855636 ps
CPU time 911.75 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 02:46:13 PM PDT 24
Peak memory 267336 kb
Host smart-81f328b9-288d-4e78-bdd4-d34064fc0b93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831534980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1831534980
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4104799819
Short name T640
Test name
Test status
Simulation time 11303048094 ps
CPU time 308.91 seconds
Started May 19 02:30:56 PM PDT 24
Finished May 19 02:36:05 PM PDT 24
Peak memory 256976 kb
Host smart-5c6af844-b878-47b0-8a27-cb107853a183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41047
99819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4104799819
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1587031620
Short name T606
Test name
Test status
Simulation time 904105754 ps
CPU time 14.54 seconds
Started May 19 02:30:52 PM PDT 24
Finished May 19 02:31:07 PM PDT 24
Peak memory 252616 kb
Host smart-c10df209-4c30-4a95-9e55-e5e40bf77503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
31620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1587031620
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3277518572
Short name T699
Test name
Test status
Simulation time 269252254614 ps
CPU time 1462.87 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 02:55:24 PM PDT 24
Peak memory 288148 kb
Host smart-5a37544d-e0a1-48c4-bff9-b39c25fe9861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277518572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3277518572
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3520758821
Short name T305
Test name
Test status
Simulation time 13692424954 ps
CPU time 305.64 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 02:36:07 PM PDT 24
Peak memory 256272 kb
Host smart-0b8c9453-177e-4807-ad3e-dfdc832c5a4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520758821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3520758821
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2591693658
Short name T355
Test name
Test status
Simulation time 633539386 ps
CPU time 35.16 seconds
Started May 19 02:30:52 PM PDT 24
Finished May 19 02:31:28 PM PDT 24
Peak memory 256956 kb
Host smart-f21c5b07-23cd-43da-9530-f9629900daf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25916
93658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2591693658
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1231089139
Short name T651
Test name
Test status
Simulation time 229741878 ps
CPU time 18.83 seconds
Started May 19 02:30:52 PM PDT 24
Finished May 19 02:31:11 PM PDT 24
Peak memory 248772 kb
Host smart-61f3fced-76d9-4703-ae35-4cabc3cab9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12310
89139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1231089139
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2218660231
Short name T81
Test name
Test status
Simulation time 693814374 ps
CPU time 44.2 seconds
Started May 19 02:30:57 PM PDT 24
Finished May 19 02:31:41 PM PDT 24
Peak memory 249028 kb
Host smart-1c936405-a857-420d-b28e-dd24c84985a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186
60231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2218660231
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1362634364
Short name T560
Test name
Test status
Simulation time 365839246 ps
CPU time 25.09 seconds
Started May 19 02:30:54 PM PDT 24
Finished May 19 02:31:19 PM PDT 24
Peak memory 248732 kb
Host smart-bd426131-d5ea-47ff-89c0-f9408ac1df01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
34364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1362634364
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3225369697
Short name T262
Test name
Test status
Simulation time 311384893746 ps
CPU time 7701.26 seconds
Started May 19 02:30:58 PM PDT 24
Finished May 19 04:39:21 PM PDT 24
Peak memory 354824 kb
Host smart-56333d94-e2c4-4236-aceb-0a83118a5f96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225369697 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3225369697
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3458889323
Short name T599
Test name
Test status
Simulation time 37460468925 ps
CPU time 2046.45 seconds
Started May 19 02:31:13 PM PDT 24
Finished May 19 03:05:20 PM PDT 24
Peak memory 272396 kb
Host smart-233276ed-27c8-4e09-902e-c8676dc2a218
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458889323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3458889323
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2261924101
Short name T477
Test name
Test status
Simulation time 7717253858 ps
CPU time 117.6 seconds
Started May 19 02:31:05 PM PDT 24
Finished May 19 02:33:03 PM PDT 24
Peak memory 257068 kb
Host smart-369f00a0-1225-4086-9ca9-32a6aa5fcb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22619
24101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2261924101
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4211016668
Short name T688
Test name
Test status
Simulation time 1163742661 ps
CPU time 26.41 seconds
Started May 19 02:31:02 PM PDT 24
Finished May 19 02:31:29 PM PDT 24
Peak memory 248756 kb
Host smart-9bb25653-1383-458a-9d29-254416576b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
16668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4211016668
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2424612462
Short name T323
Test name
Test status
Simulation time 15151739096 ps
CPU time 1299.76 seconds
Started May 19 02:31:12 PM PDT 24
Finished May 19 02:52:52 PM PDT 24
Peak memory 287616 kb
Host smart-18572f2c-ffd0-4235-b33f-af3622caa137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424612462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2424612462
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.813992201
Short name T90
Test name
Test status
Simulation time 23255934554 ps
CPU time 733.32 seconds
Started May 19 02:31:13 PM PDT 24
Finished May 19 02:43:27 PM PDT 24
Peak memory 273296 kb
Host smart-f6ce3d8d-983c-4074-a59d-2252c2540f89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813992201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.813992201
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3136808863
Short name T298
Test name
Test status
Simulation time 11322511075 ps
CPU time 234.21 seconds
Started May 19 02:31:14 PM PDT 24
Finished May 19 02:35:09 PM PDT 24
Peak memory 248200 kb
Host smart-effa937d-2256-410c-88ae-a6e098f76e00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136808863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3136808863
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2025407701
Short name T21
Test name
Test status
Simulation time 118415102 ps
CPU time 11.02 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 02:31:12 PM PDT 24
Peak memory 248880 kb
Host smart-c685113f-0f84-4621-84c9-9c0d7603e985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20254
07701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2025407701
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2844552737
Short name T407
Test name
Test status
Simulation time 9217799299 ps
CPU time 58.32 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 02:31:59 PM PDT 24
Peak memory 248904 kb
Host smart-b2f9b315-82b3-4041-b79e-7daa0bc72ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28445
52737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2844552737
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2474768996
Short name T425
Test name
Test status
Simulation time 512142740 ps
CPU time 12.33 seconds
Started May 19 02:31:03 PM PDT 24
Finished May 19 02:31:16 PM PDT 24
Peak memory 248788 kb
Host smart-e091f42f-7330-405f-8f5b-f2ee2a8b2368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24747
68996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2474768996
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2224285166
Short name T470
Test name
Test status
Simulation time 2233367224 ps
CPU time 14.41 seconds
Started May 19 02:31:00 PM PDT 24
Finished May 19 02:31:15 PM PDT 24
Peak memory 255952 kb
Host smart-06869620-793c-488f-bad9-6b6db3131734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22242
85166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2224285166
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3142033860
Short name T268
Test name
Test status
Simulation time 12684652680 ps
CPU time 263.1 seconds
Started May 19 02:31:14 PM PDT 24
Finished May 19 02:35:38 PM PDT 24
Peak memory 256996 kb
Host smart-59d81ae1-6ea3-4f9c-943f-adeb13caeffc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142033860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3142033860
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.4116689131
Short name T60
Test name
Test status
Simulation time 122297474230 ps
CPU time 8159.18 seconds
Started May 19 02:31:12 PM PDT 24
Finished May 19 04:47:12 PM PDT 24
Peak memory 349708 kb
Host smart-17d2a512-6c2d-41a4-bfd9-811cefde9424
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116689131 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.4116689131
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2837868159
Short name T634
Test name
Test status
Simulation time 22501944517 ps
CPU time 1092.65 seconds
Started May 19 02:31:15 PM PDT 24
Finished May 19 02:49:28 PM PDT 24
Peak memory 284936 kb
Host smart-cb285f67-6e2c-46b2-aee2-38288740305f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837868159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2837868159
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2401971464
Short name T45
Test name
Test status
Simulation time 1431941351 ps
CPU time 76.69 seconds
Started May 19 02:31:14 PM PDT 24
Finished May 19 02:32:32 PM PDT 24
Peak memory 256832 kb
Host smart-40cf6815-0dfd-4a5f-843a-96b378977fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24019
71464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2401971464
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1202253052
Short name T476
Test name
Test status
Simulation time 673850150 ps
CPU time 15.09 seconds
Started May 19 02:31:16 PM PDT 24
Finished May 19 02:31:32 PM PDT 24
Peak memory 255648 kb
Host smart-d9ea561a-cbeb-4e77-a376-b504c31bd248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12022
53052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1202253052
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3634417723
Short name T230
Test name
Test status
Simulation time 20707509077 ps
CPU time 993.07 seconds
Started May 19 02:31:17 PM PDT 24
Finished May 19 02:47:51 PM PDT 24
Peak memory 272932 kb
Host smart-a4931d7d-56d8-4655-b1e0-1556bae94aeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634417723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3634417723
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1422969552
Short name T493
Test name
Test status
Simulation time 1280365297 ps
CPU time 37.85 seconds
Started May 19 02:31:16 PM PDT 24
Finished May 19 02:31:54 PM PDT 24
Peak memory 248804 kb
Host smart-c510c4b7-6421-424e-933c-b1be1de25634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14229
69552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1422969552
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.172512561
Short name T543
Test name
Test status
Simulation time 402340434 ps
CPU time 32.8 seconds
Started May 19 02:31:18 PM PDT 24
Finished May 19 02:31:51 PM PDT 24
Peak memory 248976 kb
Host smart-4c3a317e-c539-48ee-a92f-631148ef8b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17251
2561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.172512561
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2908118595
Short name T82
Test name
Test status
Simulation time 3113354251 ps
CPU time 59.53 seconds
Started May 19 02:31:16 PM PDT 24
Finished May 19 02:32:16 PM PDT 24
Peak memory 255568 kb
Host smart-b6f24f04-5d66-4a8f-b694-5eb100816c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081
18595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2908118595
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.67394717
Short name T568
Test name
Test status
Simulation time 471618977 ps
CPU time 27.74 seconds
Started May 19 02:31:14 PM PDT 24
Finished May 19 02:31:43 PM PDT 24
Peak memory 248920 kb
Host smart-b23c288f-33f9-43ff-ad35-dbd43b4ae031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67394
717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.67394717
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2337529652
Short name T96
Test name
Test status
Simulation time 200753247205 ps
CPU time 3061.59 seconds
Started May 19 02:31:23 PM PDT 24
Finished May 19 03:22:25 PM PDT 24
Peak memory 297904 kb
Host smart-2e0f6ca7-e8fd-45c4-a56c-8c574afd59aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337529652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2337529652
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2360049313
Short name T542
Test name
Test status
Simulation time 38560278273 ps
CPU time 2104.43 seconds
Started May 19 02:31:22 PM PDT 24
Finished May 19 03:06:27 PM PDT 24
Peak memory 288864 kb
Host smart-7a1494a6-7e85-4915-a725-4134bf711a13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360049313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2360049313
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.977464748
Short name T576
Test name
Test status
Simulation time 22202518924 ps
CPU time 85.75 seconds
Started May 19 02:31:21 PM PDT 24
Finished May 19 02:32:48 PM PDT 24
Peak memory 255448 kb
Host smart-f51abcfb-6f11-4db6-9505-c7ded68c840e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97746
4748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.977464748
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3015406435
Short name T613
Test name
Test status
Simulation time 2494410299 ps
CPU time 52.72 seconds
Started May 19 02:31:21 PM PDT 24
Finished May 19 02:32:15 PM PDT 24
Peak memory 256088 kb
Host smart-cd799896-54bd-4965-9ea3-df7aae27c25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30154
06435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3015406435
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1849140295
Short name T570
Test name
Test status
Simulation time 49493677501 ps
CPU time 1013.1 seconds
Started May 19 02:31:26 PM PDT 24
Finished May 19 02:48:20 PM PDT 24
Peak memory 272836 kb
Host smart-c2bece6c-ac5d-421e-89fe-be64be7bec4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849140295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1849140295
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.8354179
Short name T582
Test name
Test status
Simulation time 5676588015 ps
CPU time 224.31 seconds
Started May 19 02:31:26 PM PDT 24
Finished May 19 02:35:12 PM PDT 24
Peak memory 254556 kb
Host smart-bc24928d-f792-48a2-98f3-9c047fdadbbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8354179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.8354179
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2248396021
Short name T670
Test name
Test status
Simulation time 42649190 ps
CPU time 4.46 seconds
Started May 19 02:31:22 PM PDT 24
Finished May 19 02:31:27 PM PDT 24
Peak memory 240572 kb
Host smart-b2e110b7-83d5-45a3-91a4-6e2c6ee14127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22483
96021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2248396021
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2552725569
Short name T393
Test name
Test status
Simulation time 8083380417 ps
CPU time 78.39 seconds
Started May 19 02:31:21 PM PDT 24
Finished May 19 02:32:40 PM PDT 24
Peak memory 249404 kb
Host smart-7d85402c-6800-4ff0-9375-82eea4c01afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
25569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2552725569
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3744746289
Short name T183
Test name
Test status
Simulation time 435743135 ps
CPU time 26.81 seconds
Started May 19 02:31:22 PM PDT 24
Finished May 19 02:31:49 PM PDT 24
Peak memory 255924 kb
Host smart-369cf8c8-4c51-40c2-9425-756a939031f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37447
46289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3744746289
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2084913188
Short name T603
Test name
Test status
Simulation time 18251369885 ps
CPU time 1687.23 seconds
Started May 19 02:31:28 PM PDT 24
Finished May 19 02:59:36 PM PDT 24
Peak memory 289008 kb
Host smart-93e7baab-429c-40e9-b426-479b3fce8d8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084913188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2084913188
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.374927113
Short name T593
Test name
Test status
Simulation time 43281062689 ps
CPU time 2641.06 seconds
Started May 19 02:31:31 PM PDT 24
Finished May 19 03:15:33 PM PDT 24
Peak memory 289340 kb
Host smart-fe0e11f1-3ccb-4567-b689-64591e4e02f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374927113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.374927113
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2865584255
Short name T238
Test name
Test status
Simulation time 633396066 ps
CPU time 50.88 seconds
Started May 19 02:31:29 PM PDT 24
Finished May 19 02:32:20 PM PDT 24
Peak memory 248744 kb
Host smart-3188b77e-4190-4337-a47a-2f5b563a4ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28655
84255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2865584255
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1061787115
Short name T380
Test name
Test status
Simulation time 785306290 ps
CPU time 43.67 seconds
Started May 19 02:31:26 PM PDT 24
Finished May 19 02:32:11 PM PDT 24
Peak memory 255336 kb
Host smart-ef433c3c-b968-4e2e-a0d4-234f333a124b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10617
87115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1061787115
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2566870863
Short name T330
Test name
Test status
Simulation time 61560893123 ps
CPU time 1291.03 seconds
Started May 19 02:31:37 PM PDT 24
Finished May 19 02:53:09 PM PDT 24
Peak memory 282088 kb
Host smart-1e833a81-b61d-406b-9803-fcf49798eaa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566870863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2566870863
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2205437372
Short name T481
Test name
Test status
Simulation time 19783609165 ps
CPU time 694.4 seconds
Started May 19 02:31:38 PM PDT 24
Finished May 19 02:43:14 PM PDT 24
Peak memory 273148 kb
Host smart-acf625d4-cbee-4be7-b1fb-0e29a0bd09e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205437372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2205437372
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3795101228
Short name T317
Test name
Test status
Simulation time 15293532178 ps
CPU time 139.23 seconds
Started May 19 02:31:31 PM PDT 24
Finished May 19 02:33:51 PM PDT 24
Peak memory 248200 kb
Host smart-b525898e-d6a9-445e-ae46-14dc384031ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795101228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3795101228
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3108895950
Short name T51
Test name
Test status
Simulation time 10563609670 ps
CPU time 47.69 seconds
Started May 19 02:31:26 PM PDT 24
Finished May 19 02:32:15 PM PDT 24
Peak memory 248832 kb
Host smart-a2da1a1a-8446-464f-85d3-9e2cc6ae5e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31088
95950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3108895950
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.177081139
Short name T618
Test name
Test status
Simulation time 379243503 ps
CPU time 23.45 seconds
Started May 19 02:31:25 PM PDT 24
Finished May 19 02:31:49 PM PDT 24
Peak memory 247456 kb
Host smart-c2013398-7649-41e8-8401-2f71b9f7c77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17708
1139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.177081139
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1529344408
Short name T434
Test name
Test status
Simulation time 1009181641 ps
CPU time 12.98 seconds
Started May 19 02:31:26 PM PDT 24
Finished May 19 02:31:40 PM PDT 24
Peak memory 248756 kb
Host smart-9a5f7341-037c-4b28-99ee-9570ba61ede9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15293
44408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1529344408
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.682674178
Short name T271
Test name
Test status
Simulation time 65165894140 ps
CPU time 1690.31 seconds
Started May 19 02:31:39 PM PDT 24
Finished May 19 02:59:50 PM PDT 24
Peak memory 289336 kb
Host smart-72361cf1-ea1e-47ea-9887-2efe0c9f8f63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682674178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.682674178
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1753167988
Short name T221
Test name
Test status
Simulation time 39454095 ps
CPU time 4.4 seconds
Started May 19 02:28:48 PM PDT 24
Finished May 19 02:28:53 PM PDT 24
Peak memory 248932 kb
Host smart-575e7116-1ca9-410d-86f0-7abc1031af7c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1753167988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1753167988
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.331615932
Short name T433
Test name
Test status
Simulation time 11669425286 ps
CPU time 1077.7 seconds
Started May 19 02:28:49 PM PDT 24
Finished May 19 02:46:48 PM PDT 24
Peak memory 288704 kb
Host smart-c956af6e-b55f-4fe4-84a7-339f9d08b41a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331615932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.331615932
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2509654288
Short name T394
Test name
Test status
Simulation time 824938979 ps
CPU time 35.65 seconds
Started May 19 02:28:48 PM PDT 24
Finished May 19 02:29:25 PM PDT 24
Peak memory 240552 kb
Host smart-62404051-3b84-461c-92d2-74522521f303
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2509654288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2509654288
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3882818557
Short name T675
Test name
Test status
Simulation time 364517597 ps
CPU time 29.08 seconds
Started May 19 02:28:50 PM PDT 24
Finished May 19 02:29:19 PM PDT 24
Peak memory 256840 kb
Host smart-ebcbf10e-76b1-493a-84ab-141f0a2b51fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38828
18557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3882818557
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3145909485
Short name T259
Test name
Test status
Simulation time 1961671837 ps
CPU time 63.83 seconds
Started May 19 02:28:49 PM PDT 24
Finished May 19 02:29:54 PM PDT 24
Peak memory 255352 kb
Host smart-08d137cd-beba-4bf6-8a6e-ab8aaba1806c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459
09485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3145909485
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.192027605
Short name T243
Test name
Test status
Simulation time 104943464657 ps
CPU time 1341.23 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:51:17 PM PDT 24
Peak memory 288832 kb
Host smart-302fb090-2696-4eac-a746-86bbaf72ccb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192027605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.192027605
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3415739690
Short name T686
Test name
Test status
Simulation time 10618301458 ps
CPU time 972.67 seconds
Started May 19 02:28:50 PM PDT 24
Finished May 19 02:45:03 PM PDT 24
Peak memory 288028 kb
Host smart-3ce75d63-db7a-4edf-8877-45f5d7e45b35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415739690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3415739690
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.409247200
Short name T707
Test name
Test status
Simulation time 16021082539 ps
CPU time 166.22 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:31:42 PM PDT 24
Peak memory 254620 kb
Host smart-bb9f5e50-da2a-4143-9081-6eee6a2dc50e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409247200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.409247200
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.610444400
Short name T526
Test name
Test status
Simulation time 304570768 ps
CPU time 6.4 seconds
Started May 19 02:28:48 PM PDT 24
Finished May 19 02:28:55 PM PDT 24
Peak memory 256912 kb
Host smart-7ad5e1a1-90e4-4383-9641-38c23d24f0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61044
4400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.610444400
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1535901764
Short name T449
Test name
Test status
Simulation time 381886115 ps
CPU time 25.96 seconds
Started May 19 02:28:44 PM PDT 24
Finished May 19 02:29:11 PM PDT 24
Peak memory 248680 kb
Host smart-39522bc0-c1be-441e-8e6c-d3e557c493be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15359
01764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1535901764
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.644144773
Short name T34
Test name
Test status
Simulation time 342109966 ps
CPU time 11.32 seconds
Started May 19 02:28:49 PM PDT 24
Finished May 19 02:29:01 PM PDT 24
Peak memory 270156 kb
Host smart-efaa4fbb-85a0-4655-8245-52f704893422
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=644144773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.644144773
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1852325890
Short name T404
Test name
Test status
Simulation time 3257968545 ps
CPU time 40.35 seconds
Started May 19 02:28:49 PM PDT 24
Finished May 19 02:29:30 PM PDT 24
Peak memory 255580 kb
Host smart-6e7c3ea5-bb26-47f1-beda-dae55fb0fded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18523
25890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1852325890
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4107874116
Short name T392
Test name
Test status
Simulation time 383549716 ps
CPU time 35.83 seconds
Started May 19 02:28:54 PM PDT 24
Finished May 19 02:29:30 PM PDT 24
Peak memory 256040 kb
Host smart-dfaf2456-382e-4f0f-a4fe-c4f40c1d6455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41078
74116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4107874116
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2794832920
Short name T241
Test name
Test status
Simulation time 24659350898 ps
CPU time 371.18 seconds
Started May 19 02:28:50 PM PDT 24
Finished May 19 02:35:02 PM PDT 24
Peak memory 253240 kb
Host smart-c5317d01-f0a4-40af-b146-a5f406a7160f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794832920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2794832920
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2677700396
Short name T558
Test name
Test status
Simulation time 160884916481 ps
CPU time 2045.59 seconds
Started May 19 02:31:42 PM PDT 24
Finished May 19 03:05:49 PM PDT 24
Peak memory 273420 kb
Host smart-4f07b299-9e90-4a2f-8095-15e7dadcba73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677700396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2677700396
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3202201519
Short name T189
Test name
Test status
Simulation time 7368034990 ps
CPU time 120.71 seconds
Started May 19 02:31:43 PM PDT 24
Finished May 19 02:33:45 PM PDT 24
Peak memory 256860 kb
Host smart-b0cdcbec-f7e3-4578-986b-9394c2a62086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
01519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3202201519
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2712818680
Short name T375
Test name
Test status
Simulation time 2134581053 ps
CPU time 38.45 seconds
Started May 19 02:31:38 PM PDT 24
Finished May 19 02:32:17 PM PDT 24
Peak memory 248836 kb
Host smart-55cbd3c7-cdff-4434-bbcf-ee0b791d3c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27128
18680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2712818680
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1449028740
Short name T95
Test name
Test status
Simulation time 23601526750 ps
CPU time 1048.66 seconds
Started May 19 02:31:43 PM PDT 24
Finished May 19 02:49:13 PM PDT 24
Peak memory 273356 kb
Host smart-f7f6205b-961a-471d-a389-f90e3b0559a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449028740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1449028740
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.177352127
Short name T72
Test name
Test status
Simulation time 111145944938 ps
CPU time 1709.35 seconds
Started May 19 02:31:43 PM PDT 24
Finished May 19 03:00:13 PM PDT 24
Peak memory 282516 kb
Host smart-92e77456-1242-4462-8232-08dbe9e5ab73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177352127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.177352127
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2797238608
Short name T647
Test name
Test status
Simulation time 9107986457 ps
CPU time 357.75 seconds
Started May 19 02:31:42 PM PDT 24
Finished May 19 02:37:41 PM PDT 24
Peak memory 248120 kb
Host smart-72aae525-1a4a-42d9-9ebf-2ef6ff735044
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797238608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2797238608
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3928883364
Short name T683
Test name
Test status
Simulation time 3211667710 ps
CPU time 52.6 seconds
Started May 19 02:31:37 PM PDT 24
Finished May 19 02:32:31 PM PDT 24
Peak memory 248820 kb
Host smart-daa62933-d48c-4a5f-b562-6812842ddd2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
83364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3928883364
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1646541141
Short name T466
Test name
Test status
Simulation time 240274527 ps
CPU time 8.88 seconds
Started May 19 02:31:38 PM PDT 24
Finished May 19 02:31:48 PM PDT 24
Peak memory 248784 kb
Host smart-f8a98dcd-8e2d-4603-a616-c7e0c6fcfa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16465
41141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1646541141
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3492222865
Short name T257
Test name
Test status
Simulation time 2077842168 ps
CPU time 33.41 seconds
Started May 19 02:31:44 PM PDT 24
Finished May 19 02:32:18 PM PDT 24
Peak memory 254844 kb
Host smart-94898db7-6269-4891-8333-3c1d75b1eb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34922
22865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3492222865
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1960696191
Short name T197
Test name
Test status
Simulation time 331392566 ps
CPU time 28 seconds
Started May 19 02:31:37 PM PDT 24
Finished May 19 02:32:06 PM PDT 24
Peak memory 248740 kb
Host smart-b16c0751-0ec2-476e-954a-005b7023ccd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19606
96191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1960696191
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.985356758
Short name T62
Test name
Test status
Simulation time 254634712883 ps
CPU time 3075.14 seconds
Started May 19 02:31:44 PM PDT 24
Finished May 19 03:23:00 PM PDT 24
Peak memory 314468 kb
Host smart-d0a37e63-ff6c-449c-a410-d89e098cbf17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985356758 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.985356758
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2780326544
Short name T89
Test name
Test status
Simulation time 25634506419 ps
CPU time 1151.18 seconds
Started May 19 02:31:52 PM PDT 24
Finished May 19 02:51:04 PM PDT 24
Peak memory 288184 kb
Host smart-73beb24f-b617-4e45-b89e-bf4e78b25b2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780326544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2780326544
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2670921808
Short name T422
Test name
Test status
Simulation time 33324297643 ps
CPU time 165 seconds
Started May 19 02:31:46 PM PDT 24
Finished May 19 02:34:31 PM PDT 24
Peak memory 256968 kb
Host smart-7df97916-f367-4dea-aca5-7dfb96239d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
21808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2670921808
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3698413947
Short name T93
Test name
Test status
Simulation time 512045802 ps
CPU time 35.51 seconds
Started May 19 02:31:47 PM PDT 24
Finished May 19 02:32:23 PM PDT 24
Peak memory 248788 kb
Host smart-5ef80d0c-1370-4b53-82b9-1970e8ed9ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36984
13947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3698413947
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1363104416
Short name T382
Test name
Test status
Simulation time 38615423405 ps
CPU time 2713.97 seconds
Started May 19 02:31:52 PM PDT 24
Finished May 19 03:17:07 PM PDT 24
Peak memory 289260 kb
Host smart-66b68671-710a-44ba-a2bf-5055f381b8a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363104416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1363104416
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1618342388
Short name T324
Test name
Test status
Simulation time 23557921630 ps
CPU time 255.92 seconds
Started May 19 02:31:51 PM PDT 24
Finished May 19 02:36:08 PM PDT 24
Peak memory 247964 kb
Host smart-555718f2-513a-4ad1-aac9-ed1beb53151b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618342388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1618342388
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1855222720
Short name T363
Test name
Test status
Simulation time 293596464 ps
CPU time 10.35 seconds
Started May 19 02:31:50 PM PDT 24
Finished May 19 02:32:01 PM PDT 24
Peak memory 248780 kb
Host smart-03cb2012-ebef-489c-877f-1d391820eed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18552
22720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1855222720
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2321330217
Short name T431
Test name
Test status
Simulation time 471362928 ps
CPU time 14.91 seconds
Started May 19 02:31:50 PM PDT 24
Finished May 19 02:32:05 PM PDT 24
Peak memory 253792 kb
Host smart-a218ae5e-1feb-4a74-8a7e-589873a84b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23213
30217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2321330217
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1715089092
Short name T198
Test name
Test status
Simulation time 686866495 ps
CPU time 44.31 seconds
Started May 19 02:31:51 PM PDT 24
Finished May 19 02:32:36 PM PDT 24
Peak memory 248948 kb
Host smart-a8852401-7216-4b30-ab13-71f238ea590b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
89092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1715089092
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1697582359
Short name T619
Test name
Test status
Simulation time 184721105 ps
CPU time 19.48 seconds
Started May 19 02:31:42 PM PDT 24
Finished May 19 02:32:02 PM PDT 24
Peak memory 248728 kb
Host smart-c651eeaa-8b01-49c4-ba6b-176a4e9f35ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975
82359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1697582359
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1789611668
Short name T632
Test name
Test status
Simulation time 15335142219 ps
CPU time 1425.39 seconds
Started May 19 02:31:52 PM PDT 24
Finished May 19 02:55:38 PM PDT 24
Peak memory 288436 kb
Host smart-2fc28544-ade6-4418-bb6f-0e362c720ab7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789611668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1789611668
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3195723459
Short name T239
Test name
Test status
Simulation time 90729146381 ps
CPU time 2669.39 seconds
Started May 19 02:31:57 PM PDT 24
Finished May 19 03:16:27 PM PDT 24
Peak memory 283408 kb
Host smart-55ee29a4-60ad-4832-8675-8d52c81795c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195723459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3195723459
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1451187996
Short name T364
Test name
Test status
Simulation time 51316549414 ps
CPU time 169.75 seconds
Started May 19 02:31:56 PM PDT 24
Finished May 19 02:34:46 PM PDT 24
Peak memory 249232 kb
Host smart-b096f5cc-f073-46f4-b62c-ee02737332cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14511
87996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1451187996
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3196560445
Short name T405
Test name
Test status
Simulation time 466248015 ps
CPU time 8.59 seconds
Started May 19 02:31:53 PM PDT 24
Finished May 19 02:32:02 PM PDT 24
Peak memory 252600 kb
Host smart-6260ac92-7c42-401d-984f-877a93fafcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31965
60445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3196560445
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1084667993
Short name T320
Test name
Test status
Simulation time 69432623746 ps
CPU time 1666.84 seconds
Started May 19 02:32:02 PM PDT 24
Finished May 19 02:59:49 PM PDT 24
Peak memory 272996 kb
Host smart-1d016301-15e5-4d0f-ae75-c23338da7fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084667993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1084667993
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2380242321
Short name T463
Test name
Test status
Simulation time 30661661362 ps
CPU time 920.23 seconds
Started May 19 02:32:03 PM PDT 24
Finished May 19 02:47:23 PM PDT 24
Peak memory 273452 kb
Host smart-f896909f-051f-44de-9770-3bc14efa7400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380242321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2380242321
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2606695323
Short name T199
Test name
Test status
Simulation time 24710966825 ps
CPU time 270.71 seconds
Started May 19 02:31:58 PM PDT 24
Finished May 19 02:36:29 PM PDT 24
Peak memory 247852 kb
Host smart-b2b59056-ce8a-4411-8581-a565b5aeafd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606695323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2606695323
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.873278162
Short name T229
Test name
Test status
Simulation time 1467853056 ps
CPU time 24 seconds
Started May 19 02:31:53 PM PDT 24
Finished May 19 02:32:18 PM PDT 24
Peak memory 248796 kb
Host smart-2c7bc794-f5d9-481d-b85d-357e3cace4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87327
8162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.873278162
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3344344602
Short name T677
Test name
Test status
Simulation time 1640844061 ps
CPU time 48.2 seconds
Started May 19 02:31:54 PM PDT 24
Finished May 19 02:32:43 PM PDT 24
Peak memory 255460 kb
Host smart-5e1ddf92-c284-4ac2-be8b-2e5364ca134a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33443
44602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3344344602
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2894830887
Short name T548
Test name
Test status
Simulation time 657422076 ps
CPU time 5.31 seconds
Started May 19 02:31:58 PM PDT 24
Finished May 19 02:32:04 PM PDT 24
Peak memory 240568 kb
Host smart-c2ff1f47-86c9-4eab-b955-4876165bff11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28948
30887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2894830887
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2979503756
Short name T367
Test name
Test status
Simulation time 440773822 ps
CPU time 28.75 seconds
Started May 19 02:31:54 PM PDT 24
Finished May 19 02:32:24 PM PDT 24
Peak memory 248732 kb
Host smart-1b140700-a015-434e-aa6a-88e2154bf141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29795
03756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2979503756
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.748794854
Short name T100
Test name
Test status
Simulation time 12124302719 ps
CPU time 1445.05 seconds
Started May 19 02:32:03 PM PDT 24
Finished May 19 02:56:08 PM PDT 24
Peak memory 287812 kb
Host smart-3bf3333d-2381-426e-b8d3-19a0b6fcaf05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748794854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.748794854
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.4202179981
Short name T461
Test name
Test status
Simulation time 30297388199 ps
CPU time 3713.67 seconds
Started May 19 02:32:00 PM PDT 24
Finished May 19 03:33:55 PM PDT 24
Peak memory 314080 kb
Host smart-22522b8a-1c8a-4bad-a2ff-1e0bc1499807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202179981 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.4202179981
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3339705141
Short name T275
Test name
Test status
Simulation time 27303506297 ps
CPU time 1333.61 seconds
Started May 19 02:32:08 PM PDT 24
Finished May 19 02:54:22 PM PDT 24
Peak memory 288808 kb
Host smart-923a9800-7e46-412f-9425-261add8c1990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339705141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3339705141
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2209938906
Short name T480
Test name
Test status
Simulation time 1167197091 ps
CPU time 107.55 seconds
Started May 19 02:32:08 PM PDT 24
Finished May 19 02:33:56 PM PDT 24
Peak memory 256700 kb
Host smart-8475e088-def5-41ae-afb4-34794948848d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
38906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2209938906
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2188248298
Short name T623
Test name
Test status
Simulation time 2214538113 ps
CPU time 35.9 seconds
Started May 19 02:32:08 PM PDT 24
Finished May 19 02:32:45 PM PDT 24
Peak memory 255780 kb
Host smart-c1502562-9b95-451a-a9d0-7ba5abb3331c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
48298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2188248298
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2682236713
Short name T674
Test name
Test status
Simulation time 63119835791 ps
CPU time 1878.64 seconds
Started May 19 02:32:13 PM PDT 24
Finished May 19 03:03:32 PM PDT 24
Peak memory 271416 kb
Host smart-4349901d-61fe-4ecf-8c52-a7ce6b0b6ecc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682236713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2682236713
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2084624673
Short name T287
Test name
Test status
Simulation time 40984632761 ps
CPU time 1770.91 seconds
Started May 19 02:32:13 PM PDT 24
Finished May 19 03:01:44 PM PDT 24
Peak memory 288872 kb
Host smart-f1400741-fb63-4f65-9dcd-529e89dbf8c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084624673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2084624673
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1490708027
Short name T565
Test name
Test status
Simulation time 254176726 ps
CPU time 28.45 seconds
Started May 19 02:32:01 PM PDT 24
Finished May 19 02:32:30 PM PDT 24
Peak memory 256044 kb
Host smart-3c73c141-60e3-4847-b451-9404a24c8e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14907
08027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1490708027
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.4178842875
Short name T112
Test name
Test status
Simulation time 525094507 ps
CPU time 32.91 seconds
Started May 19 02:32:07 PM PDT 24
Finished May 19 02:32:40 PM PDT 24
Peak memory 247452 kb
Host smart-35876333-b447-4cd9-b062-7a8ade6031b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41788
42875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.4178842875
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2936471817
Short name T661
Test name
Test status
Simulation time 110889739 ps
CPU time 4.55 seconds
Started May 19 02:32:08 PM PDT 24
Finished May 19 02:32:13 PM PDT 24
Peak memory 239228 kb
Host smart-0895ceaa-d966-4160-92c9-479d5a554e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29364
71817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2936471817
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3999131167
Short name T360
Test name
Test status
Simulation time 5120212527 ps
CPU time 69.24 seconds
Started May 19 02:32:03 PM PDT 24
Finished May 19 02:33:13 PM PDT 24
Peak memory 256324 kb
Host smart-cff40e3b-8dd7-4a0a-a777-a8580d218ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39991
31167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3999131167
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2812961846
Short name T692
Test name
Test status
Simulation time 5349332066 ps
CPU time 153.4 seconds
Started May 19 02:32:12 PM PDT 24
Finished May 19 02:34:46 PM PDT 24
Peak memory 256996 kb
Host smart-1a995b60-4b34-4a97-9854-9fd90da0c98d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812961846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2812961846
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2730057798
Short name T673
Test name
Test status
Simulation time 58091791311 ps
CPU time 1239.16 seconds
Started May 19 02:32:16 PM PDT 24
Finished May 19 02:52:56 PM PDT 24
Peak memory 265224 kb
Host smart-25a0a1f3-a748-49df-ae1b-25855ce07d95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730057798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2730057798
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3723534836
Short name T627
Test name
Test status
Simulation time 1499708496 ps
CPU time 132.32 seconds
Started May 19 02:32:18 PM PDT 24
Finished May 19 02:34:31 PM PDT 24
Peak memory 249960 kb
Host smart-a79bb049-6ebc-4791-a495-cbecbd37a469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235
34836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3723534836
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1876527439
Short name T503
Test name
Test status
Simulation time 1129840043 ps
CPU time 19.28 seconds
Started May 19 02:32:16 PM PDT 24
Finished May 19 02:32:35 PM PDT 24
Peak memory 255580 kb
Host smart-7cefa2ba-9c45-4591-9691-05eeb8dccca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18765
27439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1876527439
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3601810514
Short name T313
Test name
Test status
Simulation time 47153013206 ps
CPU time 3106.82 seconds
Started May 19 02:32:23 PM PDT 24
Finished May 19 03:24:11 PM PDT 24
Peak memory 289080 kb
Host smart-da9350e6-b070-4c9e-93d6-618f9b3f9aa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601810514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3601810514
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1556473577
Short name T547
Test name
Test status
Simulation time 7053279615 ps
CPU time 726.21 seconds
Started May 19 02:32:25 PM PDT 24
Finished May 19 02:44:32 PM PDT 24
Peak memory 272924 kb
Host smart-a72baf22-a340-4236-8c05-34e8c4c97cc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556473577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1556473577
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.24473187
Short name T321
Test name
Test status
Simulation time 25184066124 ps
CPU time 276.5 seconds
Started May 19 02:32:23 PM PDT 24
Finished May 19 02:37:00 PM PDT 24
Peak memory 248172 kb
Host smart-acf93daa-f01b-438f-93fc-c833b914b37e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24473187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.24473187
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2298522621
Short name T42
Test name
Test status
Simulation time 613318368 ps
CPU time 30.96 seconds
Started May 19 02:32:12 PM PDT 24
Finished May 19 02:32:43 PM PDT 24
Peak memory 248704 kb
Host smart-ce94458b-3e1b-40ee-885e-f34d170cfcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
22621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2298522621
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3058278768
Short name T54
Test name
Test status
Simulation time 1328962492 ps
CPU time 19.36 seconds
Started May 19 02:32:12 PM PDT 24
Finished May 19 02:32:32 PM PDT 24
Peak memory 255092 kb
Host smart-41db1ce4-757c-4233-bde3-384acf971fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
78768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3058278768
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3219243800
Short name T413
Test name
Test status
Simulation time 838211819 ps
CPU time 47.09 seconds
Started May 19 02:32:16 PM PDT 24
Finished May 19 02:33:04 PM PDT 24
Peak memory 255644 kb
Host smart-a23ee07d-f22c-4231-bd86-0a168ccec7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
43800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3219243800
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4219126432
Short name T36
Test name
Test status
Simulation time 358880192 ps
CPU time 18.33 seconds
Started May 19 02:32:12 PM PDT 24
Finished May 19 02:32:31 PM PDT 24
Peak memory 256052 kb
Host smart-2939625a-11ba-46c1-805c-5f3b7c653610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42191
26432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4219126432
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.4179974824
Short name T282
Test name
Test status
Simulation time 32279600901 ps
CPU time 1901.08 seconds
Started May 19 02:32:25 PM PDT 24
Finished May 19 03:04:07 PM PDT 24
Peak memory 289580 kb
Host smart-9c6c92ec-61a8-4031-8b1f-3061d4a6630c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179974824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.4179974824
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4209562727
Short name T190
Test name
Test status
Simulation time 34837480272 ps
CPU time 1024.25 seconds
Started May 19 02:32:27 PM PDT 24
Finished May 19 02:49:32 PM PDT 24
Peak memory 272688 kb
Host smart-d545a701-1fc8-4970-8327-d7781ac6a0e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209562727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4209562727
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.238002929
Short name T374
Test name
Test status
Simulation time 3440227411 ps
CPU time 47.98 seconds
Started May 19 02:32:27 PM PDT 24
Finished May 19 02:33:16 PM PDT 24
Peak memory 256760 kb
Host smart-bc029bd5-0798-4c9a-a252-15bc514640b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23800
2929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.238002929
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1201575056
Short name T237
Test name
Test status
Simulation time 321386642 ps
CPU time 26.92 seconds
Started May 19 02:32:27 PM PDT 24
Finished May 19 02:32:54 PM PDT 24
Peak memory 256068 kb
Host smart-36bb00a0-ac9c-4d0d-adb0-4f808a95c493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12015
75056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1201575056
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.53015957
Short name T341
Test name
Test status
Simulation time 30432724701 ps
CPU time 1873.54 seconds
Started May 19 02:32:32 PM PDT 24
Finished May 19 03:03:46 PM PDT 24
Peak memory 273440 kb
Host smart-1c900809-4c2f-4471-ab76-b104f4452bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53015957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.53015957
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2607574898
Short name T612
Test name
Test status
Simulation time 216247714058 ps
CPU time 3287.29 seconds
Started May 19 02:32:32 PM PDT 24
Finished May 19 03:27:20 PM PDT 24
Peak memory 288720 kb
Host smart-c6d03716-993b-4000-b099-b8cbd4b4c6db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607574898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2607574898
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3647913828
Short name T8
Test name
Test status
Simulation time 6671260648 ps
CPU time 225.88 seconds
Started May 19 02:32:26 PM PDT 24
Finished May 19 02:36:13 PM PDT 24
Peak memory 248324 kb
Host smart-9d6bada4-f352-45ab-a69b-81d458a020b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647913828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3647913828
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.65127194
Short name T514
Test name
Test status
Simulation time 529854009 ps
CPU time 6.83 seconds
Started May 19 02:32:22 PM PDT 24
Finished May 19 02:32:30 PM PDT 24
Peak memory 248712 kb
Host smart-9514cff1-c95f-400d-8a9d-74b32f3d1a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65127
194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.65127194
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2015361410
Short name T668
Test name
Test status
Simulation time 2409418979 ps
CPU time 33.16 seconds
Started May 19 02:32:27 PM PDT 24
Finished May 19 02:33:00 PM PDT 24
Peak memory 248800 kb
Host smart-a5541fc9-dc88-4397-8a9a-309dad70a9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
61410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2015361410
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1205750417
Short name T580
Test name
Test status
Simulation time 1173191453 ps
CPU time 36.04 seconds
Started May 19 02:32:25 PM PDT 24
Finished May 19 02:33:01 PM PDT 24
Peak memory 248772 kb
Host smart-6d747be6-d02d-4a0c-a8c8-0d614b53a6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057
50417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1205750417
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2925733079
Short name T269
Test name
Test status
Simulation time 34687980241 ps
CPU time 2309.84 seconds
Started May 19 02:32:33 PM PDT 24
Finished May 19 03:11:03 PM PDT 24
Peak memory 289788 kb
Host smart-5def787d-fef6-456e-907a-c4851618c086
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925733079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2925733079
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2710757409
Short name T545
Test name
Test status
Simulation time 9941196836 ps
CPU time 1027.71 seconds
Started May 19 02:32:33 PM PDT 24
Finished May 19 02:49:41 PM PDT 24
Peak memory 281752 kb
Host smart-a5d9a588-2474-4f92-a655-dd406502769e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710757409 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2710757409
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2270291330
Short name T17
Test name
Test status
Simulation time 9308108461 ps
CPU time 973.02 seconds
Started May 19 02:32:39 PM PDT 24
Finished May 19 02:48:53 PM PDT 24
Peak memory 288896 kb
Host smart-7eea1658-b588-47ed-9263-59c5b6e37106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270291330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2270291330
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3536982970
Short name T19
Test name
Test status
Simulation time 9269474501 ps
CPU time 157.02 seconds
Started May 19 02:32:40 PM PDT 24
Finished May 19 02:35:17 PM PDT 24
Peak memory 256996 kb
Host smart-6353bea8-2421-4677-bb63-67bae5ff6163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35369
82970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3536982970
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3180305420
Short name T70
Test name
Test status
Simulation time 936814183 ps
CPU time 59.26 seconds
Started May 19 02:32:37 PM PDT 24
Finished May 19 02:33:37 PM PDT 24
Peak memory 248980 kb
Host smart-9b72ac5d-8fa0-4329-917f-aaa89a3f240b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31803
05420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3180305420
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3156851328
Short name T591
Test name
Test status
Simulation time 171295672505 ps
CPU time 2639.8 seconds
Started May 19 02:32:36 PM PDT 24
Finished May 19 03:16:37 PM PDT 24
Peak memory 281560 kb
Host smart-e2ab0253-c7bb-444e-a1b9-d5d0397a7d47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156851328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3156851328
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4067346041
Short name T281
Test name
Test status
Simulation time 8509873456 ps
CPU time 189.81 seconds
Started May 19 02:32:38 PM PDT 24
Finished May 19 02:35:48 PM PDT 24
Peak memory 248308 kb
Host smart-117ba396-1bb0-4932-8181-0106394500ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067346041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4067346041
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4261724609
Short name T390
Test name
Test status
Simulation time 224965048 ps
CPU time 16.31 seconds
Started May 19 02:32:37 PM PDT 24
Finished May 19 02:32:54 PM PDT 24
Peak memory 248772 kb
Host smart-2fdd67a0-a64f-47e8-a228-8d350bd05b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42617
24609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4261724609
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3260475092
Short name T39
Test name
Test status
Simulation time 16914619392 ps
CPU time 59.07 seconds
Started May 19 02:32:37 PM PDT 24
Finished May 19 02:33:36 PM PDT 24
Peak memory 255424 kb
Host smart-47a15bdb-22f4-4924-8b7a-540f3fdfdf8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32604
75092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3260475092
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1127758258
Short name T537
Test name
Test status
Simulation time 261472507 ps
CPU time 35.61 seconds
Started May 19 02:32:37 PM PDT 24
Finished May 19 02:33:13 PM PDT 24
Peak memory 248732 kb
Host smart-ffd60bf7-2b8b-4e03-9f82-de1e293bb559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
58258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1127758258
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2703553870
Short name T388
Test name
Test status
Simulation time 817410748 ps
CPU time 53.41 seconds
Started May 19 02:32:37 PM PDT 24
Finished May 19 02:33:31 PM PDT 24
Peak memory 248788 kb
Host smart-28db4824-a7a3-41c0-9d15-b8dfdadeb47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27035
53870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2703553870
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2604788093
Short name T705
Test name
Test status
Simulation time 21366664844 ps
CPU time 2333.51 seconds
Started May 19 02:32:37 PM PDT 24
Finished May 19 03:11:32 PM PDT 24
Peak memory 304608 kb
Host smart-ef1007c1-8a66-4afe-9ddc-8c84bea7fbdc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604788093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2604788093
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1272179056
Short name T283
Test name
Test status
Simulation time 43701498199 ps
CPU time 3304.68 seconds
Started May 19 02:32:42 PM PDT 24
Finished May 19 03:27:47 PM PDT 24
Peak memory 281968 kb
Host smart-2328610a-3607-4585-888d-6cc8cd463f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272179056 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1272179056
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2143997896
Short name T396
Test name
Test status
Simulation time 594886039405 ps
CPU time 2482.53 seconds
Started May 19 02:32:46 PM PDT 24
Finished May 19 03:14:10 PM PDT 24
Peak memory 289148 kb
Host smart-d4cd8c10-cf0f-4407-8bc9-a96fbf08debf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143997896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2143997896
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.985644011
Short name T641
Test name
Test status
Simulation time 5901786251 ps
CPU time 71.23 seconds
Started May 19 02:32:42 PM PDT 24
Finished May 19 02:33:54 PM PDT 24
Peak memory 256876 kb
Host smart-c77b3093-a4f7-41a4-8b5e-93dec73fdb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98564
4011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.985644011
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.452634657
Short name T376
Test name
Test status
Simulation time 1983467367 ps
CPU time 23.27 seconds
Started May 19 02:32:42 PM PDT 24
Finished May 19 02:33:06 PM PDT 24
Peak memory 255368 kb
Host smart-13b65855-9bf6-4ffa-929e-3afcaa4c9dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45263
4657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.452634657
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.620610019
Short name T706
Test name
Test status
Simulation time 9915270583 ps
CPU time 955.07 seconds
Started May 19 02:32:47 PM PDT 24
Finished May 19 02:48:42 PM PDT 24
Peak memory 272380 kb
Host smart-5fc08889-8077-4840-81fe-a78174554863
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620610019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.620610019
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.323797200
Short name T508
Test name
Test status
Simulation time 39007446974 ps
CPU time 835.67 seconds
Started May 19 02:32:48 PM PDT 24
Finished May 19 02:46:44 PM PDT 24
Peak memory 272968 kb
Host smart-32382233-cffa-4c9a-8375-a3f99310d145
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323797200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.323797200
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.578109066
Short name T479
Test name
Test status
Simulation time 4552486922 ps
CPU time 48.64 seconds
Started May 19 02:32:43 PM PDT 24
Finished May 19 02:33:32 PM PDT 24
Peak memory 248836 kb
Host smart-7fbad646-7ff9-4129-a5e2-ecea24aa26cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57810
9066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.578109066
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2794449909
Short name T485
Test name
Test status
Simulation time 75912338 ps
CPU time 8.43 seconds
Started May 19 02:32:43 PM PDT 24
Finished May 19 02:32:52 PM PDT 24
Peak memory 253120 kb
Host smart-126d955f-88f8-4162-a9e2-a6b69673ff38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
49909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2794449909
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1816025891
Short name T263
Test name
Test status
Simulation time 121714544 ps
CPU time 8.52 seconds
Started May 19 02:32:49 PM PDT 24
Finished May 19 02:32:58 PM PDT 24
Peak memory 250288 kb
Host smart-af289bab-da49-474e-b798-97a1f1736e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
25891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1816025891
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.655584095
Short name T636
Test name
Test status
Simulation time 788684687 ps
CPU time 27.39 seconds
Started May 19 02:32:42 PM PDT 24
Finished May 19 02:33:10 PM PDT 24
Peak memory 248756 kb
Host smart-9abd761a-5b54-403d-889e-f9395679f737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65558
4095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.655584095
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3230677512
Short name T114
Test name
Test status
Simulation time 38409692536 ps
CPU time 1808 seconds
Started May 19 02:32:49 PM PDT 24
Finished May 19 03:02:58 PM PDT 24
Peak memory 289544 kb
Host smart-b82fd8cd-5a55-4bc8-898c-21af643ffce6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230677512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3230677512
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2753106779
Short name T265
Test name
Test status
Simulation time 30067545695 ps
CPU time 3284.75 seconds
Started May 19 02:32:47 PM PDT 24
Finished May 19 03:27:33 PM PDT 24
Peak memory 322700 kb
Host smart-f9829048-3947-4490-9770-e8a6d916007c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753106779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2753106779
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3990377628
Short name T370
Test name
Test status
Simulation time 48636186050 ps
CPU time 852.99 seconds
Started May 19 02:32:53 PM PDT 24
Finished May 19 02:47:07 PM PDT 24
Peak memory 273448 kb
Host smart-49c1d082-31e1-4fa9-a952-330ccd85e660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990377628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3990377628
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2505754393
Short name T1
Test name
Test status
Simulation time 3224171364 ps
CPU time 192.16 seconds
Started May 19 02:32:55 PM PDT 24
Finished May 19 02:36:07 PM PDT 24
Peak memory 250464 kb
Host smart-a6ff3762-bfae-40e7-9717-a56d25a5a514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25057
54393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2505754393
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3732259689
Short name T659
Test name
Test status
Simulation time 312194115 ps
CPU time 27.99 seconds
Started May 19 02:32:54 PM PDT 24
Finished May 19 02:33:22 PM PDT 24
Peak memory 255748 kb
Host smart-4fb3fefd-fb76-439f-b0de-f620a3caf963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
59689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3732259689
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2041125959
Short name T340
Test name
Test status
Simulation time 75316244069 ps
CPU time 2374.42 seconds
Started May 19 02:32:57 PM PDT 24
Finished May 19 03:12:32 PM PDT 24
Peak memory 288944 kb
Host smart-512971b6-d3e4-4c4c-b442-942cb31ddadd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041125959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2041125959
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.531803983
Short name T498
Test name
Test status
Simulation time 214049255708 ps
CPU time 2109.27 seconds
Started May 19 02:33:04 PM PDT 24
Finished May 19 03:08:14 PM PDT 24
Peak memory 286336 kb
Host smart-15cbb7af-3fc4-4a0d-b1b0-80d8dd818c32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531803983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.531803983
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2747410862
Short name T318
Test name
Test status
Simulation time 2897160419 ps
CPU time 117.96 seconds
Started May 19 02:32:56 PM PDT 24
Finished May 19 02:34:55 PM PDT 24
Peak memory 248268 kb
Host smart-2a6d7eea-3388-4d20-9a29-369a177636be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747410862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2747410862
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1102110122
Short name T512
Test name
Test status
Simulation time 283478402 ps
CPU time 34.95 seconds
Started May 19 02:32:53 PM PDT 24
Finished May 19 02:33:29 PM PDT 24
Peak memory 248784 kb
Host smart-e4a326d9-689f-4530-995a-231a33f6b3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11021
10122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1102110122
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.896529631
Short name T608
Test name
Test status
Simulation time 425927797 ps
CPU time 13.86 seconds
Started May 19 02:32:54 PM PDT 24
Finished May 19 02:33:08 PM PDT 24
Peak memory 249092 kb
Host smart-4b274836-5786-4837-8776-3fb34cb02ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89652
9631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.896529631
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1535532463
Short name T436
Test name
Test status
Simulation time 179935964 ps
CPU time 4.91 seconds
Started May 19 02:32:53 PM PDT 24
Finished May 19 02:32:59 PM PDT 24
Peak memory 240832 kb
Host smart-62519ceb-b845-4aae-846b-5227910fded1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15355
32463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1535532463
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3375157572
Short name T365
Test name
Test status
Simulation time 960876471 ps
CPU time 22.56 seconds
Started May 19 02:32:47 PM PDT 24
Finished May 19 02:33:10 PM PDT 24
Peak memory 248704 kb
Host smart-3c2e9cfc-a414-4ed8-b334-bd1401de487a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33751
57572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3375157572
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1910969466
Short name T578
Test name
Test status
Simulation time 186836061339 ps
CPU time 2820.93 seconds
Started May 19 02:33:03 PM PDT 24
Finished May 19 03:20:04 PM PDT 24
Peak memory 289620 kb
Host smart-85e993af-5102-430d-ac03-267785cdeb20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910969466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1910969466
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3893962023
Short name T99
Test name
Test status
Simulation time 313533273993 ps
CPU time 6128.53 seconds
Started May 19 02:33:04 PM PDT 24
Finished May 19 04:15:13 PM PDT 24
Peak memory 306244 kb
Host smart-bddc2318-97ae-4e86-b16f-64f567b3be58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893962023 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3893962023
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.63718868
Short name T596
Test name
Test status
Simulation time 71535653571 ps
CPU time 2068.7 seconds
Started May 19 02:33:08 PM PDT 24
Finished May 19 03:07:38 PM PDT 24
Peak memory 287368 kb
Host smart-438136dd-c217-47a9-bcf5-d11594aa9418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63718868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.63718868
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1527383658
Short name T500
Test name
Test status
Simulation time 9644526363 ps
CPU time 98.11 seconds
Started May 19 02:33:08 PM PDT 24
Finished May 19 02:34:47 PM PDT 24
Peak memory 256892 kb
Host smart-2ff4b911-86e5-4cbb-8ed9-982a4b97a0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15273
83658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1527383658
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1955840633
Short name T539
Test name
Test status
Simulation time 542195697 ps
CPU time 34.99 seconds
Started May 19 02:33:10 PM PDT 24
Finished May 19 02:33:45 PM PDT 24
Peak memory 255960 kb
Host smart-a1a3af5f-80be-4cb3-a0ec-4f9022e3b22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19558
40633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1955840633
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1930613774
Short name T314
Test name
Test status
Simulation time 9350691845 ps
CPU time 365.86 seconds
Started May 19 02:33:08 PM PDT 24
Finished May 19 02:39:15 PM PDT 24
Peak memory 248204 kb
Host smart-79b892ea-c624-4cb5-96de-bae3d22d6a82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930613774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1930613774
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1605178786
Short name T646
Test name
Test status
Simulation time 369901657 ps
CPU time 21.81 seconds
Started May 19 02:33:04 PM PDT 24
Finished May 19 02:33:26 PM PDT 24
Peak memory 248780 kb
Host smart-69284dec-bd63-4780-a2d2-b38163ac1b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
78786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1605178786
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1172237563
Short name T501
Test name
Test status
Simulation time 91108776 ps
CPU time 3.03 seconds
Started May 19 02:33:10 PM PDT 24
Finished May 19 02:33:13 PM PDT 24
Peak memory 239124 kb
Host smart-9a8cd5de-9739-4cda-b172-d4b9ab6da529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
37563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1172237563
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3326039132
Short name T635
Test name
Test status
Simulation time 892993852 ps
CPU time 21.86 seconds
Started May 19 02:33:08 PM PDT 24
Finished May 19 02:33:31 PM PDT 24
Peak memory 255684 kb
Host smart-d8021a64-e576-42cd-889b-1b7bd9cb9d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33260
39132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3326039132
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.621618572
Short name T587
Test name
Test status
Simulation time 1310001751 ps
CPU time 32.03 seconds
Started May 19 02:33:06 PM PDT 24
Finished May 19 02:33:39 PM PDT 24
Peak memory 256940 kb
Host smart-55aa578e-130a-4033-9851-ad4b902049a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62161
8572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.621618572
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1075325472
Short name T101
Test name
Test status
Simulation time 45225220959 ps
CPU time 2621.63 seconds
Started May 19 02:33:15 PM PDT 24
Finished May 19 03:16:58 PM PDT 24
Peak memory 287524 kb
Host smart-2c527a69-3c9f-44a7-917a-e296d1dda44c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075325472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1075325472
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1072344095
Short name T538
Test name
Test status
Simulation time 10308900447 ps
CPU time 1411.08 seconds
Started May 19 02:33:12 PM PDT 24
Finished May 19 02:56:44 PM PDT 24
Peak memory 289948 kb
Host smart-097bf73f-3a5f-4b3f-8a65-ddfc0f2e79b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072344095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1072344095
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1951161593
Short name T68
Test name
Test status
Simulation time 50214529 ps
CPU time 2.54 seconds
Started May 19 02:28:48 PM PDT 24
Finished May 19 02:28:51 PM PDT 24
Peak memory 248920 kb
Host smart-4e6d3ec8-6052-40c4-a7c7-9ec3326504db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1951161593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1951161593
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2229655676
Short name T47
Test name
Test status
Simulation time 53572999905 ps
CPU time 1794.46 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:58:50 PM PDT 24
Peak memory 269552 kb
Host smart-ca76225a-e59c-4cab-87fc-6a2c6b0694b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229655676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2229655676
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.978476744
Short name T510
Test name
Test status
Simulation time 258145052 ps
CPU time 14.63 seconds
Started May 19 02:28:52 PM PDT 24
Finished May 19 02:29:07 PM PDT 24
Peak memory 248728 kb
Host smart-fd96ea32-b3c4-49ca-abac-8ccfdcde2e50
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=978476744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.978476744
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2943537814
Short name T483
Test name
Test status
Simulation time 914558982 ps
CPU time 63.82 seconds
Started May 19 02:28:47 PM PDT 24
Finished May 19 02:29:52 PM PDT 24
Peak memory 255208 kb
Host smart-16fe0711-5c67-49a4-ae07-598aa94361a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29435
37814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2943537814
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2416667043
Short name T491
Test name
Test status
Simulation time 97832438 ps
CPU time 4.07 seconds
Started May 19 02:28:50 PM PDT 24
Finished May 19 02:28:54 PM PDT 24
Peak memory 250568 kb
Host smart-54c5d5a3-5fd0-4207-833c-7cbe670a7f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24166
67043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2416667043
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3612968630
Short name T427
Test name
Test status
Simulation time 38295882817 ps
CPU time 623.76 seconds
Started May 19 02:28:49 PM PDT 24
Finished May 19 02:39:13 PM PDT 24
Peak memory 265208 kb
Host smart-2ea045e4-b690-497a-8292-01ef3986451f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612968630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3612968630
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.379706943
Short name T572
Test name
Test status
Simulation time 38101617341 ps
CPU time 2178.88 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 03:05:15 PM PDT 24
Peak memory 281192 kb
Host smart-8d17b056-f12e-49fa-806d-58184a19f068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379706943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.379706943
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2519618013
Short name T553
Test name
Test status
Simulation time 8903197282 ps
CPU time 180.34 seconds
Started May 19 02:28:52 PM PDT 24
Finished May 19 02:31:53 PM PDT 24
Peak memory 248184 kb
Host smart-eed51e3b-d1d1-4bd3-ae6e-17f407135508
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519618013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2519618013
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1233028546
Short name T59
Test name
Test status
Simulation time 1643875858 ps
CPU time 37.75 seconds
Started May 19 02:28:51 PM PDT 24
Finished May 19 02:29:29 PM PDT 24
Peak memory 248760 kb
Host smart-807f9b4e-1bdd-4713-9534-cd4f396e2264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12330
28546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1233028546
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1504176049
Short name T495
Test name
Test status
Simulation time 1394557155 ps
CPU time 23.2 seconds
Started May 19 02:28:52 PM PDT 24
Finished May 19 02:29:16 PM PDT 24
Peak memory 255208 kb
Host smart-3b1f55f8-e61e-4883-9c50-b0ad309aab26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15041
76049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1504176049
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3223322139
Short name T40
Test name
Test status
Simulation time 968590721 ps
CPU time 18.11 seconds
Started May 19 02:28:51 PM PDT 24
Finished May 19 02:29:10 PM PDT 24
Peak memory 255876 kb
Host smart-77d9ed65-e43a-4592-9694-3d10acd6d6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233
22139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3223322139
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1433038895
Short name T233
Test name
Test status
Simulation time 571825162198 ps
CPU time 2365.56 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 03:08:22 PM PDT 24
Peak memory 283016 kb
Host smart-16dda1df-0a8c-4f9e-932f-9686fe59ef00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433038895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1433038895
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2957747647
Short name T273
Test name
Test status
Simulation time 518503961954 ps
CPU time 2934.48 seconds
Started May 19 02:33:28 PM PDT 24
Finished May 19 03:22:23 PM PDT 24
Peak memory 289396 kb
Host smart-464e4389-e2d6-4a00-8ad6-8dc32a2f5b53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957747647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2957747647
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3312882718
Short name T663
Test name
Test status
Simulation time 18467220567 ps
CPU time 266.2 seconds
Started May 19 02:33:21 PM PDT 24
Finished May 19 02:37:48 PM PDT 24
Peak memory 257188 kb
Host smart-23b7812f-d954-445b-bb3d-6d7ad53cc114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33128
82718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3312882718
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3943335037
Short name T419
Test name
Test status
Simulation time 398715198 ps
CPU time 19.05 seconds
Started May 19 02:33:16 PM PDT 24
Finished May 19 02:33:35 PM PDT 24
Peak memory 248780 kb
Host smart-f822221b-160d-4ff1-a67c-b78d8231f02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39433
35037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3943335037
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3495785732
Short name T616
Test name
Test status
Simulation time 63354223886 ps
CPU time 1546.48 seconds
Started May 19 02:33:26 PM PDT 24
Finished May 19 02:59:13 PM PDT 24
Peak memory 289540 kb
Host smart-f1b6e6fa-eba3-4535-9d31-f739e51bc78c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495785732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3495785732
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1336467347
Short name T488
Test name
Test status
Simulation time 9359322673 ps
CPU time 57.5 seconds
Started May 19 02:33:15 PM PDT 24
Finished May 19 02:34:13 PM PDT 24
Peak memory 248816 kb
Host smart-d24b8ace-65fb-45e2-832f-ba3bcac29cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13364
67347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1336467347
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3049661852
Short name T424
Test name
Test status
Simulation time 157116514 ps
CPU time 10.79 seconds
Started May 19 02:33:17 PM PDT 24
Finished May 19 02:33:28 PM PDT 24
Peak memory 252852 kb
Host smart-ff59f6ba-21bd-4f97-b72c-cd3b579d06bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30496
61852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3049661852
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.90786655
Short name T529
Test name
Test status
Simulation time 85517503 ps
CPU time 6.36 seconds
Started May 19 02:33:23 PM PDT 24
Finished May 19 02:33:29 PM PDT 24
Peak memory 248784 kb
Host smart-5de5000e-0146-4945-ae5d-17a6920c5871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90786
655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.90786655
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3524049075
Short name T502
Test name
Test status
Simulation time 779929758 ps
CPU time 50.36 seconds
Started May 19 02:33:15 PM PDT 24
Finished May 19 02:34:06 PM PDT 24
Peak memory 248780 kb
Host smart-d4be1bbf-2848-4593-8f9e-97a6feeb642b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35240
49075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3524049075
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.991665126
Short name T24
Test name
Test status
Simulation time 6904779665 ps
CPU time 112.84 seconds
Started May 19 02:33:32 PM PDT 24
Finished May 19 02:35:25 PM PDT 24
Peak memory 249188 kb
Host smart-7ec6048b-540d-486f-a36b-f0c31931c90c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991665126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.991665126
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1486751446
Short name T32
Test name
Test status
Simulation time 72241218297 ps
CPU time 2065.01 seconds
Started May 19 02:33:38 PM PDT 24
Finished May 19 03:08:03 PM PDT 24
Peak memory 289208 kb
Host smart-b3c34c7f-57f3-4d66-9934-804734ff987f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486751446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1486751446
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1688218338
Short name T658
Test name
Test status
Simulation time 20669591365 ps
CPU time 292.15 seconds
Started May 19 02:33:31 PM PDT 24
Finished May 19 02:38:24 PM PDT 24
Peak memory 256976 kb
Host smart-eb5caa51-ef19-446d-aad0-316bda00c34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
18338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1688218338
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1995913264
Short name T549
Test name
Test status
Simulation time 1725348020 ps
CPU time 53.73 seconds
Started May 19 02:33:31 PM PDT 24
Finished May 19 02:34:26 PM PDT 24
Peak memory 248756 kb
Host smart-39b2590e-3488-470d-956c-fbd04e35e38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19959
13264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1995913264
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1593451832
Short name T290
Test name
Test status
Simulation time 51121279257 ps
CPU time 1509.76 seconds
Started May 19 02:33:42 PM PDT 24
Finished May 19 02:58:52 PM PDT 24
Peak memory 270384 kb
Host smart-106478d1-2b40-42db-b58c-e55fa625e602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593451832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1593451832
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1419773816
Short name T643
Test name
Test status
Simulation time 16650417614 ps
CPU time 1181.45 seconds
Started May 19 02:33:43 PM PDT 24
Finished May 19 02:53:25 PM PDT 24
Peak memory 284148 kb
Host smart-b18aa5dc-c88a-49b8-9395-84268da684ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419773816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1419773816
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2777930880
Short name T309
Test name
Test status
Simulation time 28229572369 ps
CPU time 140.24 seconds
Started May 19 02:33:37 PM PDT 24
Finished May 19 02:35:58 PM PDT 24
Peak memory 247856 kb
Host smart-c2eb909b-9ef9-42f8-b78d-84adc9cd7013
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777930880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2777930880
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1484446742
Short name T377
Test name
Test status
Simulation time 1562955257 ps
CPU time 21.11 seconds
Started May 19 02:33:31 PM PDT 24
Finished May 19 02:33:53 PM PDT 24
Peak memory 248732 kb
Host smart-51c1fbd9-5323-4573-8223-3f485de91678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14844
46742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1484446742
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2092489241
Short name T94
Test name
Test status
Simulation time 415318065 ps
CPU time 13.56 seconds
Started May 19 02:33:31 PM PDT 24
Finished May 19 02:33:45 PM PDT 24
Peak memory 255964 kb
Host smart-840c553a-1406-41c7-b62e-c4ce8007ed16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20924
89241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2092489241
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.510592335
Short name T669
Test name
Test status
Simulation time 613147007 ps
CPU time 31.62 seconds
Started May 19 02:33:37 PM PDT 24
Finished May 19 02:34:09 PM PDT 24
Peak memory 248696 kb
Host smart-24163bd3-b194-405e-8540-4a2e31d2dabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51059
2335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.510592335
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1915515239
Short name T403
Test name
Test status
Simulation time 755995554 ps
CPU time 51.48 seconds
Started May 19 02:33:31 PM PDT 24
Finished May 19 02:34:24 PM PDT 24
Peak memory 256188 kb
Host smart-397de961-1d33-40f7-b7a3-71eebb347166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19155
15239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1915515239
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.691805580
Short name T30
Test name
Test status
Simulation time 515447510388 ps
CPU time 2423.91 seconds
Started May 19 02:33:42 PM PDT 24
Finished May 19 03:14:07 PM PDT 24
Peak memory 285968 kb
Host smart-c4fe9518-c2bf-4e75-9168-c78737b8c27c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691805580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.691805580
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3184622975
Short name T432
Test name
Test status
Simulation time 7124826408 ps
CPU time 916.16 seconds
Started May 19 02:33:43 PM PDT 24
Finished May 19 02:49:01 PM PDT 24
Peak memory 273344 kb
Host smart-2b551ab8-96c2-431d-95c0-f70fb336d3f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184622975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3184622975
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3553642872
Short name T490
Test name
Test status
Simulation time 3680640258 ps
CPU time 172.88 seconds
Started May 19 02:33:43 PM PDT 24
Finished May 19 02:36:37 PM PDT 24
Peak memory 256932 kb
Host smart-32152dc2-41fd-47dd-8c61-f2a628505b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35536
42872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3553642872
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1948588898
Short name T373
Test name
Test status
Simulation time 534155253 ps
CPU time 34.84 seconds
Started May 19 02:33:43 PM PDT 24
Finished May 19 02:34:19 PM PDT 24
Peak memory 255968 kb
Host smart-0f5a2951-2951-456e-8f69-8fdf07bf4d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19485
88898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1948588898
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3017543985
Short name T569
Test name
Test status
Simulation time 36787266424 ps
CPU time 2248.95 seconds
Started May 19 02:33:48 PM PDT 24
Finished May 19 03:11:18 PM PDT 24
Peak memory 272316 kb
Host smart-d458057d-efec-4a7b-9568-e2cb4938c349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017543985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3017543985
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1855696443
Short name T610
Test name
Test status
Simulation time 10593617015 ps
CPU time 1606.49 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 03:00:37 PM PDT 24
Peak memory 289288 kb
Host smart-d832432f-43c2-4fd9-9b45-ddd7b008aedd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855696443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1855696443
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2437589208
Short name T297
Test name
Test status
Simulation time 5992315544 ps
CPU time 258.16 seconds
Started May 19 02:33:47 PM PDT 24
Finished May 19 02:38:06 PM PDT 24
Peak memory 247124 kb
Host smart-82a74ed7-3a93-42ce-93fc-407f12783a68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437589208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2437589208
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.765080076
Short name T519
Test name
Test status
Simulation time 584560487 ps
CPU time 11.19 seconds
Started May 19 02:33:43 PM PDT 24
Finished May 19 02:33:55 PM PDT 24
Peak memory 248812 kb
Host smart-15fb3ded-ac05-46fe-bf7d-58cec9d888fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76508
0076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.765080076
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3589397646
Short name T38
Test name
Test status
Simulation time 454126781 ps
CPU time 30.71 seconds
Started May 19 02:33:42 PM PDT 24
Finished May 19 02:34:14 PM PDT 24
Peak memory 248948 kb
Host smart-58024bcc-a47b-48c0-b52d-fde1678687de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
97646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3589397646
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3127505899
Short name T260
Test name
Test status
Simulation time 1376723454 ps
CPU time 48.6 seconds
Started May 19 02:33:42 PM PDT 24
Finished May 19 02:34:31 PM PDT 24
Peak memory 255588 kb
Host smart-1973b029-fa38-4bb4-a95c-df8149d8795b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31275
05899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3127505899
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2918968640
Short name T679
Test name
Test status
Simulation time 34458757 ps
CPU time 4.82 seconds
Started May 19 02:33:42 PM PDT 24
Finished May 19 02:33:48 PM PDT 24
Peak memory 240868 kb
Host smart-e084ec52-b223-4fe3-a6dd-8cc4b0805ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
68640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2918968640
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.235325755
Short name T88
Test name
Test status
Simulation time 77491573236 ps
CPU time 2227.34 seconds
Started May 19 02:33:47 PM PDT 24
Finished May 19 03:10:55 PM PDT 24
Peak memory 288440 kb
Host smart-3219aaec-1d42-41a8-964d-7c4b84a4f9fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235325755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.235325755
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4285989179
Short name T56
Test name
Test status
Simulation time 22783510284 ps
CPU time 1561.26 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 02:59:52 PM PDT 24
Peak memory 289712 kb
Host smart-f39c7087-c5ed-4139-9bf8-50252d0ca9d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285989179 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4285989179
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.95960150
Short name T638
Test name
Test status
Simulation time 69117431681 ps
CPU time 2635.72 seconds
Started May 19 02:33:48 PM PDT 24
Finished May 19 03:17:45 PM PDT 24
Peak memory 289288 kb
Host smart-0aaa1eda-67d7-4290-a920-414e05633f3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95960150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.95960150
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2782797029
Short name T499
Test name
Test status
Simulation time 4527056332 ps
CPU time 263.59 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 02:38:13 PM PDT 24
Peak memory 249812 kb
Host smart-481b2f99-f74f-47d2-8ee7-eb2aab2b5eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27827
97029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2782797029
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2646504863
Short name T358
Test name
Test status
Simulation time 96787059 ps
CPU time 9.1 seconds
Started May 19 02:33:48 PM PDT 24
Finished May 19 02:33:58 PM PDT 24
Peak memory 248744 kb
Host smart-17b92a2f-3818-41a2-8e8f-b83b79c72d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26465
04863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2646504863
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1168050587
Short name T602
Test name
Test status
Simulation time 106448333372 ps
CPU time 1987.59 seconds
Started May 19 02:33:55 PM PDT 24
Finished May 19 03:07:03 PM PDT 24
Peak memory 281552 kb
Host smart-06776322-c1b2-4676-9d04-0c255ecb1ef4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168050587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1168050587
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2492889026
Short name T475
Test name
Test status
Simulation time 18888606501 ps
CPU time 955.8 seconds
Started May 19 02:33:54 PM PDT 24
Finished May 19 02:49:51 PM PDT 24
Peak memory 272716 kb
Host smart-6173026d-c443-4f77-ba4a-05b8531418e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492889026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2492889026
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.428894742
Short name T660
Test name
Test status
Simulation time 19605903965 ps
CPU time 546.72 seconds
Started May 19 02:33:54 PM PDT 24
Finished May 19 02:43:02 PM PDT 24
Peak memory 248196 kb
Host smart-91b76994-f046-41c5-863a-e13a97a9087a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428894742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.428894742
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2623254952
Short name T372
Test name
Test status
Simulation time 571756383 ps
CPU time 17.46 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 02:34:08 PM PDT 24
Peak memory 256940 kb
Host smart-9e2dd055-12f6-4688-9da5-4a64af2423c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26232
54952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2623254952
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2287090059
Short name T505
Test name
Test status
Simulation time 113243755 ps
CPU time 4.91 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 02:33:54 PM PDT 24
Peak memory 239236 kb
Host smart-c1394cac-ab7b-4d52-a2a0-9fbdef227560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22870
90059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2287090059
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2918948921
Short name T497
Test name
Test status
Simulation time 1922308930 ps
CPU time 53.92 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 02:34:44 PM PDT 24
Peak memory 255896 kb
Host smart-81010872-badd-4c89-8fb3-e8663c4ff3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
48921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2918948921
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2721669818
Short name T462
Test name
Test status
Simulation time 136859092 ps
CPU time 13.68 seconds
Started May 19 02:33:49 PM PDT 24
Finished May 19 02:34:04 PM PDT 24
Peak memory 248784 kb
Host smart-d98254a2-ee05-41da-be47-a7e27a685574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27216
69818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2721669818
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1402229277
Short name T245
Test name
Test status
Simulation time 197034353644 ps
CPU time 3056.28 seconds
Started May 19 02:33:54 PM PDT 24
Finished May 19 03:24:52 PM PDT 24
Peak memory 289532 kb
Host smart-9e78288c-d868-48f8-9d1b-1e3cf48398d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402229277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1402229277
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3759440264
Short name T115
Test name
Test status
Simulation time 58637205895 ps
CPU time 1727.96 seconds
Started May 19 02:34:03 PM PDT 24
Finished May 19 03:02:51 PM PDT 24
Peak memory 281660 kb
Host smart-2845b4e4-688b-4511-9cb5-a7a9cb9934e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759440264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3759440264
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2146626242
Short name T371
Test name
Test status
Simulation time 595818457 ps
CPU time 56.7 seconds
Started May 19 02:34:00 PM PDT 24
Finished May 19 02:34:57 PM PDT 24
Peak memory 256748 kb
Host smart-721b25b0-29eb-4d1c-8643-9fe36c73512f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21466
26242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2146626242
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3497791381
Short name T639
Test name
Test status
Simulation time 267197150 ps
CPU time 15.84 seconds
Started May 19 02:33:58 PM PDT 24
Finished May 19 02:34:14 PM PDT 24
Peak memory 255408 kb
Host smart-43c58ad5-4309-4032-b428-08674b5eef82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34977
91381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3497791381
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.460203188
Short name T322
Test name
Test status
Simulation time 354046132621 ps
CPU time 1241.35 seconds
Started May 19 02:34:04 PM PDT 24
Finished May 19 02:54:46 PM PDT 24
Peak memory 273356 kb
Host smart-464333bf-8c3d-43de-9214-1b260ae243dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460203188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.460203188
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1295384094
Short name T105
Test name
Test status
Simulation time 205208903551 ps
CPU time 2763.54 seconds
Started May 19 02:34:02 PM PDT 24
Finished May 19 03:20:07 PM PDT 24
Peak memory 282344 kb
Host smart-1358659c-0848-4b9c-b6b6-32d861cd07fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295384094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1295384094
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.311449502
Short name T299
Test name
Test status
Simulation time 30747221955 ps
CPU time 337 seconds
Started May 19 02:34:03 PM PDT 24
Finished May 19 02:39:41 PM PDT 24
Peak memory 247996 kb
Host smart-d3cbb90e-524a-4e7d-897d-734bdcb44354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311449502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.311449502
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.793380376
Short name T440
Test name
Test status
Simulation time 2584333091 ps
CPU time 44.81 seconds
Started May 19 02:33:56 PM PDT 24
Finished May 19 02:34:42 PM PDT 24
Peak memory 256304 kb
Host smart-719776dd-f58e-40e0-a869-74e9f2138999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79338
0376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.793380376
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3637156827
Short name T605
Test name
Test status
Simulation time 245331728 ps
CPU time 20.16 seconds
Started May 19 02:34:01 PM PDT 24
Finished May 19 02:34:21 PM PDT 24
Peak memory 248728 kb
Host smart-d030ebb5-ae02-4158-aa98-75dd9eca571e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36371
56827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3637156827
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2263973683
Short name T182
Test name
Test status
Simulation time 1210319391 ps
CPU time 47.52 seconds
Started May 19 02:34:02 PM PDT 24
Finished May 19 02:34:50 PM PDT 24
Peak memory 248760 kb
Host smart-7a21e9de-7b55-40fb-8e33-519e89ac9d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22639
73683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2263973683
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2581733361
Short name T494
Test name
Test status
Simulation time 881960800 ps
CPU time 7.83 seconds
Started May 19 02:33:59 PM PDT 24
Finished May 19 02:34:08 PM PDT 24
Peak memory 252972 kb
Host smart-59ef8ba5-45bc-4b69-9556-427268c4161b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25817
33361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2581733361
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.4015633094
Short name T452
Test name
Test status
Simulation time 46125071299 ps
CPU time 731.68 seconds
Started May 19 02:34:04 PM PDT 24
Finished May 19 02:46:16 PM PDT 24
Peak memory 256968 kb
Host smart-6dc0721d-4617-46e9-91f1-7e5c41ede07e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015633094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.4015633094
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.211653967
Short name T103
Test name
Test status
Simulation time 705214592030 ps
CPU time 9407.68 seconds
Started May 19 02:34:02 PM PDT 24
Finished May 19 05:10:52 PM PDT 24
Peak memory 338084 kb
Host smart-a40c45c4-539f-4d09-89b7-8cb7c524acb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211653967 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.211653967
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2063361378
Short name T451
Test name
Test status
Simulation time 203315912563 ps
CPU time 2903.64 seconds
Started May 19 02:34:13 PM PDT 24
Finished May 19 03:22:38 PM PDT 24
Peak memory 289472 kb
Host smart-a2de3c3e-ecdd-4c44-aa0e-d5b7692defe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063361378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2063361378
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4050233981
Short name T574
Test name
Test status
Simulation time 239743397 ps
CPU time 12.84 seconds
Started May 19 02:34:12 PM PDT 24
Finished May 19 02:34:26 PM PDT 24
Peak memory 256112 kb
Host smart-e9affbf2-d35e-4c76-98be-f3d5911215ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40502
33981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4050233981
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2846241643
Short name T438
Test name
Test status
Simulation time 292820354 ps
CPU time 24.17 seconds
Started May 19 02:34:08 PM PDT 24
Finished May 19 02:34:33 PM PDT 24
Peak memory 255668 kb
Host smart-f8d021fe-3f3d-4d6e-90a6-256c5b5b4592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28462
41643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2846241643
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2068833008
Short name T621
Test name
Test status
Simulation time 12759568249 ps
CPU time 1226.17 seconds
Started May 19 02:34:13 PM PDT 24
Finished May 19 02:54:41 PM PDT 24
Peak memory 288596 kb
Host smart-7fb9b9a4-a6bd-4270-a9c2-b2c131473bdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068833008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2068833008
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1536687027
Short name T530
Test name
Test status
Simulation time 209912588962 ps
CPU time 2115.82 seconds
Started May 19 02:34:12 PM PDT 24
Finished May 19 03:09:29 PM PDT 24
Peak memory 281608 kb
Host smart-a33b3d14-5395-41ac-a67d-7bbccd94a777
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536687027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1536687027
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3127279131
Short name T307
Test name
Test status
Simulation time 28572064268 ps
CPU time 335.69 seconds
Started May 19 02:34:12 PM PDT 24
Finished May 19 02:39:48 PM PDT 24
Peak memory 247900 kb
Host smart-53940710-be59-4f3f-8968-d6ca15fdd31e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127279131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3127279131
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.462444115
Short name T411
Test name
Test status
Simulation time 126473776 ps
CPU time 5.28 seconds
Started May 19 02:34:09 PM PDT 24
Finished May 19 02:34:15 PM PDT 24
Peak memory 240512 kb
Host smart-81d2231a-6296-4e38-8a61-f3ccd009c5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46244
4115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.462444115
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3663128002
Short name T357
Test name
Test status
Simulation time 885989827 ps
CPU time 19.38 seconds
Started May 19 02:34:10 PM PDT 24
Finished May 19 02:34:29 PM PDT 24
Peak memory 256524 kb
Host smart-023dd9b1-3a73-4061-b748-fc032543e15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
28002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3663128002
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2649596395
Short name T534
Test name
Test status
Simulation time 745083534 ps
CPU time 40.96 seconds
Started May 19 02:34:14 PM PDT 24
Finished May 19 02:34:55 PM PDT 24
Peak memory 248768 kb
Host smart-80a5502f-dc45-45d2-a306-9d7546365b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26495
96395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2649596395
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1788732609
Short name T387
Test name
Test status
Simulation time 150735794 ps
CPU time 19.67 seconds
Started May 19 02:34:08 PM PDT 24
Finished May 19 02:34:28 PM PDT 24
Peak memory 248776 kb
Host smart-d11fa515-f2df-4afb-854d-9d6e352afbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17887
32609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1788732609
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2162738071
Short name T527
Test name
Test status
Simulation time 1101260994 ps
CPU time 56.74 seconds
Started May 19 02:34:17 PM PDT 24
Finished May 19 02:35:15 PM PDT 24
Peak memory 254692 kb
Host smart-829d841d-f7ee-48dc-aeeb-beba8df45cca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162738071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2162738071
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3892968338
Short name T445
Test name
Test status
Simulation time 96064373802 ps
CPU time 1574.35 seconds
Started May 19 02:34:29 PM PDT 24
Finished May 19 03:00:44 PM PDT 24
Peak memory 273404 kb
Host smart-0931a267-639b-422c-bfa3-1d66433aa07f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892968338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3892968338
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3093901692
Short name T402
Test name
Test status
Simulation time 230044887 ps
CPU time 5.13 seconds
Started May 19 02:34:22 PM PDT 24
Finished May 19 02:34:27 PM PDT 24
Peak memory 251120 kb
Host smart-af5e1319-aa90-423d-b056-6c931903f171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30939
01692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3093901692
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2763325573
Short name T620
Test name
Test status
Simulation time 2353814131 ps
CPU time 72.85 seconds
Started May 19 02:34:30 PM PDT 24
Finished May 19 02:35:44 PM PDT 24
Peak memory 256188 kb
Host smart-c4c7a103-8e21-4684-8b70-0a219fb167cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27633
25573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2763325573
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.226814382
Short name T327
Test name
Test status
Simulation time 13280388360 ps
CPU time 1105.16 seconds
Started May 19 02:34:30 PM PDT 24
Finished May 19 02:52:55 PM PDT 24
Peak memory 269376 kb
Host smart-10d98a79-d19f-4260-ad03-7c1cad42121c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226814382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.226814382
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.300522834
Short name T3
Test name
Test status
Simulation time 178744932736 ps
CPU time 2474.53 seconds
Started May 19 02:34:29 PM PDT 24
Finished May 19 03:15:45 PM PDT 24
Peak memory 282796 kb
Host smart-722e2ec1-59aa-418d-89b9-345a8a313fee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300522834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.300522834
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.253022926
Short name T292
Test name
Test status
Simulation time 60137517865 ps
CPU time 624.74 seconds
Started May 19 02:34:31 PM PDT 24
Finished May 19 02:44:56 PM PDT 24
Peak memory 247868 kb
Host smart-a0cb320a-3f2f-432f-bfef-9a0cfe243b8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253022926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.253022926
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1218725573
Short name T628
Test name
Test status
Simulation time 266208272 ps
CPU time 14.82 seconds
Started May 19 02:34:17 PM PDT 24
Finished May 19 02:34:33 PM PDT 24
Peak memory 256956 kb
Host smart-56654579-0abd-462f-85d2-cc80e07976cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12187
25573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1218725573
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.343534606
Short name T44
Test name
Test status
Simulation time 4447369565 ps
CPU time 50.99 seconds
Started May 19 02:34:22 PM PDT 24
Finished May 19 02:35:13 PM PDT 24
Peak memory 255532 kb
Host smart-27f115ae-8d00-43af-a7bf-da4d14e3ac08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34353
4606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.343534606
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1587208645
Short name T64
Test name
Test status
Simulation time 599145000 ps
CPU time 23.02 seconds
Started May 19 02:34:28 PM PDT 24
Finished May 19 02:34:51 PM PDT 24
Peak memory 247436 kb
Host smart-825013d7-1c5b-4224-83ab-eedbce1fd4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872
08645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1587208645
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2467952628
Short name T366
Test name
Test status
Simulation time 347176079 ps
CPU time 27.46 seconds
Started May 19 02:34:17 PM PDT 24
Finished May 19 02:34:46 PM PDT 24
Peak memory 248892 kb
Host smart-670d415c-cba1-4db7-9b01-c79a17acda63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
52628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2467952628
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2831458839
Short name T507
Test name
Test status
Simulation time 46097264966 ps
CPU time 2979.85 seconds
Started May 19 02:34:30 PM PDT 24
Finished May 19 03:24:11 PM PDT 24
Peak memory 300548 kb
Host smart-73d5e604-b186-4a10-884f-6255a591ff44
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831458839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2831458839
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1354142406
Short name T65
Test name
Test status
Simulation time 187312461048 ps
CPU time 722.18 seconds
Started May 19 02:34:39 PM PDT 24
Finished May 19 02:46:42 PM PDT 24
Peak memory 266256 kb
Host smart-34bc83ca-226b-46ca-b6ad-76323b26e53b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354142406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1354142406
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.159841262
Short name T552
Test name
Test status
Simulation time 509626860 ps
CPU time 14.36 seconds
Started May 19 02:34:32 PM PDT 24
Finished May 19 02:34:47 PM PDT 24
Peak memory 256396 kb
Host smart-c9c9ec21-ff95-40a0-8e79-497af3cd702e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15984
1262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.159841262
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2118307682
Short name T484
Test name
Test status
Simulation time 3205871194 ps
CPU time 26.93 seconds
Started May 19 02:34:32 PM PDT 24
Finished May 19 02:34:59 PM PDT 24
Peak memory 249096 kb
Host smart-df93e155-9d4f-4bce-9d0d-5eccfed5b504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21183
07682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2118307682
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2312307321
Short name T334
Test name
Test status
Simulation time 7895858705 ps
CPU time 724.81 seconds
Started May 19 02:34:42 PM PDT 24
Finished May 19 02:46:48 PM PDT 24
Peak memory 265408 kb
Host smart-7e2f44f9-c25d-439c-b6a9-403d174ed1d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312307321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2312307321
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.961626556
Short name T16
Test name
Test status
Simulation time 53355892822 ps
CPU time 1671.02 seconds
Started May 19 02:34:43 PM PDT 24
Finished May 19 03:02:35 PM PDT 24
Peak memory 265464 kb
Host smart-dda1cca9-44b2-4cb6-81ad-dad07345e932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961626556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.961626556
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2846633512
Short name T409
Test name
Test status
Simulation time 603462568 ps
CPU time 34.6 seconds
Started May 19 02:34:32 PM PDT 24
Finished May 19 02:35:07 PM PDT 24
Peak memory 256032 kb
Host smart-a6286339-f0b9-4fba-aeb7-8a8013987ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
33512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2846633512
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1180035678
Short name T386
Test name
Test status
Simulation time 33454163 ps
CPU time 3.93 seconds
Started May 19 02:34:31 PM PDT 24
Finished May 19 02:34:36 PM PDT 24
Peak memory 239216 kb
Host smart-4459e450-fd23-4aac-a1b7-18fe01f6c39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11800
35678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1180035678
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.235970863
Short name T255
Test name
Test status
Simulation time 329921812 ps
CPU time 16.86 seconds
Started May 19 02:34:35 PM PDT 24
Finished May 19 02:34:53 PM PDT 24
Peak memory 247352 kb
Host smart-4ab42366-3b66-4e55-aa10-f7af3243ec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23597
0863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.235970863
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1482198315
Short name T416
Test name
Test status
Simulation time 2065995206 ps
CPU time 16.82 seconds
Started May 19 02:34:31 PM PDT 24
Finished May 19 02:34:48 PM PDT 24
Peak memory 253412 kb
Host smart-8ac74142-640b-4d27-9644-9fb931b8cf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14821
98315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1482198315
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4224073009
Short name T654
Test name
Test status
Simulation time 657895548304 ps
CPU time 3241.81 seconds
Started May 19 02:34:43 PM PDT 24
Finished May 19 03:28:46 PM PDT 24
Peak memory 289060 kb
Host smart-32e40dc1-4e30-4142-8398-f4238e46ad28
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224073009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4224073009
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2936146091
Short name T71
Test name
Test status
Simulation time 18835560446 ps
CPU time 1962.34 seconds
Started May 19 02:34:43 PM PDT 24
Finished May 19 03:07:27 PM PDT 24
Peak memory 298152 kb
Host smart-0890328c-f41a-4af6-896d-00dd4d94961a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936146091 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2936146091
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4110137532
Short name T55
Test name
Test status
Simulation time 11785889642 ps
CPU time 1069.84 seconds
Started May 19 02:34:52 PM PDT 24
Finished May 19 02:52:42 PM PDT 24
Peak memory 282304 kb
Host smart-c8ef94e5-ab62-42b8-bbaa-b959d8e59876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110137532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4110137532
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2470729267
Short name T554
Test name
Test status
Simulation time 3375605491 ps
CPU time 96.42 seconds
Started May 19 02:34:47 PM PDT 24
Finished May 19 02:36:23 PM PDT 24
Peak memory 248764 kb
Host smart-c3c00cd8-9e77-418a-a7d8-7e62689f5b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24707
29267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2470729267
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.963888268
Short name T119
Test name
Test status
Simulation time 135507342 ps
CPU time 9.28 seconds
Started May 19 02:34:47 PM PDT 24
Finished May 19 02:34:57 PM PDT 24
Peak memory 254188 kb
Host smart-aa16e6c2-1346-4ece-8cbf-3b332f4e8c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96388
8268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.963888268
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3796163564
Short name T471
Test name
Test status
Simulation time 12029330715 ps
CPU time 1300.89 seconds
Started May 19 02:34:58 PM PDT 24
Finished May 19 02:56:40 PM PDT 24
Peak memory 284448 kb
Host smart-4f8e9ca2-f1cb-4511-8021-06a1159b1c30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796163564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3796163564
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1377982741
Short name T696
Test name
Test status
Simulation time 13287767703 ps
CPU time 579.54 seconds
Started May 19 02:34:56 PM PDT 24
Finished May 19 02:44:36 PM PDT 24
Peak memory 265256 kb
Host smart-e28e5b5e-fb67-4a19-b523-8fdbb02ff6ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377982741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1377982741
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1147968177
Short name T306
Test name
Test status
Simulation time 23094613578 ps
CPU time 323.6 seconds
Started May 19 02:34:55 PM PDT 24
Finished May 19 02:40:20 PM PDT 24
Peak memory 248224 kb
Host smart-b596b48e-52a6-4053-badb-620e55cb212b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147968177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1147968177
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1811111376
Short name T535
Test name
Test status
Simulation time 737127986 ps
CPU time 48.05 seconds
Started May 19 02:34:42 PM PDT 24
Finished May 19 02:35:30 PM PDT 24
Peak memory 248784 kb
Host smart-e599b0a0-29ac-4d53-9bdb-3c1be509f58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18111
11376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1811111376
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4142943898
Short name T557
Test name
Test status
Simulation time 3981643948 ps
CPU time 59.67 seconds
Started May 19 02:34:48 PM PDT 24
Finished May 19 02:35:48 PM PDT 24
Peak memory 255784 kb
Host smart-345e1532-db90-4eda-a1f8-ab7a107e9ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
43898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4142943898
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3579818859
Short name T185
Test name
Test status
Simulation time 968756432 ps
CPU time 28.23 seconds
Started May 19 02:34:47 PM PDT 24
Finished May 19 02:35:16 PM PDT 24
Peak memory 255284 kb
Host smart-dcfeef28-2ae2-46dc-94d0-ce3b21999288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35798
18859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3579818859
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.851627418
Short name T383
Test name
Test status
Simulation time 220409176 ps
CPU time 15.39 seconds
Started May 19 02:34:41 PM PDT 24
Finished May 19 02:34:57 PM PDT 24
Peak memory 248756 kb
Host smart-6f304521-eb96-4c56-8557-b7519d540daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85162
7418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.851627418
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2358718989
Short name T614
Test name
Test status
Simulation time 28369115948 ps
CPU time 1843.22 seconds
Started May 19 02:34:56 PM PDT 24
Finished May 19 03:05:40 PM PDT 24
Peak memory 281008 kb
Host smart-a8ad888b-fd6d-4aa2-a085-4e0c5ee6ca1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358718989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2358718989
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2388697178
Short name T104
Test name
Test status
Simulation time 63652080468 ps
CPU time 2094.68 seconds
Started May 19 02:35:05 PM PDT 24
Finished May 19 03:10:01 PM PDT 24
Peak memory 273444 kb
Host smart-9fa936f6-ef57-4b75-aa38-c1f1ef01fd7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388697178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2388697178
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1605476243
Short name T691
Test name
Test status
Simulation time 4009825018 ps
CPU time 127.66 seconds
Started May 19 02:35:06 PM PDT 24
Finished May 19 02:37:15 PM PDT 24
Peak memory 249120 kb
Host smart-9fd2f94a-f07a-4808-be63-02287153cbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16054
76243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1605476243
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.588046058
Short name T459
Test name
Test status
Simulation time 320366529 ps
CPU time 29.06 seconds
Started May 19 02:35:01 PM PDT 24
Finished May 19 02:35:31 PM PDT 24
Peak memory 248768 kb
Host smart-90a8b348-35f8-45a2-b8d3-20d7ad0168f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58804
6058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.588046058
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1586527645
Short name T697
Test name
Test status
Simulation time 51616297246 ps
CPU time 3076.27 seconds
Started May 19 02:35:06 PM PDT 24
Finished May 19 03:26:24 PM PDT 24
Peak memory 281132 kb
Host smart-21fc58aa-1c4c-4d50-bb8f-f50c423458f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586527645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1586527645
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1580595783
Short name T622
Test name
Test status
Simulation time 52959299701 ps
CPU time 3289.94 seconds
Started May 19 02:35:12 PM PDT 24
Finished May 19 03:30:02 PM PDT 24
Peak memory 288804 kb
Host smart-24d62d0a-edc3-4e13-a1a5-75de49a027cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580595783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1580595783
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2689398030
Short name T308
Test name
Test status
Simulation time 27565076711 ps
CPU time 285.48 seconds
Started May 19 02:35:06 PM PDT 24
Finished May 19 02:39:53 PM PDT 24
Peak memory 247884 kb
Host smart-ae7ff2d5-889a-488e-a6ed-cb14d8c3f727
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689398030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2689398030
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.205197744
Short name T577
Test name
Test status
Simulation time 42780313 ps
CPU time 6.28 seconds
Started May 19 02:35:01 PM PDT 24
Finished May 19 02:35:08 PM PDT 24
Peak memory 240516 kb
Host smart-757cbea6-9596-4516-bfcf-ef35a7e7468b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
7744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.205197744
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.34389423
Short name T381
Test name
Test status
Simulation time 133480242 ps
CPU time 4.11 seconds
Started May 19 02:35:02 PM PDT 24
Finished May 19 02:35:06 PM PDT 24
Peak memory 240564 kb
Host smart-6fefbc62-f776-47a0-9396-f381e72f071a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34389
423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.34389423
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.290079783
Short name T18
Test name
Test status
Simulation time 1001189824 ps
CPU time 54.85 seconds
Started May 19 02:35:06 PM PDT 24
Finished May 19 02:36:02 PM PDT 24
Peak memory 248832 kb
Host smart-66c30da9-1500-4188-9bd0-6f73e405ace1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29007
9783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.290079783
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3632314993
Short name T66
Test name
Test status
Simulation time 894926134 ps
CPU time 61.57 seconds
Started May 19 02:35:01 PM PDT 24
Finished May 19 02:36:04 PM PDT 24
Peak memory 248720 kb
Host smart-487e6b52-84b3-49ab-bacc-59421a7ec6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
14993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3632314993
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1945261850
Short name T671
Test name
Test status
Simulation time 9418568234 ps
CPU time 301.88 seconds
Started May 19 02:35:16 PM PDT 24
Finished May 19 02:40:18 PM PDT 24
Peak memory 257168 kb
Host smart-5a566fd5-3f6d-4dc0-87cd-cbbe8411f571
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945261850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1945261850
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1967087363
Short name T181
Test name
Test status
Simulation time 99153886199 ps
CPU time 3605.72 seconds
Started May 19 02:35:15 PM PDT 24
Finished May 19 03:35:22 PM PDT 24
Peak memory 314480 kb
Host smart-06541962-1be7-4b1f-9608-d523f8653805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967087363 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1967087363
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3265008787
Short name T211
Test name
Test status
Simulation time 72859857 ps
CPU time 2.42 seconds
Started May 19 02:28:56 PM PDT 24
Finished May 19 02:28:59 PM PDT 24
Peak memory 248932 kb
Host smart-c4a40056-118d-4605-bed3-ed1059930d94
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3265008787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3265008787
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3095990189
Short name T624
Test name
Test status
Simulation time 28298327694 ps
CPU time 1600.51 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:55:37 PM PDT 24
Peak memory 265200 kb
Host smart-4bded5e9-ece7-4208-9f09-b4f650f08c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095990189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3095990189
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3271275793
Short name T653
Test name
Test status
Simulation time 689441054 ps
CPU time 10.31 seconds
Started May 19 02:28:53 PM PDT 24
Finished May 19 02:29:04 PM PDT 24
Peak memory 248796 kb
Host smart-b33c79c7-a33a-4666-8f74-0ba85d6ef8a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3271275793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3271275793
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.916875377
Short name T439
Test name
Test status
Simulation time 23475389980 ps
CPU time 133.85 seconds
Started May 19 02:28:53 PM PDT 24
Finished May 19 02:31:08 PM PDT 24
Peak memory 256944 kb
Host smart-35ce8f23-1fb9-4587-af22-b157db3499c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91687
5377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.916875377
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2635479510
Short name T522
Test name
Test status
Simulation time 407670091 ps
CPU time 29.92 seconds
Started May 19 02:28:57 PM PDT 24
Finished May 19 02:29:27 PM PDT 24
Peak memory 255568 kb
Host smart-f344fcfc-1e8d-44c8-b071-543a57d8c99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26354
79510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2635479510
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2804800533
Short name T291
Test name
Test status
Simulation time 35832466572 ps
CPU time 799.06 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:42:15 PM PDT 24
Peak memory 267316 kb
Host smart-1f5e3e63-36af-4dc0-b982-a294f49431f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804800533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2804800533
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.868115871
Short name T633
Test name
Test status
Simulation time 25489314158 ps
CPU time 1794.33 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:58:54 PM PDT 24
Peak memory 281564 kb
Host smart-0e6f31aa-37d2-42b2-8cb1-6047b1d50802
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868115871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.868115871
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2542974387
Short name T304
Test name
Test status
Simulation time 2964124077 ps
CPU time 124.06 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:31:00 PM PDT 24
Peak memory 248172 kb
Host smart-60f760d8-8197-4e80-a556-9a92a4234c6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542974387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2542974387
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1577300122
Short name T474
Test name
Test status
Simulation time 606236350 ps
CPU time 36.38 seconds
Started May 19 02:28:58 PM PDT 24
Finished May 19 02:29:35 PM PDT 24
Peak memory 248752 kb
Host smart-56f56804-6264-4b13-9053-563757fcfeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
00122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1577300122
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2273098867
Short name T415
Test name
Test status
Simulation time 680393319 ps
CPU time 36.5 seconds
Started May 19 02:28:54 PM PDT 24
Finished May 19 02:29:31 PM PDT 24
Peak memory 255320 kb
Host smart-9cbde7b7-baef-4e44-82e0-8b77b3f77726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22730
98867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2273098867
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1735027536
Short name T447
Test name
Test status
Simulation time 3347971314 ps
CPU time 30.15 seconds
Started May 19 02:28:54 PM PDT 24
Finished May 19 02:29:25 PM PDT 24
Peak memory 247492 kb
Host smart-47583002-6430-4a96-8c86-3e87ff2323c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17350
27536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1735027536
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.287794612
Short name T478
Test name
Test status
Simulation time 1195405822 ps
CPU time 68.49 seconds
Started May 19 02:28:56 PM PDT 24
Finished May 19 02:30:05 PM PDT 24
Peak memory 248752 kb
Host smart-aeed00be-87bd-4916-b744-701692bc8482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28779
4612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.287794612
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.741135147
Short name T523
Test name
Test status
Simulation time 191456509334 ps
CPU time 2967.12 seconds
Started May 19 02:28:58 PM PDT 24
Finished May 19 03:18:26 PM PDT 24
Peak memory 302120 kb
Host smart-314f3bf3-10a3-4052-8e68-8c132700fdb9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741135147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.741135147
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4292643107
Short name T219
Test name
Test status
Simulation time 113086484 ps
CPU time 3.28 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:29:03 PM PDT 24
Peak memory 248952 kb
Host smart-0927236c-1591-4e81-a326-24b6a45588fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4292643107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4292643107
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1856085722
Short name T571
Test name
Test status
Simulation time 10331455188 ps
CPU time 591.76 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:38:48 PM PDT 24
Peak memory 272284 kb
Host smart-dd259156-f398-46a6-927e-d1a762dab85d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856085722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1856085722
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1891406978
Short name T664
Test name
Test status
Simulation time 719865095 ps
CPU time 16.42 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:29:16 PM PDT 24
Peak memory 248764 kb
Host smart-eee4e2a5-8506-4680-8551-896edb8257b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1891406978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1891406978
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.818192764
Short name T450
Test name
Test status
Simulation time 6513020049 ps
CPU time 229.62 seconds
Started May 19 02:28:57 PM PDT 24
Finished May 19 02:32:47 PM PDT 24
Peak memory 256680 kb
Host smart-34a0dd4e-a719-4605-9c0b-a1ef7e649c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81819
2764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.818192764
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2242032758
Short name T513
Test name
Test status
Simulation time 6172845207 ps
CPU time 40.27 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:29:36 PM PDT 24
Peak memory 256048 kb
Host smart-6b22abf0-6703-4e89-84c8-a12a59bfde2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22420
32758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2242032758
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2823291645
Short name T685
Test name
Test status
Simulation time 31951563086 ps
CPU time 1803.11 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:59:02 PM PDT 24
Peak memory 267280 kb
Host smart-7a0caf69-d418-4018-9d6a-9ff67eca233a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823291645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2823291645
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3618015155
Short name T650
Test name
Test status
Simulation time 57891385229 ps
CPU time 3153.72 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 03:21:37 PM PDT 24
Peak memory 289364 kb
Host smart-9f84a527-3207-4692-9357-f605dd50fc72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618015155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3618015155
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2483698615
Short name T184
Test name
Test status
Simulation time 49894725618 ps
CPU time 499.41 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 02:37:24 PM PDT 24
Peak memory 247860 kb
Host smart-1369c212-9310-4cb6-b3ab-e54efccb1586
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483698615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2483698615
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.67728050
Short name T544
Test name
Test status
Simulation time 308166166 ps
CPU time 12.17 seconds
Started May 19 02:28:54 PM PDT 24
Finished May 19 02:29:07 PM PDT 24
Peak memory 253952 kb
Host smart-7c21e277-6a5c-4336-9581-d09a478fa726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67728
050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.67728050
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4056755382
Short name T395
Test name
Test status
Simulation time 2735662472 ps
CPU time 19.05 seconds
Started May 19 02:28:58 PM PDT 24
Finished May 19 02:29:17 PM PDT 24
Peak memory 254632 kb
Host smart-015d92d1-2f70-44c2-9c36-5c81c97f0c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40567
55382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4056755382
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4109105979
Short name T107
Test name
Test status
Simulation time 412627258 ps
CPU time 25.07 seconds
Started May 19 02:28:55 PM PDT 24
Finished May 19 02:29:21 PM PDT 24
Peak memory 255428 kb
Host smart-c98e6eeb-a995-402d-9285-06c214303676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41091
05979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4109105979
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.697278958
Short name T607
Test name
Test status
Simulation time 183533278 ps
CPU time 17.3 seconds
Started May 19 02:28:57 PM PDT 24
Finished May 19 02:29:15 PM PDT 24
Peak memory 248932 kb
Host smart-be56de73-1920-4e3a-88c3-8cb45f61c2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69727
8958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.697278958
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1096888996
Short name T617
Test name
Test status
Simulation time 145791989113 ps
CPU time 2534.2 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 03:11:19 PM PDT 24
Peak memory 281536 kb
Host smart-47bf784e-6188-4189-94cf-3035ece8bb9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096888996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1096888996
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1285323825
Short name T448
Test name
Test status
Simulation time 76026921036 ps
CPU time 2142.18 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 03:04:44 PM PDT 24
Peak memory 305380 kb
Host smart-e6e01e7a-fae8-435f-bb3e-80fa68ce2abf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285323825 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1285323825
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.76169050
Short name T567
Test name
Test status
Simulation time 124058434435 ps
CPU time 2470.22 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 03:10:14 PM PDT 24
Peak memory 281648 kb
Host smart-d1bcbab5-16a3-4348-a323-e2cede4839a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76169050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.76169050
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1583017680
Short name T246
Test name
Test status
Simulation time 177477030 ps
CPU time 9.92 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:29:10 PM PDT 24
Peak memory 240548 kb
Host smart-9dbc1ef3-f842-4960-825c-a1d6b5611f5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1583017680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1583017680
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1951379230
Short name T644
Test name
Test status
Simulation time 6569815663 ps
CPU time 147.01 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 02:31:30 PM PDT 24
Peak memory 257000 kb
Host smart-b1731ae8-c351-4252-9878-988135a9283d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19513
79230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1951379230
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1627030817
Short name T77
Test name
Test status
Simulation time 631762668 ps
CPU time 37.65 seconds
Started May 19 02:29:08 PM PDT 24
Finished May 19 02:29:46 PM PDT 24
Peak memory 248764 kb
Host smart-a6291264-2712-4662-9eff-767009d89896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16270
30817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1627030817
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.103040212
Short name T336
Test name
Test status
Simulation time 62739798915 ps
CPU time 1562.1 seconds
Started May 19 02:29:02 PM PDT 24
Finished May 19 02:55:06 PM PDT 24
Peak memory 289212 kb
Host smart-7d61aaa3-fead-4ff3-b17b-ccae6c49f68e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103040212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.103040212
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.191674852
Short name T15
Test name
Test status
Simulation time 67752053875 ps
CPU time 1915.75 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 03:00:57 PM PDT 24
Peak memory 272724 kb
Host smart-43fd23b4-8b84-4a64-8b89-18d3d94a3760
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191674852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.191674852
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.538026989
Short name T303
Test name
Test status
Simulation time 9124960680 ps
CPU time 351.45 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 02:34:54 PM PDT 24
Peak memory 248328 kb
Host smart-71d197ee-107f-43c8-a944-05e9a999aeff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538026989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.538026989
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.581611168
Short name T625
Test name
Test status
Simulation time 877618520 ps
CPU time 17.1 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 02:29:19 PM PDT 24
Peak memory 248756 kb
Host smart-04a5c8be-a135-4f33-aedf-4d0e0c68389f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58161
1168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.581611168
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3516396263
Short name T444
Test name
Test status
Simulation time 813315424 ps
CPU time 48.56 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:29:48 PM PDT 24
Peak memory 255696 kb
Host smart-d96f52a3-fcea-4fa6-b804-b297b380fe77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35163
96263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3516396263
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.692910073
Short name T665
Test name
Test status
Simulation time 787734149 ps
CPU time 14.68 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 02:29:17 PM PDT 24
Peak memory 248600 kb
Host smart-9dbfb016-0f6c-4687-baf7-e345f759608f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69291
0073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.692910073
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.137192837
Short name T672
Test name
Test status
Simulation time 223531591 ps
CPU time 22.59 seconds
Started May 19 02:28:59 PM PDT 24
Finished May 19 02:29:23 PM PDT 24
Peak memory 248808 kb
Host smart-dd83fcfa-e4dd-424a-ad8c-7c518cd771ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13719
2837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.137192837
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3964780664
Short name T84
Test name
Test status
Simulation time 167826768897 ps
CPU time 6205.53 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 04:12:29 PM PDT 24
Peak memory 354640 kb
Host smart-9c4f224d-e977-4aa5-b99a-700757aa5aea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964780664 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3964780664
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1852911215
Short name T217
Test name
Test status
Simulation time 165004200 ps
CPU time 3.61 seconds
Started May 19 02:28:58 PM PDT 24
Finished May 19 02:29:02 PM PDT 24
Peak memory 249120 kb
Host smart-82b6c257-6b89-4b8b-9ad1-d14d8e60f3b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1852911215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1852911215
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.614910991
Short name T278
Test name
Test status
Simulation time 41962404169 ps
CPU time 2589.43 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 03:12:13 PM PDT 24
Peak memory 282400 kb
Host smart-b569e161-7c18-4a3c-a581-1c86e16309b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614910991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.614910991
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3908982268
Short name T423
Test name
Test status
Simulation time 794431271 ps
CPU time 17.97 seconds
Started May 19 02:29:08 PM PDT 24
Finished May 19 02:29:27 PM PDT 24
Peak memory 248780 kb
Host smart-7d66d017-75c7-491c-8c30-48fd4daeeba5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3908982268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3908982268
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4257289551
Short name T689
Test name
Test status
Simulation time 2389965512 ps
CPU time 128.69 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:31:18 PM PDT 24
Peak memory 249160 kb
Host smart-e03ea90a-8770-4f7e-bcc5-63692f904e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42572
89551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4257289551
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3279068168
Short name T120
Test name
Test status
Simulation time 5450029888 ps
CPU time 80.62 seconds
Started May 19 02:29:02 PM PDT 24
Finished May 19 02:30:24 PM PDT 24
Peak memory 249028 kb
Host smart-5b67e273-581b-48e3-9b15-1e327db476ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
68168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3279068168
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2926056451
Short name T536
Test name
Test status
Simulation time 177633373151 ps
CPU time 1257.2 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 02:50:01 PM PDT 24
Peak memory 281548 kb
Host smart-6d29a726-8fea-44ff-a3d9-392715a46900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926056451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2926056451
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.181825917
Short name T225
Test name
Test status
Simulation time 59751034238 ps
CPU time 571.11 seconds
Started May 19 02:29:03 PM PDT 24
Finished May 19 02:38:35 PM PDT 24
Peak memory 248112 kb
Host smart-92d3d940-c0b2-4a45-a508-c663205ab42e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181825917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.181825917
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.593215171
Short name T551
Test name
Test status
Simulation time 612608925 ps
CPU time 40.4 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 02:29:43 PM PDT 24
Peak memory 248820 kb
Host smart-027c55a4-3476-42e3-9e65-705d8706adb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59321
5171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.593215171
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3957523985
Short name T98
Test name
Test status
Simulation time 2118260832 ps
CPU time 29.44 seconds
Started May 19 02:29:02 PM PDT 24
Finished May 19 02:29:33 PM PDT 24
Peak memory 248840 kb
Host smart-0068c71b-edab-44b0-8775-5554a99cc0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39575
23985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3957523985
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3736673450
Short name T454
Test name
Test status
Simulation time 583357937 ps
CPU time 37.39 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 02:29:40 PM PDT 24
Peak memory 256132 kb
Host smart-0c1d58f8-e257-4713-b5b0-e622955b5ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37366
73450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3736673450
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3819771984
Short name T231
Test name
Test status
Simulation time 70060077 ps
CPU time 3.39 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 02:29:05 PM PDT 24
Peak memory 240544 kb
Host smart-bd00d567-d50b-474e-bd1e-9172d53b65c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
71984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3819771984
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3191236862
Short name T441
Test name
Test status
Simulation time 58166492324 ps
CPU time 1863.94 seconds
Started May 19 02:29:08 PM PDT 24
Finished May 19 03:00:13 PM PDT 24
Peak memory 272444 kb
Host smart-f37a2bc2-0e5e-40cf-be92-7d35317b6372
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191236862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3191236862
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.4140081330
Short name T4
Test name
Test status
Simulation time 5422728093 ps
CPU time 96.75 seconds
Started May 19 02:29:06 PM PDT 24
Finished May 19 02:30:44 PM PDT 24
Peak memory 265332 kb
Host smart-bcfe8b89-eec8-49aa-b125-e1fbed2db58f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140081330 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.4140081330
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3178968158
Short name T49
Test name
Test status
Simulation time 188498199 ps
CPU time 3.68 seconds
Started May 19 02:29:04 PM PDT 24
Finished May 19 02:29:09 PM PDT 24
Peak memory 248892 kb
Host smart-b0b076cf-93db-4ed3-8c88-63ee5b1bfece
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3178968158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3178968158
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1723981692
Short name T465
Test name
Test status
Simulation time 803711118 ps
CPU time 35.32 seconds
Started May 19 02:29:08 PM PDT 24
Finished May 19 02:29:44 PM PDT 24
Peak memory 248796 kb
Host smart-d47e3759-5cc6-4da2-99a2-1898b475dc7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1723981692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1723981692
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.281958592
Short name T573
Test name
Test status
Simulation time 8325006249 ps
CPU time 162.84 seconds
Started May 19 02:29:09 PM PDT 24
Finished May 19 02:31:53 PM PDT 24
Peak memory 256968 kb
Host smart-d01ce66b-ed12-4312-94c4-f19c2477f2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28195
8592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.281958592
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.280583257
Short name T645
Test name
Test status
Simulation time 84401579 ps
CPU time 9.45 seconds
Started May 19 02:29:06 PM PDT 24
Finished May 19 02:29:17 PM PDT 24
Peak memory 256312 kb
Host smart-653d6389-66ef-4bbe-80c4-7d42f130b98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
3257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.280583257
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3787219932
Short name T284
Test name
Test status
Simulation time 21659057784 ps
CPU time 990.04 seconds
Started May 19 02:29:04 PM PDT 24
Finished May 19 02:45:36 PM PDT 24
Peak memory 281012 kb
Host smart-200a800e-6fb5-4bb8-aaf4-1c5abe723c72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787219932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3787219932
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.913799391
Short name T28
Test name
Test status
Simulation time 182636984844 ps
CPU time 2842.54 seconds
Started May 19 02:29:07 PM PDT 24
Finished May 19 03:16:30 PM PDT 24
Peak memory 289540 kb
Host smart-fe672647-c4fa-4b98-8169-616a8e53d7bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913799391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.913799391
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2666440533
Short name T585
Test name
Test status
Simulation time 26447685693 ps
CPU time 269.22 seconds
Started May 19 02:29:05 PM PDT 24
Finished May 19 02:33:35 PM PDT 24
Peak memory 247040 kb
Host smart-a09719fa-32c7-4879-9782-8a09bc575753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666440533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2666440533
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3611501671
Short name T236
Test name
Test status
Simulation time 2944931359 ps
CPU time 45.85 seconds
Started May 19 02:29:01 PM PDT 24
Finished May 19 02:29:49 PM PDT 24
Peak memory 256108 kb
Host smart-183d1f1e-8f51-4f8c-9b27-0160785fe8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36115
01671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3611501671
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3936615651
Short name T666
Test name
Test status
Simulation time 702068562 ps
CPU time 43.14 seconds
Started May 19 02:29:00 PM PDT 24
Finished May 19 02:29:44 PM PDT 24
Peak memory 249180 kb
Host smart-4ecaf1df-a164-4740-8bbc-4ca6bc6b198e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39366
15651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3936615651
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2733189245
Short name T256
Test name
Test status
Simulation time 378298003 ps
CPU time 41.28 seconds
Started May 19 02:29:06 PM PDT 24
Finished May 19 02:29:49 PM PDT 24
Peak memory 256728 kb
Host smart-aec5dfa9-ed71-4078-9e4d-d7ed35c30de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27331
89245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2733189245
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3088538765
Short name T590
Test name
Test status
Simulation time 218978073 ps
CPU time 13.81 seconds
Started May 19 02:29:02 PM PDT 24
Finished May 19 02:29:17 PM PDT 24
Peak memory 248744 kb
Host smart-53808fec-67bb-472a-bbce-eb30570a2ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30885
38765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3088538765
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2884067926
Short name T86
Test name
Test status
Simulation time 131200322282 ps
CPU time 1284.96 seconds
Started May 19 02:29:04 PM PDT 24
Finished May 19 02:50:30 PM PDT 24
Peak memory 288384 kb
Host smart-c7b4bfab-acf4-4603-b9b4-ceb79e093299
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884067926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2884067926
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%