Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	50489	1			T7	146		T35	7		T14	58
class_i[0x1]	60753	1			T7	7		T14	50		T37	4
class_i[0x2]	63319	1			T7	10		T35	11		T14	19
class_i[0x3]	59008	1			T35	5		T14	11		T16	103

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	57521	1			T7	6		T35	2		T14	51
alert[0x1]	60776	1			T7	1		T35	5		T14	42
alert[0x2]	59298	1			T7	147		T35	1		T14	19
alert[0x3]	55974	1			T7	9		T35	15		T14	26

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

233291

1

T7

163

T35

23

T14

138

esc_ping_fail

278

1

T96

3

T64

3

T114

11

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	57444	1			T7	6		T35	2		T14	51
esc_integrity_fail	alert[0x1]	60708	1			T7	1		T35	5		T14	42
esc_integrity_fail	alert[0x2]	59225	1			T7	147		T35	1		T14	19
esc_integrity_fail	alert[0x3]	55914	1			T7	9		T35	15		T14	26
esc_ping_fail	alert[0x0]	77	1			T64	1		T114	3		T274	1
esc_ping_fail	alert[0x1]	68	1			T96	1		T64	1		T114	2
esc_ping_fail	alert[0x2]	73	1			T96	1		T64	1		T114	4
esc_ping_fail	alert[0x3]	60	1			T96	1		T114	2		T275	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	50410	1			T7	146		T35	7		T14	58
esc_integrity_fail	class_i[0x1]	60706	1			T7	7		T14	50		T37	4
esc_integrity_fail	class_i[0x2]	63258	1			T7	10		T35	11		T14	19
esc_integrity_fail	class_i[0x3]	58917	1			T35	5		T14	11		T16	103
esc_ping_fail	class_i[0x0]	79	1			T114	11		T278	1		T284	7
esc_ping_fail	class_i[0x1]	47	1			T274	1		T277	3		T276	4
esc_ping_fail	class_i[0x2]	61	1			T96	3		T239	6		T282	3
esc_ping_fail	class_i[0x3]	91	1			T64	3		T275	7		T273	8