Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	177	1			T1	1		T3	1		T6	1
index[0x1]	187	1			T2	1		T3	3		T37	1
index[0x2]	167	1			T1	1		T2	2		T6	2
index[0x3]	164	1			T6	1		T7	1		T14	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	210	1			T1	1		T2	2		T3	3
lens_less_than_1000[1]	142	1			T2	1		T3	1		T14	1
lens_less_than_1000[2]	103	1			T35	1		T14	1		T39	1
lens_less_than_1000[3]	76	1			T6	1		T16	2		T66	1
lens_less_than_1000[4]	51	1			T6	2		T20	2		T93	2
lens_less_than_1000[5]	33	1			T1	1		T6	1		T16	2
lens_less_than_1000[6]	34	1			T14	1		T41	2		T99	1
lens_less_than_1000[7]	24	1			T42	1		T19	1		T76	1
lens_less_than_1000[8]	11	1			T99	1		T42	1		T50	1
lens_less_than_1000[9]	3	1			T228	1		T229	1		T230	1
len_2	8	1			T44	1		T51	1		T89	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2]]	[len_2]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	40	1			T9	1		T14	2		T16	1
index[0x0]	lens_less_than_1000[1]	45	1			T3	1		T39	2		T16	1
index[0x0]	lens_less_than_1000[2]	29	1			T14	1		T231	1		T48	1
index[0x0]	lens_less_than_1000[3]	21	1			T6	1		T16	1		T42	1
index[0x0]	lens_less_than_1000[4]	19	1			T20	1		T93	1		T32	1
index[0x0]	lens_less_than_1000[5]	7	1			T1	1		T70	1		T47	1
index[0x0]	lens_less_than_1000[6]	6	1			T41	1		T99	1		T232	1
index[0x0]	lens_less_than_1000[7]	6	1			T92	1		T89	2		T233	1
index[0x0]	lens_less_than_1000[8]	3	1			T42	1		T51	1		T89	1
index[0x0]	len_2	1	1			T234	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	62	1			T3	3		T37	1		T66	1
index[0x1]	lens_less_than_1000[1]	40	1			T2	1		T16	1		T18	2
index[0x1]	lens_less_than_1000[2]	27	1			T47	1		T49	2		T235	1
index[0x1]	lens_less_than_1000[3]	21	1			T46	1		T112	1		T212	1
index[0x1]	lens_less_than_1000[4]	9	1			T92	1		T186	1		T236	1
index[0x1]	lens_less_than_1000[5]	6	1			T44	1		T237	1		T102	1
index[0x1]	lens_less_than_1000[6]	9	1			T76	1		T50	2		T238	1
index[0x1]	lens_less_than_1000[7]	5	1			T239	1		T50	1		T232	1
index[0x1]	lens_less_than_1000[8]	2	1			T50	1		T240	1		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T230	1		-	-		-	-
index[0x1]	len_2	5	1			T51	1		T89	2		T103	1
index[0x2]	lens_less_than_1000[0]	58	1			T1	1		T2	2		T14	2
index[0x2]	lens_less_than_1000[1]	28	1			T14	1		T42	1		T19	1
index[0x2]	lens_less_than_1000[2]	24	1			T35	1		T39	1		T66	1
index[0x2]	lens_less_than_1000[3]	17	1			T19	1		T44	1		T241	1
index[0x2]	lens_less_than_1000[4]	11	1			T6	1		T20	1		T93	1
index[0x2]	lens_less_than_1000[5]	10	1			T6	1		T16	2		T66	1
index[0x2]	lens_less_than_1000[6]	5	1			T232	1		T242	1		T243	1
index[0x2]	lens_less_than_1000[7]	8	1			T42	1		T76	1		T92	1
index[0x2]	lens_less_than_1000[8]	4	1			T99	1		T177	1		T235	1
index[0x2]	lens_less_than_1000[9]	2	1			T228	1		T229	1		-	-
index[0x3]	lens_less_than_1000[0]	50	1			T7	1		T16	1		T42	2
index[0x3]	lens_less_than_1000[1]	29	1			T37	1		T19	1		T244	1
index[0x3]	lens_less_than_1000[2]	23	1			T245	1		T23	1		T244	1
index[0x3]	lens_less_than_1000[3]	17	1			T16	1		T66	1		T23	1
index[0x3]	lens_less_than_1000[4]	12	1			T6	1		T28	1		T52	1
index[0x3]	lens_less_than_1000[5]	10	1			T42	1		T246	1		T115	1
index[0x3]	lens_less_than_1000[6]	14	1			T14	1		T41	1		T44	2
index[0x3]	lens_less_than_1000[7]	5	1			T19	1		T233	2		T247	1
index[0x3]	lens_less_than_1000[8]	2	1			T235	1		T248	1		-	-
index[0x3]	len_2	2	1			T44	1		T249	1		-	-