Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	71	1			T14	1		T15	1		T16	2
class_index[0x1]	69	1			T42	1		T27	1		T32	4
class_index[0x2]	60	1			T16	1		T29	1		T32	1
class_index[0x3]	71	1			T16	3		T71	2		T42	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T14	1		T15	1		T71	2
intr_timeout_cnt[1]	52	1			T16	2		T76	2		T105	1
intr_timeout_cnt[2]	27	1			T32	4		T76	1		T46	1
intr_timeout_cnt[3]	15	1			T16	1		T250	2		T78	1
intr_timeout_cnt[4]	12	1			T19	1		T32	1		T51	1
intr_timeout_cnt[5]	21	1			T16	1		T76	1		T79	1
intr_timeout_cnt[6]	15	1			T16	1		T74	1		T23	2
intr_timeout_cnt[7]	7	1			T42	1		T49	1		T251	1
intr_timeout_cnt[8]	13	1			T16	1		T42	3		T33	1
intr_timeout_cnt[9]	7	1			T76	1		T104	1		T252	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	24	1			T14	1		T15	1		T75	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T76	1		T49	2		T177	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T76	1		T92	1		T89	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T16	1		T92	1		T253	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T254	1		T88	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	5	1			T16	1		T79	1		T251	1
class_index[0x0]	intr_timeout_cnt[6]	7	1			T74	1		T23	2		T32	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T42	1		T33	1		T238	1
class_index[0x0]	intr_timeout_cnt[9]	5	1			T76	1		T104	1		T252	1
class_index[0x1]	intr_timeout_cnt[0]	26	1			T27	1		T76	1		T77	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T51	1		T255	1		T251	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T32	3		T92	1		T256	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T78	1		T17	1		T257	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T32	1		T254	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	9	1			T76	1		T80	5		T252	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T79	1		T233	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T42	1		T258	3		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T108	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	23	1			T29	1		T32	1		T33	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T76	1		T82	1		T259	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T46	1		T177	3		T51	2
class_index[0x2]	intr_timeout_cnt[3]	1	1			T257	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	3	1			T51	1		T89	1		T260	1
class_index[0x2]	intr_timeout_cnt[5]	5	1			T261	1		T262	2		T263	1
class_index[0x2]	intr_timeout_cnt[6]	4	1			T16	1		T76	1		T53	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T264	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	5	1			T233	1		T265	1		T103	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T266	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	29	1			T71	2		T42	1		T109	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T16	2		T105	1		T51	2
class_index[0x3]	intr_timeout_cnt[2]	8	1			T32	1		T110	1		T252	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T250	2		T79	1		T267	1
class_index[0x3]	intr_timeout_cnt[4]	5	1			T19	1		T268	1		T262	3
class_index[0x3]	intr_timeout_cnt[5]	2	1			T80	2		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T103	1		T263	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T49	1		T251	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T16	1		T42	2		T78	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T269	1		-	-		-	-