Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	366886	1			T1	1789		T2	35		T3	1573
all_values[1]	366886	1			T1	1789		T2	35		T3	1573
all_values[2]	366886	1			T1	1789		T2	35		T3	1573
all_values[3]	366886	1			T1	1789		T2	35		T3	1573

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

730581

1

T1

3578

T2

72

T3

3117

auto[1]

736963

1

T1

3578

T2

68

T3

3175

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

879239

1

T1

3871

T2

73

T3

3156

auto[1]

588305

1

T1

3285

T2

67

T3

3136

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106184	1			T1	525		T2	13		T3	405
all_values[0]	auto[0]	auto[1]	76885	1			T1	322		T2	10		T3	400
all_values[0]	auto[1]	auto[0]	107014	1			T1	573		T2	6		T3	385
all_values[0]	auto[1]	auto[1]	76803	1			T1	369		T2	6		T3	383
all_values[1]	auto[0]	auto[0]	111612	1			T1	470		T2	8		T3	379
all_values[1]	auto[0]	auto[1]	71029	1			T1	445		T2	7		T3	378
all_values[1]	auto[1]	auto[0]	112723	1			T1	447		T2	10		T3	408
all_values[1]	auto[1]	auto[1]	71522	1			T1	427		T2	10		T3	408
all_values[2]	auto[0]	auto[0]	109484	1			T1	461		T2	10		T3	380
all_values[2]	auto[0]	auto[1]	72747	1			T1	408		T2	9		T3	380
all_values[2]	auto[1]	auto[0]	111305	1			T1	486		T2	8		T3	412
all_values[2]	auto[1]	auto[1]	73350	1			T1	434		T2	8		T3	401
all_values[3]	auto[0]	auto[0]	109713	1			T1	480		T2	8		T3	398
all_values[3]	auto[0]	auto[1]	72927	1			T1	467		T2	7		T3	397
all_values[3]	auto[1]	auto[0]	111204	1			T1	429		T2	10		T3	389
all_values[3]	auto[1]	auto[1]	73042	1			T1	413		T2	10		T3	389