Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	366886	1			T1	1789		T2	35		T3	1573
all_pins[1]	366886	1			T1	1789		T2	35		T3	1573
all_pins[2]	366886	1			T1	1789		T2	35		T3	1573
all_pins[3]	366886	1			T1	1789		T2	35		T3	1573

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1172827	1			T1	5513		T2	106		T3	4711
values[0x1]	294717	1			T1	1643		T2	34		T3	1581
transitions[0x0=>0x1]	195792	1			T1	1076		T2	20		T3	960
transitions[0x1=>0x0]	196054	1			T1	1076		T2	20		T3	961

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	290083	1			T1	1420		T2	29		T3	1190
all_pins[0]	values[0x1]	76803	1			T1	369		T2	6		T3	383
all_pins[0]	transitions[0x0=>0x1]	76122	1			T1	369		T2	6		T3	382
all_pins[0]	transitions[0x1=>0x0]	72623	1			T1	413		T2	10		T3	389
all_pins[1]	values[0x0]	295364	1			T1	1362		T2	25		T3	1165
all_pins[1]	values[0x1]	71522	1			T1	427		T2	10		T3	408
all_pins[1]	transitions[0x0=>0x1]	39191	1			T1	254		T2	5		T3	204
all_pins[1]	transitions[0x1=>0x0]	44472	1			T1	196		T2	1		T3	179
all_pins[2]	values[0x0]	293536	1			T1	1355		T2	27		T3	1172
all_pins[2]	values[0x1]	73350	1			T1	434		T2	8		T3	401
all_pins[2]	transitions[0x0=>0x1]	40589	1			T1	233		T2	4		T3	193
all_pins[2]	transitions[0x1=>0x0]	38761	1			T1	226		T2	6		T3	200
all_pins[3]	values[0x0]	293844	1			T1	1376		T2	25		T3	1184
all_pins[3]	values[0x1]	73042	1			T1	413		T2	10		T3	389
all_pins[3]	transitions[0x0=>0x1]	39890	1			T1	220		T2	5		T3	181
all_pins[3]	transitions[0x1=>0x0]	40198	1			T1	241		T2	3		T3	193