Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T154	4		T155	4		T156	4
all_values[1]	287	1			T154	4		T155	4		T156	4
all_values[2]	287	1			T154	4		T155	4		T156	4
all_values[3]	287	1			T154	4		T155	4		T156	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T154

9

T155

13

T156

6

auto[1]

533

1

T154

7

T155

3

T156

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

428

1

T154

8

T155

7

T156

6

auto[1]

720

1

T154

8

T155

9

T156

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660

1

T154

11

T155

9

T156

9

auto[1]

488

1

T154

5

T155

7

T156

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T154

1

T317

1

T318

3

all_values[0]

auto[0]

auto[0]

auto[1]

31

1

T156

1

T318

1

T319

1

all_values[0]

auto[0]

auto[1]

auto[0]

49

1

T155

2

T156

2

T215

2

all_values[0]

auto[0]

auto[1]

auto[1]

31

1

T154

1

T317

3

T320

1

all_values[0]

auto[1]

auto[0]

auto[1]

63

1

T154

1

T155

1

T156

1

all_values[0]

auto[1]

auto[1]

auto[1]

54

1

T154

1

T155

1

T224

2

all_values[1]

auto[0]

auto[0]

auto[0]

43

1

T155

1

T215

2

T224

4

all_values[1]

auto[0]

auto[0]

auto[1]

36

1

T154

2

T155

1

T318

1

all_values[1]

auto[0]

auto[1]

auto[0]

61

1

T156

1

T224

1

T317

1

all_values[1]

auto[0]

auto[1]

auto[1]

23

1

T156

1

T319

1

T321

1

all_values[1]

auto[1]

auto[0]

auto[1]

76

1

T154

2

T155

2

T156

1

all_values[1]

auto[1]

auto[1]

auto[1]

48

1

T156

1

T215

1

T224

1

all_values[2]

auto[0]

auto[0]

auto[0]

57

1

T154

1

T155

1

T215

1

all_values[2]

auto[0]

auto[0]

auto[1]

34

1

T155

1

T156

1

T215

1

all_values[2]

auto[0]

auto[1]

auto[0]

49

1

T154

2

T224

1

T322

3

all_values[2]

auto[0]

auto[1]

auto[1]

22

1

T224

1

T317

1

T319

1

all_values[2]

auto[1]

auto[0]

auto[1]

74

1

T154

1

T155

2

T156

1

all_values[2]

auto[1]

auto[1]

auto[1]

51

1

T156

2

T215

1

T224

2

all_values[3]

auto[0]

auto[0]

auto[0]

48

1

T154

1

T155

3

T215

1

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T215

1

T224

1

T322

3

all_values[3]

auto[0]

auto[1]

auto[0]

62

1

T154

3

T156

3

T215

1

all_values[3]

auto[0]

auto[1]

auto[1]

27

1

T318

2

T321

1

T323

1

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T155

1

T156

1

T215

1

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T224

2

T317

1

T318

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal