Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	96349	1			T3	1019		T6	1120		T35	112
accum_cnt_1000	222752	1			T1	1194		T3	864		T6	1133
accum_cnt_100	26632	1			T1	1402		T2	3		T3	44
accum_cnt_50	69185	1			T1	59		T2	25		T3	41
accum_cnt_10	191265	1			T1	2685		T2	43		T3	23
accum_cnt_0	431141	1			T1	12		T2	29		T3	2327

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	270962	1			T1	1338		T2	25		T3	1161
class_index[0x1]	270962	1			T1	1338		T2	25		T3	1161
class_index[0x2]	270962	1			T1	1338		T2	25		T3	1161
class_index[0x3]	270962	1			T1	1338		T2	25		T3	1161

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	29384	1			T6	482		T72	421		T42	275
class_index[0x0]	accum_cnt_1000	59279	1			T1	1194		T6	427		T14	26
class_index[0x0]	accum_cnt_100	6570	1			T1	68		T6	27		T14	22
class_index[0x0]	accum_cnt_50	15891	1			T1	59		T4	4		T6	18
class_index[0x0]	accum_cnt_10	51051	1			T1	13		T2	25		T4	7
class_index[0x0]	accum_cnt_0	91240	1			T1	4		T3	1161		T4	4
class_index[0x1]	accum_cnt_2000	21567	1			T3	519		T6	638		T37	527
class_index[0x1]	accum_cnt_1000	56990	1			T3	441		T6	706		T14	21
class_index[0x1]	accum_cnt_100	6927	1			T3	23		T6	35		T14	23
class_index[0x1]	accum_cnt_50	16272	1			T2	8		T3	21		T6	27
class_index[0x1]	accum_cnt_10	52910	1			T1	1332		T2	12		T3	11
class_index[0x1]	accum_cnt_0	106872	1			T1	6		T2	5		T3	3
class_index[0x2]	accum_cnt_2000	21617	1			T14	165		T37	223		T16	275
class_index[0x2]	accum_cnt_1000	52985	1			T14	810		T37	218		T16	248
class_index[0x2]	accum_cnt_100	5918	1			T2	3		T14	56		T37	12
class_index[0x2]	accum_cnt_50	18066	1			T2	17		T14	46		T37	6
class_index[0x2]	accum_cnt_10	43362	1			T1	1338		T2	4		T3	1
class_index[0x2]	accum_cnt_0	118648	1			T2	1		T3	1160		T4	15
class_index[0x3]	accum_cnt_2000	23781	1			T3	500		T35	112		T14	493
class_index[0x3]	accum_cnt_1000	53498	1			T3	423		T35	558		T14	481
class_index[0x3]	accum_cnt_100	7217	1			T1	1334		T3	21		T35	34
class_index[0x3]	accum_cnt_50	18956	1			T3	20		T8	4		T35	16
class_index[0x3]	accum_cnt_10	43942	1			T1	2		T2	2		T3	11
class_index[0x3]	accum_cnt_0	114381	1			T1	2		T2	23		T3	3