Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9547	1			T1	238		T72	26		T19	10
alert[0x1]	3974	1			T1	48		T72	4		T42	80
alert[0x2]	3187	1			T72	87		T22	43		T19	2
alert[0x3]	3118	1			T1	68		T35	2		T72	23
alert[0x4]	1584	1			T18	1		T72	130		T42	113
alert[0x5]	9679	1			T1	87		T16	5		T19	4
alert[0x6]	5306	1			T35	1		T40	1		T72	47
alert[0x7]	7798	1			T1	25		T35	1		T16	16
alert[0x8]	7408	1			T1	374		T42	228		T67	22
alert[0x9]	8617	1			T42	516		T22	299		T114	1
alert[0xa]	2661	1			T1	305		T18	1		T42	4
alert[0xb]	4993	1			T273	1		T76	12		T115	1
alert[0xc]	6616	1			T1	143		T35	2		T37	12
alert[0xd]	4615	1			T35	11		T72	12		T42	5
alert[0xe]	7936	1			T1	110		T35	2		T42	26
alert[0xf]	6191	1			T1	58		T16	2		T42	527
alert[0x10]	10938	1			T1	89		T72	143		T19	1
alert[0x11]	5839	1			T72	134		T67	4		T274	1
alert[0x12]	7918	1			T1	3		T42	19		T67	2
alert[0x13]	12099	1			T18	1		T22	8		T70	35
alert[0x14]	11249	1			T35	2		T37	2		T42	51
alert[0x15]	6139	1			T42	12		T275	1		T29	2396
alert[0x16]	5175	1			T16	1		T96	1		T72	152
alert[0x17]	3044	1			T23	1		T46	60		T210	23
alert[0x18]	4106	1			T1	340		T16	4		T72	493
alert[0x19]	3897	1			T35	1		T72	60		T42	1
alert[0x1a]	8729	1			T1	240		T37	3		T16	19
alert[0x1b]	1997	1			T1	1		T7	5		T96	1
alert[0x1c]	5955	1			T18	2		T66	2		T42	83
alert[0x1d]	8927	1			T64	1		T42	145		T70	41
alert[0x1e]	4777	1			T1	17		T72	84		T29	158
alert[0x1f]	4939	1			T1	3		T14	21		T64	1
alert[0x20]	5706	1			T16	2		T275	1		T273	1
alert[0x21]	8664	1			T72	309		T22	129		T70	78
alert[0x22]	13310	1			T35	17		T16	2		T72	338
alert[0x23]	6856	1			T72	41		T42	515		T22	46
alert[0x24]	6057	1			T35	4		T14	2		T42	2165
alert[0x25]	7707	1			T14	1		T18	1		T29	205
alert[0x26]	4646	1			T72	35		T42	8		T276	1
alert[0x27]	9492	1			T14	76		T16	51		T72	216
alert[0x28]	4306	1			T14	6		T18	2		T72	11
alert[0x29]	20769	1			T1	28		T16	3		T275	1
alert[0x2a]	13717	1			T1	3818		T72	247		T22	14
alert[0x2b]	10927	1			T1	40		T98	1		T19	1
alert[0x2c]	15791	1			T35	11		T72	8131		T22	53
alert[0x2d]	3506	1			T66	4		T72	343		T19	1
alert[0x2e]	5844	1			T72	254		T22	75		T70	412
alert[0x2f]	6515	1			T35	1		T42	4		T22	149
alert[0x30]	11896	1			T14	7		T18	1		T72	2591
alert[0x31]	18292	1			T35	52		T72	497		T42	26
alert[0x32]	4383	1			T35	6		T72	808		T42	44
alert[0x33]	7901	1			T14	4		T72	30		T42	9
alert[0x34]	3334	1			T1	6		T14	1		T96	1
alert[0x35]	11294	1			T42	2		T19	4		T29	466
alert[0x36]	6106	1			T1	27		T64	1		T275	1
alert[0x37]	13273	1			T14	9		T64	1		T66	1
alert[0x38]	6865	1			T22	222		T19	2		T70	75
alert[0x39]	2159	1			T35	1		T14	2		T96	1
alert[0x3a]	6782	1			T72	1574		T42	442		T70	183
alert[0x3b]	4095	1			T96	1		T42	9		T19	58
alert[0x3c]	5230	1			T14	6		T16	5		T19	1
alert[0x3d]	8510	1			T1	1542		T72	112		T42	368
alert[0x3e]	5121	1			T1	85		T275	1		T277	1
alert[0x3f]	6928	1			T1	52		T22	123		T19	4
alert[0x40]	6319	1			T14	2		T42	23		T19	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	140129	1			T35	24		T37	17		T40	1
class_i[0x1]	85688	1			T35	57		T14	109		T98	1
class_i[0x2]	143788	1			T7	5		T35	5		T14	28
class_i[0x3]	101654	1			T1	7747		T35	28		T96	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

470596

1

T1

7747

T7

5

T35

114

alert_ping_fail

663

1

T40

1

T96

6

T98

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9541	1			T1	238		T72	26		T19	10
alert_integrity_fail	alert[0x1]	3960	1			T1	48		T72	4		T42	80
alert_integrity_fail	alert[0x2]	3181	1			T72	87		T22	43		T19	2
alert_integrity_fail	alert[0x3]	3110	1			T1	68		T35	2		T72	23
alert_integrity_fail	alert[0x4]	1578	1			T18	1		T72	130		T42	113
alert_integrity_fail	alert[0x5]	9664	1			T1	87		T16	5		T19	4
alert_integrity_fail	alert[0x6]	5289	1			T35	1		T72	47		T42	8
alert_integrity_fail	alert[0x7]	7787	1			T1	25		T35	1		T16	16
alert_integrity_fail	alert[0x8]	7399	1			T1	374		T42	228		T67	22
alert_integrity_fail	alert[0x9]	8611	1			T42	516		T22	299		T29	4
alert_integrity_fail	alert[0xa]	2644	1			T1	305		T18	1		T42	4
alert_integrity_fail	alert[0xb]	4989	1			T76	12		T115	1		T48	30
alert_integrity_fail	alert[0xc]	6610	1			T1	143		T35	2		T37	12
alert_integrity_fail	alert[0xd]	4608	1			T35	11		T72	12		T42	5
alert_integrity_fail	alert[0xe]	7922	1			T1	110		T35	2		T42	26
alert_integrity_fail	alert[0xf]	6182	1			T1	58		T16	2		T42	527
alert_integrity_fail	alert[0x10]	10928	1			T1	89		T72	143		T19	1
alert_integrity_fail	alert[0x11]	5832	1			T72	134		T67	4		T23	16
alert_integrity_fail	alert[0x12]	7912	1			T1	3		T42	19		T67	2
alert_integrity_fail	alert[0x13]	12082	1			T18	1		T22	8		T70	35
alert_integrity_fail	alert[0x14]	11240	1			T35	2		T37	2		T42	51
alert_integrity_fail	alert[0x15]	6125	1			T42	12		T29	2396		T115	4
alert_integrity_fail	alert[0x16]	5162	1			T16	1		T72	152		T42	263
alert_integrity_fail	alert[0x17]	3034	1			T23	1		T46	60		T210	23
alert_integrity_fail	alert[0x18]	4093	1			T1	340		T16	4		T72	493
alert_integrity_fail	alert[0x19]	3891	1			T35	1		T72	60		T42	1
alert_integrity_fail	alert[0x1a]	8723	1			T1	240		T37	3		T16	19
alert_integrity_fail	alert[0x1b]	1986	1			T1	1		T7	5		T22	38
alert_integrity_fail	alert[0x1c]	5946	1			T18	2		T66	2		T42	83
alert_integrity_fail	alert[0x1d]	8915	1			T42	145		T70	41		T76	11
alert_integrity_fail	alert[0x1e]	4763	1			T1	17		T72	84		T29	158
alert_integrity_fail	alert[0x1f]	4927	1			T1	3		T14	21		T42	210
alert_integrity_fail	alert[0x20]	5695	1			T16	2		T29	1486		T76	186
alert_integrity_fail	alert[0x21]	8656	1			T72	309		T22	129		T70	78
alert_integrity_fail	alert[0x22]	13301	1			T35	17		T16	2		T72	338
alert_integrity_fail	alert[0x23]	6853	1			T72	41		T42	515		T22	46
alert_integrity_fail	alert[0x24]	6045	1			T35	4		T14	2		T42	2165
alert_integrity_fail	alert[0x25]	7699	1			T14	1		T18	1		T29	205
alert_integrity_fail	alert[0x26]	4638	1			T72	35		T42	8		T48	107
alert_integrity_fail	alert[0x27]	9486	1			T14	76		T16	51		T72	216
alert_integrity_fail	alert[0x28]	4287	1			T14	6		T18	2		T72	11
alert_integrity_fail	alert[0x29]	20754	1			T1	28		T16	3		T210	52
alert_integrity_fail	alert[0x2a]	13705	1			T1	3818		T72	247		T22	14
alert_integrity_fail	alert[0x2b]	10915	1			T1	40		T19	1		T23	5
alert_integrity_fail	alert[0x2c]	15774	1			T35	11		T72	8131		T22	53
alert_integrity_fail	alert[0x2d]	3498	1			T66	4		T72	343		T19	1
alert_integrity_fail	alert[0x2e]	5836	1			T72	254		T22	75		T70	412
alert_integrity_fail	alert[0x2f]	6507	1			T35	1		T42	4		T22	149
alert_integrity_fail	alert[0x30]	11880	1			T14	7		T18	1		T72	2591
alert_integrity_fail	alert[0x31]	18282	1			T35	52		T72	497		T42	26
alert_integrity_fail	alert[0x32]	4375	1			T35	6		T72	808		T42	44
alert_integrity_fail	alert[0x33]	7889	1			T14	4		T72	30		T42	9
alert_integrity_fail	alert[0x34]	3320	1			T1	6		T14	1		T42	981
alert_integrity_fail	alert[0x35]	11287	1			T42	2		T19	4		T29	466
alert_integrity_fail	alert[0x36]	6096	1			T1	27		T104	65		T79	2
alert_integrity_fail	alert[0x37]	13262	1			T14	9		T66	1		T19	13
alert_integrity_fail	alert[0x38]	6851	1			T22	222		T19	2		T70	75
alert_integrity_fail	alert[0x39]	2154	1			T35	1		T14	2		T42	105
alert_integrity_fail	alert[0x3a]	6777	1			T72	1574		T42	442		T70	183
alert_integrity_fail	alert[0x3b]	4079	1			T42	9		T19	58		T23	16
alert_integrity_fail	alert[0x3c]	5224	1			T14	6		T16	5		T19	1
alert_integrity_fail	alert[0x3d]	8500	1			T1	1542		T72	112		T42	368
alert_integrity_fail	alert[0x3e]	5102	1			T1	85		T32	3		T76	399
alert_integrity_fail	alert[0x3f]	6920	1			T1	52		T22	123		T19	4
alert_integrity_fail	alert[0x40]	6315	1			T14	2		T42	23		T19	1
alert_ping_fail	alert[0x0]	6	1			T278	1		T279	1		T280	1
alert_ping_fail	alert[0x1]	14	1			T275	1		T281	1		T279	1
alert_ping_fail	alert[0x2]	6	1			T282	1		T113	1		T283	1
alert_ping_fail	alert[0x3]	8	1			T284	1		T239	1		T285	1
alert_ping_fail	alert[0x4]	6	1			T273	2		T241	1		T239	1
alert_ping_fail	alert[0x5]	15	1			T273	1		T277	1		T278	1
alert_ping_fail	alert[0x6]	17	1			T40	1		T114	1		T273	1
alert_ping_fail	alert[0x7]	11	1			T96	1		T275	2		T277	1
alert_ping_fail	alert[0x8]	9	1			T231	1		T113	1		T286	2
alert_ping_fail	alert[0x9]	6	1			T114	1		T280	1		T287	1
alert_ping_fail	alert[0xa]	17	1			T281	1		T284	1		T282	1
alert_ping_fail	alert[0xb]	4	1			T273	1		T241	1		T282	1
alert_ping_fail	alert[0xc]	6	1			T279	1		T283	1		T280	1
alert_ping_fail	alert[0xd]	7	1			T279	1		T288	1		T289	1
alert_ping_fail	alert[0xe]	14	1			T114	1		T278	1		T290	2
alert_ping_fail	alert[0xf]	9	1			T274	1		T290	1		T284	1
alert_ping_fail	alert[0x10]	10	1			T275	1		T281	1		T239	1
alert_ping_fail	alert[0x11]	7	1			T274	1		T241	1		T282	1
alert_ping_fail	alert[0x12]	6	1			T114	2		T286	1		T291	1
alert_ping_fail	alert[0x13]	17	1			T114	1		T273	3		T113	2
alert_ping_fail	alert[0x14]	9	1			T114	1		T273	1		T290	1
alert_ping_fail	alert[0x15]	14	1			T275	1		T276	1		T284	1
alert_ping_fail	alert[0x16]	13	1			T96	1		T276	2		T113	1
alert_ping_fail	alert[0x17]	10	1			T282	1		T113	1		T292	1
alert_ping_fail	alert[0x18]	13	1			T273	1		T281	1		T241	1
alert_ping_fail	alert[0x19]	6	1			T114	1		T290	1		T279	1
alert_ping_fail	alert[0x1a]	6	1			T274	1		T279	1		T285	1
alert_ping_fail	alert[0x1b]	11	1			T96	1		T281	1		T279	2
alert_ping_fail	alert[0x1c]	9	1			T279	1		T292	1		T283	1
alert_ping_fail	alert[0x1d]	12	1			T64	1		T114	1		T273	1
alert_ping_fail	alert[0x1e]	14	1			T113	1		T283	2		T293	2
alert_ping_fail	alert[0x1f]	12	1			T64	1		T114	1		T276	1
alert_ping_fail	alert[0x20]	11	1			T275	1		T273	1		T277	1
alert_ping_fail	alert[0x21]	8	1			T275	1		T278	1		T279	1
alert_ping_fail	alert[0x22]	9	1			T277	1		T271	1		T282	1
alert_ping_fail	alert[0x23]	3	1			T114	1		T291	1		T294	1
alert_ping_fail	alert[0x24]	12	1			T275	1		T278	1		T281	1
alert_ping_fail	alert[0x25]	8	1			T284	1		T279	2		T285	1
alert_ping_fail	alert[0x26]	8	1			T276	1		T113	1		T292	1
alert_ping_fail	alert[0x27]	6	1			T274	1		T275	1		T273	1
alert_ping_fail	alert[0x28]	19	1			T114	2		T278	1		T284	1
alert_ping_fail	alert[0x29]	15	1			T275	1		T273	1		T278	1
alert_ping_fail	alert[0x2a]	12	1			T275	1		T277	1		T239	1
alert_ping_fail	alert[0x2b]	12	1			T98	1		T114	1		T271	1
alert_ping_fail	alert[0x2c]	17	1			T114	1		T275	1		T273	1
alert_ping_fail	alert[0x2d]	8	1			T273	1		T281	1		T113	1
alert_ping_fail	alert[0x2e]	8	1			T274	1		T275	1		T241	2
alert_ping_fail	alert[0x2f]	8	1			T286	1		T295	1		T296	1
alert_ping_fail	alert[0x30]	16	1			T274	1		T276	1		T284	1
alert_ping_fail	alert[0x31]	10	1			T114	1		T275	1		T278	1
alert_ping_fail	alert[0x32]	8	1			T278	1		T284	1		T113	1
alert_ping_fail	alert[0x33]	12	1			T277	1		T284	1		T241	1
alert_ping_fail	alert[0x34]	14	1			T96	1		T274	1		T290	2
alert_ping_fail	alert[0x35]	7	1			T282	1		T113	1		T288	1
alert_ping_fail	alert[0x36]	10	1			T64	1		T275	1		T278	1
alert_ping_fail	alert[0x37]	11	1			T64	1		T114	1		T275	1
alert_ping_fail	alert[0x38]	14	1			T275	1		T273	1		T239	1
alert_ping_fail	alert[0x39]	5	1			T96	1		T113	1		T285	1
alert_ping_fail	alert[0x3a]	5	1			T278	1		T113	1		T285	1
alert_ping_fail	alert[0x3b]	16	1			T96	1		T114	1		T275	1
alert_ping_fail	alert[0x3c]	6	1			T281	1		T282	1		T293	1
alert_ping_fail	alert[0x3d]	10	1			T114	1		T273	1		T239	2
alert_ping_fail	alert[0x3e]	19	1			T275	1		T277	1		T278	1
alert_ping_fail	alert[0x3f]	8	1			T114	1		T284	1		T241	1
alert_ping_fail	alert[0x40]	4	1			T281	1		T292	1		T297	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	140004	1			T35	24		T37	17		T66	5
alert_integrity_fail	class_i[0x1]	85534	1			T35	57		T14	109		T72	6
alert_integrity_fail	class_i[0x2]	143578	1			T7	5		T35	5		T14	28
alert_integrity_fail	class_i[0x3]	101480	1			T1	7747		T35	28		T72	1
alert_ping_fail	class_i[0x0]	125	1			T40	1		T274	2		T275	1
alert_ping_fail	class_i[0x1]	154	1			T98	1		T275	18		T277	2
alert_ping_fail	class_i[0x2]	210	1			T64	4		T274	3		T273	18
alert_ping_fail	class_i[0x3]	174	1			T96	6		T114	20		T274	2