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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.78 100.00 100.00 100.00 99.38 99.60


Total test records in report: 831
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T771 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3742407902 May 26 02:48:22 PM PDT 24 May 26 02:48:26 PM PDT 24 18389201 ps
T772 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2396032849 May 26 02:47:50 PM PDT 24 May 26 02:47:53 PM PDT 24 8948199 ps
T157 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3771006927 May 26 02:47:50 PM PDT 24 May 26 02:49:03 PM PDT 24 973539789 ps
T773 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2560626238 May 26 02:48:21 PM PDT 24 May 26 02:48:24 PM PDT 24 9825119 ps
T774 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1874738529 May 26 02:48:03 PM PDT 24 May 26 02:48:18 PM PDT 24 898272427 ps
T775 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.131179618 May 26 02:48:10 PM PDT 24 May 26 02:48:18 PM PDT 24 60976412 ps
T160 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3549156313 May 26 02:48:04 PM PDT 24 May 26 02:48:09 PM PDT 24 58796878 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2516058933 May 26 02:47:41 PM PDT 24 May 26 02:47:46 PM PDT 24 90338138 ps
T777 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.169879364 May 26 02:47:42 PM PDT 24 May 26 02:47:47 PM PDT 24 20535784 ps
T778 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1413575107 May 26 02:48:03 PM PDT 24 May 26 02:48:31 PM PDT 24 1851928457 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.913032929 May 26 02:48:11 PM PDT 24 May 26 02:48:23 PM PDT 24 66969991 ps
T145 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2547398290 May 26 02:47:52 PM PDT 24 May 26 02:55:18 PM PDT 24 12728411906 ps
T780 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.678208541 May 26 02:47:58 PM PDT 24 May 26 02:48:03 PM PDT 24 121006734 ps
T781 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1273797630 May 26 02:48:05 PM PDT 24 May 26 02:48:08 PM PDT 24 16179852 ps
T782 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3264143070 May 26 02:48:13 PM PDT 24 May 26 02:48:25 PM PDT 24 72871395 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3239459704 May 26 02:47:49 PM PDT 24 May 26 02:47:56 PM PDT 24 107647398 ps
T784 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2855267221 May 26 02:47:48 PM PDT 24 May 26 02:48:02 PM PDT 24 758302426 ps
T785 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3544980900 May 26 02:48:05 PM PDT 24 May 26 02:48:14 PM PDT 24 656009016 ps
T137 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.901081011 May 26 02:47:57 PM PDT 24 May 26 02:53:45 PM PDT 24 19633307904 ps
T139 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2239157826 May 26 02:47:52 PM PDT 24 May 26 02:51:36 PM PDT 24 2885273113 ps
T786 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3707380341 May 26 02:47:58 PM PDT 24 May 26 02:48:04 PM PDT 24 121076766 ps
T148 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1113429881 May 26 02:47:49 PM PDT 24 May 26 02:57:34 PM PDT 24 32384879404 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.366928247 May 26 02:47:43 PM PDT 24 May 26 02:47:53 PM PDT 24 112998061 ps
T788 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2087254202 May 26 02:47:58 PM PDT 24 May 26 02:48:01 PM PDT 24 17712431 ps
T171 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2815412041 May 26 02:47:52 PM PDT 24 May 26 02:47:57 PM PDT 24 205012356 ps
T789 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1887768864 May 26 02:47:55 PM PDT 24 May 26 02:48:03 PM PDT 24 182243684 ps
T790 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3906453623 May 26 02:48:20 PM PDT 24 May 26 02:48:24 PM PDT 24 6823017 ps
T791 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3231417713 May 26 02:47:56 PM PDT 24 May 26 02:48:02 PM PDT 24 400673534 ps
T792 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1019713048 May 26 02:47:57 PM PDT 24 May 26 02:47:59 PM PDT 24 9180345 ps
T793 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.352911389 May 26 02:48:04 PM PDT 24 May 26 02:48:12 PM PDT 24 67737367 ps
T175 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1742314340 May 26 02:48:04 PM PDT 24 May 26 02:48:28 PM PDT 24 565487090 ps
T141 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2815562262 May 26 02:48:12 PM PDT 24 May 26 03:05:36 PM PDT 24 59865276737 ps
T794 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.100261419 May 26 02:47:52 PM PDT 24 May 26 02:48:04 PM PDT 24 91612659 ps
T795 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3386177301 May 26 02:47:58 PM PDT 24 May 26 02:48:43 PM PDT 24 611945463 ps
T796 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3908396102 May 26 02:48:11 PM PDT 24 May 26 02:48:21 PM PDT 24 102833974 ps
T161 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1582017442 May 26 02:47:59 PM PDT 24 May 26 02:48:47 PM PDT 24 342794917 ps
T140 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2748833523 May 26 02:48:13 PM PDT 24 May 26 02:51:24 PM PDT 24 6365114633 ps
T797 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4025221568 May 26 02:48:05 PM PDT 24 May 26 02:48:08 PM PDT 24 8064359 ps
T798 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1428189937 May 26 02:48:09 PM PDT 24 May 26 02:48:23 PM PDT 24 198977396 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.226618346 May 26 02:47:39 PM PDT 24 May 26 02:53:54 PM PDT 24 28938783203 ps
T800 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3381046936 May 26 02:47:47 PM PDT 24 May 26 02:47:57 PM PDT 24 635631408 ps
T801 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3719775694 May 26 02:48:10 PM PDT 24 May 26 02:48:14 PM PDT 24 13826968 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1524653413 May 26 02:47:58 PM PDT 24 May 26 02:48:04 PM PDT 24 128810479 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1947144570 May 26 02:47:40 PM PDT 24 May 26 02:47:43 PM PDT 24 7944884 ps
T804 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3744121691 May 26 02:47:48 PM PDT 24 May 26 02:47:58 PM PDT 24 108859002 ps
T805 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3766305280 May 26 02:48:30 PM PDT 24 May 26 02:48:33 PM PDT 24 10326628 ps
T806 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1154967314 May 26 02:48:16 PM PDT 24 May 26 02:48:22 PM PDT 24 34937155 ps
T807 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.291769007 May 26 02:47:40 PM PDT 24 May 26 02:50:04 PM PDT 24 1113054451 ps
T808 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.535978854 May 26 02:48:15 PM PDT 24 May 26 02:48:18 PM PDT 24 31883277 ps
T809 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3024584961 May 26 02:48:08 PM PDT 24 May 26 02:48:19 PM PDT 24 321011236 ps
T328 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.738483746 May 26 02:47:58 PM PDT 24 May 26 02:58:36 PM PDT 24 16563845360 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1355732379 May 26 02:47:40 PM PDT 24 May 26 02:47:47 PM PDT 24 266317415 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3144759126 May 26 02:47:51 PM PDT 24 May 26 02:50:31 PM PDT 24 4237848817 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1997785327 May 26 02:47:55 PM PDT 24 May 26 02:48:04 PM PDT 24 383498237 ps
T813 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1795847046 May 26 02:48:05 PM PDT 24 May 26 02:48:18 PM PDT 24 274734726 ps
T814 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1025861469 May 26 02:48:11 PM PDT 24 May 26 02:48:17 PM PDT 24 20152673 ps
T815 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1394413832 May 26 02:47:58 PM PDT 24 May 26 02:48:23 PM PDT 24 1225049473 ps
T329 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.624570071 May 26 02:47:49 PM PDT 24 May 26 03:04:54 PM PDT 24 12597698637 ps
T816 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2984299002 May 26 02:48:19 PM PDT 24 May 26 02:48:21 PM PDT 24 10748233 ps
T817 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2507524095 May 26 02:48:20 PM PDT 24 May 26 02:48:24 PM PDT 24 10393586 ps
T818 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3679071930 May 26 02:48:14 PM PDT 24 May 26 02:48:17 PM PDT 24 11169700 ps
T819 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.317232404 May 26 02:48:13 PM PDT 24 May 26 02:48:17 PM PDT 24 9278417 ps
T142 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1446416277 May 26 02:47:45 PM PDT 24 May 26 03:03:12 PM PDT 24 27553597782 ps
T820 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1416760211 May 26 02:48:15 PM PDT 24 May 26 02:48:54 PM PDT 24 1024680694 ps
T149 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.367029782 May 26 02:48:04 PM PDT 24 May 26 02:50:23 PM PDT 24 1989370472 ps
T821 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3278840638 May 26 02:47:55 PM PDT 24 May 26 03:03:30 PM PDT 24 56587809567 ps
T143 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1763497123 May 26 02:47:55 PM PDT 24 May 26 02:51:22 PM PDT 24 6315706122 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1920753950 May 26 02:47:55 PM PDT 24 May 26 02:47:58 PM PDT 24 44096959 ps
T165 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3267896184 May 26 02:48:14 PM PDT 24 May 26 02:49:47 PM PDT 24 1666883373 ps
T823 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3670910331 May 26 02:47:57 PM PDT 24 May 26 02:48:05 PM PDT 24 85328090 ps
T150 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3102459388 May 26 02:48:13 PM PDT 24 May 26 03:04:28 PM PDT 24 12605066926 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2720600829 May 26 02:47:59 PM PDT 24 May 26 02:53:09 PM PDT 24 16142791701 ps
T170 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3797589660 May 26 02:47:57 PM PDT 24 May 26 02:48:02 PM PDT 24 145736246 ps
T824 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3946810137 May 26 02:48:21 PM PDT 24 May 26 02:48:24 PM PDT 24 12108505 ps
T825 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1991665789 May 26 02:47:55 PM PDT 24 May 26 02:48:20 PM PDT 24 594747150 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.535345178 May 26 02:48:14 PM PDT 24 May 26 02:48:28 PM PDT 24 182429006 ps
T827 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2634725680 May 26 02:47:46 PM PDT 24 May 26 02:50:05 PM PDT 24 2051852947 ps
T828 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3763042118 May 26 02:48:13 PM PDT 24 May 26 02:48:17 PM PDT 24 20716943 ps
T829 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1732242597 May 26 02:48:03 PM PDT 24 May 26 02:48:14 PM PDT 24 424116007 ps
T830 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2088470451 May 26 02:47:59 PM PDT 24 May 26 02:48:05 PM PDT 24 32461747 ps
T831 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2894742714 May 26 02:48:11 PM PDT 24 May 26 02:48:14 PM PDT 24 9369538 ps

Test location /workspace/coverage/default/11.alert_handler_entropy.3597583926
Short name T1
Test name
Test status
Simulation time 333889815254 ps
CPU time 2536.18 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 02:04:45 PM PDT 24
Peak memory 281556 kb
Host smart-8bd1b8ba-7466-49d2-88f6-e0b1a607dc8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597583926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3597583926
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.110817518
Short name T14
Test name
Test status
Simulation time 18483712939 ps
CPU time 1190.13 seconds
Started May 26 01:22:21 PM PDT 24
Finished May 26 01:42:12 PM PDT 24
Peak memory 289292 kb
Host smart-2f7ca0ce-1626-4900-8957-83e7cda16e47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110817518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.110817518
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2561246032
Short name T11
Test name
Test status
Simulation time 627037814 ps
CPU time 27.73 seconds
Started May 26 01:22:33 PM PDT 24
Finished May 26 01:23:01 PM PDT 24
Peak memory 277452 kb
Host smart-ba9db828-7cfe-4704-a0d4-ac8e32ef4337
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2561246032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2561246032
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1344202657
Short name T49
Test name
Test status
Simulation time 52830474489 ps
CPU time 4916.9 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 02:44:42 PM PDT 24
Peak memory 347340 kb
Host smart-6335717d-b03e-46e1-a3f4-4fa60cf77734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344202657 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1344202657
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.4123399181
Short name T152
Test name
Test status
Simulation time 1262609179 ps
CPU time 47.85 seconds
Started May 26 02:47:43 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 239340 kb
Host smart-ed6ca34a-737f-4c5a-aa4d-fbc839f7a3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4123399181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.4123399181
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3042089450
Short name T130
Test name
Test status
Simulation time 6939247042 ps
CPU time 325.37 seconds
Started May 26 02:47:56 PM PDT 24
Finished May 26 02:53:22 PM PDT 24
Peak memory 272292 kb
Host smart-d3b0a26d-8a23-45d6-8f40-7cd67b1526a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3042089450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3042089450
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1265143570
Short name T3
Test name
Test status
Simulation time 152814993103 ps
CPU time 2082.43 seconds
Started May 26 01:23:15 PM PDT 24
Finished May 26 01:57:59 PM PDT 24
Peak memory 285968 kb
Host smart-4a8bedbb-1159-45f3-8d9d-72906920dd71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265143570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1265143570
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1843244025
Short name T97
Test name
Test status
Simulation time 1249983398 ps
CPU time 17.26 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:23:03 PM PDT 24
Peak memory 248776 kb
Host smart-c87a2259-d7bc-4e8c-91ad-1f4a76c098b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1843244025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1843244025
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1673632462
Short name T48
Test name
Test status
Simulation time 37602017583 ps
CPU time 2044.28 seconds
Started May 26 01:22:22 PM PDT 24
Finished May 26 01:56:27 PM PDT 24
Peak memory 298972 kb
Host smart-abb02b60-bb02-4f32-bff9-763f7eb04d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673632462 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1673632462
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3384591589
Short name T46
Test name
Test status
Simulation time 37393905906 ps
CPU time 820.99 seconds
Started May 26 01:22:11 PM PDT 24
Finished May 26 01:35:53 PM PDT 24
Peak memory 281620 kb
Host smart-837d7dfd-756a-4684-949c-c536327cf936
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384591589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3384591589
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2756871404
Short name T271
Test name
Test status
Simulation time 132697771314 ps
CPU time 2300.52 seconds
Started May 26 01:24:23 PM PDT 24
Finished May 26 02:02:44 PM PDT 24
Peak memory 288556 kb
Host smart-62781a0f-9a86-4e4c-b196-d40d362e5fcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756871404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2756871404
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1294552035
Short name T51
Test name
Test status
Simulation time 78639492142 ps
CPU time 4638.75 seconds
Started May 26 01:22:23 PM PDT 24
Finished May 26 02:39:43 PM PDT 24
Peak memory 297628 kb
Host smart-91204b3e-0fa2-4663-b9c1-1334fc1c9914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294552035 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1294552035
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.984734477
Short name T122
Test name
Test status
Simulation time 12398710829 ps
CPU time 1047.92 seconds
Started May 26 02:48:06 PM PDT 24
Finished May 26 03:05:36 PM PDT 24
Peak memory 265248 kb
Host smart-49d047d6-078e-45e1-9fef-6111cd565a5f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984734477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.984734477
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1961319744
Short name T103
Test name
Test status
Simulation time 69443286645 ps
CPU time 4566.27 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 02:38:38 PM PDT 24
Peak memory 302376 kb
Host smart-8971b698-192c-4b67-906d-9bb5f8db64a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961319744 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1961319744
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.734019226
Short name T129
Test name
Test status
Simulation time 5083379418 ps
CPU time 590.01 seconds
Started May 26 02:48:16 PM PDT 24
Finished May 26 02:58:07 PM PDT 24
Peak memory 265164 kb
Host smart-2665ca10-5b61-4ef1-baef-a33a2dee24f9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734019226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.734019226
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.901081011
Short name T137
Test name
Test status
Simulation time 19633307904 ps
CPU time 348.19 seconds
Started May 26 02:47:57 PM PDT 24
Finished May 26 02:53:45 PM PDT 24
Peak memory 273108 kb
Host smart-e0c22dbe-13e1-4a3a-9b9e-e41426a1e23b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=901081011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.901081011
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2948764184
Short name T86
Test name
Test status
Simulation time 107570800382 ps
CPU time 1601.5 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:49:10 PM PDT 24
Peak memory 265168 kb
Host smart-744710bc-6dcc-4097-b547-59c3bfd9dd1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948764184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2948764184
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2500206912
Short name T231
Test name
Test status
Simulation time 99526476264 ps
CPU time 2872.4 seconds
Started May 26 01:23:01 PM PDT 24
Finished May 26 02:10:54 PM PDT 24
Peak memory 288104 kb
Host smart-61c651a6-2088-401d-ad42-0eb5e5ef9a17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500206912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2500206912
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2133569971
Short name T42
Test name
Test status
Simulation time 378246210074 ps
CPU time 6827.62 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 03:17:53 PM PDT 24
Peak memory 330160 kb
Host smart-f741b53c-7985-4eed-b89b-f68d3c997754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133569971 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2133569971
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3858202226
Short name T275
Test name
Test status
Simulation time 28775904966 ps
CPU time 579.82 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 248084 kb
Host smart-a0cfc8b5-1a23-4b1e-a9f2-0f446d232fc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858202226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3858202226
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.4094171307
Short name T224
Test name
Test status
Simulation time 11114845 ps
CPU time 1.67 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:08 PM PDT 24
Peak memory 235592 kb
Host smart-5718c605-e31e-4b29-a339-b92b663b1ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4094171307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4094171307
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1030730324
Short name T133
Test name
Test status
Simulation time 6681039545 ps
CPU time 204.63 seconds
Started May 26 02:48:07 PM PDT 24
Finished May 26 02:51:33 PM PDT 24
Peak memory 265180 kb
Host smart-d38eb49d-8b2f-4430-9f72-b0eb3a410423
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1030730324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1030730324
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1622481587
Short name T279
Test name
Test status
Simulation time 14084080150 ps
CPU time 543.82 seconds
Started May 26 01:24:23 PM PDT 24
Finished May 26 01:33:28 PM PDT 24
Peak memory 248208 kb
Host smart-23d32e61-9d3c-4905-b1e7-98f84da5950e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622481587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1622481587
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1753174164
Short name T132
Test name
Test status
Simulation time 50619873639 ps
CPU time 976.84 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 03:03:59 PM PDT 24
Peak memory 272708 kb
Host smart-7accc7d4-3f09-45b5-ade9-6139096d8b4f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753174164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1753174164
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3558567107
Short name T300
Test name
Test status
Simulation time 153394559851 ps
CPU time 2166.6 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:58:56 PM PDT 24
Peak memory 269236 kb
Host smart-928f6aa8-e89c-4bad-8996-d1241bacb8c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558567107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3558567107
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1342944414
Short name T113
Test name
Test status
Simulation time 12721718626 ps
CPU time 529.93 seconds
Started May 26 01:22:33 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 248080 kb
Host smart-f04a411a-0850-4747-918d-cb5727d400ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342944414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1342944414
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1204118268
Short name T128
Test name
Test status
Simulation time 4407602990 ps
CPU time 585.3 seconds
Started May 26 02:48:06 PM PDT 24
Finished May 26 02:57:53 PM PDT 24
Peak memory 265332 kb
Host smart-31657346-6d7a-4daf-8947-d1d1af2c0bae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204118268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1204118268
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3806619387
Short name T237
Test name
Test status
Simulation time 49933780536 ps
CPU time 1402.79 seconds
Started May 26 01:24:15 PM PDT 24
Finished May 26 01:47:38 PM PDT 24
Peak memory 272348 kb
Host smart-ad104b1d-4cf3-4ad6-96f9-d573f2e8dd19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806619387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3806619387
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3388261702
Short name T37
Test name
Test status
Simulation time 39714508396 ps
CPU time 2386.78 seconds
Started May 26 01:22:18 PM PDT 24
Finished May 26 02:02:05 PM PDT 24
Peak memory 289340 kb
Host smart-ffeb5010-3602-4a39-a3f1-d3294ea97a80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388261702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3388261702
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3102459388
Short name T150
Test name
Test status
Simulation time 12605066926 ps
CPU time 972.83 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 03:04:28 PM PDT 24
Peak memory 273056 kb
Host smart-6c39ab6a-4f36-4fda-8768-36ede7bebec7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102459388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3102459388
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3604841998
Short name T555
Test name
Test status
Simulation time 239142580691 ps
CPU time 3397.58 seconds
Started May 26 01:24:20 PM PDT 24
Finished May 26 02:20:58 PM PDT 24
Peak memory 289416 kb
Host smart-c09613d4-94cd-4aa0-bb9b-fbbcf7c872bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604841998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3604841998
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.793239009
Short name T76
Test name
Test status
Simulation time 662671876392 ps
CPU time 3351.86 seconds
Started May 26 01:23:00 PM PDT 24
Finished May 26 02:18:53 PM PDT 24
Peak memory 299820 kb
Host smart-2bf96fd8-d5ae-48b3-b043-bd44170e37e6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793239009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.793239009
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1446416277
Short name T142
Test name
Test status
Simulation time 27553597782 ps
CPU time 926.42 seconds
Started May 26 02:47:45 PM PDT 24
Finished May 26 03:03:12 PM PDT 24
Peak memory 265144 kb
Host smart-491748b4-2def-4a5e-9729-1d470d25a7a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446416277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1446416277
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3582351399
Short name T728
Test name
Test status
Simulation time 10665329 ps
CPU time 1.32 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:15 PM PDT 24
Peak memory 236616 kb
Host smart-3e827ba0-62e2-4e2c-b784-8b531687be06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3582351399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3582351399
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1908282822
Short name T298
Test name
Test status
Simulation time 82528126341 ps
CPU time 1194.96 seconds
Started May 26 01:22:31 PM PDT 24
Finished May 26 01:42:28 PM PDT 24
Peak memory 265144 kb
Host smart-76dd3a3d-a529-4ac6-94f1-ecb63a87f1ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908282822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1908282822
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2891088707
Short name T114
Test name
Test status
Simulation time 13363797443 ps
CPU time 561.64 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:32:09 PM PDT 24
Peak memory 248244 kb
Host smart-f0dd9d5b-26c9-46e6-8cc4-6265ae4a6e5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891088707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2891088707
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.70710
Short name T125
Test name
Test status
Simulation time 11540875875 ps
CPU time 191.52 seconds
Started May 26 02:48:15 PM PDT 24
Finished May 26 02:51:28 PM PDT 24
Peak memory 270776 kb
Host smart-d0bcee24-7eba-4932-985e-b38344544aba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.70710
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.885645250
Short name T16
Test name
Test status
Simulation time 141074572960 ps
CPU time 2150.28 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:58:35 PM PDT 24
Peak memory 289672 kb
Host smart-9992ca7d-a232-4799-b33c-0b67ef9bb3c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885645250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.885645250
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3574411602
Short name T305
Test name
Test status
Simulation time 41690862260 ps
CPU time 2670.71 seconds
Started May 26 01:23:31 PM PDT 24
Finished May 26 02:08:03 PM PDT 24
Peak memory 287588 kb
Host smart-bb2054d8-167e-48ba-bcc3-2c1721c460f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574411602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3574411602
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3607502801
Short name T166
Test name
Test status
Simulation time 114471301 ps
CPU time 6.04 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:47:47 PM PDT 24
Peak memory 236596 kb
Host smart-66fee1e4-d68a-46eb-8da9-7c07cda962e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3607502801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3607502801
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2748833523
Short name T140
Test name
Test status
Simulation time 6365114633 ps
CPU time 189.71 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:51:24 PM PDT 24
Peak memory 272260 kb
Host smart-b448ae2e-69bd-44ed-8c48-5cd58418f092
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2748833523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2748833523
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3002410533
Short name T232
Test name
Test status
Simulation time 114645240248 ps
CPU time 1656.84 seconds
Started May 26 01:21:56 PM PDT 24
Finished May 26 01:49:34 PM PDT 24
Peak memory 266284 kb
Host smart-700d2756-8627-4da2-826d-0e3a1b3bbbf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002410533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3002410533
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.804665332
Short name T270
Test name
Test status
Simulation time 40863343215 ps
CPU time 2382.46 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 02:02:21 PM PDT 24
Peak memory 281604 kb
Host smart-6ecf632e-dda1-4014-be7f-ec1a4af61b3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804665332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.804665332
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4111562152
Short name T241
Test name
Test status
Simulation time 58354602361 ps
CPU time 597.66 seconds
Started May 26 01:23:07 PM PDT 24
Finished May 26 01:33:06 PM PDT 24
Peak memory 248272 kb
Host smart-9be01f8d-4238-4d8e-b17e-efabe9f4a79e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111562152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4111562152
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2576769995
Short name T233
Test name
Test status
Simulation time 91723211336 ps
CPU time 2336.02 seconds
Started May 26 01:23:53 PM PDT 24
Finished May 26 02:02:50 PM PDT 24
Peak memory 289512 kb
Host smart-c6515351-ad3e-4799-a31c-f3918e0a980b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576769995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2576769995
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.655303399
Short name T32
Test name
Test status
Simulation time 212466252535 ps
CPU time 3767.62 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 02:26:52 PM PDT 24
Peak memory 305492 kb
Host smart-176ea998-4cb8-4f4f-98eb-e5c443941f0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655303399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.655303399
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2128068271
Short name T264
Test name
Test status
Simulation time 110001772611 ps
CPU time 9797.9 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 04:07:24 PM PDT 24
Peak memory 338540 kb
Host smart-235b06bf-f269-4fec-a0ec-6e54e9720276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128068271 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2128068271
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3278840638
Short name T821
Test name
Test status
Simulation time 56587809567 ps
CPU time 933.71 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 03:03:30 PM PDT 24
Peak memory 273320 kb
Host smart-61390063-67a4-49f9-81bf-1eed739759d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278840638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3278840638
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1515276733
Short name T202
Test name
Test status
Simulation time 39895723 ps
CPU time 3.48 seconds
Started May 26 01:21:57 PM PDT 24
Finished May 26 01:22:01 PM PDT 24
Peak memory 248936 kb
Host smart-3e19d049-85e7-4a31-a348-ec70d96b6c2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1515276733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1515276733
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1513151786
Short name T5
Test name
Test status
Simulation time 112091734 ps
CPU time 3.02 seconds
Started May 26 01:22:10 PM PDT 24
Finished May 26 01:22:14 PM PDT 24
Peak memory 248940 kb
Host smart-677ba5af-864b-41a5-b8c5-cdc94e3b8328
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1513151786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1513151786
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3942614355
Short name T10
Test name
Test status
Simulation time 130267988 ps
CPU time 3.8 seconds
Started May 26 01:22:28 PM PDT 24
Finished May 26 01:22:34 PM PDT 24
Peak memory 249084 kb
Host smart-08364550-1afe-48b4-9bd5-7c1e5f65d0d4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3942614355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3942614355
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3037813195
Short name T194
Test name
Test status
Simulation time 31981018 ps
CPU time 3.01 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:32 PM PDT 24
Peak memory 248956 kb
Host smart-1f220c8e-5f38-47d8-bc97-b22e6a75f675
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3037813195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3037813195
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2702770166
Short name T126
Test name
Test status
Simulation time 15249711511 ps
CPU time 261.92 seconds
Started May 26 02:47:45 PM PDT 24
Finished May 26 02:52:08 PM PDT 24
Peak memory 265120 kb
Host smart-4d0d1d02-cb7c-4f01-b072-777e28585b8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2702770166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2702770166
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3873154372
Short name T317
Test name
Test status
Simulation time 39944070 ps
CPU time 1.48 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:14 PM PDT 24
Peak memory 235644 kb
Host smart-adbefb4d-c60c-4387-a885-b51bf886714f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3873154372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3873154372
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.577509760
Short name T228
Test name
Test status
Simulation time 1197610355 ps
CPU time 73.98 seconds
Started May 26 01:22:33 PM PDT 24
Finished May 26 01:23:48 PM PDT 24
Peak memory 256108 kb
Host smart-04e47068-5372-47f4-b6a0-31cc902dc506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57750
9760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.577509760
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2115510385
Short name T257
Test name
Test status
Simulation time 198782919268 ps
CPU time 2830.77 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 02:09:42 PM PDT 24
Peak memory 289096 kb
Host smart-3a2f163a-222b-44ce-8790-ed1f6a559812
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115510385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2115510385
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3341268814
Short name T235
Test name
Test status
Simulation time 413836521482 ps
CPU time 4037.26 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 02:30:05 PM PDT 24
Peak memory 297424 kb
Host smart-37b6ec40-ab2e-4e92-bea3-4746cbf3d67e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341268814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3341268814
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2792226959
Short name T297
Test name
Test status
Simulation time 33014470721 ps
CPU time 615.17 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:32:58 PM PDT 24
Peak memory 254980 kb
Host smart-387fbd87-30ca-4687-a689-7157fbf25257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792226959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2792226959
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2263186916
Short name T262
Test name
Test status
Simulation time 4105258939 ps
CPU time 51.73 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:24:31 PM PDT 24
Peak memory 248504 kb
Host smart-0d1aeccd-e10f-4013-a9a6-7f4437e4c99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
86916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2263186916
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1234166042
Short name T44
Test name
Test status
Simulation time 54219267122 ps
CPU time 2475.18 seconds
Started May 26 01:22:32 PM PDT 24
Finished May 26 02:03:48 PM PDT 24
Peak memory 289784 kb
Host smart-3105a7de-7c50-426e-a35b-315c8f70c813
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234166042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1234166042
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1117204902
Short name T234
Test name
Test status
Simulation time 62360925861 ps
CPU time 1414.22 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:46:26 PM PDT 24
Peak memory 289728 kb
Host smart-ce5941ea-947d-41bb-8710-e93af8ea76d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117204902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1117204902
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1625300814
Short name T718
Test name
Test status
Simulation time 141013244 ps
CPU time 7.02 seconds
Started May 26 02:47:41 PM PDT 24
Finished May 26 02:47:50 PM PDT 24
Peak memory 240144 kb
Host smart-ce43eb0e-d848-4b2f-af0d-c2403942e071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625300814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1625300814
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1836792220
Short name T284
Test name
Test status
Simulation time 46611966007 ps
CPU time 476.19 seconds
Started May 26 01:21:58 PM PDT 24
Finished May 26 01:29:54 PM PDT 24
Peak memory 247908 kb
Host smart-1fceb43c-1697-4a70-9930-7f07590588e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836792220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1836792220
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3622245499
Short name T266
Test name
Test status
Simulation time 2790748105 ps
CPU time 42.22 seconds
Started May 26 01:22:07 PM PDT 24
Finished May 26 01:22:50 PM PDT 24
Peak memory 248768 kb
Host smart-e6ea78d4-7faf-4f40-9186-c929e12fb3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36222
45499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3622245499
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1253536149
Short name T296
Test name
Test status
Simulation time 7461610582 ps
CPU time 228.13 seconds
Started May 26 01:21:58 PM PDT 24
Finished May 26 01:25:47 PM PDT 24
Peak memory 247940 kb
Host smart-2684effd-f96b-46c2-9bd7-d361c9bdbb40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253536149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1253536149
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.945474402
Short name T267
Test name
Test status
Simulation time 57063876189 ps
CPU time 1288.64 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:44:12 PM PDT 24
Peak memory 281692 kb
Host smart-0b407278-ff1b-46e9-9e59-48692ae91eb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945474402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.945474402
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2042011373
Short name T230
Test name
Test status
Simulation time 2299683217 ps
CPU time 202.09 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:25:59 PM PDT 24
Peak memory 257004 kb
Host smart-e2c98b2a-0598-4d74-b518-6a1819fead91
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042011373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2042011373
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2075385155
Short name T254
Test name
Test status
Simulation time 592626479 ps
CPU time 40.21 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:27 PM PDT 24
Peak memory 247660 kb
Host smart-96e3f1a2-b0b5-4d0d-b9f1-2a9a5eacb56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
85155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2075385155
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.754197660
Short name T40
Test name
Test status
Simulation time 19940755735 ps
CPU time 1548.43 seconds
Started May 26 01:22:06 PM PDT 24
Finished May 26 01:47:55 PM PDT 24
Peak memory 289176 kb
Host smart-00ee461b-cba2-40ba-9b45-95a24d04df08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754197660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.754197660
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1270205490
Short name T50
Test name
Test status
Simulation time 66467439273 ps
CPU time 1708.58 seconds
Started May 26 01:23:11 PM PDT 24
Finished May 26 01:51:41 PM PDT 24
Peak memory 305132 kb
Host smart-9149d223-6451-4337-89e6-72c62928c319
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270205490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1270205490
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2073738555
Short name T108
Test name
Test status
Simulation time 1071591630 ps
CPU time 32.29 seconds
Started May 26 01:23:17 PM PDT 24
Finished May 26 01:23:50 PM PDT 24
Peak memory 248736 kb
Host smart-d48d6bec-b40e-4a74-985b-ff6588a2d72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20737
38555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2073738555
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3693639895
Short name T269
Test name
Test status
Simulation time 893048230 ps
CPU time 37.42 seconds
Started May 26 01:23:51 PM PDT 24
Finished May 26 01:24:29 PM PDT 24
Peak memory 255392 kb
Host smart-8b701d46-9d95-451c-a0ae-49a1c43b6858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36936
39895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3693639895
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3087987060
Short name T80
Test name
Test status
Simulation time 502942986 ps
CPU time 31.86 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:23:01 PM PDT 24
Peak memory 248016 kb
Host smart-bc935521-5aa0-4552-aa54-11aedf8f9ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30879
87060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3087987060
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3549156313
Short name T160
Test name
Test status
Simulation time 58796878 ps
CPU time 3.17 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:09 PM PDT 24
Peak memory 235660 kb
Host smart-aef303fc-2861-48fc-8e60-f21062c07f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3549156313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3549156313
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3562661561
Short name T164
Test name
Test status
Simulation time 238192878 ps
CPU time 3.94 seconds
Started May 26 02:48:03 PM PDT 24
Finished May 26 02:48:09 PM PDT 24
Peak memory 236560 kb
Host smart-c71a7405-958b-480b-85f3-52bdf93ef6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3562661561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3562661561
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3267896184
Short name T165
Test name
Test status
Simulation time 1666883373 ps
CPU time 91.93 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:49:47 PM PDT 24
Peak memory 239384 kb
Host smart-5425346e-a82a-423d-95fb-712b3fa70df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3267896184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3267896184
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1898949625
Short name T151
Test name
Test status
Simulation time 63998031 ps
CPU time 3.23 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:10 PM PDT 24
Peak memory 236588 kb
Host smart-6666c55b-2710-4458-87e2-35ad63a41c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1898949625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1898949625
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3797589660
Short name T170
Test name
Test status
Simulation time 145736246 ps
CPU time 5.08 seconds
Started May 26 02:47:57 PM PDT 24
Finished May 26 02:48:02 PM PDT 24
Peak memory 237012 kb
Host smart-3f831a04-5fd7-4a72-b219-6c6e7dd462b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3797589660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3797589660
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.623811634
Short name T163
Test name
Test status
Simulation time 1177633057 ps
CPU time 37.29 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:48:53 PM PDT 24
Peak memory 244764 kb
Host smart-05a1d2b0-5539-4316-b3c2-4bc20bddd8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=623811634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.623811634
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2861371072
Short name T168
Test name
Test status
Simulation time 1267708354 ps
CPU time 76.14 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:49:05 PM PDT 24
Peak memory 236892 kb
Host smart-6a8828bc-8f76-4fd5-a3a6-22cb6d6e25a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2861371072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2861371072
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1520050292
Short name T153
Test name
Test status
Simulation time 624074049 ps
CPU time 42.82 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:56 PM PDT 24
Peak memory 248320 kb
Host smart-92ac30c3-3152-415a-ab57-b4688af0a069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1520050292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1520050292
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3738228777
Short name T118
Test name
Test status
Simulation time 964303327 ps
CPU time 112.27 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:50:06 PM PDT 24
Peak memory 256864 kb
Host smart-2672f0d7-8f3d-4e8a-a08f-1793db077053
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3738228777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3738228777
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.588938272
Short name T158
Test name
Test status
Simulation time 102033893 ps
CPU time 2.51 seconds
Started May 26 02:47:54 PM PDT 24
Finished May 26 02:47:57 PM PDT 24
Peak memory 236580 kb
Host smart-17bd8ad0-a09b-4929-9cbb-cc5f3caa446b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=588938272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.588938272
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4213731702
Short name T169
Test name
Test status
Simulation time 61280423 ps
CPU time 2.79 seconds
Started May 26 02:47:42 PM PDT 24
Finished May 26 02:47:47 PM PDT 24
Peak memory 236976 kb
Host smart-2b1d0766-a88a-44cc-b75a-c6b6f5e33236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4213731702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4213731702
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2840361731
Short name T159
Test name
Test status
Simulation time 115011008 ps
CPU time 2.95 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:09 PM PDT 24
Peak memory 236592 kb
Host smart-e8c9f2fd-3896-481b-a72c-eb211c1c3509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2840361731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2840361731
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.688235469
Short name T167
Test name
Test status
Simulation time 32347271 ps
CPU time 2.92 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 236884 kb
Host smart-17d32ccc-cb17-45b1-b387-ba6befbcafd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=688235469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.688235469
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3771006927
Short name T157
Test name
Test status
Simulation time 973539789 ps
CPU time 70.95 seconds
Started May 26 02:47:50 PM PDT 24
Finished May 26 02:49:03 PM PDT 24
Peak memory 236780 kb
Host smart-9020cd30-31a0-4029-9707-658fcf89f270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3771006927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3771006927
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2815412041
Short name T171
Test name
Test status
Simulation time 205012356 ps
CPU time 3.83 seconds
Started May 26 02:47:52 PM PDT 24
Finished May 26 02:47:57 PM PDT 24
Peak memory 235640 kb
Host smart-6d600474-4531-4171-b69c-1d5114ab6a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2815412041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2815412041
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1582017442
Short name T161
Test name
Test status
Simulation time 342794917 ps
CPU time 47.33 seconds
Started May 26 02:47:59 PM PDT 24
Finished May 26 02:48:47 PM PDT 24
Peak memory 239404 kb
Host smart-689b1356-bdb7-4a51-9317-4c64f3dab18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1582017442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1582017442
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4278600149
Short name T162
Test name
Test status
Simulation time 1864004305 ps
CPU time 41.85 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:41 PM PDT 24
Peak memory 236732 kb
Host smart-2513c1d5-12b1-467c-a41d-99890f681024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4278600149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4278600149
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3254898182
Short name T17
Test name
Test status
Simulation time 224523421 ps
CPU time 16.73 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:23:04 PM PDT 24
Peak memory 253856 kb
Host smart-373293cc-88d2-4735-bbfd-a81ff52e29af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32548
98182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3254898182
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.847027843
Short name T221
Test name
Test status
Simulation time 2130638129 ps
CPU time 137.03 seconds
Started May 26 02:47:42 PM PDT 24
Finished May 26 02:50:00 PM PDT 24
Peak memory 236520 kb
Host smart-fc2453c5-6f42-4e13-9ffc-f94d9cd8260a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=847027843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.847027843
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2002074925
Short name T723
Test name
Test status
Simulation time 11913428769 ps
CPU time 191.43 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:50:53 PM PDT 24
Peak memory 235700 kb
Host smart-0aa2209b-8691-4da1-8985-dd5b661944dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2002074925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2002074925
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.366928247
Short name T787
Test name
Test status
Simulation time 112998061 ps
CPU time 9.13 seconds
Started May 26 02:47:43 PM PDT 24
Finished May 26 02:47:53 PM PDT 24
Peak memory 240116 kb
Host smart-4ec8705e-7fe7-403e-874c-2c55dddd4659
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=366928247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.366928247
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2528610550
Short name T736
Test name
Test status
Simulation time 355027256 ps
CPU time 7.62 seconds
Started May 26 02:47:43 PM PDT 24
Finished May 26 02:47:52 PM PDT 24
Peak memory 236572 kb
Host smart-b32edd2a-0e72-4bdb-9866-7b95c7d74ece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2528610550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2528610550
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3929627593
Short name T757
Test name
Test status
Simulation time 14058491 ps
CPU time 1.47 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:47:44 PM PDT 24
Peak memory 236608 kb
Host smart-3664f5e7-43e1-406d-9446-86a6aa34d37e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3929627593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3929627593
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3404943943
Short name T760
Test name
Test status
Simulation time 2472131021 ps
CPU time 21.29 seconds
Started May 26 02:47:41 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 248384 kb
Host smart-ff33206a-97c0-43c8-a5dd-ad851113506e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3404943943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3404943943
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1710292803
Short name T124
Test name
Test status
Simulation time 1097179079 ps
CPU time 102.84 seconds
Started May 26 02:47:44 PM PDT 24
Finished May 26 02:49:28 PM PDT 24
Peak memory 256856 kb
Host smart-2d1f9d22-3c59-4be6-a7cb-e6007a4c08f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1710292803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1710292803
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2831888760
Short name T147
Test name
Test status
Simulation time 2505934412 ps
CPU time 290.08 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:52:32 PM PDT 24
Peak memory 265272 kb
Host smart-10084928-c108-4f73-8530-4c465f757e22
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831888760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2831888760
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3183020175
Short name T763
Test name
Test status
Simulation time 102068931 ps
CPU time 6.09 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:47:47 PM PDT 24
Peak memory 240244 kb
Host smart-d0058201-98ed-41db-b38b-022b75e0acad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3183020175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3183020175
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3719552329
Short name T183
Test name
Test status
Simulation time 2123918809 ps
CPU time 69.98 seconds
Started May 26 02:47:42 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 236596 kb
Host smart-16818fe0-b31e-4fe6-9b97-cf81d3e5ea54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3719552329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3719552329
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3811484106
Short name T326
Test name
Test status
Simulation time 1819740038 ps
CPU time 100.5 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:49:22 PM PDT 24
Peak memory 236572 kb
Host smart-28a4b233-2585-42a5-a2e1-06072dfa0875
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3811484106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3811484106
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1680719290
Short name T727
Test name
Test status
Simulation time 46354766 ps
CPU time 5.96 seconds
Started May 26 02:47:43 PM PDT 24
Finished May 26 02:47:50 PM PDT 24
Peak memory 240136 kb
Host smart-ce6aa417-25dd-4cef-b509-74eb81fa4679
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1680719290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1680719290
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1355732379
Short name T810
Test name
Test status
Simulation time 266317415 ps
CPU time 5.82 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:47:47 PM PDT 24
Peak memory 240176 kb
Host smart-0d242972-d46f-47ef-b224-4a60691abd1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355732379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1355732379
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.169879364
Short name T777
Test name
Test status
Simulation time 20535784 ps
CPU time 3.2 seconds
Started May 26 02:47:42 PM PDT 24
Finished May 26 02:47:47 PM PDT 24
Peak memory 238480 kb
Host smart-24551212-05f9-41e4-87cd-bf19f67f6424
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=169879364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.169879364
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1947144570
Short name T803
Test name
Test status
Simulation time 7944884 ps
CPU time 1.49 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:47:43 PM PDT 24
Peak memory 235660 kb
Host smart-cd7f3bd9-8f12-4d0c-9f2d-22554cd94e9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1947144570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1947144570
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1784577747
Short name T174
Test name
Test status
Simulation time 113170048 ps
CPU time 12.92 seconds
Started May 26 02:47:45 PM PDT 24
Finished May 26 02:47:59 PM PDT 24
Peak memory 244752 kb
Host smart-8d492e15-a4b8-44e5-96ad-d560b13b2c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1784577747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1784577747
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1027578281
Short name T716
Test name
Test status
Simulation time 244937931 ps
CPU time 10.2 seconds
Started May 26 02:47:42 PM PDT 24
Finished May 26 02:47:54 PM PDT 24
Peak memory 248380 kb
Host smart-1a253ba4-fee7-492d-b47f-d6cfd9643361
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1027578281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1027578281
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2072993184
Short name T769
Test name
Test status
Simulation time 66737315 ps
CPU time 9.7 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:16 PM PDT 24
Peak memory 256520 kb
Host smart-e416a96d-e3ad-40e0-a4da-75b3922b22b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072993184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2072993184
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.352911389
Short name T793
Test name
Test status
Simulation time 67737367 ps
CPU time 5.9 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:12 PM PDT 24
Peak memory 239412 kb
Host smart-5b69f4ab-74a5-45b9-ac89-8a7d65db0e7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=352911389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.352911389
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1920753950
Short name T822
Test name
Test status
Simulation time 44096959 ps
CPU time 1.5 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:47:58 PM PDT 24
Peak memory 236628 kb
Host smart-eb80f0b2-46f6-4793-877d-22479553605d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1920753950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1920753950
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3905456923
Short name T179
Test name
Test status
Simulation time 2386462716 ps
CPU time 19.25 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:25 PM PDT 24
Peak memory 248356 kb
Host smart-281bb158-8cc2-4f67-abe6-27ed7c8dc3f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3905456923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3905456923
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.738483746
Short name T328
Test name
Test status
Simulation time 16563845360 ps
CPU time 636.64 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:58:36 PM PDT 24
Peak memory 265148 kb
Host smart-51811868-efba-429c-94df-569c73011597
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738483746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.738483746
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2290161809
Short name T752
Test name
Test status
Simulation time 127566816 ps
CPU time 6.57 seconds
Started May 26 02:48:01 PM PDT 24
Finished May 26 02:48:08 PM PDT 24
Peak memory 247120 kb
Host smart-7c4a388f-6c32-49e1-9e8b-1cab5bc3cba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290161809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2290161809
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.909088082
Short name T745
Test name
Test status
Simulation time 1886351795 ps
CPU time 22 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:21 PM PDT 24
Peak memory 240124 kb
Host smart-2d3657d7-e9a4-446b-bef8-cae5a2e6e36a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=909088082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.909088082
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3544980900
Short name T785
Test name
Test status
Simulation time 656009016 ps
CPU time 6.68 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:14 PM PDT 24
Peak memory 239556 kb
Host smart-ed748c4a-d55e-462d-a672-1da124c8b45b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544980900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3544980900
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3313837574
Short name T741
Test name
Test status
Simulation time 57835452 ps
CPU time 3.25 seconds
Started May 26 02:48:03 PM PDT 24
Finished May 26 02:48:08 PM PDT 24
Peak memory 239440 kb
Host smart-666d6e1c-fbfc-4bbe-aebb-d69d97295e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3313837574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3313837574
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3602918660
Short name T730
Test name
Test status
Simulation time 22476589 ps
CPU time 1.42 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:09 PM PDT 24
Peak memory 236528 kb
Host smart-00b022f4-9f23-4ffa-92ff-93326014ab0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3602918660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3602918660
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3621101326
Short name T172
Test name
Test status
Simulation time 1260575558 ps
CPU time 37.02 seconds
Started May 26 02:48:08 PM PDT 24
Finished May 26 02:48:46 PM PDT 24
Peak memory 243836 kb
Host smart-c3b4377b-6b6c-416f-8499-34883d39786e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3621101326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3621101326
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.230122956
Short name T120
Test name
Test status
Simulation time 11479863290 ps
CPU time 182.2 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:51:08 PM PDT 24
Peak memory 265152 kb
Host smart-f2c4e279-d4a0-4446-acbe-3f02329d8c76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=230122956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.230122956
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3911720252
Short name T116
Test name
Test status
Simulation time 4331345819 ps
CPU time 318.5 seconds
Started May 26 02:48:06 PM PDT 24
Finished May 26 02:53:26 PM PDT 24
Peak memory 265124 kb
Host smart-56cb0128-854d-49b5-a8ca-b2ba29069930
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911720252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3911720252
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1428189937
Short name T798
Test name
Test status
Simulation time 198977396 ps
CPU time 12.92 seconds
Started May 26 02:48:09 PM PDT 24
Finished May 26 02:48:23 PM PDT 24
Peak memory 253824 kb
Host smart-01885c80-47f7-48a9-9a25-0c8e3ee20e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1428189937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1428189937
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.821980693
Short name T749
Test name
Test status
Simulation time 58742279 ps
CPU time 9.86 seconds
Started May 26 02:48:08 PM PDT 24
Finished May 26 02:48:19 PM PDT 24
Peak memory 252208 kb
Host smart-cff4cd66-c570-430f-93ac-e461c1c2a0b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821980693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.821980693
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1141290635
Short name T181
Test name
Test status
Simulation time 36744376 ps
CPU time 5.36 seconds
Started May 26 02:48:07 PM PDT 24
Finished May 26 02:48:13 PM PDT 24
Peak memory 240064 kb
Host smart-f3fb9d73-17ce-4216-9bf5-3baecae349de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1141290635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1141290635
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1273797630
Short name T781
Test name
Test status
Simulation time 16179852 ps
CPU time 1.35 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:08 PM PDT 24
Peak memory 236748 kb
Host smart-89b0e9a5-e8af-4ec8-8228-b270a3821e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1273797630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1273797630
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1927398420
Short name T729
Test name
Test status
Simulation time 3478414064 ps
CPU time 20.89 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:27 PM PDT 24
Peak memory 244856 kb
Host smart-25c4fae1-1a26-4c70-ad3e-b30976fae217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1927398420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1927398420
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2228772206
Short name T123
Test name
Test status
Simulation time 2135164909 ps
CPU time 200.32 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:51:27 PM PDT 24
Peak memory 265228 kb
Host smart-109cda41-c2b1-48af-96f0-725348eca2c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2228772206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2228772206
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.516708433
Short name T715
Test name
Test status
Simulation time 1144026935 ps
CPU time 19.98 seconds
Started May 26 02:48:06 PM PDT 24
Finished May 26 02:48:28 PM PDT 24
Peak memory 248392 kb
Host smart-f3a4ffc3-2a66-4253-b484-51dd6fa729c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=516708433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.516708433
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1874738529
Short name T774
Test name
Test status
Simulation time 898272427 ps
CPU time 13.06 seconds
Started May 26 02:48:03 PM PDT 24
Finished May 26 02:48:18 PM PDT 24
Peak memory 242196 kb
Host smart-896bbead-8ce3-49ee-a477-fdb0d675ea9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874738529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1874738529
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2492397429
Short name T743
Test name
Test status
Simulation time 106849309 ps
CPU time 4.94 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:12 PM PDT 24
Peak memory 236560 kb
Host smart-3b66e12b-915e-4921-bf76-401518d73f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2492397429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2492397429
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2200152826
Short name T219
Test name
Test status
Simulation time 1313095716 ps
CPU time 24.63 seconds
Started May 26 02:48:08 PM PDT 24
Finished May 26 02:48:34 PM PDT 24
Peak memory 244776 kb
Host smart-ef454717-349a-4b14-b441-dbd31ac86ab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2200152826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2200152826
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.367029782
Short name T149
Test name
Test status
Simulation time 1989370472 ps
CPU time 137.63 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:50:23 PM PDT 24
Peak memory 256888 kb
Host smart-33f95882-124d-4657-a486-14e111b3a88f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=367029782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.367029782
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1696625918
Short name T717
Test name
Test status
Simulation time 52879015 ps
CPU time 7.9 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:14 PM PDT 24
Peak memory 248388 kb
Host smart-185a514a-5026-4b80-9061-477e8b7e3133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1696625918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1696625918
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1742314340
Short name T175
Test name
Test status
Simulation time 565487090 ps
CPU time 21.43 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:28 PM PDT 24
Peak memory 239356 kb
Host smart-f0fef72a-68bc-48b8-8202-cb4b134a8977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1742314340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1742314340
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1360064031
Short name T765
Test name
Test status
Simulation time 313608121 ps
CPU time 12.01 seconds
Started May 26 02:48:07 PM PDT 24
Finished May 26 02:48:21 PM PDT 24
Peak memory 250680 kb
Host smart-f8d90c8b-7b57-407e-926f-7bd8d2ea163c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360064031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1360064031
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3024584961
Short name T809
Test name
Test status
Simulation time 321011236 ps
CPU time 9.46 seconds
Started May 26 02:48:08 PM PDT 24
Finished May 26 02:48:19 PM PDT 24
Peak memory 236560 kb
Host smart-01b5d66c-b213-4111-8c7e-9beaa733a407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3024584961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3024584961
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4025221568
Short name T797
Test name
Test status
Simulation time 8064359 ps
CPU time 1.37 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:08 PM PDT 24
Peak memory 234624 kb
Host smart-9c787d2f-3f1b-4917-b20a-23867246282b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4025221568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4025221568
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1880459694
Short name T742
Test name
Test status
Simulation time 1316405572 ps
CPU time 22.94 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:29 PM PDT 24
Peak memory 248280 kb
Host smart-9eee160b-4cb9-4e9f-b2a4-2dc2a3afb848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1880459694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1880459694
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3565393088
Short name T136
Test name
Test status
Simulation time 17923657642 ps
CPU time 614.85 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:58:21 PM PDT 24
Peak memory 265172 kb
Host smart-2b288109-d80b-4e50-950e-26b8a76593ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565393088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3565393088
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1413575107
Short name T778
Test name
Test status
Simulation time 1851928457 ps
CPU time 25.57 seconds
Started May 26 02:48:03 PM PDT 24
Finished May 26 02:48:31 PM PDT 24
Peak memory 248280 kb
Host smart-8c219033-f6ba-49b0-8b84-ef5665e583d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413575107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1413575107
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1795847046
Short name T813
Test name
Test status
Simulation time 274734726 ps
CPU time 10.75 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:48:18 PM PDT 24
Peak memory 237332 kb
Host smart-8c368eb5-cadf-49d7-a176-59a4ac977250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795847046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1795847046
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1941570036
Short name T755
Test name
Test status
Simulation time 70992399 ps
CPU time 3.28 seconds
Started May 26 02:48:04 PM PDT 24
Finished May 26 02:48:09 PM PDT 24
Peak memory 236552 kb
Host smart-e959895f-4d2d-4631-a106-71b4de4b8234
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1941570036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1941570036
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3446474534
Short name T726
Test name
Test status
Simulation time 34303843 ps
CPU time 1.4 seconds
Started May 26 02:48:01 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 235684 kb
Host smart-afc31017-7d61-458b-b534-8475e5e56890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3446474534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3446474534
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1125888305
Short name T223
Test name
Test status
Simulation time 2714760891 ps
CPU time 42.54 seconds
Started May 26 02:48:03 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 244832 kb
Host smart-631acd26-221f-43ac-bfca-8ac2a3609939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1125888305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1125888305
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3991639518
Short name T135
Test name
Test status
Simulation time 4398589165 ps
CPU time 99.56 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:49:46 PM PDT 24
Peak memory 256936 kb
Host smart-713bbfcc-5cda-41e6-8fd4-90a178b250cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3991639518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3991639518
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3169065365
Short name T138
Test name
Test status
Simulation time 49981390039 ps
CPU time 879.44 seconds
Started May 26 02:48:08 PM PDT 24
Finished May 26 03:02:49 PM PDT 24
Peak memory 272652 kb
Host smart-9ca7fe9c-1989-4915-b21a-5949d2c04a2a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169065365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3169065365
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1732242597
Short name T829
Test name
Test status
Simulation time 424116007 ps
CPU time 8.86 seconds
Started May 26 02:48:03 PM PDT 24
Finished May 26 02:48:14 PM PDT 24
Peak memory 251952 kb
Host smart-5564a7c7-6de9-4c0a-a091-414494c6597c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1732242597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1732242597
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3264143070
Short name T782
Test name
Test status
Simulation time 72871395 ps
CPU time 10.17 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:48:25 PM PDT 24
Peak memory 252164 kb
Host smart-58f5a734-6aa6-43d5-8557-9870e9ed9ffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264143070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3264143070
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1025861469
Short name T814
Test name
Test status
Simulation time 20152673 ps
CPU time 3.29 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 235652 kb
Host smart-9d44c228-9b6b-481f-a1a9-7a21fa18cb63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1025861469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1025861469
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2894742714
Short name T831
Test name
Test status
Simulation time 9369538 ps
CPU time 1.67 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:14 PM PDT 24
Peak memory 235628 kb
Host smart-c6d06279-306c-48b3-bcfa-ebfe93012717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2894742714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2894742714
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.544387433
Short name T759
Test name
Test status
Simulation time 2125819215 ps
CPU time 40.52 seconds
Started May 26 02:48:10 PM PDT 24
Finished May 26 02:48:52 PM PDT 24
Peak memory 244740 kb
Host smart-20d067d9-b845-4e1f-b002-01a68b937820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=544387433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.544387433
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1448094694
Short name T131
Test name
Test status
Simulation time 12935841094 ps
CPU time 495 seconds
Started May 26 02:48:05 PM PDT 24
Finished May 26 02:56:22 PM PDT 24
Peak memory 266548 kb
Host smart-19b81311-c06c-4cfc-8967-7cb7399788ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448094694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1448094694
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2482068147
Short name T764
Test name
Test status
Simulation time 149689591 ps
CPU time 9.73 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 248336 kb
Host smart-1cdf7567-5a4e-4589-a048-20dcb573856b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2482068147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2482068147
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2284105988
Short name T218
Test name
Test status
Simulation time 987538734 ps
CPU time 9.56 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 239364 kb
Host smart-f66da882-9537-41a0-8304-9706417eb2d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284105988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2284105988
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.131179618
Short name T775
Test name
Test status
Simulation time 60976412 ps
CPU time 5.28 seconds
Started May 26 02:48:10 PM PDT 24
Finished May 26 02:48:18 PM PDT 24
Peak memory 235640 kb
Host smart-20f3dd81-5d69-4a55-9d49-9db536586cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=131179618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.131179618
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1949260829
Short name T320
Test name
Test status
Simulation time 13895626 ps
CPU time 1.33 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:15 PM PDT 24
Peak memory 235624 kb
Host smart-aab0af88-fcad-4443-9f21-3b81c92ff367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1949260829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1949260829
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4075826075
Short name T733
Test name
Test status
Simulation time 259046688 ps
CPU time 17.67 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 248316 kb
Host smart-c9fc5752-0ba3-49d0-8a8f-ab944347515c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4075826075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4075826075
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1138679158
Short name T119
Test name
Test status
Simulation time 18356364118 ps
CPU time 321.11 seconds
Started May 26 02:48:16 PM PDT 24
Finished May 26 02:53:39 PM PDT 24
Peak memory 266324 kb
Host smart-a10c793d-039b-49e6-a738-fca6e6f017a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1138679158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1138679158
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3895672280
Short name T768
Test name
Test status
Simulation time 269293874 ps
CPU time 18.23 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:32 PM PDT 24
Peak memory 248384 kb
Host smart-27307be5-91a6-4bb7-989f-0c931f96dcf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3895672280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3895672280
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.893340676
Short name T722
Test name
Test status
Simulation time 105134918 ps
CPU time 8.32 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:22 PM PDT 24
Peak memory 239172 kb
Host smart-2264f86a-76f9-42a4-a502-53a73614a51f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893340676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.893340676
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.493780275
Short name T751
Test name
Test status
Simulation time 137454450 ps
CPU time 5.28 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:19 PM PDT 24
Peak memory 236572 kb
Host smart-78bc36d3-1e7b-49cd-bf0c-0067de284019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=493780275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.493780275
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3763042118
Short name T828
Test name
Test status
Simulation time 20716943 ps
CPU time 1.43 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 236568 kb
Host smart-1fa4fc47-37a6-459c-9723-876211fce771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3763042118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3763042118
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1416760211
Short name T820
Test name
Test status
Simulation time 1024680694 ps
CPU time 38.18 seconds
Started May 26 02:48:15 PM PDT 24
Finished May 26 02:48:54 PM PDT 24
Peak memory 244940 kb
Host smart-bc5eb3d1-c7be-4710-8e36-4f72da5e0060
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1416760211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1416760211
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2815562262
Short name T141
Test name
Test status
Simulation time 59865276737 ps
CPU time 1041.55 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 03:05:36 PM PDT 24
Peak memory 265064 kb
Host smart-16948f1e-f178-4e4b-be57-ef97cd5c8cfc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815562262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2815562262
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1154967314
Short name T806
Test name
Test status
Simulation time 34937155 ps
CPU time 4.37 seconds
Started May 26 02:48:16 PM PDT 24
Finished May 26 02:48:22 PM PDT 24
Peak memory 248364 kb
Host smart-48387230-9b3d-4aba-86be-f003828e9ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1154967314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1154967314
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.913032929
Short name T779
Test name
Test status
Simulation time 66969991 ps
CPU time 9.7 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:23 PM PDT 24
Peak memory 251632 kb
Host smart-68ca4da7-ae19-485f-a9e7-5bd0ea97ff7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913032929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.913032929
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.522209756
Short name T747
Test name
Test status
Simulation time 188261659 ps
CPU time 8.43 seconds
Started May 26 02:48:10 PM PDT 24
Finished May 26 02:48:21 PM PDT 24
Peak memory 236544 kb
Host smart-164bbe76-a3e6-4545-b33b-7aaa37ce60ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=522209756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.522209756
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.337865988
Short name T156
Test name
Test status
Simulation time 10509664 ps
CPU time 1.45 seconds
Started May 26 02:48:17 PM PDT 24
Finished May 26 02:48:20 PM PDT 24
Peak memory 236608 kb
Host smart-952a3f00-6c80-44e6-9c26-79cc643bd05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=337865988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.337865988
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.535345178
Short name T826
Test name
Test status
Simulation time 182429006 ps
CPU time 12.97 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:48:28 PM PDT 24
Peak memory 245876 kb
Host smart-e3ff982c-1a75-4f57-88db-cb4260486c51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=535345178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.535345178
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3908396102
Short name T796
Test name
Test status
Simulation time 102833974 ps
CPU time 7.78 seconds
Started May 26 02:48:11 PM PDT 24
Finished May 26 02:48:21 PM PDT 24
Peak memory 248376 kb
Host smart-2f02e8b6-864f-4acb-86b8-907c54c90f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3908396102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3908396102
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.291769007
Short name T807
Test name
Test status
Simulation time 1113054451 ps
CPU time 142.43 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:50:04 PM PDT 24
Peak memory 238912 kb
Host smart-4760ae73-524e-4da2-8101-d37291e8e9f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=291769007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.291769007
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2034351669
Short name T180
Test name
Test status
Simulation time 4087197399 ps
CPU time 87.83 seconds
Started May 26 02:47:39 PM PDT 24
Finished May 26 02:49:08 PM PDT 24
Peak memory 235684 kb
Host smart-771e8a9d-88ec-4ed4-a031-cb664f60cf84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2034351669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2034351669
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2516058933
Short name T776
Test name
Test status
Simulation time 90338138 ps
CPU time 3.89 seconds
Started May 26 02:47:41 PM PDT 24
Finished May 26 02:47:46 PM PDT 24
Peak memory 240104 kb
Host smart-f7f8ee5e-301a-49cb-8ae9-67ddb7f5ed8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2516058933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2516058933
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3239459704
Short name T783
Test name
Test status
Simulation time 107647398 ps
CPU time 5.07 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:47:56 PM PDT 24
Peak memory 256476 kb
Host smart-14908bb1-2884-48dc-9ed0-a1dd43e05d6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239459704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3239459704
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1712614289
Short name T746
Test name
Test status
Simulation time 126111241 ps
CPU time 4.59 seconds
Started May 26 02:47:40 PM PDT 24
Finished May 26 02:47:45 PM PDT 24
Peak memory 240080 kb
Host smart-a2e8bab5-88d2-4b57-a94d-0538c4588362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1712614289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1712614289
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1987589052
Short name T318
Test name
Test status
Simulation time 9576239 ps
CPU time 1.57 seconds
Started May 26 02:47:41 PM PDT 24
Finished May 26 02:47:44 PM PDT 24
Peak memory 236568 kb
Host smart-1c59d570-726d-4f14-a87e-c1296a2884bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987589052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1987589052
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2768569447
Short name T720
Test name
Test status
Simulation time 93259023 ps
CPU time 15.37 seconds
Started May 26 02:47:44 PM PDT 24
Finished May 26 02:48:00 PM PDT 24
Peak memory 244740 kb
Host smart-5609e089-8359-4507-ad72-a42933349598
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2768569447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2768569447
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.226618346
Short name T799
Test name
Test status
Simulation time 28938783203 ps
CPU time 373.84 seconds
Started May 26 02:47:39 PM PDT 24
Finished May 26 02:53:54 PM PDT 24
Peak memory 265156 kb
Host smart-dd686f23-c6f7-48ed-8b91-df48d4155ab7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=226618346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.226618346
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.751369190
Short name T222
Test name
Test status
Simulation time 1817222443 ps
CPU time 26.4 seconds
Started May 26 02:47:45 PM PDT 24
Finished May 26 02:48:12 PM PDT 24
Peak memory 248144 kb
Host smart-13ab3341-01d1-4265-be8b-b26dc4eea496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=751369190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.751369190
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2219712838
Short name T155
Test name
Test status
Simulation time 10715406 ps
CPU time 1.42 seconds
Started May 26 02:48:12 PM PDT 24
Finished May 26 02:48:15 PM PDT 24
Peak memory 234620 kb
Host smart-26242663-9897-4c85-96ef-f60fc469fa76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2219712838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2219712838
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3719775694
Short name T801
Test name
Test status
Simulation time 13826968 ps
CPU time 1.54 seconds
Started May 26 02:48:10 PM PDT 24
Finished May 26 02:48:14 PM PDT 24
Peak memory 235668 kb
Host smart-f34dc76f-8a29-4fa2-9551-0c62c9e4670d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3719775694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3719775694
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4049560016
Short name T154
Test name
Test status
Simulation time 18594534 ps
CPU time 1.35 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 236528 kb
Host smart-470e26f2-4c0c-42be-8e56-5b6eb0d3f4ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4049560016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4049560016
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1323268153
Short name T724
Test name
Test status
Simulation time 11605222 ps
CPU time 1.48 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 236760 kb
Host smart-30da3a07-12dc-4904-ba9b-1b03d60fdc08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323268153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1323268153
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.126381982
Short name T739
Test name
Test status
Simulation time 10775857 ps
CPU time 1.57 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 234672 kb
Host smart-2b83c5a4-d273-4583-903e-9e141d309ed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126381982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.126381982
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2024577710
Short name T215
Test name
Test status
Simulation time 27997613 ps
CPU time 1.41 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:48:16 PM PDT 24
Peak memory 234632 kb
Host smart-292e52a3-7a02-4607-b0d6-b2735d0bc74f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2024577710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2024577710
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3679071930
Short name T818
Test name
Test status
Simulation time 11169700 ps
CPU time 1.26 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 236612 kb
Host smart-f4f0d1aa-9237-44d5-b900-892e5bb4295a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3679071930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3679071930
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.535978854
Short name T808
Test name
Test status
Simulation time 31883277 ps
CPU time 1.18 seconds
Started May 26 02:48:15 PM PDT 24
Finished May 26 02:48:18 PM PDT 24
Peak memory 235560 kb
Host smart-2e1b6220-efdf-4426-8039-75165dd21cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=535978854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.535978854
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3899157932
Short name T754
Test name
Test status
Simulation time 4144243687 ps
CPU time 67.65 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:48:59 PM PDT 24
Peak memory 240196 kb
Host smart-d5cc0730-332b-4085-b817-5148e6267202
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3899157932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3899157932
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3516746003
Short name T750
Test name
Test status
Simulation time 77799584845 ps
CPU time 480.71 seconds
Started May 26 02:47:52 PM PDT 24
Finished May 26 02:55:54 PM PDT 24
Peak memory 236504 kb
Host smart-cc67ef15-f862-4108-9dbb-c479bffeb949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3516746003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3516746003
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2917587735
Short name T192
Test name
Test status
Simulation time 68031264 ps
CPU time 6.21 seconds
Started May 26 02:47:47 PM PDT 24
Finished May 26 02:47:55 PM PDT 24
Peak memory 240132 kb
Host smart-99e2b7a3-6275-4e22-83bf-abaa862e63c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2917587735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2917587735
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3230216334
Short name T327
Test name
Test status
Simulation time 101044060 ps
CPU time 4.76 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:47:55 PM PDT 24
Peak memory 240128 kb
Host smart-85abb7b9-bba4-4958-99df-0898fcff4858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230216334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3230216334
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2398216787
Short name T753
Test name
Test status
Simulation time 482679813 ps
CPU time 8.78 seconds
Started May 26 02:47:50 PM PDT 24
Finished May 26 02:48:01 PM PDT 24
Peak memory 236572 kb
Host smart-e2e6d311-e1a9-44d9-8eb3-5686d96c8bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2398216787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2398216787
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2396032849
Short name T772
Test name
Test status
Simulation time 8948199 ps
CPU time 1.58 seconds
Started May 26 02:47:50 PM PDT 24
Finished May 26 02:47:53 PM PDT 24
Peak memory 235684 kb
Host smart-8335f973-72ce-456a-b0b9-999dcb5d8115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2396032849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2396032849
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3934688925
Short name T761
Test name
Test status
Simulation time 181819014 ps
CPU time 25.19 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:48:16 PM PDT 24
Peak memory 244768 kb
Host smart-d3bf8f6d-2d2a-4c27-bcd0-2797a7bcd03c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3934688925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3934688925
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2634725680
Short name T827
Test name
Test status
Simulation time 2051852947 ps
CPU time 137.17 seconds
Started May 26 02:47:46 PM PDT 24
Finished May 26 02:50:05 PM PDT 24
Peak memory 265072 kb
Host smart-e1486fda-59f2-4659-9b05-8532878af693
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2634725680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2634725680
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2547398290
Short name T145
Test name
Test status
Simulation time 12728411906 ps
CPU time 445.05 seconds
Started May 26 02:47:52 PM PDT 24
Finished May 26 02:55:18 PM PDT 24
Peak memory 265124 kb
Host smart-5b09a0a1-c15d-4231-a0a4-856fd44ff457
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547398290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2547398290
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2285752872
Short name T719
Test name
Test status
Simulation time 440157536 ps
CPU time 16.04 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:48:07 PM PDT 24
Peak memory 253876 kb
Host smart-69238cac-736d-43be-be08-c310bcc275d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2285752872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2285752872
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2565932214
Short name T322
Test name
Test status
Simulation time 14915387 ps
CPU time 1.68 seconds
Started May 26 02:48:14 PM PDT 24
Finished May 26 02:48:18 PM PDT 24
Peak memory 236600 kb
Host smart-77e8a1b5-7967-4855-9cb3-ce262c4ab050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2565932214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2565932214
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.317232404
Short name T819
Test name
Test status
Simulation time 9278417 ps
CPU time 1.61 seconds
Started May 26 02:48:13 PM PDT 24
Finished May 26 02:48:17 PM PDT 24
Peak memory 235632 kb
Host smart-066680b1-7f3b-49fa-a00f-acac81ef93de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=317232404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.317232404
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2560626238
Short name T773
Test name
Test status
Simulation time 9825119 ps
CPU time 1.56 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 235680 kb
Host smart-ac3f649f-e169-4076-9733-60273a3eb4a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2560626238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2560626238
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2980484203
Short name T738
Test name
Test status
Simulation time 22770462 ps
CPU time 1.41 seconds
Started May 26 02:48:19 PM PDT 24
Finished May 26 02:48:22 PM PDT 24
Peak memory 236604 kb
Host smart-dfbf32ef-3dfb-4d7c-bbc6-016a4030f37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2980484203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2980484203
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.980302718
Short name T748
Test name
Test status
Simulation time 9381782 ps
CPU time 1.34 seconds
Started May 26 02:48:22 PM PDT 24
Finished May 26 02:48:25 PM PDT 24
Peak memory 234668 kb
Host smart-f6e4c107-5d97-4857-801e-747711d9bcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=980302718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.980302718
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1016380070
Short name T319
Test name
Test status
Simulation time 8991388 ps
CPU time 1.51 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:25 PM PDT 24
Peak memory 236608 kb
Host smart-602f75b6-633a-482e-a85d-132cbf31a8d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016380070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1016380070
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1876376222
Short name T323
Test name
Test status
Simulation time 20632698 ps
CPU time 1.43 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:33 PM PDT 24
Peak memory 236592 kb
Host smart-394ca535-37fb-40c1-a84b-550a3dde64ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1876376222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1876376222
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3906453623
Short name T790
Test name
Test status
Simulation time 6823017 ps
CPU time 1.4 seconds
Started May 26 02:48:20 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 236616 kb
Host smart-affc150b-8660-4006-8268-93a471a0461b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3906453623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3906453623
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2225285473
Short name T756
Test name
Test status
Simulation time 7665690 ps
CPU time 1.47 seconds
Started May 26 02:48:20 PM PDT 24
Finished May 26 02:48:22 PM PDT 24
Peak memory 234652 kb
Host smart-564046d0-212a-4368-9ff4-683d28f658a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2225285473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2225285473
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1722847533
Short name T767
Test name
Test status
Simulation time 7542582 ps
CPU time 1.48 seconds
Started May 26 02:48:20 PM PDT 24
Finished May 26 02:48:23 PM PDT 24
Peak memory 234640 kb
Host smart-21eb0e73-e240-4c75-bf12-2ad7b0bdb9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1722847533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1722847533
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3144759126
Short name T811
Test name
Test status
Simulation time 4237848817 ps
CPU time 159.18 seconds
Started May 26 02:47:51 PM PDT 24
Finished May 26 02:50:31 PM PDT 24
Peak memory 240208 kb
Host smart-97ba97b5-e23c-42f7-b815-d7df2502cb17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3144759126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3144759126
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1038399240
Short name T732
Test name
Test status
Simulation time 5692712557 ps
CPU time 325.11 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:53:16 PM PDT 24
Peak memory 240196 kb
Host smart-63dfa850-82ef-4d8c-a040-c36983deb6d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1038399240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1038399240
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3381046936
Short name T800
Test name
Test status
Simulation time 635631408 ps
CPU time 9.29 seconds
Started May 26 02:47:47 PM PDT 24
Finished May 26 02:47:57 PM PDT 24
Peak memory 240128 kb
Host smart-3447087f-878e-4a85-be93-e0c0b4692ce5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3381046936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3381046936
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4223817526
Short name T324
Test name
Test status
Simulation time 220584976 ps
CPU time 12.09 seconds
Started May 26 02:47:50 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 250496 kb
Host smart-9f48797c-7de3-4e5c-8bcc-07d009f389f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223817526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4223817526
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3744121691
Short name T804
Test name
Test status
Simulation time 108859002 ps
CPU time 8.31 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:47:58 PM PDT 24
Peak memory 235604 kb
Host smart-8c42229e-c8cc-4da5-998e-a64aaa8bd649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3744121691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3744121691
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1453090825
Short name T734
Test name
Test status
Simulation time 6895826 ps
CPU time 1.54 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:47:52 PM PDT 24
Peak memory 235668 kb
Host smart-71c10ffc-3fcb-4551-846b-108539de3b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1453090825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1453090825
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1818378912
Short name T182
Test name
Test status
Simulation time 166683089 ps
CPU time 23.51 seconds
Started May 26 02:47:50 PM PDT 24
Finished May 26 02:48:15 PM PDT 24
Peak memory 244784 kb
Host smart-d610db83-35ad-40af-a541-3be07a0ce242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1818378912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1818378912
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2239157826
Short name T139
Test name
Test status
Simulation time 2885273113 ps
CPU time 222.59 seconds
Started May 26 02:47:52 PM PDT 24
Finished May 26 02:51:36 PM PDT 24
Peak memory 265136 kb
Host smart-8a2c64ca-d3f0-4a8b-9512-86e066cfcb2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2239157826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2239157826
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.624570071
Short name T329
Test name
Test status
Simulation time 12597698637 ps
CPU time 1022.79 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 03:04:54 PM PDT 24
Peak memory 265056 kb
Host smart-69143dd9-7f5a-41e4-9154-49b2afc364c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624570071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.624570071
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3133095015
Short name T744
Test name
Test status
Simulation time 570196431 ps
CPU time 11.5 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:48:01 PM PDT 24
Peak memory 248364 kb
Host smart-64dea012-ef5a-4bde-81ff-bdb0ec492eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3133095015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3133095015
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2507524095
Short name T817
Test name
Test status
Simulation time 10393586 ps
CPU time 1.66 seconds
Started May 26 02:48:20 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 235644 kb
Host smart-3c9bc15b-448f-4294-bbca-bca8a90fd023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2507524095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2507524095
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2984299002
Short name T816
Test name
Test status
Simulation time 10748233 ps
CPU time 1.43 seconds
Started May 26 02:48:19 PM PDT 24
Finished May 26 02:48:21 PM PDT 24
Peak memory 236564 kb
Host smart-360bb805-28e9-4d66-92b0-c8e846a1fe8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2984299002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2984299002
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1413120903
Short name T770
Test name
Test status
Simulation time 12492786 ps
CPU time 1.35 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 236612 kb
Host smart-15f77bf9-41ec-4f70-a216-76cf0b699c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1413120903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1413120903
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1570867631
Short name T758
Test name
Test status
Simulation time 29232097 ps
CPU time 1.45 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:33 PM PDT 24
Peak memory 236596 kb
Host smart-97558977-7b81-4ce8-a071-468acb8baa4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1570867631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1570867631
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3766305280
Short name T805
Test name
Test status
Simulation time 10326628 ps
CPU time 1.6 seconds
Started May 26 02:48:30 PM PDT 24
Finished May 26 02:48:33 PM PDT 24
Peak memory 236596 kb
Host smart-0ec53e59-27a2-4ad3-b6d8-a721fef3bfb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3766305280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3766305280
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1209238110
Short name T737
Test name
Test status
Simulation time 7438513 ps
CPU time 1.41 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 236612 kb
Host smart-a339461d-6df3-4fe8-9ccc-7c18a42182ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1209238110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1209238110
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1611776898
Short name T725
Test name
Test status
Simulation time 8040152 ps
CPU time 1.54 seconds
Started May 26 02:48:20 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 235672 kb
Host smart-41c87460-6c61-43df-90b0-32361fb40582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1611776898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1611776898
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3742407902
Short name T771
Test name
Test status
Simulation time 18389201 ps
CPU time 1.92 seconds
Started May 26 02:48:22 PM PDT 24
Finished May 26 02:48:26 PM PDT 24
Peak memory 235688 kb
Host smart-a812f319-a890-4775-b651-05fc01079efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3742407902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3742407902
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3946810137
Short name T824
Test name
Test status
Simulation time 12108505 ps
CPU time 1.36 seconds
Started May 26 02:48:21 PM PDT 24
Finished May 26 02:48:24 PM PDT 24
Peak memory 236532 kb
Host smart-f5ffce5e-6cf5-4893-9e9c-81fa4c49965b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3946810137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3946810137
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.289739823
Short name T762
Test name
Test status
Simulation time 10626423 ps
CPU time 1.24 seconds
Started May 26 02:48:19 PM PDT 24
Finished May 26 02:48:21 PM PDT 24
Peak memory 236580 kb
Host smart-26374fe3-51f1-4cdb-8eda-7f9eda8b9a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289739823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.289739823
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4247159769
Short name T173
Test name
Test status
Simulation time 37704035 ps
CPU time 5.32 seconds
Started May 26 02:47:51 PM PDT 24
Finished May 26 02:47:57 PM PDT 24
Peak memory 250564 kb
Host smart-2894582d-7a2f-40a0-9914-0d3a6e078dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247159769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4247159769
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1834595158
Short name T220
Test name
Test status
Simulation time 125155557 ps
CPU time 9.25 seconds
Started May 26 02:47:47 PM PDT 24
Finished May 26 02:47:58 PM PDT 24
Peak memory 236592 kb
Host smart-21e67663-1404-466b-a396-67481b30375c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1834595158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1834595158
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.225021209
Short name T731
Test name
Test status
Simulation time 8006643 ps
CPU time 1.56 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:47:52 PM PDT 24
Peak memory 236588 kb
Host smart-d66ff52c-e700-47a2-955e-37a82cf51c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=225021209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.225021209
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.100261419
Short name T794
Test name
Test status
Simulation time 91612659 ps
CPU time 11.69 seconds
Started May 26 02:47:52 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 244776 kb
Host smart-61a3438d-c612-4faf-83ce-cdab3f4c4bb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=100261419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.100261419
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1058022392
Short name T134
Test name
Test status
Simulation time 5346485749 ps
CPU time 98.25 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:49:30 PM PDT 24
Peak memory 266148 kb
Host smart-b3d1b8f4-177d-42c6-a6eb-dd2cc5ef988d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1058022392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1058022392
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1113429881
Short name T148
Test name
Test status
Simulation time 32384879404 ps
CPU time 583.5 seconds
Started May 26 02:47:49 PM PDT 24
Finished May 26 02:57:34 PM PDT 24
Peak memory 267696 kb
Host smart-0afca1ff-c47d-4d41-98ad-e89497ad515a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113429881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1113429881
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2855267221
Short name T784
Test name
Test status
Simulation time 758302426 ps
CPU time 12.83 seconds
Started May 26 02:47:48 PM PDT 24
Finished May 26 02:48:02 PM PDT 24
Peak memory 248352 kb
Host smart-96314e1d-727a-4d67-922c-3e220bbe29b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2855267221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2855267221
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2088470451
Short name T830
Test name
Test status
Simulation time 32461747 ps
CPU time 5.34 seconds
Started May 26 02:47:59 PM PDT 24
Finished May 26 02:48:05 PM PDT 24
Peak memory 240476 kb
Host smart-9758eb72-ed2e-44de-85ef-f9f1c3d239a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088470451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2088470451
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3707380341
Short name T786
Test name
Test status
Simulation time 121076766 ps
CPU time 5.9 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 236572 kb
Host smart-1916afe1-3e3b-4c54-af54-43747f22a698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3707380341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3707380341
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1019713048
Short name T792
Test name
Test status
Simulation time 9180345 ps
CPU time 1.45 seconds
Started May 26 02:47:57 PM PDT 24
Finished May 26 02:47:59 PM PDT 24
Peak memory 234652 kb
Host smart-44758578-71f4-495a-ad46-ec3ebcc7669b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019713048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1019713048
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3883375587
Short name T178
Test name
Test status
Simulation time 1371744084 ps
CPU time 47.86 seconds
Started May 26 02:47:59 PM PDT 24
Finished May 26 02:48:48 PM PDT 24
Peak memory 244780 kb
Host smart-230c976c-9a7b-499a-9bf7-7ef1a3a88bc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3883375587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3883375587
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3082169601
Short name T117
Test name
Test status
Simulation time 15748770178 ps
CPU time 312.4 seconds
Started May 26 02:47:47 PM PDT 24
Finished May 26 02:53:01 PM PDT 24
Peak memory 265300 kb
Host smart-d24ee62c-52a1-4500-a2c2-1c6bdf39ce52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3082169601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3082169601
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3664380527
Short name T144
Test name
Test status
Simulation time 4087848614 ps
CPU time 314.65 seconds
Started May 26 02:47:47 PM PDT 24
Finished May 26 02:53:03 PM PDT 24
Peak memory 265332 kb
Host smart-ce7c7d76-95b6-4c09-82e7-8da6d3f19086
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664380527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3664380527
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1997785327
Short name T812
Test name
Test status
Simulation time 383498237 ps
CPU time 8.41 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 248388 kb
Host smart-60e3af86-e60f-4852-bfae-9515ce8c13d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1997785327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1997785327
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3670910331
Short name T823
Test name
Test status
Simulation time 85328090 ps
CPU time 7.09 seconds
Started May 26 02:47:57 PM PDT 24
Finished May 26 02:48:05 PM PDT 24
Peak memory 242424 kb
Host smart-604e984e-95d0-4498-972a-75aa5ad5d7a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670910331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3670910331
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1887768864
Short name T789
Test name
Test status
Simulation time 182243684 ps
CPU time 8.16 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:48:03 PM PDT 24
Peak memory 240108 kb
Host smart-7737f1c7-6428-4013-9aa0-80a6cbdcf677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1887768864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1887768864
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4233289895
Short name T766
Test name
Test status
Simulation time 16121037 ps
CPU time 1.8 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:47:58 PM PDT 24
Peak memory 236616 kb
Host smart-e4244b6b-8a0f-49b5-b0e6-6e3f4c0b188b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233289895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4233289895
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3615184900
Short name T740
Test name
Test status
Simulation time 98352855 ps
CPU time 13.65 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:48:10 PM PDT 24
Peak memory 244784 kb
Host smart-1f9acbb2-f006-4cf7-a748-3ef81e1f8deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3615184900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3615184900
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1763497123
Short name T143
Test name
Test status
Simulation time 6315706122 ps
CPU time 205.39 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:51:22 PM PDT 24
Peak memory 265224 kb
Host smart-8f8d10ea-a128-43b9-af4f-08c213d4f5f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1763497123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1763497123
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1814839858
Short name T121
Test name
Test status
Simulation time 2315106787 ps
CPU time 321.28 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:53:21 PM PDT 24
Peak memory 265296 kb
Host smart-2b67c5ca-5c3c-4a93-b0ac-a95ed9dda882
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814839858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1814839858
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1394413832
Short name T815
Test name
Test status
Simulation time 1225049473 ps
CPU time 23.74 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:23 PM PDT 24
Peak memory 247540 kb
Host smart-908b10e5-9d41-4286-9c35-9bc89e559d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1394413832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1394413832
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3095772278
Short name T735
Test name
Test status
Simulation time 37790932 ps
CPU time 5.51 seconds
Started May 26 02:47:57 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 242108 kb
Host smart-64eaa91d-f6fe-4d70-8004-7dd352fa16ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095772278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3095772278
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.678208541
Short name T780
Test name
Test status
Simulation time 121006734 ps
CPU time 3.39 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:03 PM PDT 24
Peak memory 238432 kb
Host smart-1c05c1c5-5da9-4126-abe3-c8cdedc03896
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=678208541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.678208541
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.970410236
Short name T321
Test name
Test status
Simulation time 27294732 ps
CPU time 1.54 seconds
Started May 26 02:47:59 PM PDT 24
Finished May 26 02:48:02 PM PDT 24
Peak memory 236592 kb
Host smart-c1a5f001-9673-497b-bfb5-5121f8f130c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=970410236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.970410236
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3386177301
Short name T795
Test name
Test status
Simulation time 611945463 ps
CPU time 42.92 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:43 PM PDT 24
Peak memory 240080 kb
Host smart-917f2822-a2ed-460d-9aef-0853f17c6767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3386177301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3386177301
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3805719645
Short name T127
Test name
Test status
Simulation time 44327654322 ps
CPU time 517.59 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:56:37 PM PDT 24
Peak memory 265140 kb
Host smart-ee0cb0d3-9333-4459-bde9-7fd7d2c8e8e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805719645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3805719645
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1524653413
Short name T802
Test name
Test status
Simulation time 128810479 ps
CPU time 4.51 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:04 PM PDT 24
Peak memory 249688 kb
Host smart-9e8be27c-8cf9-4fe5-9665-f337d5ef7545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1524653413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1524653413
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2225476450
Short name T325
Test name
Test status
Simulation time 70783421 ps
CPU time 5.71 seconds
Started May 26 02:47:59 PM PDT 24
Finished May 26 02:48:06 PM PDT 24
Peak memory 237160 kb
Host smart-5ca2f656-dff8-4d13-9899-630e6d906516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225476450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2225476450
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1573096490
Short name T721
Test name
Test status
Simulation time 276078328 ps
CPU time 4.34 seconds
Started May 26 02:48:01 PM PDT 24
Finished May 26 02:48:06 PM PDT 24
Peak memory 238424 kb
Host smart-7be801c9-e583-4b65-873b-ad59a23fcee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1573096490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1573096490
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2087254202
Short name T788
Test name
Test status
Simulation time 17712431 ps
CPU time 1.89 seconds
Started May 26 02:47:58 PM PDT 24
Finished May 26 02:48:01 PM PDT 24
Peak memory 235680 kb
Host smart-b2f50af6-5cee-467d-9fd7-4ca609564595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2087254202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2087254202
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1991665789
Short name T825
Test name
Test status
Simulation time 594747150 ps
CPU time 23.34 seconds
Started May 26 02:47:55 PM PDT 24
Finished May 26 02:48:20 PM PDT 24
Peak memory 248320 kb
Host smart-be3c5984-d8cb-439e-ac63-2d06019b1268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1991665789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1991665789
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2720600829
Short name T146
Test name
Test status
Simulation time 16142791701 ps
CPU time 308.62 seconds
Started May 26 02:47:59 PM PDT 24
Finished May 26 02:53:09 PM PDT 24
Peak memory 265300 kb
Host smart-0fcc3c42-9968-40b6-9781-c473ee5245ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2720600829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2720600829
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3231417713
Short name T791
Test name
Test status
Simulation time 400673534 ps
CPU time 5.56 seconds
Started May 26 02:47:56 PM PDT 24
Finished May 26 02:48:02 PM PDT 24
Peak memory 248184 kb
Host smart-b921f337-1d44-4b15-9271-de0c48a5091a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3231417713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3231417713
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.276449677
Short name T584
Test name
Test status
Simulation time 21341178071 ps
CPU time 1227.4 seconds
Started May 26 01:22:12 PM PDT 24
Finished May 26 01:42:40 PM PDT 24
Peak memory 272008 kb
Host smart-c7aac25c-81a9-45e7-91b5-8192bfc1f0c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276449677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.276449677
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4272913397
Short name T600
Test name
Test status
Simulation time 262194984 ps
CPU time 8.97 seconds
Started May 26 01:21:56 PM PDT 24
Finished May 26 01:22:06 PM PDT 24
Peak memory 240604 kb
Host smart-1df35c6b-0dba-4a54-91f7-fda81c5ff4fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4272913397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4272913397
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1840790270
Short name T395
Test name
Test status
Simulation time 4227083214 ps
CPU time 72.96 seconds
Started May 26 01:22:01 PM PDT 24
Finished May 26 01:23:15 PM PDT 24
Peak memory 255608 kb
Host smart-c133dfb4-ee10-46e6-a1b1-92753d6eab05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18407
90270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1840790270
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.361739259
Short name T603
Test name
Test status
Simulation time 501723466 ps
CPU time 8.67 seconds
Started May 26 01:22:18 PM PDT 24
Finished May 26 01:22:27 PM PDT 24
Peak memory 248784 kb
Host smart-0876307b-3460-40f9-b821-909923ff028c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36173
9259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.361739259
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2073832841
Short name T306
Test name
Test status
Simulation time 30041999205 ps
CPU time 1761.48 seconds
Started May 26 01:22:10 PM PDT 24
Finished May 26 01:51:32 PM PDT 24
Peak memory 273460 kb
Host smart-f7c5e7cb-681c-4167-8832-fe2c05d648af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073832841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2073832841
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3588087901
Short name T550
Test name
Test status
Simulation time 24667796267 ps
CPU time 1455.92 seconds
Started May 26 01:21:58 PM PDT 24
Finished May 26 01:46:14 PM PDT 24
Peak memory 273052 kb
Host smart-a2604d2e-55e1-4886-884a-707bcc7cd90c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588087901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3588087901
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3056944816
Short name T539
Test name
Test status
Simulation time 5346669223 ps
CPU time 25.16 seconds
Started May 26 01:22:14 PM PDT 24
Finished May 26 01:22:40 PM PDT 24
Peak memory 256024 kb
Host smart-29168f8d-e503-4188-aa30-b9ed49a2817d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30569
44816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3056944816
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1118738783
Short name T69
Test name
Test status
Simulation time 1031250779 ps
CPU time 62.39 seconds
Started May 26 01:22:03 PM PDT 24
Finished May 26 01:23:06 PM PDT 24
Peak memory 256684 kb
Host smart-a75accee-3092-4276-bec9-6e6dbcf3daf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11187
38783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1118738783
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1100422843
Short name T25
Test name
Test status
Simulation time 1795453615 ps
CPU time 24.92 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:22:35 PM PDT 24
Peak memory 270172 kb
Host smart-9f2030f5-eb42-4c0e-9fc0-36c1650706f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1100422843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1100422843
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3448742218
Short name T390
Test name
Test status
Simulation time 1972426158 ps
CPU time 18.79 seconds
Started May 26 01:21:57 PM PDT 24
Finished May 26 01:22:16 PM PDT 24
Peak memory 255892 kb
Host smart-7024a5fb-697a-4e5b-9b03-a6e7b5766b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34487
42218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3448742218
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1051513372
Short name T570
Test name
Test status
Simulation time 34281041825 ps
CPU time 940.05 seconds
Started May 26 01:21:59 PM PDT 24
Finished May 26 01:37:39 PM PDT 24
Peak memory 272656 kb
Host smart-d18f5f60-7e42-4ad5-9f28-fade030f2d94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051513372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1051513372
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3366472297
Short name T261
Test name
Test status
Simulation time 41908228904 ps
CPU time 810.8 seconds
Started May 26 01:22:05 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 270868 kb
Host smart-87959bf8-8b56-49e5-888a-2a86025c0b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366472297 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3366472297
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1970147725
Short name T389
Test name
Test status
Simulation time 3683403658 ps
CPU time 41.38 seconds
Started May 26 01:22:02 PM PDT 24
Finished May 26 01:22:44 PM PDT 24
Peak memory 251696 kb
Host smart-f29e9604-eee0-4201-be50-3ffb848fa3e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1970147725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1970147725
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1598157426
Short name T504
Test name
Test status
Simulation time 7010716220 ps
CPU time 108.61 seconds
Started May 26 01:22:15 PM PDT 24
Finished May 26 01:24:04 PM PDT 24
Peak memory 249180 kb
Host smart-6d52320e-60eb-459b-8a66-47ea05a40528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
57426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1598157426
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3357054059
Short name T255
Test name
Test status
Simulation time 3257615804 ps
CPU time 31.09 seconds
Started May 26 01:22:10 PM PDT 24
Finished May 26 01:22:42 PM PDT 24
Peak memory 248836 kb
Host smart-1ae26c25-8b77-4b1a-81f4-846c3c591cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33570
54059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3357054059
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2235667802
Short name T310
Test name
Test status
Simulation time 66106569079 ps
CPU time 2153.28 seconds
Started May 26 01:22:03 PM PDT 24
Finished May 26 01:57:57 PM PDT 24
Peak memory 286704 kb
Host smart-65bf5978-5488-4aaf-8f1e-5bf029af24a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235667802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2235667802
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.862601697
Short name T401
Test name
Test status
Simulation time 6174285709 ps
CPU time 28.2 seconds
Started May 26 01:21:59 PM PDT 24
Finished May 26 01:22:28 PM PDT 24
Peak memory 256896 kb
Host smart-5b8b1ef7-8e2e-43bf-a18c-9785a2ee6926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86260
1697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.862601697
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2343094419
Short name T520
Test name
Test status
Simulation time 444984033 ps
CPU time 24.93 seconds
Started May 26 01:21:57 PM PDT 24
Finished May 26 01:22:22 PM PDT 24
Peak memory 248720 kb
Host smart-aafad9a2-0926-4e67-abc8-a55a75e9f646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
94419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2343094419
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.344724624
Short name T12
Test name
Test status
Simulation time 1443546128 ps
CPU time 21.33 seconds
Started May 26 01:22:02 PM PDT 24
Finished May 26 01:22:24 PM PDT 24
Peak memory 266728 kb
Host smart-62c384a0-3e9f-436e-b165-5f64ddb35fae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=344724624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.344724624
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1229301777
Short name T442
Test name
Test status
Simulation time 274919860 ps
CPU time 18.6 seconds
Started May 26 01:21:58 PM PDT 24
Finished May 26 01:22:17 PM PDT 24
Peak memory 248728 kb
Host smart-fd894c22-e900-4050-bf79-0e61ac92b5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293
01777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1229301777
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1728322453
Short name T681
Test name
Test status
Simulation time 255056641 ps
CPU time 8.99 seconds
Started May 26 01:22:02 PM PDT 24
Finished May 26 01:22:12 PM PDT 24
Peak memory 257100 kb
Host smart-699b0e5e-c4ce-4d46-b002-aa0dc8883b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17283
22453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1728322453
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.829636335
Short name T391
Test name
Test status
Simulation time 5030533751 ps
CPU time 73.48 seconds
Started May 26 01:21:57 PM PDT 24
Finished May 26 01:23:11 PM PDT 24
Peak memory 257152 kb
Host smart-f19ff032-a44a-48ad-9114-0c2c655271e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829636335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.829636335
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3760358416
Short name T195
Test name
Test status
Simulation time 87364257 ps
CPU time 2.33 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:22:44 PM PDT 24
Peak memory 248896 kb
Host smart-c35cdb51-cf43-4669-b1dd-429b1113e5bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3760358416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3760358416
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.252825582
Short name T541
Test name
Test status
Simulation time 56919286471 ps
CPU time 3344.78 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 02:18:14 PM PDT 24
Peak memory 289464 kb
Host smart-33e065b2-5c25-49f7-897b-c1a77176bda2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252825582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.252825582
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.4096687250
Short name T430
Test name
Test status
Simulation time 1663986100 ps
CPU time 66.54 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:23:48 PM PDT 24
Peak memory 248780 kb
Host smart-daf621b7-5e3f-4041-b0f4-ca010e9ee26a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4096687250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.4096687250
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4264213054
Short name T387
Test name
Test status
Simulation time 42381946652 ps
CPU time 278.6 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:27:24 PM PDT 24
Peak memory 252020 kb
Host smart-84de9619-1119-43e7-a191-2cefbe657f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642
13054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4264213054
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4231002785
Short name T476
Test name
Test status
Simulation time 418244516 ps
CPU time 33.87 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:23:09 PM PDT 24
Peak memory 255972 kb
Host smart-804a68db-0eb2-49a2-8295-72692f575e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
02785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4231002785
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2960501673
Short name T299
Test name
Test status
Simulation time 29410627768 ps
CPU time 1765.17 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:51:50 PM PDT 24
Peak memory 273404 kb
Host smart-17ef9bbd-9296-4019-8ef8-f0bc025e45a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960501673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2960501673
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3622814449
Short name T685
Test name
Test status
Simulation time 6326622197 ps
CPU time 666.64 seconds
Started May 26 01:22:37 PM PDT 24
Finished May 26 01:33:44 PM PDT 24
Peak memory 273436 kb
Host smart-29d8adb0-2f80-4e8d-9ae2-1468df62e165
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622814449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3622814449
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3752092784
Short name T679
Test name
Test status
Simulation time 32079434218 ps
CPU time 645.11 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 248100 kb
Host smart-3aa19454-42c3-482a-8f29-554bbd953240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752092784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3752092784
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.111854902
Short name T546
Test name
Test status
Simulation time 1026777392 ps
CPU time 26.17 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:55 PM PDT 24
Peak memory 255608 kb
Host smart-fbd69250-ea0f-4ff1-8638-aec0396d8615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
4902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.111854902
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4235373993
Short name T444
Test name
Test status
Simulation time 139590685 ps
CPU time 4.14 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:22:31 PM PDT 24
Peak memory 240500 kb
Host smart-c7ee85c6-c112-46d3-adc7-0c0f03afddc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42353
73993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4235373993
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1517906560
Short name T377
Test name
Test status
Simulation time 1356733969 ps
CPU time 37.26 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:23:06 PM PDT 24
Peak memory 248772 kb
Host smart-b5fa0ba2-1b46-4c76-9fff-31596a683bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
06560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1517906560
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.288659728
Short name T193
Test name
Test status
Simulation time 52052709 ps
CPU time 2.64 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:22:44 PM PDT 24
Peak memory 248924 kb
Host smart-cdab64eb-aa22-4f83-8baf-3cdb04e631cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=288659728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.288659728
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4157584538
Short name T214
Test name
Test status
Simulation time 258618578 ps
CPU time 9.24 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:22:41 PM PDT 24
Peak memory 248816 kb
Host smart-0ca41b17-2733-440c-b72a-381bd13dfc53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4157584538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4157584538
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1556881681
Short name T515
Test name
Test status
Simulation time 4924902048 ps
CPU time 272.33 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:27:09 PM PDT 24
Peak memory 256920 kb
Host smart-f858ad6b-dc39-454c-b61c-4dbfc0803e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15568
81681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1556881681
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2033532900
Short name T711
Test name
Test status
Simulation time 4815260152 ps
CPU time 72.47 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:23:40 PM PDT 24
Peak memory 256360 kb
Host smart-6cf80c61-2eef-44f6-b7b8-c05afc65b86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20335
32900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2033532900
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1344049620
Short name T308
Test name
Test status
Simulation time 48527518276 ps
CPU time 867.75 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:36:57 PM PDT 24
Peak memory 272824 kb
Host smart-d12a4ae8-1bdd-4af2-81f4-93f3965ccb0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344049620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1344049620
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3363459159
Short name T101
Test name
Test status
Simulation time 17670472977 ps
CPU time 1200.36 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:42:30 PM PDT 24
Peak memory 272308 kb
Host smart-b1e14474-9b5a-415c-87a8-98e2147c12c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363459159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3363459159
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1319748124
Short name T249
Test name
Test status
Simulation time 6370051601 ps
CPU time 248.23 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:26:44 PM PDT 24
Peak memory 248068 kb
Host smart-c2004a0c-452c-413c-843e-8496033dbee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319748124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1319748124
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2542971641
Short name T365
Test name
Test status
Simulation time 400131264 ps
CPU time 7.56 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:22:54 PM PDT 24
Peak memory 253176 kb
Host smart-6ff3d20e-fd16-4d52-9411-8eb0c6fe2c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25429
71641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2542971641
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.756001206
Short name T190
Test name
Test status
Simulation time 250756118 ps
CPU time 7.58 seconds
Started May 26 01:22:37 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 254108 kb
Host smart-9213f5f2-6c02-47b2-896f-e0417d5e7be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75600
1206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.756001206
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.177767734
Short name T28
Test name
Test status
Simulation time 1375328855 ps
CPU time 43.93 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 249152 kb
Host smart-b0ba36d8-8a9d-4dea-ad73-d67b7120798a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
7734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.177767734
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2048087982
Short name T680
Test name
Test status
Simulation time 8017896530 ps
CPU time 32.28 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:23:08 PM PDT 24
Peak memory 256276 kb
Host smart-f1c0bcaf-285d-4329-9c3e-1cf5913f9f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20480
87982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2048087982
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.4082108609
Short name T54
Test name
Test status
Simulation time 40766657546 ps
CPU time 711.17 seconds
Started May 26 01:22:32 PM PDT 24
Finished May 26 01:34:24 PM PDT 24
Peak memory 269544 kb
Host smart-6e679766-980c-4c2c-9a6b-5dfe56cc1aa6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082108609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.4082108609
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4068772416
Short name T360
Test name
Test status
Simulation time 58371539104 ps
CPU time 2321.65 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 02:01:22 PM PDT 24
Peak memory 288776 kb
Host smart-03e0578c-884d-4a12-8832-c4bc1b80d26e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068772416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4068772416
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1571083161
Short name T343
Test name
Test status
Simulation time 1025657833 ps
CPU time 10.52 seconds
Started May 26 01:22:31 PM PDT 24
Finished May 26 01:22:43 PM PDT 24
Peak memory 248700 kb
Host smart-ac2bb755-289e-4ff4-991c-dc3dffeed324
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1571083161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1571083161
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1749181481
Short name T538
Test name
Test status
Simulation time 1313905084 ps
CPU time 131.24 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:24:40 PM PDT 24
Peak memory 256912 kb
Host smart-b001887d-040a-4698-b701-4156d8c48479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17491
81481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1749181481
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3661701405
Short name T27
Test name
Test status
Simulation time 240282485 ps
CPU time 12.17 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:22:39 PM PDT 24
Peak memory 247500 kb
Host smart-7231abe2-dd38-48d7-bcc0-a5dc945b9a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36617
01405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3661701405
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2943448439
Short name T632
Test name
Test status
Simulation time 70153640399 ps
CPU time 3469.83 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 02:20:19 PM PDT 24
Peak memory 288600 kb
Host smart-e3761164-4fe8-42ad-9a7d-efafb3c924bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943448439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2943448439
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1920527419
Short name T461
Test name
Test status
Simulation time 56415505040 ps
CPU time 2309.01 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 02:00:58 PM PDT 24
Peak memory 272892 kb
Host smart-e88cff0f-b747-4009-bac3-b13e61b7bd47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920527419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1920527419
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3090475743
Short name T277
Test name
Test status
Simulation time 13240578370 ps
CPU time 138.51 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:24:51 PM PDT 24
Peak memory 248108 kb
Host smart-aaf827d4-7fb2-480d-98d5-9f0461026f5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090475743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3090475743
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3262719604
Short name T392
Test name
Test status
Simulation time 198590956 ps
CPU time 20.55 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:22:52 PM PDT 24
Peak memory 248740 kb
Host smart-b1014565-ce2d-48c2-b610-a70a4d2b8d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32627
19604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3262719604
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1967628655
Short name T363
Test name
Test status
Simulation time 493406731 ps
CPU time 12.63 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:22:42 PM PDT 24
Peak memory 248760 kb
Host smart-eeba4dee-a23b-4c56-9753-44ad23cd573b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19676
28655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1967628655
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1770982943
Short name T517
Test name
Test status
Simulation time 276191487 ps
CPU time 38.53 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:23:15 PM PDT 24
Peak memory 248704 kb
Host smart-e4ec964d-054c-473b-9cd5-3cd7dd10461a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17709
82943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1770982943
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3581601786
Short name T697
Test name
Test status
Simulation time 204166042 ps
CPU time 15.48 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:44 PM PDT 24
Peak memory 248924 kb
Host smart-13ee1796-0a0d-4197-90ba-ed1ec225797e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35816
01786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3581601786
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.278801045
Short name T435
Test name
Test status
Simulation time 54609574096 ps
CPU time 4406.32 seconds
Started May 26 01:22:23 PM PDT 24
Finished May 26 02:35:51 PM PDT 24
Peak memory 305520 kb
Host smart-2f0f4205-051f-4ba4-a3ab-4f62b645a174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278801045 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.278801045
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3628208846
Short name T208
Test name
Test status
Simulation time 20131144 ps
CPU time 2.91 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:22:47 PM PDT 24
Peak memory 248896 kb
Host smart-98b77db1-0e03-4cd9-9018-fd96c27655d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3628208846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3628208846
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3465172203
Short name T645
Test name
Test status
Simulation time 7597049114 ps
CPU time 888.39 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 268424 kb
Host smart-8c37056b-455e-4216-bf13-7c90d5034b8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465172203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3465172203
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.251286712
Short name T496
Test name
Test status
Simulation time 2462601963 ps
CPU time 54.69 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:23:26 PM PDT 24
Peak memory 240592 kb
Host smart-51b3e976-b432-4ea5-84e0-8d350e4ea65e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=251286712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.251286712
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2437427743
Short name T337
Test name
Test status
Simulation time 1569969684 ps
CPU time 136.79 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:24:58 PM PDT 24
Peak memory 256820 kb
Host smart-394c3479-b218-403e-8dea-759a50e5dfe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24374
27743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2437427743
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.924662190
Short name T595
Test name
Test status
Simulation time 815210462 ps
CPU time 39.89 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:23:21 PM PDT 24
Peak memory 248884 kb
Host smart-32c13acc-c25d-43cd-b817-2bf0931fe6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92466
2190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.924662190
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4152185513
Short name T481
Test name
Test status
Simulation time 52737090690 ps
CPU time 3068.11 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 02:13:54 PM PDT 24
Peak memory 288708 kb
Host smart-9d1dc4d1-2cbf-444c-bcc1-0d2b05c1cce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152185513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4152185513
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.186097200
Short name T278
Test name
Test status
Simulation time 42242239205 ps
CPU time 457.1 seconds
Started May 26 01:22:37 PM PDT 24
Finished May 26 01:30:15 PM PDT 24
Peak memory 248028 kb
Host smart-6f086518-c24f-4197-b640-f327deafef22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186097200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.186097200
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1826334934
Short name T9
Test name
Test status
Simulation time 184654470 ps
CPU time 16.29 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 248736 kb
Host smart-8e3927f5-9593-4ed0-8700-46e3d0e4937d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
34934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1826334934
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1316484149
Short name T629
Test name
Test status
Simulation time 113385843 ps
CPU time 5.03 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:22:48 PM PDT 24
Peak memory 249820 kb
Host smart-7357e9a8-bb8b-4e6d-bcd8-77d770c32658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
84149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1316484149
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3628144429
Short name T67
Test name
Test status
Simulation time 151192185 ps
CPU time 20.66 seconds
Started May 26 01:22:33 PM PDT 24
Finished May 26 01:22:54 PM PDT 24
Peak memory 248708 kb
Host smart-3d233d0f-9b1a-4fa8-a1f3-49cf03fa6ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36281
44429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3628144429
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3089683182
Short name T403
Test name
Test status
Simulation time 1905561254 ps
CPU time 43.27 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:29 PM PDT 24
Peak memory 248788 kb
Host smart-2be77e84-b854-40d2-a731-073dabbf4e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30896
83182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3089683182
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4199822658
Short name T518
Test name
Test status
Simulation time 146540534100 ps
CPU time 1165.92 seconds
Started May 26 01:22:31 PM PDT 24
Finished May 26 01:41:59 PM PDT 24
Peak memory 289264 kb
Host smart-87222f06-17e8-41ed-8855-0430fa52e05a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199822658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4199822658
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3673451761
Short name T443
Test name
Test status
Simulation time 324638313 ps
CPU time 9.86 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:39 PM PDT 24
Peak memory 240572 kb
Host smart-0021f76b-5830-457c-8afe-7047ea0e7363
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3673451761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3673451761
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.4124653476
Short name T393
Test name
Test status
Simulation time 1492140859 ps
CPU time 23.31 seconds
Started May 26 01:22:32 PM PDT 24
Finished May 26 01:22:56 PM PDT 24
Peak memory 248808 kb
Host smart-4db86cf8-2196-41cc-b979-a03fb38cc1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41246
53476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.4124653476
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2743851362
Short name T388
Test name
Test status
Simulation time 172814295 ps
CPU time 10.51 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:22:57 PM PDT 24
Peak memory 252136 kb
Host smart-6c2e80db-8d23-447d-a706-07221a4f13ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27438
51362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2743851362
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1019234266
Short name T668
Test name
Test status
Simulation time 12742568841 ps
CPU time 976.17 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 272072 kb
Host smart-ebb61bfe-71d1-4d58-96e3-fe418890fc63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019234266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1019234266
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1071177333
Short name T6
Test name
Test status
Simulation time 38957954630 ps
CPU time 2461.37 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 02:03:29 PM PDT 24
Peak memory 288408 kb
Host smart-936b8e8f-84a5-461d-b340-14306df45bda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071177333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1071177333
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.197887902
Short name T289
Test name
Test status
Simulation time 8794010546 ps
CPU time 166.56 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:25:30 PM PDT 24
Peak memory 248204 kb
Host smart-afd30774-af0e-4323-97bd-c310f16c6e21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197887902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.197887902
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.4002798879
Short name T336
Test name
Test status
Simulation time 629227667 ps
CPU time 7.56 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 250800 kb
Host smart-14d733f9-a0be-49b8-b8af-0e06184acb42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40027
98879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.4002798879
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4140038027
Short name T65
Test name
Test status
Simulation time 2719341717 ps
CPU time 36.1 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:22 PM PDT 24
Peak memory 255696 kb
Host smart-e723c2c3-95b7-4a9c-9f06-a269d55b6307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41400
38027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4140038027
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3826806188
Short name T7
Test name
Test status
Simulation time 1248958602 ps
CPU time 22.92 seconds
Started May 26 01:22:28 PM PDT 24
Finished May 26 01:22:53 PM PDT 24
Peak memory 248704 kb
Host smart-7373eb1d-0c04-414c-9850-b20a12ac7206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38268
06188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3826806188
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3424484602
Short name T618
Test name
Test status
Simulation time 668656306 ps
CPU time 37.16 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:23:09 PM PDT 24
Peak memory 248736 kb
Host smart-ecaeda63-dc53-4563-9765-429739833b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34244
84602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3424484602
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1923527058
Short name T52
Test name
Test status
Simulation time 926023587606 ps
CPU time 8124.34 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 03:37:56 PM PDT 24
Peak memory 394748 kb
Host smart-3476f93b-d847-4fcd-ae21-689b651b1c54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923527058 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1923527058
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.220833929
Short name T209
Test name
Test status
Simulation time 46555024 ps
CPU time 3.57 seconds
Started May 26 01:22:32 PM PDT 24
Finished May 26 01:22:37 PM PDT 24
Peak memory 248860 kb
Host smart-fbe6cb3b-72db-49dc-a56c-e186ab3a8d6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=220833929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.220833929
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.438631830
Short name T628
Test name
Test status
Simulation time 73975741298 ps
CPU time 1441.32 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:46:33 PM PDT 24
Peak memory 288456 kb
Host smart-f4992683-ff81-4ecb-8473-78eb98e2dcc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438631830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.438631830
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3513297581
Short name T469
Test name
Test status
Simulation time 436781609 ps
CPU time 21.94 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:23:03 PM PDT 24
Peak memory 248672 kb
Host smart-1a00ad03-2c3f-4b1c-ba1a-2c2542741888
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3513297581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3513297581
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1506367754
Short name T524
Test name
Test status
Simulation time 2932682631 ps
CPU time 186.19 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:25:48 PM PDT 24
Peak memory 248836 kb
Host smart-d5e96b38-2061-4442-a74b-625c380723fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063
67754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1506367754
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2598011725
Short name T452
Test name
Test status
Simulation time 172243784 ps
CPU time 14.86 seconds
Started May 26 01:22:34 PM PDT 24
Finished May 26 01:22:49 PM PDT 24
Peak memory 252496 kb
Host smart-10d06c4b-11bd-4fc2-8a33-4fdaf1e65b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25980
11725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2598011725
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4226226114
Short name T314
Test name
Test status
Simulation time 87702070219 ps
CPU time 1469.09 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:47:01 PM PDT 24
Peak memory 272576 kb
Host smart-122565e1-c7cd-473e-86b7-5b2ebd26d484
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226226114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4226226114
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3633450281
Short name T451
Test name
Test status
Simulation time 112415045458 ps
CPU time 2296.59 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 02:00:46 PM PDT 24
Peak memory 288120 kb
Host smart-0ca4b7bb-fbcc-473f-a450-77a2a2a2ed42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633450281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3633450281
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2356211966
Short name T283
Test name
Test status
Simulation time 43467378241 ps
CPU time 566.94 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:32:17 PM PDT 24
Peak memory 247848 kb
Host smart-1a9d0d74-7677-476f-996a-47f776cecbe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356211966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2356211966
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4163742671
Short name T373
Test name
Test status
Simulation time 577367372 ps
CPU time 8.73 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 252108 kb
Host smart-bdef36a7-968e-4ecb-b0da-5496d4e3440e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41637
42671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4163742671
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.517164779
Short name T30
Test name
Test status
Simulation time 41196766 ps
CPU time 7.17 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:22:40 PM PDT 24
Peak memory 254100 kb
Host smart-93f457c0-11b5-4027-ad27-d8667987e643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51716
4779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.517164779
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.353395136
Short name T581
Test name
Test status
Simulation time 1052691114 ps
CPU time 26.88 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:23:03 PM PDT 24
Peak memory 249084 kb
Host smart-e43625f1-c6a8-4751-8fd8-6c85af8f6042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35339
5136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.353395136
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2884699895
Short name T425
Test name
Test status
Simulation time 44284272 ps
CPU time 3.98 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:22:50 PM PDT 24
Peak memory 240580 kb
Host smart-ebd89f49-1f43-4e32-8ab3-0f108ce8f368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28846
99895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2884699895
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2841691797
Short name T707
Test name
Test status
Simulation time 3740808127 ps
CPU time 159.63 seconds
Started May 26 01:22:33 PM PDT 24
Finished May 26 01:25:14 PM PDT 24
Peak memory 256972 kb
Host smart-9bfbb6ac-8ded-4c04-874a-bf5e11f80231
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841691797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2841691797
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2459121294
Short name T205
Test name
Test status
Simulation time 15212291 ps
CPU time 2.24 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:22:46 PM PDT 24
Peak memory 248852 kb
Host smart-2161fada-0a3c-44e4-a51f-53dd00298c5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2459121294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2459121294
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3229510863
Short name T18
Test name
Test status
Simulation time 7723216560 ps
CPU time 759.27 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:35:25 PM PDT 24
Peak memory 266260 kb
Host smart-6eb20e05-587c-4de8-a3e4-3639478a8599
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229510863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3229510863
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3799408892
Short name T508
Test name
Test status
Simulation time 331175319 ps
CPU time 17.68 seconds
Started May 26 01:22:34 PM PDT 24
Finished May 26 01:22:52 PM PDT 24
Peak memory 248784 kb
Host smart-851fa730-4752-47ec-bca9-70319ff3b4ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3799408892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3799408892
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1408962106
Short name T227
Test name
Test status
Simulation time 5990305389 ps
CPU time 188.15 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 01:25:48 PM PDT 24
Peak memory 257164 kb
Host smart-6fe92580-8077-454e-b655-734ed5d12482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14089
62106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1408962106
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3650164317
Short name T537
Test name
Test status
Simulation time 267226571 ps
CPU time 13.14 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:22:55 PM PDT 24
Peak memory 248700 kb
Host smart-ed1e1d6f-d2d0-4487-b0e1-d7e79a5823e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
64317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3650164317
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1291631257
Short name T502
Test name
Test status
Simulation time 29540158300 ps
CPU time 1283.4 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:44:09 PM PDT 24
Peak memory 273120 kb
Host smart-76bede39-f791-448f-9ea6-9f574420d52a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291631257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1291631257
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2247784347
Short name T690
Test name
Test status
Simulation time 166186900203 ps
CPU time 1479.88 seconds
Started May 26 01:22:34 PM PDT 24
Finished May 26 01:47:15 PM PDT 24
Peak memory 271384 kb
Host smart-038d3ee4-6baa-4c64-8567-4175ff7860c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247784347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2247784347
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2697612601
Short name T488
Test name
Test status
Simulation time 55369907403 ps
CPU time 530.51 seconds
Started May 26 01:22:46 PM PDT 24
Finished May 26 01:31:39 PM PDT 24
Peak memory 248160 kb
Host smart-14dc1a37-51ee-4c6c-bda1-dcd517e772d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697612601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2697612601
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.4110210390
Short name T513
Test name
Test status
Simulation time 1496548037 ps
CPU time 44.01 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:29 PM PDT 24
Peak memory 256284 kb
Host smart-405e8554-1d35-4f2b-9d7c-4470c56ed0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41102
10390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4110210390
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3681340759
Short name T566
Test name
Test status
Simulation time 1232143329 ps
CPU time 27.26 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 248676 kb
Host smart-64cdd7e4-c843-46d9-a688-dbc894bce3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36813
40759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3681340759
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1798984816
Short name T526
Test name
Test status
Simulation time 1070259524 ps
CPU time 22.75 seconds
Started May 26 01:22:31 PM PDT 24
Finished May 26 01:22:55 PM PDT 24
Peak memory 256676 kb
Host smart-a427f6f6-8bd7-44e5-a6e7-39d61eeac73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17989
84816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1798984816
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3281243489
Short name T660
Test name
Test status
Simulation time 970950570 ps
CPU time 51.1 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:23:32 PM PDT 24
Peak memory 255936 kb
Host smart-6f0c15e4-b77a-48ef-977a-2c25b8f17077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32812
43489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3281243489
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3208619128
Short name T199
Test name
Test status
Simulation time 765244543 ps
CPU time 3.72 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:22:51 PM PDT 24
Peak memory 248876 kb
Host smart-7fcd7990-8191-4a57-97b9-2574145e3a18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3208619128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3208619128
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2841787719
Short name T468
Test name
Test status
Simulation time 85361842691 ps
CPU time 1188.07 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:42:33 PM PDT 24
Peak memory 273316 kb
Host smart-6a9e8e15-0aff-47f4-b0ba-c39a6604600d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841787719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2841787719
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1403065560
Short name T713
Test name
Test status
Simulation time 2838473585 ps
CPU time 169.3 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:25:31 PM PDT 24
Peak memory 249780 kb
Host smart-f6727c9b-3985-4a3a-9d91-c3677ee531bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14030
65560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1403065560
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.753660186
Short name T467
Test name
Test status
Simulation time 505076291 ps
CPU time 34.16 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:19 PM PDT 24
Peak memory 248780 kb
Host smart-d97122c4-9d81-4fe3-abd0-b1465cf86247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75366
0186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.753660186
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.600907298
Short name T447
Test name
Test status
Simulation time 69674894568 ps
CPU time 2303.6 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 02:01:08 PM PDT 24
Peak memory 288200 kb
Host smart-16f7a11f-5864-4adc-bee2-fdb6288a9006
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600907298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.600907298
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.257534706
Short name T714
Test name
Test status
Simulation time 64543018175 ps
CPU time 357.7 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 248044 kb
Host smart-2cf42ec4-3fe2-478f-9432-b73d1a7dd047
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257534706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.257534706
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.596219969
Short name T568
Test name
Test status
Simulation time 1195519519 ps
CPU time 17.17 seconds
Started May 26 01:22:46 PM PDT 24
Finished May 26 01:23:05 PM PDT 24
Peak memory 248392 kb
Host smart-fcb1e9ca-595c-4a9b-aa9b-12b5cb91850d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59621
9969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.596219969
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.359049706
Short name T406
Test name
Test status
Simulation time 552023360 ps
CPU time 37.25 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:23:24 PM PDT 24
Peak memory 256360 kb
Host smart-f4f60f8b-22f1-41fb-87b3-c52966a62476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904
9706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.359049706
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3031871261
Short name T608
Test name
Test status
Simulation time 503276108 ps
CPU time 34.9 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:22 PM PDT 24
Peak memory 255172 kb
Host smart-1fa64edd-b6dc-4d58-b766-c1a5dbbac781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
71261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3031871261
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.819402880
Short name T531
Test name
Test status
Simulation time 1733855658 ps
CPU time 31.63 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:19 PM PDT 24
Peak memory 248736 kb
Host smart-35e83f20-2a21-4ac9-9827-fc816d1bd0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81940
2880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.819402880
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1862609099
Short name T612
Test name
Test status
Simulation time 24816159005 ps
CPU time 1037.46 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:39:54 PM PDT 24
Peak memory 289284 kb
Host smart-173e62ce-54e3-49b6-aa51-97c7e6f50b65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862609099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1862609099
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2113946970
Short name T206
Test name
Test status
Simulation time 55171187 ps
CPU time 2.91 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 248748 kb
Host smart-bbafbfdd-de6b-4a70-8696-c1af6a889672
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2113946970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2113946970
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2186416422
Short name T94
Test name
Test status
Simulation time 10153965766 ps
CPU time 862.3 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:37:03 PM PDT 24
Peak memory 271828 kb
Host smart-7186350f-431d-4112-8be5-43c4ab8d94ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186416422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2186416422
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2016909700
Short name T356
Test name
Test status
Simulation time 1318590043 ps
CPU time 28.9 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:16 PM PDT 24
Peak memory 248732 kb
Host smart-3b466931-e998-4c64-93d2-520de82b4f51
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2016909700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2016909700
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1115978300
Short name T412
Test name
Test status
Simulation time 25281648273 ps
CPU time 133.2 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:24:59 PM PDT 24
Peak memory 257152 kb
Host smart-a212a76d-4029-47f4-97c5-9317218325c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11159
78300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1115978300
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.520115226
Short name T642
Test name
Test status
Simulation time 506912582 ps
CPU time 19.11 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:23:05 PM PDT 24
Peak memory 248876 kb
Host smart-f1610f58-4e8d-4ddb-843d-33a013c80ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52011
5226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.520115226
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3449265943
Short name T303
Test name
Test status
Simulation time 35419559598 ps
CPU time 1917.24 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:54:40 PM PDT 24
Peak memory 270792 kb
Host smart-1a2ea97d-8f7b-443e-8074-f756adb0135c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449265943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3449265943
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2855454302
Short name T111
Test name
Test status
Simulation time 59688948041 ps
CPU time 1706.3 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:51:08 PM PDT 24
Peak memory 269292 kb
Host smart-9633c3f8-5ec4-4e8f-b0a0-13e9a62fe358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855454302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2855454302
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2887516325
Short name T276
Test name
Test status
Simulation time 3800511211 ps
CPU time 151.18 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:25:17 PM PDT 24
Peak memory 254708 kb
Host smart-60960908-df24-4102-a021-89f747dac917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887516325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2887516325
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.643797779
Short name T34
Test name
Test status
Simulation time 446836700 ps
CPU time 9.41 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:22:51 PM PDT 24
Peak memory 250764 kb
Host smart-cc70d0b7-f6da-479a-a2e4-bbad6c369734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64379
7779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.643797779
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3196962599
Short name T498
Test name
Test status
Simulation time 74461488 ps
CPU time 5.32 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:22:47 PM PDT 24
Peak memory 240576 kb
Host smart-cc798fb2-abde-4e8f-b8a5-3c8966fe5f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31969
62599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3196962599
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3953781004
Short name T250
Test name
Test status
Simulation time 207488514 ps
CPU time 6.89 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:22:48 PM PDT 24
Peak memory 248780 kb
Host smart-ba442976-fca0-49cc-b4f0-1799de8f6139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
81004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3953781004
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3406411331
Short name T246
Test name
Test status
Simulation time 417555502 ps
CPU time 26.19 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:23:10 PM PDT 24
Peak memory 248812 kb
Host smart-a484e7a8-4de4-4069-a16b-1b20088554e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064
11331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3406411331
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3552280096
Short name T58
Test name
Test status
Simulation time 45570119 ps
CPU time 2.4 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:22:49 PM PDT 24
Peak memory 248932 kb
Host smart-9b43400b-1a86-4420-8c95-bc1da3b44dab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3552280096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3552280096
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.554112916
Short name T70
Test name
Test status
Simulation time 114518254835 ps
CPU time 3404.1 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 02:19:30 PM PDT 24
Peak memory 289656 kb
Host smart-8734d36f-8e56-45ff-bf5f-c8ce8e4ee2c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554112916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.554112916
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.807086512
Short name T375
Test name
Test status
Simulation time 601865988 ps
CPU time 15.52 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:00 PM PDT 24
Peak memory 248712 kb
Host smart-73f3e0ab-2369-4ac1-ac87-50eee8f2a66a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=807086512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.807086512
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1201486424
Short name T558
Test name
Test status
Simulation time 727206967 ps
CPU time 57.7 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 01:23:36 PM PDT 24
Peak memory 248736 kb
Host smart-9854d1ba-5ba6-4105-ba76-d8c4c489d5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014
86424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1201486424
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1682895224
Short name T664
Test name
Test status
Simulation time 285963758 ps
CPU time 21.34 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:06 PM PDT 24
Peak memory 256368 kb
Host smart-85108784-f733-47bc-909e-1495175cb4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16828
95224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1682895224
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3993941636
Short name T304
Test name
Test status
Simulation time 62289974635 ps
CPU time 942.17 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:38:23 PM PDT 24
Peak memory 269320 kb
Host smart-6b1791b8-199d-432a-803c-8c86d4b2524b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993941636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3993941636
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.14583670
Short name T475
Test name
Test status
Simulation time 133231696192 ps
CPU time 2333.27 seconds
Started May 26 01:22:46 PM PDT 24
Finished May 26 02:01:42 PM PDT 24
Peak memory 289068 kb
Host smart-4c349913-913c-4b05-9266-6b5649618a41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14583670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.14583670
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2396837934
Short name T602
Test name
Test status
Simulation time 143754060358 ps
CPU time 324.76 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:28:06 PM PDT 24
Peak memory 248696 kb
Host smart-d0dc3aa8-846c-4f9c-a967-9cdaa4e15d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396837934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2396837934
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.363037503
Short name T416
Test name
Test status
Simulation time 689930772 ps
CPU time 18.12 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:02 PM PDT 24
Peak memory 256004 kb
Host smart-7a85d5f5-4ba2-4bc3-991b-80e8bb0e5819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
7503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.363037503
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2897946524
Short name T648
Test name
Test status
Simulation time 236875609 ps
CPU time 23.48 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:23:00 PM PDT 24
Peak memory 255648 kb
Host smart-370fdbd6-b0eb-4c55-b45d-0696b8960374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28979
46524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2897946524
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3977675436
Short name T347
Test name
Test status
Simulation time 923234330 ps
CPU time 55.86 seconds
Started May 26 01:22:46 PM PDT 24
Finished May 26 01:23:44 PM PDT 24
Peak memory 248808 kb
Host smart-451f71a4-ed94-4af9-b09d-12bee0025515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39776
75436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3977675436
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1265553318
Short name T683
Test name
Test status
Simulation time 566453563 ps
CPU time 20.67 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:23:03 PM PDT 24
Peak memory 248872 kb
Host smart-ec6b289f-7502-459c-b0ae-10f384221543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12655
53318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1265553318
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3469305621
Short name T428
Test name
Test status
Simulation time 3101304145 ps
CPU time 48.5 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:23:32 PM PDT 24
Peak memory 256432 kb
Host smart-b972e0b7-bd22-429c-beb4-5bbcc5de4774
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469305621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3469305621
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.399395984
Short name T191
Test name
Test status
Simulation time 91178061461 ps
CPU time 7487.69 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 03:27:31 PM PDT 24
Peak memory 364732 kb
Host smart-da0b8337-dbc3-4484-8292-4bb74d19d0fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399395984 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.399395984
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3325013279
Short name T200
Test name
Test status
Simulation time 81095550 ps
CPU time 2.92 seconds
Started May 26 01:22:06 PM PDT 24
Finished May 26 01:22:09 PM PDT 24
Peak memory 248860 kb
Host smart-0df7c658-4ec2-4829-ad11-3c8bd11c572d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3325013279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3325013279
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2390439074
Short name T563
Test name
Test status
Simulation time 245098274150 ps
CPU time 3374.41 seconds
Started May 26 01:22:08 PM PDT 24
Finished May 26 02:18:23 PM PDT 24
Peak memory 289368 kb
Host smart-09dc3417-baaf-4bed-a9ca-8c8c56ef4b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390439074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2390439074
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.364295338
Short name T458
Test name
Test status
Simulation time 907824631 ps
CPU time 12.71 seconds
Started May 26 01:22:06 PM PDT 24
Finished May 26 01:22:20 PM PDT 24
Peak memory 248796 kb
Host smart-a34468c1-c33e-4878-95f1-171e84a57f4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=364295338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.364295338
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2879910301
Short name T548
Test name
Test status
Simulation time 2555750109 ps
CPU time 170.52 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:25:01 PM PDT 24
Peak memory 256956 kb
Host smart-341aab9a-451c-4256-bcb5-c6f111f9c25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28799
10301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2879910301
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2379342044
Short name T672
Test name
Test status
Simulation time 796259232 ps
CPU time 50.32 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:23:00 PM PDT 24
Peak memory 255964 kb
Host smart-ee808a04-94f9-4c83-899c-34187994cc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
42044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2379342044
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1394094391
Short name T691
Test name
Test status
Simulation time 214607666520 ps
CPU time 1573.68 seconds
Started May 26 01:22:10 PM PDT 24
Finished May 26 01:48:25 PM PDT 24
Peak memory 269432 kb
Host smart-fc638f18-c90a-4aa7-baf8-f9c0fdbaf89a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394094391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1394094391
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1026634528
Short name T688
Test name
Test status
Simulation time 34737708194 ps
CPU time 2178.6 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:58:29 PM PDT 24
Peak memory 286496 kb
Host smart-acc39207-062a-4423-922d-48b8c25aa888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026634528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1026634528
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1260078174
Short name T667
Test name
Test status
Simulation time 6768523008 ps
CPU time 144.83 seconds
Started May 26 01:22:06 PM PDT 24
Finished May 26 01:24:32 PM PDT 24
Peak memory 248228 kb
Host smart-c9e3df13-a89b-49f2-961c-89f056788c3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260078174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1260078174
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3878607945
Short name T622
Test name
Test status
Simulation time 2101632941 ps
CPU time 57.71 seconds
Started May 26 01:22:05 PM PDT 24
Finished May 26 01:23:04 PM PDT 24
Peak memory 248708 kb
Host smart-b611e41e-7433-4e61-bfed-4595630eb760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786
07945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3878607945
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.972198140
Short name T666
Test name
Test status
Simulation time 95298061 ps
CPU time 8.18 seconds
Started May 26 01:22:04 PM PDT 24
Finished May 26 01:22:12 PM PDT 24
Peak memory 248676 kb
Host smart-fb52cd60-5be6-40a8-a0ef-98af4bf061bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97219
8140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.972198140
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1476758612
Short name T13
Test name
Test status
Simulation time 434594713 ps
CPU time 23.03 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:22:48 PM PDT 24
Peak memory 266136 kb
Host smart-6ab6e371-4fb3-40a0-886e-2abb38e1b24e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1476758612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1476758612
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3579797955
Short name T110
Test name
Test status
Simulation time 1098747602 ps
CPU time 58.79 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:23:24 PM PDT 24
Peak memory 255492 kb
Host smart-5aa0e311-bf20-4abb-872b-5755536f9d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35797
97955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3579797955
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1716137370
Short name T621
Test name
Test status
Simulation time 4637482526 ps
CPU time 64.67 seconds
Started May 26 01:21:55 PM PDT 24
Finished May 26 01:23:01 PM PDT 24
Peak memory 248972 kb
Host smart-a93d24ef-0a29-45fd-8e50-dd7a63936cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
37370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1716137370
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1014338625
Short name T658
Test name
Test status
Simulation time 44452410797 ps
CPU time 2227.97 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:59:18 PM PDT 24
Peak memory 321908 kb
Host smart-332b8a2b-9a1f-4c20-a462-e22151de3681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014338625 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1014338625
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.209286911
Short name T646
Test name
Test status
Simulation time 16201390065 ps
CPU time 1445.4 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:46:52 PM PDT 24
Peak memory 288384 kb
Host smart-2a6727f8-6d93-4832-9514-345772a99be6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209286911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.209286911
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1419489892
Short name T225
Test name
Test status
Simulation time 3615123013 ps
CPU time 87.56 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:24:14 PM PDT 24
Peak memory 257016 kb
Host smart-c5342ba2-fe8e-4ba4-8c9a-a8ed3c4cdaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
89892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1419489892
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2103823301
Short name T470
Test name
Test status
Simulation time 407570602 ps
CPU time 37.03 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:23:18 PM PDT 24
Peak memory 248128 kb
Host smart-333f5c67-3d00-4043-ac84-52edfc9edaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
23301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2103823301
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1775207962
Short name T295
Test name
Test status
Simulation time 43952159854 ps
CPU time 1621.18 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:49:48 PM PDT 24
Peak memory 268304 kb
Host smart-d64425d5-9b32-4e7f-a44e-e7c382a9e67b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775207962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1775207962
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.274193939
Short name T369
Test name
Test status
Simulation time 113100381359 ps
CPU time 2877.12 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 02:10:45 PM PDT 24
Peak memory 289200 kb
Host smart-f391f0a9-3d5e-4ba5-b3c6-da5c88e5599f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274193939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.274193939
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2787866212
Short name T576
Test name
Test status
Simulation time 372368645 ps
CPU time 14.13 seconds
Started May 26 01:22:46 PM PDT 24
Finished May 26 01:23:02 PM PDT 24
Peak memory 248332 kb
Host smart-ffff4287-d02b-4d80-aa20-0a317f1fed2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27878
66212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2787866212
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2123056956
Short name T586
Test name
Test status
Simulation time 236079546 ps
CPU time 8.87 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 247332 kb
Host smart-b2c3ffa7-3d5f-4709-949e-2fe727b5a6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21230
56956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2123056956
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1229171445
Short name T561
Test name
Test status
Simulation time 599245163 ps
CPU time 25.16 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 248736 kb
Host smart-c09312ad-0a02-4f09-ab67-b38802157ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12291
71445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1229171445
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1654160731
Short name T78
Test name
Test status
Simulation time 22140203131 ps
CPU time 1554.56 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:48:37 PM PDT 24
Peak memory 289524 kb
Host smart-f5054cc3-eb2c-4b0e-9ce1-8abbc774a92c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654160731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1654160731
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.121214654
Short name T93
Test name
Test status
Simulation time 256928480263 ps
CPU time 2285.39 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 02:00:54 PM PDT 24
Peak memory 289380 kb
Host smart-e83a0941-9ebb-48e5-9cf6-93ce3b82186a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121214654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.121214654
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2435644914
Short name T597
Test name
Test status
Simulation time 1051564161 ps
CPU time 99.85 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:24:28 PM PDT 24
Peak memory 256904 kb
Host smart-0dc4f767-970b-4457-83a6-8df1899c78c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24356
44914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2435644914
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.646052335
Short name T506
Test name
Test status
Simulation time 95550145 ps
CPU time 5.69 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:22:53 PM PDT 24
Peak memory 240532 kb
Host smart-35ee4cc7-5464-45ef-a896-46505ca1e932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64605
2335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.646052335
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2602905699
Short name T211
Test name
Test status
Simulation time 173639650673 ps
CPU time 2250.5 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 02:00:16 PM PDT 24
Peak memory 289312 kb
Host smart-2afd68ff-8fca-4862-8358-bd8459b7d91f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602905699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2602905699
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2020268601
Short name T462
Test name
Test status
Simulation time 157123329396 ps
CPU time 1489.02 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:47:25 PM PDT 24
Peak memory 272948 kb
Host smart-a19bab6e-703c-4e52-9093-62906f76a07f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020268601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2020268601
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.490069218
Short name T239
Test name
Test status
Simulation time 32359736118 ps
CPU time 357.03 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:28:44 PM PDT 24
Peak memory 248004 kb
Host smart-d1178e64-a669-4022-85f2-f0f5525ac8dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490069218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.490069218
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1897915149
Short name T248
Test name
Test status
Simulation time 827576120 ps
CPU time 53.85 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:23:42 PM PDT 24
Peak memory 256188 kb
Host smart-dd05314f-1ab9-457a-9b15-8a94f2b732dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18979
15149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1897915149
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1846870342
Short name T527
Test name
Test status
Simulation time 945820753 ps
CPU time 57.42 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:23:48 PM PDT 24
Peak memory 256752 kb
Host smart-141a22f4-eff9-4125-a9ec-6dff6ed992d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18468
70342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1846870342
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2085743204
Short name T370
Test name
Test status
Simulation time 192455457 ps
CPU time 16.44 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:02 PM PDT 24
Peak memory 248988 kb
Host smart-aa19286b-ae4a-4bee-ba3b-c488e6cbc5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20857
43204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2085743204
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2391894975
Short name T243
Test name
Test status
Simulation time 39376608593 ps
CPU time 2404.72 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 02:02:45 PM PDT 24
Peak memory 289068 kb
Host smart-ad105edc-e557-4e68-9653-66509f8da96d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391894975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2391894975
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2127360969
Short name T23
Test name
Test status
Simulation time 79546359779 ps
CPU time 4925.73 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 02:44:49 PM PDT 24
Peak memory 298904 kb
Host smart-c1c89bc6-d63c-47d8-93e1-094fcfd59c6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127360969 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2127360969
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.763682719
Short name T653
Test name
Test status
Simulation time 71399949608 ps
CPU time 2309.15 seconds
Started May 26 01:22:51 PM PDT 24
Finished May 26 02:01:21 PM PDT 24
Peak memory 289612 kb
Host smart-7e68f2d8-bf0c-4d63-a924-5623bfeb0c76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763682719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.763682719
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.567205923
Short name T480
Test name
Test status
Simulation time 3604512451 ps
CPU time 88.65 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:24:20 PM PDT 24
Peak memory 248692 kb
Host smart-8151f1aa-5630-478b-a01a-48c2b1d8bea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56720
5923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.567205923
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4200579256
Short name T620
Test name
Test status
Simulation time 1710176408 ps
CPU time 26 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 249080 kb
Host smart-2284dca7-979e-4862-88c5-76890482e25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
79256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4200579256
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2531003084
Short name T655
Test name
Test status
Simulation time 11402620628 ps
CPU time 952.47 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:38:42 PM PDT 24
Peak memory 272956 kb
Host smart-3fdfc325-0198-4784-bfec-ff3877c4b26c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531003084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2531003084
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2594945105
Short name T571
Test name
Test status
Simulation time 41926139278 ps
CPU time 923.63 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:38:15 PM PDT 24
Peak memory 268376 kb
Host smart-f343c00e-f9e6-4f86-9801-7fa1aa9998d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594945105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2594945105
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2930503721
Short name T381
Test name
Test status
Simulation time 5084105866 ps
CPU time 210.38 seconds
Started May 26 01:22:34 PM PDT 24
Finished May 26 01:26:05 PM PDT 24
Peak memory 247152 kb
Host smart-381e66ef-b4d1-46a1-aa02-c9e82de98cf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930503721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2930503721
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1984691892
Short name T687
Test name
Test status
Simulation time 2268793731 ps
CPU time 34.86 seconds
Started May 26 01:22:53 PM PDT 24
Finished May 26 01:23:28 PM PDT 24
Peak memory 248732 kb
Host smart-16a335cc-73d8-44b3-8d32-2ec5020e2080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846
91892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1984691892
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.90289577
Short name T385
Test name
Test status
Simulation time 457084012 ps
CPU time 40.7 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:28 PM PDT 24
Peak memory 254576 kb
Host smart-a461dba7-0909-43a2-817b-ae92b296b79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90289
577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.90289577
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3301869260
Short name T466
Test name
Test status
Simulation time 324060362 ps
CPU time 10.19 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:22:53 PM PDT 24
Peak memory 247376 kb
Host smart-753e38b4-f608-4d72-9be8-78392bb5209a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
69260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3301869260
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.569281835
Short name T592
Test name
Test status
Simulation time 5227181144 ps
CPU time 78.81 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:24:10 PM PDT 24
Peak memory 248756 kb
Host smart-f69c3075-9def-455c-8ce5-433b1114fcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56928
1835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.569281835
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.107397599
Short name T176
Test name
Test status
Simulation time 55926113792 ps
CPU time 2038.59 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:56:49 PM PDT 24
Peak memory 289140 kb
Host smart-1ff959c1-4a97-4e07-922d-ce7e2e07dbaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107397599 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.107397599
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1885461269
Short name T702
Test name
Test status
Simulation time 61529580105 ps
CPU time 1213.49 seconds
Started May 26 01:22:48 PM PDT 24
Finished May 26 01:43:02 PM PDT 24
Peak memory 283548 kb
Host smart-ab8735fc-33fb-4bfb-ac36-baf60ba120ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885461269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1885461269
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1656723852
Short name T588
Test name
Test status
Simulation time 3602029221 ps
CPU time 56.57 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:23:42 PM PDT 24
Peak memory 255212 kb
Host smart-68f85f8b-c301-4ffa-be43-1815541f47e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16567
23852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1656723852
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1018290403
Short name T703
Test name
Test status
Simulation time 2671512061 ps
CPU time 36.94 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 01:23:15 PM PDT 24
Peak memory 249236 kb
Host smart-c9473938-b740-4a55-92ba-c6f051b13aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10182
90403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1018290403
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2467515708
Short name T419
Test name
Test status
Simulation time 44396272042 ps
CPU time 2490.71 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 02:04:21 PM PDT 24
Peak memory 288676 kb
Host smart-300df3b5-229b-490f-881e-967fb4385070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467515708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2467515708
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3452200143
Short name T280
Test name
Test status
Simulation time 10042676311 ps
CPU time 376.08 seconds
Started May 26 01:22:55 PM PDT 24
Finished May 26 01:29:12 PM PDT 24
Peak memory 254536 kb
Host smart-4c0c1f0c-d414-46c5-8c6d-099600c0ed68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452200143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3452200143
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1264842287
Short name T409
Test name
Test status
Simulation time 290214405 ps
CPU time 23.97 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:23:11 PM PDT 24
Peak memory 248696 kb
Host smart-271b1f96-ca35-4e75-bdc2-e1e254d2db4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12648
42287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1264842287
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2026800447
Short name T483
Test name
Test status
Simulation time 805165612 ps
CPU time 49.55 seconds
Started May 26 01:22:36 PM PDT 24
Finished May 26 01:23:26 PM PDT 24
Peak memory 255436 kb
Host smart-ac95082b-6131-47be-9e7e-e5059a1638e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20268
00447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2026800447
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.686460529
Short name T494
Test name
Test status
Simulation time 4181938269 ps
CPU time 61.59 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:46 PM PDT 24
Peak memory 256892 kb
Host smart-1bcd05ce-11f2-4cd9-9a85-fb8c0b04932a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68646
0529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.686460529
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.539466593
Short name T532
Test name
Test status
Simulation time 763514792 ps
CPU time 15.43 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:23:06 PM PDT 24
Peak memory 256008 kb
Host smart-903987e0-0971-4a95-a309-3c6625ab1c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53946
6593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.539466593
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1573782998
Short name T514
Test name
Test status
Simulation time 52574269024 ps
CPU time 1262.31 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:43:48 PM PDT 24
Peak memory 289744 kb
Host smart-15dd024c-6b0d-450d-a2ff-fca1c4b11c26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573782998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1573782998
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2817377507
Short name T89
Test name
Test status
Simulation time 99001976378 ps
CPU time 4458.96 seconds
Started May 26 01:22:51 PM PDT 24
Finished May 26 02:37:11 PM PDT 24
Peak memory 314012 kb
Host smart-553929e4-c734-425b-99d3-220d1ebcf08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817377507 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2817377507
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3494680145
Short name T83
Test name
Test status
Simulation time 104490963653 ps
CPU time 1577.57 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:49:05 PM PDT 24
Peak memory 273444 kb
Host smart-381946ee-c501-4065-8306-1713214d9a51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494680145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3494680145
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2419962546
Short name T579
Test name
Test status
Simulation time 20106365386 ps
CPU time 257.01 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:27:04 PM PDT 24
Peak memory 256808 kb
Host smart-26ba1a48-6c0a-43b2-a2fd-95e8b8c2f5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24199
62546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2419962546
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2772700770
Short name T61
Test name
Test status
Simulation time 6698526885 ps
CPU time 45.21 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:23:31 PM PDT 24
Peak memory 256092 kb
Host smart-f88dc150-59a8-44c0-b1da-9a1bd503afa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27727
00770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2772700770
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1268451004
Short name T98
Test name
Test status
Simulation time 69918052429 ps
CPU time 1439.75 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:46:41 PM PDT 24
Peak memory 287348 kb
Host smart-2a95dbe1-6919-420b-8358-c2f7493e81b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268451004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1268451004
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4251549150
Short name T382
Test name
Test status
Simulation time 63298046176 ps
CPU time 1716.36 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:51:24 PM PDT 24
Peak memory 273388 kb
Host smart-b1e45266-f20f-4ca3-a3c8-a24189597405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251549150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4251549150
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3477119803
Short name T609
Test name
Test status
Simulation time 551828055 ps
CPU time 29.99 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:23:14 PM PDT 24
Peak memory 248788 kb
Host smart-61395512-624d-4966-bb60-a5eda0ac4646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34771
19803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3477119803
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2407374355
Short name T422
Test name
Test status
Simulation time 1312286398 ps
CPU time 8.78 seconds
Started May 26 01:22:51 PM PDT 24
Finished May 26 01:23:01 PM PDT 24
Peak memory 249620 kb
Host smart-1b6328e4-a031-41f2-a3aa-30a4d607cde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
74355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2407374355
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1425134685
Short name T673
Test name
Test status
Simulation time 3165620152 ps
CPU time 23.74 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:11 PM PDT 24
Peak memory 248792 kb
Host smart-2589ef93-27a1-4498-b247-478bcce4d702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
34685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1425134685
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3197046994
Short name T75
Test name
Test status
Simulation time 4373347896 ps
CPU time 69.55 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:23:59 PM PDT 24
Peak memory 256084 kb
Host smart-2409588f-9e01-4ff1-ae65-c3fbdf0a5f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31970
46994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3197046994
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1915852850
Short name T85
Test name
Test status
Simulation time 13860445583 ps
CPU time 1768.62 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:52:16 PM PDT 24
Peak memory 305588 kb
Host smart-e7c6dec9-4d9b-4960-8a8a-fe534902ea31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915852850 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1915852850
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2729835407
Short name T472
Test name
Test status
Simulation time 5497813088 ps
CPU time 503.25 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:31:11 PM PDT 24
Peak memory 265096 kb
Host smart-ad7be121-c638-4c41-b3e3-1de7b0fa057a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729835407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2729835407
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4189350234
Short name T438
Test name
Test status
Simulation time 5678222362 ps
CPU time 297.47 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:27:45 PM PDT 24
Peak memory 256804 kb
Host smart-cf398723-b786-4edc-a671-15146da1f58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893
50234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4189350234
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2924838786
Short name T426
Test name
Test status
Simulation time 1136283607 ps
CPU time 69.84 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:23:58 PM PDT 24
Peak memory 249004 kb
Host smart-b9b08f03-e9f1-415f-957f-f2e56e7b1e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29248
38786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2924838786
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1189113446
Short name T41
Test name
Test status
Simulation time 19481584918 ps
CPU time 1295.99 seconds
Started May 26 01:22:40 PM PDT 24
Finished May 26 01:44:18 PM PDT 24
Peak memory 288488 kb
Host smart-4e242508-3792-4b6b-880d-fcbafd74278d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189113446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1189113446
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1025506115
Short name T367
Test name
Test status
Simulation time 70064985137 ps
CPU time 1832.72 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:53:18 PM PDT 24
Peak memory 273284 kb
Host smart-a3b45ac8-7f4b-43eb-99cb-1dc04383fd1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025506115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1025506115
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.4232730764
Short name T624
Test name
Test status
Simulation time 3451874090 ps
CPU time 116.46 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:24:44 PM PDT 24
Peak memory 248276 kb
Host smart-34768b3a-f38d-4e2d-a666-505fda5f2b55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232730764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.4232730764
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1599959725
Short name T184
Test name
Test status
Simulation time 3172588164 ps
CPU time 63.34 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:23:51 PM PDT 24
Peak memory 248824 kb
Host smart-4f8e0292-9d18-4183-82ed-da4c0137dcc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999
59725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1599959725
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3243324557
Short name T460
Test name
Test status
Simulation time 47355862 ps
CPU time 5.45 seconds
Started May 26 01:22:55 PM PDT 24
Finished May 26 01:23:01 PM PDT 24
Peak memory 248720 kb
Host smart-2e141db4-cee7-4507-9956-9a4c88724224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32433
24557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3243324557
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.356758288
Short name T33
Test name
Test status
Simulation time 400227336 ps
CPU time 26.23 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:23:14 PM PDT 24
Peak memory 248524 kb
Host smart-e0835dd2-962b-445e-aae7-ab4b60298fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35675
8288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.356758288
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3401896404
Short name T709
Test name
Test status
Simulation time 691695430 ps
CPU time 8.84 seconds
Started May 26 01:22:45 PM PDT 24
Finished May 26 01:22:56 PM PDT 24
Peak memory 248764 kb
Host smart-0967c007-39aa-40b0-b61e-083e47f77d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
96404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3401896404
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.724839213
Short name T258
Test name
Test status
Simulation time 288826920715 ps
CPU time 3057.48 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 02:13:48 PM PDT 24
Peak memory 299952 kb
Host smart-d444c9dd-7c10-428d-a0d5-8af0263e8068
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724839213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.724839213
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3395832878
Short name T177
Test name
Test status
Simulation time 78831629984 ps
CPU time 3731.01 seconds
Started May 26 01:22:53 PM PDT 24
Finished May 26 02:25:05 PM PDT 24
Peak memory 338940 kb
Host smart-8eb4391a-ece4-4691-b375-a07965b8bc97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395832878 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3395832878
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3591207182
Short name T567
Test name
Test status
Simulation time 23880344490 ps
CPU time 1474.01 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:47:24 PM PDT 24
Peak memory 265064 kb
Host smart-8c19a176-b708-45a5-90eb-08097277899e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591207182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3591207182
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3191585404
Short name T630
Test name
Test status
Simulation time 632409166 ps
CPU time 38 seconds
Started May 26 01:22:56 PM PDT 24
Finished May 26 01:23:35 PM PDT 24
Peak memory 248632 kb
Host smart-2e9b6d01-41e4-4af1-9e2e-e74a6e04c985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
85404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3191585404
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.726874171
Short name T433
Test name
Test status
Simulation time 1196035390 ps
CPU time 13.97 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 248852 kb
Host smart-659cc862-58a5-4b13-81bd-99955be9ea4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72687
4171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.726874171
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.78343342
Short name T312
Test name
Test status
Simulation time 103570462815 ps
CPU time 1370.71 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:45:36 PM PDT 24
Peak memory 268304 kb
Host smart-13fc8aac-67f5-4b72-8760-f36f109788f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78343342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.78343342
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2891252259
Short name T615
Test name
Test status
Simulation time 16805109333 ps
CPU time 1659.56 seconds
Started May 26 01:22:41 PM PDT 24
Finished May 26 01:50:24 PM PDT 24
Peak memory 289848 kb
Host smart-0b2b0f54-3b71-4d91-bd31-107c94a62d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891252259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2891252259
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1620135613
Short name T290
Test name
Test status
Simulation time 60843394721 ps
CPU time 425.28 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:29:52 PM PDT 24
Peak memory 254392 kb
Host smart-76de8570-b62a-44a6-8d03-cd8db71760c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620135613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1620135613
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.355031513
Short name T245
Test name
Test status
Simulation time 179919839 ps
CPU time 17.91 seconds
Started May 26 01:22:46 PM PDT 24
Finished May 26 01:23:06 PM PDT 24
Peak memory 256996 kb
Host smart-d2c33035-e032-4578-9862-fb6aaa3ec420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35503
1513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.355031513
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.18329352
Short name T500
Test name
Test status
Simulation time 891421739 ps
CPU time 30.29 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:23:21 PM PDT 24
Peak memory 248604 kb
Host smart-7d030ce8-9dfc-4b4f-9024-aadf9c73c69a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18329
352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.18329352
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2957510077
Short name T569
Test name
Test status
Simulation time 926283955 ps
CPU time 26.32 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:25 PM PDT 24
Peak memory 255680 kb
Host smart-77d1b5fa-c46f-4033-a04a-eb64a3880db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29575
10077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2957510077
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3684656995
Short name T692
Test name
Test status
Simulation time 150892334 ps
CPU time 19.24 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:17 PM PDT 24
Peak memory 248776 kb
Host smart-6004e677-b504-42cf-b873-2bf2c9acd61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36846
56995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3684656995
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.51643115
Short name T256
Test name
Test status
Simulation time 56935473371 ps
CPU time 3249.08 seconds
Started May 26 01:22:56 PM PDT 24
Finished May 26 02:17:06 PM PDT 24
Peak memory 289768 kb
Host smart-1d3b2fa4-c6de-4bad-b696-e784c326d890
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51643115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_hand
ler_stress_all.51643115
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3891100923
Short name T210
Test name
Test status
Simulation time 55488307464 ps
CPU time 3339.94 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 02:18:25 PM PDT 24
Peak memory 289432 kb
Host smart-630847f8-4d84-437c-9d57-a5491ce58fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891100923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3891100923
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4059262026
Short name T701
Test name
Test status
Simulation time 4225174450 ps
CPU time 120.76 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:24:45 PM PDT 24
Peak memory 256920 kb
Host smart-7d17ecbd-b21b-475f-8d41-a9e989e308ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40592
62026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4059262026
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1357327383
Short name T411
Test name
Test status
Simulation time 580137489 ps
CPU time 8.53 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:07 PM PDT 24
Peak memory 252948 kb
Host smart-d72112b5-50e6-46ec-b24c-b2a1a97ac8bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13573
27383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1357327383
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3726921921
Short name T309
Test name
Test status
Simulation time 21389808008 ps
CPU time 1646.47 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:50:25 PM PDT 24
Peak memory 289084 kb
Host smart-9ea74b9f-c424-4d64-98c3-cc0e086b1edb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726921921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3726921921
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2446067373
Short name T352
Test name
Test status
Simulation time 47252800219 ps
CPU time 2553.46 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 02:05:23 PM PDT 24
Peak memory 289092 kb
Host smart-127d0204-176a-472a-8b22-2c8265d67f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446067373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2446067373
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.878832697
Short name T293
Test name
Test status
Simulation time 17215219898 ps
CPU time 173.68 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:25:38 PM PDT 24
Peak memory 255080 kb
Host smart-bac7f468-ab3f-42f9-a956-879b1c74814c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878832697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.878832697
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3110513187
Short name T408
Test name
Test status
Simulation time 1119120603 ps
CPU time 66.85 seconds
Started May 26 01:22:44 PM PDT 24
Finished May 26 01:23:54 PM PDT 24
Peak memory 256624 kb
Host smart-f7e4ae22-f379-4833-9f60-4079c4555c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31105
13187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3110513187
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.935925990
Short name T641
Test name
Test status
Simulation time 2974611813 ps
CPU time 36.98 seconds
Started May 26 01:22:54 PM PDT 24
Finished May 26 01:23:32 PM PDT 24
Peak memory 255684 kb
Host smart-8e398675-4154-4ed0-b2d7-ea2ee85aff9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93592
5990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.935925990
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3514713092
Short name T100
Test name
Test status
Simulation time 168677835 ps
CPU time 5.37 seconds
Started May 26 01:22:51 PM PDT 24
Finished May 26 01:22:57 PM PDT 24
Peak memory 252852 kb
Host smart-45f24555-a201-42e1-a6df-c73687dd9f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147
13092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3514713092
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3614129232
Short name T557
Test name
Test status
Simulation time 205305944 ps
CPU time 14.34 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:23:05 PM PDT 24
Peak memory 248604 kb
Host smart-f7dc711f-01c5-4fea-aa71-a5e65f85f047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
29232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3614129232
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1226742812
Short name T354
Test name
Test status
Simulation time 5337444649 ps
CPU time 63.64 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:23:54 PM PDT 24
Peak memory 256316 kb
Host smart-479a27b7-a98b-4d23-968d-852cdf477d42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226742812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1226742812
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3965917128
Short name T22
Test name
Test status
Simulation time 61732870539 ps
CPU time 1408.1 seconds
Started May 26 01:22:55 PM PDT 24
Finished May 26 01:46:23 PM PDT 24
Peak memory 288816 kb
Host smart-ecd898d8-2255-4c7e-9c63-1c9290cf18f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965917128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3965917128
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1584680709
Short name T659
Test name
Test status
Simulation time 1929397796 ps
CPU time 28.34 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:26 PM PDT 24
Peak memory 255012 kb
Host smart-064dc3a0-22bc-41c2-8af6-eaf30a80e434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15846
80709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1584680709
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2064468969
Short name T8
Test name
Test status
Simulation time 416382684 ps
CPU time 26.75 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:25 PM PDT 24
Peak memory 248764 kb
Host smart-3b9a0890-4890-473e-a660-010786edb3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
68969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2064468969
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.427365156
Short name T560
Test name
Test status
Simulation time 75915002298 ps
CPU time 1260.92 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:43:52 PM PDT 24
Peak memory 272816 kb
Host smart-ff49336e-519f-41e9-95da-eed902ca9f05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427365156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.427365156
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.123541522
Short name T699
Test name
Test status
Simulation time 14877845708 ps
CPU time 1681.65 seconds
Started May 26 01:22:56 PM PDT 24
Finished May 26 01:50:58 PM PDT 24
Peak memory 289372 kb
Host smart-787c23cf-2f2a-42fb-b1ff-dce041d0b855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123541522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.123541522
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1496469142
Short name T281
Test name
Test status
Simulation time 10124065004 ps
CPU time 400.09 seconds
Started May 26 01:22:52 PM PDT 24
Finished May 26 01:29:33 PM PDT 24
Peak memory 253972 kb
Host smart-5d51c8a5-de65-4ef5-9dff-59c0e847e48d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496469142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1496469142
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3572769447
Short name T594
Test name
Test status
Simulation time 314514103 ps
CPU time 7.21 seconds
Started May 26 01:22:57 PM PDT 24
Finished May 26 01:23:05 PM PDT 24
Peak memory 240956 kb
Host smart-0649d4cf-2fbc-424f-a8ed-b424b9888041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35727
69447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3572769447
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3991828587
Short name T2
Test name
Test status
Simulation time 5103552100 ps
CPU time 76.1 seconds
Started May 26 01:22:55 PM PDT 24
Finished May 26 01:24:12 PM PDT 24
Peak memory 255304 kb
Host smart-cc75bc3b-7ced-490c-8a9d-f0b7dedf0ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
28587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3991828587
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1898640325
Short name T562
Test name
Test status
Simulation time 106590165 ps
CPU time 12.05 seconds
Started May 26 01:22:59 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 248728 kb
Host smart-989d9261-6868-4e39-9e7f-1fbb986e2820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
40325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1898640325
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1836501842
Short name T378
Test name
Test status
Simulation time 1295596657 ps
CPU time 38.2 seconds
Started May 26 01:22:56 PM PDT 24
Finished May 26 01:23:35 PM PDT 24
Peak memory 249072 kb
Host smart-b8b2dc13-f94b-42f0-bbf3-59b69f7a351a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18365
01842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1836501842
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.966212798
Short name T56
Test name
Test status
Simulation time 34176214993 ps
CPU time 1660.03 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:50:30 PM PDT 24
Peak memory 288116 kb
Host smart-82a66d86-bf14-4323-88a0-35e93254572a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966212798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.966212798
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.873954419
Short name T346
Test name
Test status
Simulation time 1320648279 ps
CPU time 124.68 seconds
Started May 26 01:22:59 PM PDT 24
Finished May 26 01:25:05 PM PDT 24
Peak memory 257052 kb
Host smart-0afcadbb-2d2b-4ffe-b52d-a38705645b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87395
4419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.873954419
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3030732909
Short name T610
Test name
Test status
Simulation time 1344320389 ps
CPU time 43.24 seconds
Started May 26 01:22:59 PM PDT 24
Finished May 26 01:23:43 PM PDT 24
Peak memory 256872 kb
Host smart-06b3371c-da2e-4f5e-9f12-88140456f9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30307
32909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3030732909
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2183419014
Short name T694
Test name
Test status
Simulation time 139914936769 ps
CPU time 2280.01 seconds
Started May 26 01:22:55 PM PDT 24
Finished May 26 02:00:56 PM PDT 24
Peak memory 284308 kb
Host smart-0b07168f-deee-4f8c-a256-02e77d493c5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183419014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2183419014
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.606798313
Short name T87
Test name
Test status
Simulation time 21504266146 ps
CPU time 1438.35 seconds
Started May 26 01:22:54 PM PDT 24
Finished May 26 01:46:53 PM PDT 24
Peak memory 268580 kb
Host smart-1b17a813-f538-4613-843c-8526dfbc7a3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606798313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.606798313
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.84445432
Short name T96
Test name
Test status
Simulation time 5904668092 ps
CPU time 123.61 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:24:55 PM PDT 24
Peak memory 247148 kb
Host smart-6e606da3-4d5a-4f79-81ed-94363efc75e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84445432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.84445432
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1167313556
Short name T398
Test name
Test status
Simulation time 2342893666 ps
CPU time 63.31 seconds
Started May 26 01:22:53 PM PDT 24
Finished May 26 01:23:57 PM PDT 24
Peak memory 256188 kb
Host smart-4fe6582f-b427-4cc4-a7b2-c7d08033fd6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11673
13556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1167313556
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3507435403
Short name T556
Test name
Test status
Simulation time 1254293198 ps
CPU time 35.22 seconds
Started May 26 01:22:50 PM PDT 24
Finished May 26 01:23:26 PM PDT 24
Peak memory 256060 kb
Host smart-d7959d40-650e-4d9e-8fda-188a3a584c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35074
35403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3507435403
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.609733322
Short name T418
Test name
Test status
Simulation time 2622783008 ps
CPU time 31.54 seconds
Started May 26 01:22:51 PM PDT 24
Finished May 26 01:23:23 PM PDT 24
Peak memory 247956 kb
Host smart-0a70e0f2-1dd1-4691-a40a-5522e5be16a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60973
3322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.609733322
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2914619277
Short name T565
Test name
Test status
Simulation time 963514061 ps
CPU time 21.18 seconds
Started May 26 01:22:49 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 248656 kb
Host smart-50dcb99f-2206-4b6b-8dd9-aa00f30f6d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29146
19277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2914619277
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3238044995
Short name T66
Test name
Test status
Simulation time 19319790529 ps
CPU time 953.55 seconds
Started May 26 01:23:03 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 272892 kb
Host smart-1e722914-ee65-401d-ae54-61737f2b8c9f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238044995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3238044995
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4225541732
Short name T614
Test name
Test status
Simulation time 187333913240 ps
CPU time 4657.55 seconds
Started May 26 01:22:59 PM PDT 24
Finished May 26 02:40:38 PM PDT 24
Peak memory 338500 kb
Host smart-b14db468-b037-402b-9251-d3cd64e3fd75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225541732 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4225541732
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1406018602
Short name T207
Test name
Test status
Simulation time 134315607 ps
CPU time 3.81 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:22:14 PM PDT 24
Peak memory 248864 kb
Host smart-469f66b5-2b90-4413-80e8-3cd0e25b96ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1406018602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1406018602
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.429695125
Short name T575
Test name
Test status
Simulation time 58039137183 ps
CPU time 1365.21 seconds
Started May 26 01:22:06 PM PDT 24
Finished May 26 01:44:52 PM PDT 24
Peak memory 289180 kb
Host smart-f3c9da76-04d8-4f84-a032-2c84a8433654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429695125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.429695125
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.418094434
Short name T374
Test name
Test status
Simulation time 176913931 ps
CPU time 11.17 seconds
Started May 26 01:22:05 PM PDT 24
Finished May 26 01:22:16 PM PDT 24
Peak memory 248712 kb
Host smart-7d388021-59d8-49bd-a0c8-feb0cc627de5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=418094434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.418094434
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1115389660
Short name T400
Test name
Test status
Simulation time 3409257677 ps
CPU time 239.16 seconds
Started May 26 01:22:07 PM PDT 24
Finished May 26 01:26:07 PM PDT 24
Peak memory 257000 kb
Host smart-b457bf82-77a6-44a2-b570-63660342bf02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11153
89660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1115389660
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2744222434
Short name T95
Test name
Test status
Simulation time 82763960 ps
CPU time 6.88 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:22:17 PM PDT 24
Peak memory 252148 kb
Host smart-65cc5313-3e9d-429f-bf95-78b543684eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
22434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2744222434
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3868473705
Short name T441
Test name
Test status
Simulation time 32522295757 ps
CPU time 1267.34 seconds
Started May 26 01:22:11 PM PDT 24
Finished May 26 01:43:19 PM PDT 24
Peak memory 272900 kb
Host smart-2844c974-f75d-43bf-815e-7e63f7a7d741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868473705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3868473705
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3367627936
Short name T286
Test name
Test status
Simulation time 97148159334 ps
CPU time 479.8 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 247036 kb
Host smart-61b70421-f23f-454b-b7ea-29b6f0515fe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367627936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3367627936
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2066068949
Short name T509
Test name
Test status
Simulation time 23140050 ps
CPU time 3.29 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:22:13 PM PDT 24
Peak memory 240528 kb
Host smart-de7a7de1-22b9-4928-a137-13bd56062fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20660
68949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2066068949
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1266109495
Short name T634
Test name
Test status
Simulation time 521053763 ps
CPU time 17.15 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:22:26 PM PDT 24
Peak memory 255236 kb
Host smart-de32ced8-3187-44d6-ab3a-4f6b04ec7497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12661
09495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1266109495
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1658193945
Short name T26
Test name
Test status
Simulation time 1009733290 ps
CPU time 14.5 seconds
Started May 26 01:22:09 PM PDT 24
Finished May 26 01:22:24 PM PDT 24
Peak memory 270724 kb
Host smart-59e271e1-1fd3-41e1-96a3-16726f4d88b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1658193945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1658193945
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.41073642
Short name T676
Test name
Test status
Simulation time 240417605 ps
CPU time 28.18 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:22:58 PM PDT 24
Peak memory 255976 kb
Host smart-2528b3c7-6664-49fe-b232-8af680ead950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41073
642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.41073642
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.664749626
Short name T545
Test name
Test status
Simulation time 199745490 ps
CPU time 4.24 seconds
Started May 26 01:22:06 PM PDT 24
Finished May 26 01:22:11 PM PDT 24
Peak memory 240576 kb
Host smart-8b1e0ec6-258f-4148-991b-04c0eb0e5d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66474
9626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.664749626
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1216204719
Short name T102
Test name
Test status
Simulation time 51448045251 ps
CPU time 938.51 seconds
Started May 26 01:22:11 PM PDT 24
Finished May 26 01:37:50 PM PDT 24
Peak memory 273224 kb
Host smart-efa2cfd6-ce2a-4ce8-9864-f575aa50d10e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216204719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1216204719
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1377866476
Short name T252
Test name
Test status
Simulation time 141850467828 ps
CPU time 2457.69 seconds
Started May 26 01:22:11 PM PDT 24
Finished May 26 02:03:09 PM PDT 24
Peak memory 289192 kb
Host smart-a2aca32e-a27d-4ba7-b5b4-1f5230f4b0e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377866476 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1377866476
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3594097339
Short name T72
Test name
Test status
Simulation time 139581825113 ps
CPU time 2638.04 seconds
Started May 26 01:23:03 PM PDT 24
Finished May 26 02:07:02 PM PDT 24
Peak memory 289512 kb
Host smart-2694c0ac-9fa7-4629-b59b-12c71471b828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594097339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3594097339
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.341603492
Short name T528
Test name
Test status
Simulation time 1356036007 ps
CPU time 81.44 seconds
Started May 26 01:23:03 PM PDT 24
Finished May 26 01:24:25 PM PDT 24
Peak memory 256776 kb
Host smart-a7925e21-fc63-44bc-b0fb-284ced1d96bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34160
3492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.341603492
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2670630895
Short name T394
Test name
Test status
Simulation time 115817124 ps
CPU time 9.44 seconds
Started May 26 01:23:09 PM PDT 24
Finished May 26 01:23:19 PM PDT 24
Peak memory 240580 kb
Host smart-69743b49-8e51-48d0-bc42-8b2c49ff26f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26706
30895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2670630895
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1634394919
Short name T405
Test name
Test status
Simulation time 39174326903 ps
CPU time 2172.07 seconds
Started May 26 01:23:02 PM PDT 24
Finished May 26 01:59:15 PM PDT 24
Peak memory 289272 kb
Host smart-52bd8e34-f8c4-4416-bb60-8c3adc7ce417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634394919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1634394919
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3546006117
Short name T493
Test name
Test status
Simulation time 5251270105 ps
CPU time 214.73 seconds
Started May 26 01:22:58 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 247988 kb
Host smart-d185370e-6372-4588-b6ca-80ca4b66f207
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546006117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3546006117
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1854402024
Short name T62
Test name
Test status
Simulation time 2471855735 ps
CPU time 32.76 seconds
Started May 26 01:22:51 PM PDT 24
Finished May 26 01:23:25 PM PDT 24
Peak memory 248660 kb
Host smart-e17e09fc-1b14-4951-9106-338f9e61ec33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18544
02024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1854402024
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3068295050
Short name T73
Test name
Test status
Simulation time 315468124 ps
CPU time 7.06 seconds
Started May 26 01:23:02 PM PDT 24
Finished May 26 01:23:10 PM PDT 24
Peak memory 240732 kb
Host smart-6e98fc48-b43a-4928-90fd-cfe03e96969a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
95050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3068295050
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1287299192
Short name T260
Test name
Test status
Simulation time 6897820473 ps
CPU time 49.44 seconds
Started May 26 01:23:06 PM PDT 24
Finished May 26 01:23:56 PM PDT 24
Peak memory 255572 kb
Host smart-9d310c82-eb5e-455c-9ad1-0dd63be9463a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872
99192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1287299192
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.388956941
Short name T454
Test name
Test status
Simulation time 7803019675 ps
CPU time 53.25 seconds
Started May 26 01:23:00 PM PDT 24
Finished May 26 01:23:54 PM PDT 24
Peak memory 256260 kb
Host smart-65d438bc-e264-4b77-8cbb-56890a8d70f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38895
6941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.388956941
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.84812773
Short name T677
Test name
Test status
Simulation time 202010850759 ps
CPU time 1738.62 seconds
Started May 26 01:22:58 PM PDT 24
Finished May 26 01:51:58 PM PDT 24
Peak memory 289368 kb
Host smart-bddb1d92-38c6-4cdb-9f20-ec6e09707853
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84812773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_hand
ler_stress_all.84812773
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.708118515
Short name T242
Test name
Test status
Simulation time 27019505270 ps
CPU time 2982.11 seconds
Started May 26 01:23:01 PM PDT 24
Finished May 26 02:12:44 PM PDT 24
Peak memory 314380 kb
Host smart-362999a3-0307-4c66-8ef6-a3aa374a8f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708118515 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.708118515
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1755556784
Short name T478
Test name
Test status
Simulation time 30599008728 ps
CPU time 1890.18 seconds
Started May 26 01:23:05 PM PDT 24
Finished May 26 01:54:37 PM PDT 24
Peak memory 281592 kb
Host smart-79c1cfca-0671-4cec-b0b1-f16b44ef156f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755556784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1755556784
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1824028821
Short name T63
Test name
Test status
Simulation time 3015726934 ps
CPU time 107.57 seconds
Started May 26 01:23:06 PM PDT 24
Finished May 26 01:24:54 PM PDT 24
Peak memory 249816 kb
Host smart-96a58ba7-b15b-4531-b878-2c2734a69dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
28821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1824028821
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2968892791
Short name T678
Test name
Test status
Simulation time 705527727 ps
CPU time 15.76 seconds
Started May 26 01:23:12 PM PDT 24
Finished May 26 01:23:29 PM PDT 24
Peak memory 255576 kb
Host smart-9ce3ffc4-0bc3-424f-a2a4-ed100984e966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29688
92791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2968892791
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1909914800
Short name T186
Test name
Test status
Simulation time 58206894013 ps
CPU time 1405.28 seconds
Started May 26 01:23:06 PM PDT 24
Finished May 26 01:46:32 PM PDT 24
Peak memory 289036 kb
Host smart-e026b7c9-b2b4-4429-a0db-ef8e7da2a353
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909914800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1909914800
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3621225588
Short name T344
Test name
Test status
Simulation time 56810756781 ps
CPU time 1197.71 seconds
Started May 26 01:23:08 PM PDT 24
Finished May 26 01:43:07 PM PDT 24
Peak memory 288800 kb
Host smart-c8a9a104-c899-4d82-838c-9ddd88baa79f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621225588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3621225588
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2917716861
Short name T521
Test name
Test status
Simulation time 5985896584 ps
CPU time 252.25 seconds
Started May 26 01:23:07 PM PDT 24
Finished May 26 01:27:20 PM PDT 24
Peak memory 248180 kb
Host smart-65b07d22-c22f-4d6b-9754-c14f7c2b36dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917716861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2917716861
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2723169434
Short name T616
Test name
Test status
Simulation time 2497963150 ps
CPU time 37.63 seconds
Started May 26 01:23:02 PM PDT 24
Finished May 26 01:23:40 PM PDT 24
Peak memory 248872 kb
Host smart-e7791699-a0f7-41be-8960-35cdec9ce666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27231
69434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2723169434
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3717134502
Short name T39
Test name
Test status
Simulation time 843327230 ps
CPU time 54.97 seconds
Started May 26 01:23:07 PM PDT 24
Finished May 26 01:24:02 PM PDT 24
Peak memory 255784 kb
Host smart-36b5a4fb-670f-41c9-b4cd-30eb92456338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37171
34502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3717134502
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3819990110
Short name T268
Test name
Test status
Simulation time 400986320 ps
CPU time 15.5 seconds
Started May 26 01:23:06 PM PDT 24
Finished May 26 01:23:22 PM PDT 24
Peak memory 255400 kb
Host smart-d257c6ea-022c-4254-9cc0-9bd8d0c67f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199
90110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3819990110
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2540400239
Short name T669
Test name
Test status
Simulation time 440452437 ps
CPU time 12.14 seconds
Started May 26 01:23:01 PM PDT 24
Finished May 26 01:23:14 PM PDT 24
Peak memory 249036 kb
Host smart-9127082a-cae2-44ca-b6aa-94fcdb9c8a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25404
00239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2540400239
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1093777072
Short name T492
Test name
Test status
Simulation time 36375919632 ps
CPU time 678.41 seconds
Started May 26 01:23:06 PM PDT 24
Finished May 26 01:34:25 PM PDT 24
Peak memory 273520 kb
Host smart-fbdd4da1-47c1-445a-b6f5-23fc8c22ce1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093777072 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1093777072
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.178614435
Short name T106
Test name
Test status
Simulation time 23879140418 ps
CPU time 687.19 seconds
Started May 26 01:23:07 PM PDT 24
Finished May 26 01:34:35 PM PDT 24
Peak memory 273332 kb
Host smart-f183b72c-b141-4434-a591-d0dcc89f7255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178614435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.178614435
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.4002811498
Short name T698
Test name
Test status
Simulation time 1404356351 ps
CPU time 29.45 seconds
Started May 26 01:23:08 PM PDT 24
Finished May 26 01:23:38 PM PDT 24
Peak memory 248788 kb
Host smart-b4c20cab-500f-4269-9fd6-05081f4bcfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40028
11498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4002811498
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.450998896
Short name T338
Test name
Test status
Simulation time 244180902 ps
CPU time 4.88 seconds
Started May 26 01:23:08 PM PDT 24
Finished May 26 01:23:14 PM PDT 24
Peak memory 240548 kb
Host smart-26cf86ed-a013-40d3-b209-b6bc4aed9c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45099
8896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.450998896
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1238982441
Short name T552
Test name
Test status
Simulation time 105398631379 ps
CPU time 1588.38 seconds
Started May 26 01:23:20 PM PDT 24
Finished May 26 01:49:49 PM PDT 24
Peak memory 272320 kb
Host smart-8191cd6b-227b-4477-b059-c67f882f6f99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238982441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1238982441
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2346958783
Short name T453
Test name
Test status
Simulation time 173454626041 ps
CPU time 2278.52 seconds
Started May 26 01:23:20 PM PDT 24
Finished May 26 02:01:20 PM PDT 24
Peak memory 281668 kb
Host smart-5a5b77bc-aeda-4069-9bf9-56a7ced77c20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346958783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2346958783
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1169136933
Short name T342
Test name
Test status
Simulation time 41876900 ps
CPU time 5.53 seconds
Started May 26 01:23:06 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 240504 kb
Host smart-1c721585-006b-4f2f-9142-69e06f43b21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691
36933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1169136933
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4120549182
Short name T348
Test name
Test status
Simulation time 409675650 ps
CPU time 27.08 seconds
Started May 26 01:23:07 PM PDT 24
Finished May 26 01:23:35 PM PDT 24
Peak memory 247716 kb
Host smart-2d6fd850-c3e3-49d0-842a-781423b06805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41205
49182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4120549182
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1442193745
Short name T79
Test name
Test status
Simulation time 804834896 ps
CPU time 42.36 seconds
Started May 26 01:23:10 PM PDT 24
Finished May 26 01:23:54 PM PDT 24
Peak memory 255940 kb
Host smart-45c07c50-d844-4641-95ce-a5777cea36e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
93745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1442193745
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4034069791
Short name T638
Test name
Test status
Simulation time 766559746 ps
CPU time 46.58 seconds
Started May 26 01:23:07 PM PDT 24
Finished May 26 01:23:54 PM PDT 24
Peak memory 248764 kb
Host smart-93ed810e-ef32-4a1e-b49d-1bf134d36ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40340
69791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4034069791
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.489111273
Short name T251
Test name
Test status
Simulation time 54215721265 ps
CPU time 1951.51 seconds
Started May 26 01:23:16 PM PDT 24
Finished May 26 01:55:48 PM PDT 24
Peak memory 285476 kb
Host smart-f1d20c76-6ddd-4fc7-8c5c-e95a504c37f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489111273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.489111273
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.875855047
Short name T226
Test name
Test status
Simulation time 81511071380 ps
CPU time 2157.4 seconds
Started May 26 01:23:16 PM PDT 24
Finished May 26 01:59:14 PM PDT 24
Peak memory 315168 kb
Host smart-4ad57f55-f9f0-4642-855a-5858d1603413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875855047 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.875855047
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4061730681
Short name T577
Test name
Test status
Simulation time 136916639991 ps
CPU time 2023.08 seconds
Started May 26 01:23:15 PM PDT 24
Finished May 26 01:56:59 PM PDT 24
Peak memory 281600 kb
Host smart-d40a2847-d6c4-4577-bd83-150f979f6002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061730681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4061730681
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1010332587
Short name T490
Test name
Test status
Simulation time 1901968330 ps
CPU time 42.91 seconds
Started May 26 01:23:15 PM PDT 24
Finished May 26 01:23:59 PM PDT 24
Peak memory 248980 kb
Host smart-ce95292d-05c3-40d9-9fc2-d234779dc0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
32587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1010332587
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1090026891
Short name T489
Test name
Test status
Simulation time 7641067875 ps
CPU time 29.4 seconds
Started May 26 01:23:15 PM PDT 24
Finished May 26 01:23:45 PM PDT 24
Peak memory 255768 kb
Host smart-547f40ce-787d-4f13-b3d1-b27236b2e852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10900
26891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1090026891
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2284725507
Short name T315
Test name
Test status
Simulation time 31578901588 ps
CPU time 1861.57 seconds
Started May 26 01:23:15 PM PDT 24
Finished May 26 01:54:17 PM PDT 24
Peak memory 289044 kb
Host smart-32741d40-cf6a-4b7a-89fa-9d360ce65212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284725507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2284725507
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1087964790
Short name T605
Test name
Test status
Simulation time 10032421679 ps
CPU time 171.33 seconds
Started May 26 01:23:13 PM PDT 24
Finished May 26 01:26:06 PM PDT 24
Peak memory 248212 kb
Host smart-e4fe901b-839c-40c2-9094-8595b515856c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087964790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1087964790
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1854692864
Short name T704
Test name
Test status
Simulation time 814275475 ps
CPU time 47.63 seconds
Started May 26 01:23:20 PM PDT 24
Finished May 26 01:24:08 PM PDT 24
Peak memory 248788 kb
Host smart-5fd61ee2-c05b-421b-940c-ead8c1f7776e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18546
92864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1854692864
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3345156213
Short name T345
Test name
Test status
Simulation time 935956326 ps
CPU time 30.45 seconds
Started May 26 01:23:14 PM PDT 24
Finished May 26 01:23:46 PM PDT 24
Peak memory 255460 kb
Host smart-3560d3ea-8728-491f-91d1-35e1defb9bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33451
56213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3345156213
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2567538905
Short name T574
Test name
Test status
Simulation time 255376561 ps
CPU time 19.32 seconds
Started May 26 01:23:14 PM PDT 24
Finished May 26 01:23:35 PM PDT 24
Peak memory 248704 kb
Host smart-0f868115-fefa-40cf-ade1-f932a651273e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25675
38905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2567538905
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.396542355
Short name T585
Test name
Test status
Simulation time 286952429 ps
CPU time 36.1 seconds
Started May 26 01:23:17 PM PDT 24
Finished May 26 01:23:54 PM PDT 24
Peak memory 256960 kb
Host smart-db0fbd9a-1acf-4fff-813f-cb9e641000c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396542355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.396542355
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2538795207
Short name T479
Test name
Test status
Simulation time 36441409350 ps
CPU time 2392.63 seconds
Started May 26 01:23:30 PM PDT 24
Finished May 26 02:03:24 PM PDT 24
Peak memory 289292 kb
Host smart-e406aa2b-cb98-4bbb-9e5f-453e453783d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538795207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2538795207
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.526799313
Short name T625
Test name
Test status
Simulation time 2310014315 ps
CPU time 129.09 seconds
Started May 26 01:23:27 PM PDT 24
Finished May 26 01:25:36 PM PDT 24
Peak memory 256804 kb
Host smart-91a9c46a-36d9-4755-b8a8-5b9d0d5573ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52679
9313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.526799313
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2117066621
Short name T477
Test name
Test status
Simulation time 479633212 ps
CPU time 11.52 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:23:42 PM PDT 24
Peak memory 254720 kb
Host smart-41a6e70e-86a2-4fa1-a85b-120239216beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21170
66621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2117066621
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3335027424
Short name T712
Test name
Test status
Simulation time 38219874541 ps
CPU time 2598.78 seconds
Started May 26 01:23:31 PM PDT 24
Finished May 26 02:06:50 PM PDT 24
Peak memory 289328 kb
Host smart-25bb16fb-2d6c-4eae-ae6c-a8054625f6bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335027424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3335027424
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3849303692
Short name T274
Test name
Test status
Simulation time 4287466846 ps
CPU time 187.1 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:26:38 PM PDT 24
Peak memory 248764 kb
Host smart-edcfa91f-5e46-4499-b616-14fbe57fb402
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849303692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3849303692
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1308664736
Short name T187
Test name
Test status
Simulation time 856820428 ps
CPU time 60.17 seconds
Started May 26 01:23:31 PM PDT 24
Finished May 26 01:24:32 PM PDT 24
Peak memory 255916 kb
Host smart-71971d99-e041-4dc1-9c52-183f4b950c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
64736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1308664736
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1659658866
Short name T107
Test name
Test status
Simulation time 769001639 ps
CPU time 42.09 seconds
Started May 26 01:23:32 PM PDT 24
Finished May 26 01:24:14 PM PDT 24
Peak memory 255880 kb
Host smart-b3d30107-e257-4f5b-a70f-eb66bf4bda62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16596
58866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1659658866
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.646369676
Short name T265
Test name
Test status
Simulation time 847098934 ps
CPU time 31.44 seconds
Started May 26 01:23:31 PM PDT 24
Finished May 26 01:24:03 PM PDT 24
Peak memory 247520 kb
Host smart-bbad0833-6ea0-4ed8-bb8e-a981cebde668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64636
9676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.646369676
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1280268042
Short name T355
Test name
Test status
Simulation time 1343122317 ps
CPU time 26.43 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:23:55 PM PDT 24
Peak memory 248704 kb
Host smart-ab008f3b-2e30-41d6-a914-0c020786062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
68042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1280268042
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1534914052
Short name T647
Test name
Test status
Simulation time 76412270957 ps
CPU time 1573.02 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:49:43 PM PDT 24
Peak memory 289264 kb
Host smart-503f64d5-bd46-475d-92a4-379fd81c2d9e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534914052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1534914052
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3550947981
Short name T229
Test name
Test status
Simulation time 31925066946 ps
CPU time 1959.05 seconds
Started May 26 01:23:30 PM PDT 24
Finished May 26 01:56:10 PM PDT 24
Peak memory 273412 kb
Host smart-106539a5-1568-4c9a-bf60-1d8f1f7cfef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550947981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3550947981
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.121538337
Short name T686
Test name
Test status
Simulation time 731862314 ps
CPU time 62.14 seconds
Started May 26 01:23:27 PM PDT 24
Finished May 26 01:24:30 PM PDT 24
Peak memory 256872 kb
Host smart-f8782ec3-be0d-4d64-8bef-9acea7e093ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12153
8337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.121538337
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3030225792
Short name T71
Test name
Test status
Simulation time 1144532747 ps
CPU time 60.61 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:24:29 PM PDT 24
Peak memory 249464 kb
Host smart-3124a5ac-acf5-4490-897a-950f102c1399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
25792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3030225792
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1085547249
Short name T189
Test name
Test status
Simulation time 76596737723 ps
CPU time 1335.4 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:45:46 PM PDT 24
Peak memory 289568 kb
Host smart-da103d17-787f-48b8-82b3-898f19451f50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085547249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1085547249
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1349671429
Short name T599
Test name
Test status
Simulation time 211450968902 ps
CPU time 3005.11 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 02:13:35 PM PDT 24
Peak memory 289676 kb
Host smart-1a280178-8d63-42ec-b3e1-5f4c6a12e84a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349671429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1349671429
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3359239508
Short name T294
Test name
Test status
Simulation time 2832495626 ps
CPU time 116.6 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:25:25 PM PDT 24
Peak memory 247116 kb
Host smart-577d1f6c-72de-4aba-ac8f-d462a2d75e72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359239508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3359239508
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1388682424
Short name T533
Test name
Test status
Simulation time 368200992 ps
CPU time 26.22 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:23:57 PM PDT 24
Peak memory 256104 kb
Host smart-8f829adf-90bf-4277-85d1-113bf2e16aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13886
82424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1388682424
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2451232802
Short name T396
Test name
Test status
Simulation time 924203369 ps
CPU time 5.3 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:23:36 PM PDT 24
Peak memory 239296 kb
Host smart-9f96589a-bd71-4c1d-8b73-41c08f708129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24512
32802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2451232802
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1350853008
Short name T45
Test name
Test status
Simulation time 4447229498 ps
CPU time 70.89 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:24:40 PM PDT 24
Peak memory 248720 kb
Host smart-442cec4d-a54a-4b8e-b243-f3cb72abe54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13508
53008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1350853008
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.898480560
Short name T507
Test name
Test status
Simulation time 397244084 ps
CPU time 30.69 seconds
Started May 26 01:23:27 PM PDT 24
Finished May 26 01:23:59 PM PDT 24
Peak memory 248780 kb
Host smart-4ab17807-1846-4a5e-9306-bdabd95696de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89848
0560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.898480560
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1541600765
Short name T613
Test name
Test status
Simulation time 9578824350 ps
CPU time 1308.65 seconds
Started May 26 01:23:27 PM PDT 24
Finished May 26 01:45:17 PM PDT 24
Peak memory 289116 kb
Host smart-d0cffcc3-a780-4e03-9423-6cbe35db332b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541600765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1541600765
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.603831755
Short name T643
Test name
Test status
Simulation time 46237510237 ps
CPU time 4283.67 seconds
Started May 26 01:23:31 PM PDT 24
Finished May 26 02:34:56 PM PDT 24
Peak memory 318072 kb
Host smart-19deb450-59d0-45bb-9b75-d5797b065fca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603831755 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.603831755
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2496347411
Short name T710
Test name
Test status
Simulation time 105886566160 ps
CPU time 1675.89 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:51:36 PM PDT 24
Peak memory 273456 kb
Host smart-a640df29-f8f1-49d7-bedb-f68b799f44cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496347411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2496347411
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1908226768
Short name T358
Test name
Test status
Simulation time 12188857569 ps
CPU time 222.51 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:27:12 PM PDT 24
Peak memory 256956 kb
Host smart-7be1e61c-558f-4519-9a91-4973e01e0d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19082
26768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1908226768
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3183980291
Short name T402
Test name
Test status
Simulation time 6917494052 ps
CPU time 42.15 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:24:11 PM PDT 24
Peak memory 248828 kb
Host smart-c4fe7827-813b-425b-8c63-a594d9702c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31839
80291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3183980291
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1333511090
Short name T313
Test name
Test status
Simulation time 34358232371 ps
CPU time 1950.54 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:56:07 PM PDT 24
Peak memory 268296 kb
Host smart-d0996973-acd2-49f0-844c-28952bd6cc9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333511090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1333511090
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.17964293
Short name T482
Test name
Test status
Simulation time 13906358424 ps
CPU time 1252.26 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:44:29 PM PDT 24
Peak memory 288596 kb
Host smart-263c3158-36a2-46ed-a544-455de1250709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17964293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.17964293
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.666157928
Short name T637
Test name
Test status
Simulation time 7086944081 ps
CPU time 271.9 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:28:11 PM PDT 24
Peak memory 248200 kb
Host smart-c0d9ae27-011f-4bce-92c6-18c1e9b4a0f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666157928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.666157928
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2060519115
Short name T188
Test name
Test status
Simulation time 2834979527 ps
CPU time 47.12 seconds
Started May 26 01:23:29 PM PDT 24
Finished May 26 01:24:17 PM PDT 24
Peak memory 255692 kb
Host smart-8170ff93-1f31-4d25-a1b1-3ea751429d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
19115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2060519115
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.353762202
Short name T47
Test name
Test status
Simulation time 6690436918 ps
CPU time 51.6 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:24:21 PM PDT 24
Peak memory 247928 kb
Host smart-4d4e0dec-b0a8-4286-b141-a04994c2a601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35376
2202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.353762202
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4167984688
Short name T38
Test name
Test status
Simulation time 621458453 ps
CPU time 43.91 seconds
Started May 26 01:23:30 PM PDT 24
Finished May 26 01:24:15 PM PDT 24
Peak memory 247712 kb
Host smart-05c58646-d6fe-44a3-b452-1e95b34f10ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41679
84688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4167984688
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4009176213
Short name T689
Test name
Test status
Simulation time 848790483 ps
CPU time 59.53 seconds
Started May 26 01:23:28 PM PDT 24
Finished May 26 01:24:29 PM PDT 24
Peak memory 248728 kb
Host smart-2ef3c673-0734-448e-a314-34b8aa1f74bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091
76213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4009176213
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1846098460
Short name T564
Test name
Test status
Simulation time 61054572885 ps
CPU time 1619.04 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:50:36 PM PDT 24
Peak memory 282648 kb
Host smart-8cf61fef-53e2-47b2-a0c1-bd2fc2161b81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846098460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1846098460
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2841023635
Short name T414
Test name
Test status
Simulation time 40642597480 ps
CPU time 1004.57 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:40:25 PM PDT 24
Peak memory 269272 kb
Host smart-71362eac-a164-4718-8770-62b4dcdd40f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841023635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2841023635
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.460328380
Short name T335
Test name
Test status
Simulation time 3676168056 ps
CPU time 202.42 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:27:01 PM PDT 24
Peak memory 256844 kb
Host smart-f3cda349-c8aa-4613-9b90-93bdcddd0fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46032
8380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.460328380
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.187040599
Short name T674
Test name
Test status
Simulation time 560153256 ps
CPU time 11.65 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:23:48 PM PDT 24
Peak memory 249060 kb
Host smart-743a12ad-d77c-41d9-b587-16ba40d46b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
0599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.187040599
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.4149098718
Short name T36
Test name
Test status
Simulation time 54667861477 ps
CPU time 1449.36 seconds
Started May 26 01:23:37 PM PDT 24
Finished May 26 01:47:48 PM PDT 24
Peak memory 281608 kb
Host smart-47731a2f-2f90-4722-91b1-0b4f4999692f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149098718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4149098718
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3441655703
Short name T332
Test name
Test status
Simulation time 40299538230 ps
CPU time 1432.52 seconds
Started May 26 01:23:42 PM PDT 24
Finished May 26 01:47:35 PM PDT 24
Peak memory 289332 kb
Host smart-93535189-4926-47fb-b31c-d0510265334f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441655703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3441655703
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1011868173
Short name T287
Test name
Test status
Simulation time 51189432522 ps
CPU time 221.76 seconds
Started May 26 01:23:40 PM PDT 24
Finished May 26 01:27:23 PM PDT 24
Peak memory 253664 kb
Host smart-8dd3e76b-c846-4d7a-a1f8-efbb54bcb3a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011868173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1011868173
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2706584674
Short name T519
Test name
Test status
Simulation time 14846086524 ps
CPU time 50.75 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:30 PM PDT 24
Peak memory 248828 kb
Host smart-9a245292-f49a-48de-a2f5-050caafcb68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27065
84674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2706584674
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3215983929
Short name T84
Test name
Test status
Simulation time 1076403742 ps
CPU time 20.08 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:23:59 PM PDT 24
Peak memory 247652 kb
Host smart-1a420f92-f5fc-4fb3-892c-d25ef563fce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32159
83929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3215983929
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2296679141
Short name T593
Test name
Test status
Simulation time 2673369565 ps
CPU time 47.45 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:26 PM PDT 24
Peak memory 256048 kb
Host smart-a0c9c137-1738-4154-9604-31dd45c98c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22966
79141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2296679141
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3505814435
Short name T364
Test name
Test status
Simulation time 10614726186 ps
CPU time 48.24 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:24:28 PM PDT 24
Peak memory 248872 kb
Host smart-64ae457a-38ae-4435-b50a-d46f6db9d620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
14435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3505814435
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2327917491
Short name T19
Test name
Test status
Simulation time 19304503687 ps
CPU time 1571.84 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:49:49 PM PDT 24
Peak memory 288984 kb
Host smart-c78ce147-dc82-41ec-aa3e-c6bf433c12c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327917491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2327917491
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1970049258
Short name T217
Test name
Test status
Simulation time 224791419626 ps
CPU time 3499.35 seconds
Started May 26 01:23:37 PM PDT 24
Finished May 26 02:21:58 PM PDT 24
Peak memory 305144 kb
Host smart-2b807915-432c-4a6f-8984-3e57953fb5de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970049258 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1970049258
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3733825297
Short name T536
Test name
Test status
Simulation time 110352170382 ps
CPU time 1917.43 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:55:36 PM PDT 24
Peak memory 286284 kb
Host smart-6e2c597b-2a5a-4271-905f-03ead95d790f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733825297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3733825297
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2730575849
Short name T399
Test name
Test status
Simulation time 379696381 ps
CPU time 22.65 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:24:02 PM PDT 24
Peak memory 248988 kb
Host smart-2739d301-3b5f-48bf-a391-cb2e9b91eaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
75849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2730575849
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2519664368
Short name T185
Test name
Test status
Simulation time 721827419 ps
CPU time 19.34 seconds
Started May 26 01:23:40 PM PDT 24
Finished May 26 01:24:00 PM PDT 24
Peak memory 254984 kb
Host smart-26ba40e5-cfbe-4ae5-93a6-47e33b94507b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
64368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2519664368
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2854939915
Short name T649
Test name
Test status
Simulation time 16673075951 ps
CPU time 771.86 seconds
Started May 26 01:23:37 PM PDT 24
Finished May 26 01:36:29 PM PDT 24
Peak memory 273408 kb
Host smart-0c424052-0e31-469e-9c6c-d4350d88031e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854939915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2854939915
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3485257387
Short name T671
Test name
Test status
Simulation time 37851919575 ps
CPU time 2045.52 seconds
Started May 26 01:23:37 PM PDT 24
Finished May 26 01:57:44 PM PDT 24
Peak memory 282904 kb
Host smart-f04a86bf-0e4a-4ab4-9517-7630b4d24d47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485257387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3485257387
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3431205367
Short name T619
Test name
Test status
Simulation time 2757248900 ps
CPU time 64.99 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:44 PM PDT 24
Peak memory 248264 kb
Host smart-4869017b-a743-4c0e-94e6-adf26f7f1eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431205367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3431205367
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3400958744
Short name T696
Test name
Test status
Simulation time 1127588351 ps
CPU time 41.83 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:21 PM PDT 24
Peak memory 248940 kb
Host smart-7c967c98-4bb1-4bcd-86aa-664a302727d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
58744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3400958744
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1854097244
Short name T598
Test name
Test status
Simulation time 739086052 ps
CPU time 47.15 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:24:23 PM PDT 24
Peak memory 255484 kb
Host smart-94e6d474-6653-4cde-a463-d633c59bfe15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18540
97244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1854097244
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.344282852
Short name T591
Test name
Test status
Simulation time 715352301 ps
CPU time 14.87 seconds
Started May 26 01:23:37 PM PDT 24
Finished May 26 01:23:53 PM PDT 24
Peak memory 252812 kb
Host smart-273ebf12-367a-4597-a420-7adf53e707d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34428
2852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.344282852
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.680001227
Short name T535
Test name
Test status
Simulation time 2393790053 ps
CPU time 61.59 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:41 PM PDT 24
Peak memory 248864 kb
Host smart-654262f1-2780-45dc-9b0a-ef4c8da3b195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68000
1227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.680001227
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1227288955
Short name T464
Test name
Test status
Simulation time 8159278023 ps
CPU time 241.42 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:27:40 PM PDT 24
Peak memory 257008 kb
Host smart-cd168abf-ea31-47de-bad1-0f5bd218facd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227288955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1227288955
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2365445192
Short name T104
Test name
Test status
Simulation time 18003610054 ps
CPU time 1918.1 seconds
Started May 26 01:23:36 PM PDT 24
Finished May 26 01:55:35 PM PDT 24
Peak memory 289788 kb
Host smart-1ac6336c-fd6f-4c11-9fc6-8847544ff2aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365445192 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2365445192
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3635108922
Short name T437
Test name
Test status
Simulation time 170389702841 ps
CPU time 1713.42 seconds
Started May 26 01:23:43 PM PDT 24
Finished May 26 01:52:17 PM PDT 24
Peak memory 272652 kb
Host smart-10ab8ae4-f56d-454f-9b8a-a0af3517a058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635108922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3635108922
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.602619896
Short name T384
Test name
Test status
Simulation time 32297781619 ps
CPU time 150.51 seconds
Started May 26 01:23:41 PM PDT 24
Finished May 26 01:26:12 PM PDT 24
Peak memory 249856 kb
Host smart-0788cb6e-4bee-4d54-80a9-1242570c71d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60261
9896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.602619896
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.20181578
Short name T706
Test name
Test status
Simulation time 6745039234 ps
CPU time 61.15 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:24:41 PM PDT 24
Peak memory 257036 kb
Host smart-810768fb-cccb-49c2-bccb-f535d09468fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20181
578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.20181578
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3626967552
Short name T301
Test name
Test status
Simulation time 25259731559 ps
CPU time 1065.62 seconds
Started May 26 01:23:45 PM PDT 24
Finished May 26 01:41:31 PM PDT 24
Peak memory 268112 kb
Host smart-eea85b19-5e4e-4302-92c4-d1fb5eba8f95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626967552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3626967552
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1313119595
Short name T439
Test name
Test status
Simulation time 127536233617 ps
CPU time 1866.37 seconds
Started May 26 01:23:42 PM PDT 24
Finished May 26 01:54:49 PM PDT 24
Peak memory 269224 kb
Host smart-e8c59fdd-0720-4370-b672-80f5441286a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313119595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1313119595
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.803769865
Short name T291
Test name
Test status
Simulation time 13102040756 ps
CPU time 492.69 seconds
Started May 26 01:23:43 PM PDT 24
Finished May 26 01:31:57 PM PDT 24
Peak memory 247996 kb
Host smart-5e80475d-7f20-459e-9e32-f0f37de73443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803769865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.803769865
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3149879558
Short name T429
Test name
Test status
Simulation time 5268617199 ps
CPU time 33.67 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:12 PM PDT 24
Peak memory 256904 kb
Host smart-bea50ace-f9af-4685-a1c7-7258e5b9fae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31498
79558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3149879558
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.706123843
Short name T244
Test name
Test status
Simulation time 201941345 ps
CPU time 14.97 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:23:55 PM PDT 24
Peak memory 253032 kb
Host smart-acf70572-0236-4057-ac37-3b5daada6209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70612
3843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.706123843
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2511367629
Short name T372
Test name
Test status
Simulation time 3758589000 ps
CPU time 48.72 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:24:28 PM PDT 24
Peak memory 256188 kb
Host smart-05dd122b-d995-4011-96ed-4e96eff23a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25113
67629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2511367629
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4003187104
Short name T29
Test name
Test status
Simulation time 20008125156 ps
CPU time 1640.39 seconds
Started May 26 01:23:45 PM PDT 24
Finished May 26 01:51:06 PM PDT 24
Peak memory 305244 kb
Host smart-8f0aeffb-8738-4cc8-9286-98b4b2d1d1e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003187104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4003187104
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2709029751
Short name T115
Test name
Test status
Simulation time 18210047926 ps
CPU time 1697.13 seconds
Started May 26 01:23:42 PM PDT 24
Finished May 26 01:52:00 PM PDT 24
Peak memory 305212 kb
Host smart-9b5c90ca-5da4-4aff-8b5b-312ce185456a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709029751 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2709029751
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1835087459
Short name T196
Test name
Test status
Simulation time 35466817 ps
CPU time 2.07 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:31 PM PDT 24
Peak memory 248888 kb
Host smart-6344bf18-6dbb-425a-8c93-3770a276038c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1835087459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1835087459
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3375867418
Short name T24
Test name
Test status
Simulation time 12487325833 ps
CPU time 1160.52 seconds
Started May 26 01:22:05 PM PDT 24
Finished May 26 01:41:27 PM PDT 24
Peak memory 281640 kb
Host smart-7c57f718-2907-4a11-b90e-d089c385780a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375867418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3375867418
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.951954525
Short name T216
Test name
Test status
Simulation time 165564707 ps
CPU time 9.93 seconds
Started May 26 01:22:10 PM PDT 24
Finished May 26 01:22:20 PM PDT 24
Peak memory 240620 kb
Host smart-9a7ba06c-115f-4fe5-93e5-3a96d289e313
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=951954525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.951954525
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1056180572
Short name T413
Test name
Test status
Simulation time 1251871246 ps
CPU time 11.18 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:22:41 PM PDT 24
Peak memory 256088 kb
Host smart-63c801cc-6f59-49ec-a56d-b871bee5ce88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
80572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1056180572
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.4056027827
Short name T361
Test name
Test status
Simulation time 827020020 ps
CPU time 11.67 seconds
Started May 26 01:22:04 PM PDT 24
Finished May 26 01:22:16 PM PDT 24
Peak memory 248708 kb
Host smart-efc3a788-2dfb-44e7-98a9-74164841fcfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
27827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.4056027827
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1144395264
Short name T307
Test name
Test status
Simulation time 114607347848 ps
CPU time 1460.35 seconds
Started May 26 01:22:21 PM PDT 24
Finished May 26 01:46:42 PM PDT 24
Peak memory 272968 kb
Host smart-43409341-e772-47e8-b5a5-3656f107f5f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144395264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1144395264
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3654734516
Short name T81
Test name
Test status
Simulation time 122412051640 ps
CPU time 1425.93 seconds
Started May 26 01:22:07 PM PDT 24
Finished May 26 01:45:53 PM PDT 24
Peak memory 289520 kb
Host smart-f287d08b-dfbb-4227-98df-fba5992acfcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654734516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3654734516
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3686117743
Short name T512
Test name
Test status
Simulation time 9894716282 ps
CPU time 401.7 seconds
Started May 26 01:22:11 PM PDT 24
Finished May 26 01:28:54 PM PDT 24
Peak memory 256104 kb
Host smart-40c57328-9fb4-4fef-aa5d-cc5159f900a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686117743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3686117743
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3449245806
Short name T4
Test name
Test status
Simulation time 605968293 ps
CPU time 37.22 seconds
Started May 26 01:22:12 PM PDT 24
Finished May 26 01:22:50 PM PDT 24
Peak memory 248780 kb
Host smart-3f8b5e4c-e041-49bd-92bf-562afc30502a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34492
45806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3449245806
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4096940358
Short name T522
Test name
Test status
Simulation time 705357385 ps
CPU time 51.35 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:23:21 PM PDT 24
Peak memory 256744 kb
Host smart-a822cf51-3cce-4e7c-bc7d-11577fee9a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40969
40358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4096940358
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2202837504
Short name T55
Test name
Test status
Simulation time 508537580 ps
CPU time 13.07 seconds
Started May 26 01:22:13 PM PDT 24
Finished May 26 01:22:26 PM PDT 24
Peak memory 248768 kb
Host smart-9f5e6851-dbbb-4d49-91ca-75c2f89ad10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
37504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2202837504
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2302339716
Short name T59
Test name
Test status
Simulation time 3696451143 ps
CPU time 55.7 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:23:21 PM PDT 24
Peak memory 255892 kb
Host smart-6b548fbc-4134-4fb9-85ec-2b1ea94c8f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23023
39716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2302339716
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.294142522
Short name T635
Test name
Test status
Simulation time 207393436376 ps
CPU time 3153.15 seconds
Started May 26 01:23:48 PM PDT 24
Finished May 26 02:16:22 PM PDT 24
Peak memory 289388 kb
Host smart-29e65be0-98fe-4b84-b574-073608ca8615
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294142522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.294142522
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.4191748028
Short name T651
Test name
Test status
Simulation time 1038416554 ps
CPU time 102.37 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:25:29 PM PDT 24
Peak memory 256876 kb
Host smart-414992f4-8419-4451-a437-a314e1b908a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
48028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4191748028
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3178188263
Short name T540
Test name
Test status
Simulation time 900638829 ps
CPU time 19.51 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:24:06 PM PDT 24
Peak memory 248676 kb
Host smart-35923f37-753f-43ce-bfd5-0f298cf56e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781
88263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3178188263
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3318992104
Short name T272
Test name
Test status
Simulation time 135405522517 ps
CPU time 1073.68 seconds
Started May 26 01:23:48 PM PDT 24
Finished May 26 01:41:42 PM PDT 24
Peak memory 284476 kb
Host smart-f2097ac1-83c3-460f-8379-46c17f05a25f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318992104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3318992104
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2340127811
Short name T410
Test name
Test status
Simulation time 34464536220 ps
CPU time 2124.88 seconds
Started May 26 01:23:51 PM PDT 24
Finished May 26 01:59:16 PM PDT 24
Peak memory 285400 kb
Host smart-7e93937f-8f7a-48d4-80b1-501e17db63dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340127811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2340127811
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2531402492
Short name T553
Test name
Test status
Simulation time 49911739894 ps
CPU time 472.96 seconds
Started May 26 01:23:48 PM PDT 24
Finished May 26 01:31:42 PM PDT 24
Peak memory 248280 kb
Host smart-62c120aa-18b5-4421-998c-6db3053160ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531402492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2531402492
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1592763908
Short name T623
Test name
Test status
Simulation time 194212858 ps
CPU time 12.25 seconds
Started May 26 01:23:39 PM PDT 24
Finished May 26 01:23:52 PM PDT 24
Peak memory 254312 kb
Host smart-3b9a0482-1b7c-41cb-be38-ce45579857b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15927
63908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1592763908
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2029450954
Short name T543
Test name
Test status
Simulation time 1319311906 ps
CPU time 18.83 seconds
Started May 26 01:23:40 PM PDT 24
Finished May 26 01:23:59 PM PDT 24
Peak memory 248736 kb
Host smart-1bfab603-e60e-4f4d-b6c4-9b4885bf355f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
50954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2029450954
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.605643483
Short name T491
Test name
Test status
Simulation time 835556172 ps
CPU time 16.42 seconds
Started May 26 01:23:38 PM PDT 24
Finished May 26 01:23:55 PM PDT 24
Peak memory 248788 kb
Host smart-60b15cf1-3510-4ef5-9aea-f558fef41825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60564
3483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.605643483
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2127320859
Short name T662
Test name
Test status
Simulation time 245642791447 ps
CPU time 1359 seconds
Started May 26 01:23:44 PM PDT 24
Finished May 26 01:46:24 PM PDT 24
Peak memory 288864 kb
Host smart-dc358c69-82a5-46e6-a8cb-7c00bd40d927
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127320859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2127320859
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1389724044
Short name T82
Test name
Test status
Simulation time 151487748547 ps
CPU time 3473.39 seconds
Started May 26 01:23:44 PM PDT 24
Finished May 26 02:21:39 PM PDT 24
Peak memory 322372 kb
Host smart-92fbec8b-d95c-4180-abf9-a498724ed833
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389724044 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1389724044
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2670433408
Short name T57
Test name
Test status
Simulation time 24783656542 ps
CPU time 1344.99 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:46:12 PM PDT 24
Peak memory 288204 kb
Host smart-35366b3b-525c-43f5-874b-8d3bd0fbeb12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670433408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2670433408
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.150735876
Short name T670
Test name
Test status
Simulation time 14511467608 ps
CPU time 149.09 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:26:15 PM PDT 24
Peak memory 257012 kb
Host smart-4b52ff2c-7a27-4683-80af-d5bb3c0b2807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15073
5876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.150735876
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.503887178
Short name T77
Test name
Test status
Simulation time 2551930494 ps
CPU time 41.43 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:24:27 PM PDT 24
Peak memory 257052 kb
Host smart-f0d32896-33cb-4dc6-8a42-b55cdd90f885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50388
7178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.503887178
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.633449499
Short name T499
Test name
Test status
Simulation time 154654787286 ps
CPU time 1232.57 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:44:19 PM PDT 24
Peak memory 286928 kb
Host smart-8c6b13a2-3dac-43cc-8a3c-aa4c1818ee99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633449499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.633449499
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3894156700
Short name T582
Test name
Test status
Simulation time 6337143589 ps
CPU time 787.77 seconds
Started May 26 01:23:48 PM PDT 24
Finished May 26 01:36:56 PM PDT 24
Peak memory 273416 kb
Host smart-80e64cf3-758b-4ae6-a2e4-26375251fcae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894156700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3894156700
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2736286716
Short name T285
Test name
Test status
Simulation time 17736792327 ps
CPU time 346.67 seconds
Started May 26 01:23:44 PM PDT 24
Finished May 26 01:29:31 PM PDT 24
Peak memory 247196 kb
Host smart-4f1f193f-b1f4-4347-ba19-f71ef4c741e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736286716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2736286716
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.947400962
Short name T501
Test name
Test status
Simulation time 592048673 ps
CPU time 35.09 seconds
Started May 26 01:23:48 PM PDT 24
Finished May 26 01:24:23 PM PDT 24
Peak memory 248736 kb
Host smart-5246137f-45f0-4cb6-ac1b-633ca8042760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94740
0962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.947400962
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1037071884
Short name T379
Test name
Test status
Simulation time 8931459430 ps
CPU time 40.49 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:24:27 PM PDT 24
Peak memory 255996 kb
Host smart-bec19c33-f1ce-4391-b80a-b91f529dd8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
71884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1037071884
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3452548536
Short name T644
Test name
Test status
Simulation time 920207704 ps
CPU time 27.51 seconds
Started May 26 01:23:50 PM PDT 24
Finished May 26 01:24:18 PM PDT 24
Peak memory 248704 kb
Host smart-f96a90d9-09e8-470f-8f16-f5a9e7bff391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
48536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3452548536
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3345858923
Short name T474
Test name
Test status
Simulation time 508279529 ps
CPU time 26.11 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:24:12 PM PDT 24
Peak memory 248776 kb
Host smart-ec83aa19-7e1b-4b91-a2bb-b15d39663193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
58923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3345858923
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2830978639
Short name T247
Test name
Test status
Simulation time 142361385059 ps
CPU time 2306.52 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 02:02:13 PM PDT 24
Peak memory 289048 kb
Host smart-af564f85-20c6-4cf6-92c5-45b1e5241fa5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830978639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2830978639
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1031282318
Short name T516
Test name
Test status
Simulation time 212755318479 ps
CPU time 6275.82 seconds
Started May 26 01:23:49 PM PDT 24
Finished May 26 03:08:26 PM PDT 24
Peak memory 370448 kb
Host smart-a80da263-b1de-47ff-a5ba-81b901c18777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031282318 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1031282318
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.41165218
Short name T639
Test name
Test status
Simulation time 42131845280 ps
CPU time 2496.77 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 02:05:47 PM PDT 24
Peak memory 286764 kb
Host smart-409d7379-8512-4ab3-849b-35c637612132
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41165218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.41165218
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2913412206
Short name T424
Test name
Test status
Simulation time 782551118 ps
CPU time 22.92 seconds
Started May 26 01:23:49 PM PDT 24
Finished May 26 01:24:13 PM PDT 24
Peak memory 255956 kb
Host smart-56e2b6c0-9996-4240-a69d-4cc7d798222e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
12206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2913412206
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3921814070
Short name T15
Test name
Test status
Simulation time 879776361 ps
CPU time 48.99 seconds
Started May 26 01:23:45 PM PDT 24
Finished May 26 01:24:34 PM PDT 24
Peak memory 255872 kb
Host smart-ac92685e-0af9-4ba7-beb2-39c9fc03548d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
14070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3921814070
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3947111785
Short name T684
Test name
Test status
Simulation time 70383774343 ps
CPU time 1756.68 seconds
Started May 26 01:24:02 PM PDT 24
Finished May 26 01:53:20 PM PDT 24
Peak memory 273040 kb
Host smart-58d89532-ae14-4abf-9c70-37813d317ef1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947111785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3947111785
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3429003244
Short name T611
Test name
Test status
Simulation time 36390774266 ps
CPU time 2048.09 seconds
Started May 26 01:23:58 PM PDT 24
Finished May 26 01:58:07 PM PDT 24
Peak memory 273416 kb
Host smart-c70a1b57-cd0a-457e-b8e2-3b5f8c01a5c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429003244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3429003244
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2970550034
Short name T589
Test name
Test status
Simulation time 9950077289 ps
CPU time 217.51 seconds
Started May 26 01:23:54 PM PDT 24
Finished May 26 01:27:32 PM PDT 24
Peak memory 254380 kb
Host smart-92ed616b-774e-40db-ab35-f63c0c8debce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970550034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2970550034
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3890683819
Short name T601
Test name
Test status
Simulation time 353532955 ps
CPU time 12.12 seconds
Started May 26 01:23:49 PM PDT 24
Finished May 26 01:24:01 PM PDT 24
Peak memory 248760 kb
Host smart-06abed4d-f020-4f18-98d8-a25058fa6f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
83819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3890683819
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1625579485
Short name T547
Test name
Test status
Simulation time 1059539577 ps
CPU time 65.92 seconds
Started May 26 01:23:46 PM PDT 24
Finished May 26 01:24:53 PM PDT 24
Peak memory 255276 kb
Host smart-5ea667db-7ffa-412d-b630-9d37af1ddac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16255
79485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1625579485
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2761844918
Short name T53
Test name
Test status
Simulation time 3985545898 ps
CPU time 62.9 seconds
Started May 26 01:23:49 PM PDT 24
Finished May 26 01:24:53 PM PDT 24
Peak memory 248816 kb
Host smart-7dc02d25-d15a-42aa-b338-04ed997a14ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
44918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2761844918
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2977542296
Short name T523
Test name
Test status
Simulation time 104153871 ps
CPU time 7.17 seconds
Started May 26 01:23:48 PM PDT 24
Finished May 26 01:23:56 PM PDT 24
Peak memory 250764 kb
Host smart-b1567237-8762-4903-a038-19c8e972771a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29775
42296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2977542296
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.528974778
Short name T383
Test name
Test status
Simulation time 113900742372 ps
CPU time 1726.74 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:52:57 PM PDT 24
Peak memory 273384 kb
Host smart-8dfa06d5-0338-4429-9c50-3076fa47e570
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528974778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.528974778
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.718725350
Short name T423
Test name
Test status
Simulation time 14869582470 ps
CPU time 137.18 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:26:27 PM PDT 24
Peak memory 256644 kb
Host smart-5a92887e-8a97-4246-9458-7f2f724ada51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71872
5350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.718725350
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1350511326
Short name T544
Test name
Test status
Simulation time 3698793665 ps
CPU time 61.53 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:25:11 PM PDT 24
Peak memory 255976 kb
Host smart-744fce20-b2a2-4895-9a9a-ba272061acf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13505
11326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1350511326
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.775893319
Short name T311
Test name
Test status
Simulation time 17528571339 ps
CPU time 1673.48 seconds
Started May 26 01:23:54 PM PDT 24
Finished May 26 01:51:48 PM PDT 24
Peak memory 288904 kb
Host smart-45edd828-f7a7-47c0-97ad-8eeac31f901d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775893319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.775893319
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.970689833
Short name T366
Test name
Test status
Simulation time 572219997947 ps
CPU time 2563.05 seconds
Started May 26 01:23:57 PM PDT 24
Finished May 26 02:06:41 PM PDT 24
Peak memory 281548 kb
Host smart-208d2bca-a073-4202-8751-293009d71068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970689833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.970689833
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3674426447
Short name T292
Test name
Test status
Simulation time 21622487391 ps
CPU time 233.97 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:28:04 PM PDT 24
Peak memory 248192 kb
Host smart-773f125b-4fcc-4fbb-a856-f26950132ce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674426447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3674426447
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3884301867
Short name T627
Test name
Test status
Simulation time 4554423443 ps
CPU time 46.75 seconds
Started May 26 01:23:55 PM PDT 24
Finished May 26 01:24:42 PM PDT 24
Peak memory 248792 kb
Host smart-189e63e6-57d8-432f-90a5-022be1a53d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38843
01867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3884301867
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1385568503
Short name T549
Test name
Test status
Simulation time 582800161 ps
CPU time 36.91 seconds
Started May 26 01:23:54 PM PDT 24
Finished May 26 01:24:31 PM PDT 24
Peak memory 249080 kb
Host smart-8af59289-4f78-4831-8382-81765030e501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13855
68503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1385568503
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1174819452
Short name T486
Test name
Test status
Simulation time 10588768445 ps
CPU time 42.59 seconds
Started May 26 01:24:00 PM PDT 24
Finished May 26 01:24:43 PM PDT 24
Peak memory 255648 kb
Host smart-a2fbe4d9-57fa-4749-a06d-ae4c7b4f8375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11748
19452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1174819452
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2844389214
Short name T590
Test name
Test status
Simulation time 2899584871 ps
CPU time 28.16 seconds
Started May 26 01:23:55 PM PDT 24
Finished May 26 01:24:24 PM PDT 24
Peak memory 248796 kb
Host smart-d3e8b5ae-da49-4530-9b0b-31079efbfe93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
89214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2844389214
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2526637760
Short name T650
Test name
Test status
Simulation time 51068569467 ps
CPU time 1059.72 seconds
Started May 26 01:23:55 PM PDT 24
Finished May 26 01:41:35 PM PDT 24
Peak memory 285248 kb
Host smart-3e1d032a-2b99-43f3-9697-82576c650acf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526637760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2526637760
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1725553495
Short name T92
Test name
Test status
Simulation time 84680308424 ps
CPU time 2567.82 seconds
Started May 26 01:23:54 PM PDT 24
Finished May 26 02:06:43 PM PDT 24
Peak memory 289860 kb
Host smart-ec7e95f3-b3bf-40f5-94ec-3a895caac87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725553495 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1725553495
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2271260658
Short name T708
Test name
Test status
Simulation time 9754036814 ps
CPU time 1122.75 seconds
Started May 26 01:23:53 PM PDT 24
Finished May 26 01:42:36 PM PDT 24
Peak memory 281628 kb
Host smart-f09eee3a-d7f8-4221-b800-930cf706d547
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271260658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2271260658
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2015352735
Short name T485
Test name
Test status
Simulation time 1220750033 ps
CPU time 107.44 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:25:57 PM PDT 24
Peak memory 256588 kb
Host smart-01ac1586-e5e8-430c-9404-4ac350076537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
52735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2015352735
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3847330427
Short name T665
Test name
Test status
Simulation time 2026316258 ps
CPU time 36.27 seconds
Started May 26 01:23:54 PM PDT 24
Finished May 26 01:24:31 PM PDT 24
Peak memory 248660 kb
Host smart-fc3b5fcb-3f7d-4bb5-b25d-4770ee2becf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473
30427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3847330427
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1777947181
Short name T525
Test name
Test status
Simulation time 34948708775 ps
CPU time 1520.7 seconds
Started May 26 01:24:02 PM PDT 24
Finished May 26 01:49:24 PM PDT 24
Peak memory 289608 kb
Host smart-f9bc2746-6c12-4640-ad09-3ef1689d4c09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777947181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1777947181
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.310359469
Short name T587
Test name
Test status
Simulation time 47111950936 ps
CPU time 1215.01 seconds
Started May 26 01:23:53 PM PDT 24
Finished May 26 01:44:09 PM PDT 24
Peak memory 289168 kb
Host smart-36f0348b-d64b-4861-bcda-78b644411866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310359469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.310359469
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.469691438
Short name T273
Test name
Test status
Simulation time 11175186841 ps
CPU time 471 seconds
Started May 26 01:23:55 PM PDT 24
Finished May 26 01:31:47 PM PDT 24
Peak memory 248188 kb
Host smart-82d517c3-4919-43d1-9607-e495ddec5556
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469691438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.469691438
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1767085462
Short name T331
Test name
Test status
Simulation time 43422808 ps
CPU time 4.33 seconds
Started May 26 01:23:53 PM PDT 24
Finished May 26 01:23:58 PM PDT 24
Peak memory 240508 kb
Host smart-45144b86-cf1d-48fa-a12d-cec9ddd11f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17670
85462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1767085462
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3672476426
Short name T661
Test name
Test status
Simulation time 1287887010 ps
CPU time 39.46 seconds
Started May 26 01:23:55 PM PDT 24
Finished May 26 01:24:35 PM PDT 24
Peak memory 249148 kb
Host smart-747e8718-7fda-4645-8555-b6170c03b24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724
76426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3672476426
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2002668255
Short name T633
Test name
Test status
Simulation time 1020458203 ps
CPU time 18.8 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:24:29 PM PDT 24
Peak memory 248596 kb
Host smart-d25b8158-7725-48b9-a418-e4705b15f217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20026
68255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2002668255
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2422689964
Short name T542
Test name
Test status
Simulation time 893106952 ps
CPU time 43.79 seconds
Started May 26 01:23:56 PM PDT 24
Finished May 26 01:24:40 PM PDT 24
Peak memory 255912 kb
Host smart-f818d9e3-fe85-49c6-a660-fedd38fa3229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226
89964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2422689964
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.4083224618
Short name T68
Test name
Test status
Simulation time 13583677333 ps
CPU time 432.86 seconds
Started May 26 01:24:09 PM PDT 24
Finished May 26 01:31:23 PM PDT 24
Peak memory 255888 kb
Host smart-9177dd3f-74a0-42e7-a273-152df675dbe0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083224618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.4083224618
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4152060169
Short name T35
Test name
Test status
Simulation time 21683085421 ps
CPU time 1266.45 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:45:11 PM PDT 24
Peak memory 272848 kb
Host smart-25815104-90f3-4a40-9bae-e98981e22389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152060169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4152060169
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2036482466
Short name T607
Test name
Test status
Simulation time 2161838206 ps
CPU time 36.46 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:24:40 PM PDT 24
Peak memory 249092 kb
Host smart-6b767995-5793-4401-bb63-2ff13994ff2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
82466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2036482466
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2335438134
Short name T529
Test name
Test status
Simulation time 6669428273 ps
CPU time 43.72 seconds
Started May 26 01:24:05 PM PDT 24
Finished May 26 01:24:50 PM PDT 24
Peak memory 248836 kb
Host smart-a4553db6-ecde-4b3d-a09f-3debc89ee4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23354
38134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2335438134
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3033368978
Short name T654
Test name
Test status
Simulation time 116267156197 ps
CPU time 2728.35 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 02:09:34 PM PDT 24
Peak memory 288888 kb
Host smart-bd96d394-7bc5-48a3-9609-5a18106e5148
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033368978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3033368978
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2371190817
Short name T340
Test name
Test status
Simulation time 112872039589 ps
CPU time 3149.94 seconds
Started May 26 01:24:05 PM PDT 24
Finished May 26 02:16:36 PM PDT 24
Peak memory 289096 kb
Host smart-ccb099e3-bea4-47bf-8ed4-9138d9ee557b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371190817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2371190817
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2338648187
Short name T282
Test name
Test status
Simulation time 70151482327 ps
CPU time 513.23 seconds
Started May 26 01:24:02 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 256424 kb
Host smart-dc8983f5-3a0f-472a-a7d2-d64db71a9b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338648187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2338648187
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1623780279
Short name T368
Test name
Test status
Simulation time 597676799 ps
CPU time 16.78 seconds
Started May 26 01:23:54 PM PDT 24
Finished May 26 01:24:12 PM PDT 24
Peak memory 255608 kb
Host smart-0b61db4b-e844-40d9-838a-bbfadafbb456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16237
80279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1623780279
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1896243169
Short name T559
Test name
Test status
Simulation time 251799076 ps
CPU time 24.28 seconds
Started May 26 01:24:02 PM PDT 24
Finished May 26 01:24:27 PM PDT 24
Peak memory 255832 kb
Host smart-9b94a543-164b-4d97-81f7-00b16753c362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18962
43169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1896243169
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2163484191
Short name T339
Test name
Test status
Simulation time 1018767044 ps
CPU time 41.15 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:24:45 PM PDT 24
Peak memory 248788 kb
Host smart-b9bafeef-2850-4ffe-86d2-dc744bdcbfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21634
84191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2163484191
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1616135326
Short name T341
Test name
Test status
Simulation time 116911414 ps
CPU time 8.51 seconds
Started May 26 01:23:55 PM PDT 24
Finished May 26 01:24:04 PM PDT 24
Peak memory 256936 kb
Host smart-205e023a-231d-4d77-879f-92b5943e9811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16161
35326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1616135326
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3490543437
Short name T471
Test name
Test status
Simulation time 12908459897 ps
CPU time 1168.98 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:43:33 PM PDT 24
Peak memory 284696 kb
Host smart-f437e56c-fe1c-4f04-b6c5-58d11f381ceb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490543437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3490543437
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.4106216361
Short name T359
Test name
Test status
Simulation time 71905222572 ps
CPU time 2361.82 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 02:03:26 PM PDT 24
Peak memory 288140 kb
Host smart-99606436-f020-41d2-8d62-92bad2a4f2ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106216361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.4106216361
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3152124066
Short name T700
Test name
Test status
Simulation time 5162647084 ps
CPU time 84.09 seconds
Started May 26 01:24:02 PM PDT 24
Finished May 26 01:25:26 PM PDT 24
Peak memory 248836 kb
Host smart-6ae9b8c5-93fc-4735-9c51-c5565fd36c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
24066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3152124066
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2332546370
Short name T105
Test name
Test status
Simulation time 364315671 ps
CPU time 6.55 seconds
Started May 26 01:24:06 PM PDT 24
Finished May 26 01:24:13 PM PDT 24
Peak memory 248680 kb
Host smart-68931ab3-21f7-4ef2-a3cd-9a192892731e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325
46370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2332546370
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1308639704
Short name T682
Test name
Test status
Simulation time 329949513622 ps
CPU time 2737.14 seconds
Started May 26 01:24:07 PM PDT 24
Finished May 26 02:09:44 PM PDT 24
Peak memory 282932 kb
Host smart-e360e47a-de5e-4d23-b942-9c8f3c0665c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308639704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1308639704
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2704015344
Short name T572
Test name
Test status
Simulation time 71235523041 ps
CPU time 1480.12 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:48:44 PM PDT 24
Peak memory 273420 kb
Host smart-8cc3ae36-3d28-465b-9b45-bd375d2600e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704015344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2704015344
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2120728913
Short name T510
Test name
Test status
Simulation time 2191042025 ps
CPU time 95.59 seconds
Started May 26 01:24:02 PM PDT 24
Finished May 26 01:25:39 PM PDT 24
Peak memory 247108 kb
Host smart-c2e9ffa3-cd40-4199-9d47-2537a4579e8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120728913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2120728913
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2813239070
Short name T334
Test name
Test status
Simulation time 295045296 ps
CPU time 20.8 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 01:24:26 PM PDT 24
Peak memory 248784 kb
Host smart-d33b0afc-915f-420c-ab5c-85d99911b63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
39070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2813239070
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1659285322
Short name T511
Test name
Test status
Simulation time 1260354857 ps
CPU time 45.42 seconds
Started May 26 01:24:06 PM PDT 24
Finished May 26 01:24:52 PM PDT 24
Peak memory 248756 kb
Host smart-376964d3-9fed-4ee4-b892-de418ceaa2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16592
85322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1659285322
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.930823575
Short name T695
Test name
Test status
Simulation time 921729382 ps
CPU time 13.99 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 01:24:18 PM PDT 24
Peak memory 254228 kb
Host smart-877ebc81-2fe8-4db9-b8d7-db32826806ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93082
3575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.930823575
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1390336162
Short name T457
Test name
Test status
Simulation time 1556948407 ps
CPU time 10.31 seconds
Started May 26 01:24:05 PM PDT 24
Finished May 26 01:24:16 PM PDT 24
Peak memory 250596 kb
Host smart-62b8a65f-7dcd-44ca-9aed-6c2fadf34d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13903
36162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1390336162
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2853391023
Short name T530
Test name
Test status
Simulation time 82267255579 ps
CPU time 1338.7 seconds
Started May 26 01:24:16 PM PDT 24
Finished May 26 01:46:35 PM PDT 24
Peak memory 273112 kb
Host smart-67014555-ddd7-4ae8-8097-91206b764c24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853391023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2853391023
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1657074817
Short name T484
Test name
Test status
Simulation time 11660073927 ps
CPU time 200.88 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:27:25 PM PDT 24
Peak memory 257000 kb
Host smart-761cbd81-784c-4d90-b173-594d0feae1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16570
74817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1657074817
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2378830298
Short name T596
Test name
Test status
Simulation time 1129420327 ps
CPU time 26.85 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:24:30 PM PDT 24
Peak memory 248804 kb
Host smart-22840116-69a2-418c-b1d7-10be38450918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23788
30298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2378830298
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4169661119
Short name T351
Test name
Test status
Simulation time 7445372718 ps
CPU time 739.68 seconds
Started May 26 01:24:17 PM PDT 24
Finished May 26 01:36:37 PM PDT 24
Peak memory 270592 kb
Host smart-6aa7b134-a2ac-4213-9c88-a8353af5b031
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169661119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4169661119
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.813163947
Short name T397
Test name
Test status
Simulation time 1106636171 ps
CPU time 62 seconds
Started May 26 01:24:06 PM PDT 24
Finished May 26 01:25:08 PM PDT 24
Peak memory 255868 kb
Host smart-71830945-42ca-40e2-a717-13bc8e791255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81316
3947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.813163947
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3316527621
Short name T675
Test name
Test status
Simulation time 332686326 ps
CPU time 18.9 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 01:24:24 PM PDT 24
Peak memory 248732 kb
Host smart-2bf75a92-6bda-4dc3-af44-c5d244fbd3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33165
27621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3316527621
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.211037692
Short name T253
Test name
Test status
Simulation time 890340700 ps
CPU time 39.67 seconds
Started May 26 01:24:03 PM PDT 24
Finished May 26 01:24:43 PM PDT 24
Peak memory 248652 kb
Host smart-596be9fc-460b-414b-ad46-17dae3919ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21103
7692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.211037692
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3641567959
Short name T380
Test name
Test status
Simulation time 545661652 ps
CPU time 21.42 seconds
Started May 26 01:24:04 PM PDT 24
Finished May 26 01:24:26 PM PDT 24
Peak memory 248696 kb
Host smart-1e5088fa-6d9c-42a2-a2ce-dd41826a1298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36415
67959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3641567959
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3363604064
Short name T656
Test name
Test status
Simulation time 5814899093 ps
CPU time 172.69 seconds
Started May 26 01:24:17 PM PDT 24
Finished May 26 01:27:10 PM PDT 24
Peak memory 256656 kb
Host smart-f658aa77-3a1d-47e3-b313-dac456c5fe26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363604064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3363604064
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.912690912
Short name T427
Test name
Test status
Simulation time 42220142779 ps
CPU time 2390.55 seconds
Started May 26 01:24:15 PM PDT 24
Finished May 26 02:04:06 PM PDT 24
Peak memory 288988 kb
Host smart-fee01766-73ac-4c35-a0aa-f93e5b71baaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912690912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.912690912
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.231360775
Short name T640
Test name
Test status
Simulation time 3074474051 ps
CPU time 194.94 seconds
Started May 26 01:24:17 PM PDT 24
Finished May 26 01:27:32 PM PDT 24
Peak memory 248824 kb
Host smart-d035d532-38a4-4a3e-9a86-270b566a9796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
0775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.231360775
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2599409605
Short name T109
Test name
Test status
Simulation time 162384244 ps
CPU time 6.6 seconds
Started May 26 01:24:18 PM PDT 24
Finished May 26 01:24:25 PM PDT 24
Peak memory 248740 kb
Host smart-04737c0d-8137-4fbb-a82f-4821db65c9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25994
09605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2599409605
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.514986803
Short name T449
Test name
Test status
Simulation time 673110344196 ps
CPU time 2154.77 seconds
Started May 26 01:24:15 PM PDT 24
Finished May 26 02:00:10 PM PDT 24
Peak memory 289120 kb
Host smart-e393beac-24ef-4282-a4f7-09db03d84ead
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514986803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.514986803
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2151115133
Short name T657
Test name
Test status
Simulation time 11434920162 ps
CPU time 248.32 seconds
Started May 26 01:24:19 PM PDT 24
Finished May 26 01:28:28 PM PDT 24
Peak memory 248344 kb
Host smart-11ab1020-38f2-4d76-9e3e-e1a4c31d71d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151115133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2151115133
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2380124317
Short name T112
Test name
Test status
Simulation time 866899204 ps
CPU time 30.69 seconds
Started May 26 01:24:16 PM PDT 24
Finished May 26 01:24:47 PM PDT 24
Peak memory 248768 kb
Host smart-c4ee7e33-7572-4f65-8634-c0a57f5b1cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23801
24317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2380124317
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1621311984
Short name T436
Test name
Test status
Simulation time 416433527 ps
CPU time 12.45 seconds
Started May 26 01:24:19 PM PDT 24
Finished May 26 01:24:32 PM PDT 24
Peak memory 255948 kb
Host smart-7174a03b-3000-47e8-8979-839576422a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
11984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1621311984
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.375354181
Short name T631
Test name
Test status
Simulation time 1769395219 ps
CPU time 28.1 seconds
Started May 26 01:24:16 PM PDT 24
Finished May 26 01:24:45 PM PDT 24
Peak memory 254960 kb
Host smart-371d8a9e-6aab-4f35-9dbd-affbcc80fd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37535
4181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.375354181
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2794199223
Short name T473
Test name
Test status
Simulation time 454488964 ps
CPU time 33.38 seconds
Started May 26 01:24:16 PM PDT 24
Finished May 26 01:24:50 PM PDT 24
Peak memory 248788 kb
Host smart-9b2ef2eb-fc8d-4e49-bcb9-fc98e85aafe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27941
99223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2794199223
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.416657344
Short name T455
Test name
Test status
Simulation time 160682001101 ps
CPU time 2561.35 seconds
Started May 26 01:24:16 PM PDT 24
Finished May 26 02:06:58 PM PDT 24
Peak memory 289732 kb
Host smart-53db50bc-4ed7-412a-9844-41a102fd7bf9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416657344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.416657344
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3763848377
Short name T495
Test name
Test status
Simulation time 691354102722 ps
CPU time 2639.02 seconds
Started May 26 01:24:22 PM PDT 24
Finished May 26 02:08:22 PM PDT 24
Peak memory 289320 kb
Host smart-f1bf96fd-d876-4159-aff7-932544e9e719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763848377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3763848377
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3396851191
Short name T421
Test name
Test status
Simulation time 1149771010 ps
CPU time 100.09 seconds
Started May 26 01:24:21 PM PDT 24
Finished May 26 01:26:02 PM PDT 24
Peak memory 250172 kb
Host smart-f1685b57-f283-4477-a796-122e205161cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33968
51191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3396851191
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2683954068
Short name T693
Test name
Test status
Simulation time 137395228 ps
CPU time 6.19 seconds
Started May 26 01:24:19 PM PDT 24
Finished May 26 01:24:26 PM PDT 24
Peak memory 248692 kb
Host smart-91f75877-5fc0-4143-b7ec-2ddea90ab706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26839
54068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2683954068
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.24172321
Short name T573
Test name
Test status
Simulation time 23386976850 ps
CPU time 1025.69 seconds
Started May 26 01:24:22 PM PDT 24
Finished May 26 01:41:28 PM PDT 24
Peak memory 273164 kb
Host smart-2443a127-482f-4f39-b4b4-e75509028cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24172321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.24172321
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3648847211
Short name T376
Test name
Test status
Simulation time 16691804494 ps
CPU time 171.86 seconds
Started May 26 01:24:23 PM PDT 24
Finished May 26 01:27:16 PM PDT 24
Peak memory 248164 kb
Host smart-95438b51-3f8b-4e67-ba9d-c970abc6a680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648847211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3648847211
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.880938282
Short name T554
Test name
Test status
Simulation time 1405596591 ps
CPU time 34.77 seconds
Started May 26 01:24:20 PM PDT 24
Finished May 26 01:24:55 PM PDT 24
Peak memory 248716 kb
Host smart-19643d83-bed3-47e7-8ac8-b6319abd82d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88093
8282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.880938282
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3230453235
Short name T636
Test name
Test status
Simulation time 1669773080 ps
CPU time 14.83 seconds
Started May 26 01:24:21 PM PDT 24
Finished May 26 01:24:36 PM PDT 24
Peak memory 249132 kb
Host smart-6dc51432-17b3-4db8-bf4c-f000f44b46dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32304
53235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3230453235
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1333375875
Short name T448
Test name
Test status
Simulation time 256608157 ps
CPU time 16.58 seconds
Started May 26 01:24:20 PM PDT 24
Finished May 26 01:24:37 PM PDT 24
Peak memory 255976 kb
Host smart-21f7ef5e-a8d0-4f10-95e1-072b9db299e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
75875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1333375875
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3892517632
Short name T407
Test name
Test status
Simulation time 29887146 ps
CPU time 6.08 seconds
Started May 26 01:24:23 PM PDT 24
Finished May 26 01:24:29 PM PDT 24
Peak memory 240716 kb
Host smart-3a2bf963-3e8e-4e0b-a9e5-932b6e165943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
17632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3892517632
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2733825812
Short name T259
Test name
Test status
Simulation time 105605084587 ps
CPU time 2949.35 seconds
Started May 26 01:24:22 PM PDT 24
Finished May 26 02:13:32 PM PDT 24
Peak memory 289552 kb
Host smart-6c83c085-3e25-48e1-8acb-ca22dd267011
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733825812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2733825812
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2394262592
Short name T236
Test name
Test status
Simulation time 195857973020 ps
CPU time 3904.36 seconds
Started May 26 01:24:29 PM PDT 24
Finished May 26 02:29:35 PM PDT 24
Peak memory 330876 kb
Host smart-aba4c212-0056-4e0a-a07f-81a59eaacf5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394262592 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2394262592
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4075755221
Short name T204
Test name
Test status
Simulation time 28426860 ps
CPU time 2.23 seconds
Started May 26 01:22:28 PM PDT 24
Finished May 26 01:22:32 PM PDT 24
Peak memory 248864 kb
Host smart-b4299381-ff1c-4fc9-a211-2995da05ba1b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4075755221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4075755221
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3176376509
Short name T459
Test name
Test status
Simulation time 118066025677 ps
CPU time 801.61 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:35:50 PM PDT 24
Peak memory 267284 kb
Host smart-e7880632-ef94-4549-bf41-4350d446d9b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176376509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3176376509
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3123659690
Short name T445
Test name
Test status
Simulation time 324170615 ps
CPU time 17.03 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:22:42 PM PDT 24
Peak memory 240468 kb
Host smart-e8b14f71-17d8-43c3-bc48-9b0357940cdb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3123659690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3123659690
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3723409333
Short name T99
Test name
Test status
Simulation time 2559492224 ps
CPU time 71.26 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:23:36 PM PDT 24
Peak memory 254636 kb
Host smart-e5a1096f-508b-420e-9382-5c7d20915dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37234
09333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3723409333
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2734081476
Short name T362
Test name
Test status
Simulation time 281281648 ps
CPU time 28.91 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:57 PM PDT 24
Peak memory 248764 kb
Host smart-13bd92b7-ef3e-4374-96d6-7d8ac1ccc7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27340
81476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2734081476
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3149097647
Short name T551
Test name
Test status
Simulation time 92858307427 ps
CPU time 2655.99 seconds
Started May 26 01:22:22 PM PDT 24
Finished May 26 02:06:38 PM PDT 24
Peak memory 284160 kb
Host smart-9d3b44ca-56fb-45be-b7ba-4c9c71d5233b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149097647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3149097647
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.390022204
Short name T357
Test name
Test status
Simulation time 10304500375 ps
CPU time 993.62 seconds
Started May 26 01:22:22 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 273340 kb
Host smart-4846bbae-bdaa-4776-9e8b-c0e75f2c8852
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390022204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.390022204
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3105366823
Short name T333
Test name
Test status
Simulation time 5592548205 ps
CPU time 33.99 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:22:59 PM PDT 24
Peak memory 248748 kb
Host smart-9f02a855-e916-41d2-9815-8171c4b61af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31053
66823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3105366823
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3586312225
Short name T463
Test name
Test status
Simulation time 1157495906 ps
CPU time 31.26 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:23:01 PM PDT 24
Peak memory 248776 kb
Host smart-f585b804-5f4f-4585-b49c-8be1215a9332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35863
12225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3586312225
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.247770677
Short name T353
Test name
Test status
Simulation time 929250664 ps
CPU time 56.08 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:23:23 PM PDT 24
Peak memory 248692 kb
Host smart-c6daee9e-dbb7-4e7c-b118-fbabc4979d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24777
0677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.247770677
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.62420161
Short name T20
Test name
Test status
Simulation time 712797202 ps
CPU time 46.22 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 256036 kb
Host smart-43fadf49-299c-42b4-bc12-68fb6fb203a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62420
161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.62420161
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1137614682
Short name T263
Test name
Test status
Simulation time 59837194245 ps
CPU time 2159.25 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:58:26 PM PDT 24
Peak memory 288240 kb
Host smart-a76a9d15-6fec-4872-9c5f-56045d2d10ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137614682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1137614682
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2060207758
Short name T197
Test name
Test status
Simulation time 63730006 ps
CPU time 3.16 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:22:28 PM PDT 24
Peak memory 248856 kb
Host smart-bfb15ac5-8cb8-4131-8cc2-323a198d0035
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2060207758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2060207758
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2597183961
Short name T417
Test name
Test status
Simulation time 8762961796 ps
CPU time 978.71 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 289484 kb
Host smart-40aab3b1-7c6d-437a-8b98-6dfa274d06fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597183961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2597183961
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1145053000
Short name T440
Test name
Test status
Simulation time 577772113 ps
CPU time 24.04 seconds
Started May 26 01:22:23 PM PDT 24
Finished May 26 01:22:48 PM PDT 24
Peak memory 240480 kb
Host smart-9453cef6-6470-440e-85a7-b08da58665b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1145053000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1145053000
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2372959493
Short name T497
Test name
Test status
Simulation time 2773527832 ps
CPU time 173 seconds
Started May 26 01:22:22 PM PDT 24
Finished May 26 01:25:16 PM PDT 24
Peak memory 256964 kb
Host smart-0408a47f-0915-4115-972d-538f712e4380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
59493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2372959493
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2444719757
Short name T534
Test name
Test status
Simulation time 2237161939 ps
CPU time 45.05 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:23:14 PM PDT 24
Peak memory 255992 kb
Host smart-fe1c59fa-3ef6-4b1b-a650-eac58c454a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24447
19757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2444719757
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2855768116
Short name T213
Test name
Test status
Simulation time 74301666791 ps
CPU time 1077.74 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:40:23 PM PDT 24
Peak memory 265220 kb
Host smart-9a49725b-48cb-4fb9-8235-b1d23e9a1134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855768116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2855768116
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1819963566
Short name T450
Test name
Test status
Simulation time 166008894364 ps
CPU time 2813.18 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 02:09:19 PM PDT 24
Peak memory 281608 kb
Host smart-2bd3dcb7-0aae-4874-bdb9-7fd82d5c1a48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819963566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1819963566
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.307512617
Short name T456
Test name
Test status
Simulation time 4247501328 ps
CPU time 47.25 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 252592 kb
Host smart-fa104a03-2c98-455e-9a3a-1a38dde8c9c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307512617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.307512617
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3719447970
Short name T330
Test name
Test status
Simulation time 1967100882 ps
CPU time 15.52 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 248732 kb
Host smart-db8a4322-6697-4d0f-ae4a-7d85254394b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
47970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3719447970
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2429807512
Short name T487
Test name
Test status
Simulation time 3039768964 ps
CPU time 50.73 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 01:23:20 PM PDT 24
Peak memory 256176 kb
Host smart-16e48a79-f502-4839-929e-37ed44d6aba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24298
07512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2429807512
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2508082005
Short name T431
Test name
Test status
Simulation time 93211383 ps
CPU time 9.49 seconds
Started May 26 01:22:43 PM PDT 24
Finished May 26 01:22:55 PM PDT 24
Peak memory 249108 kb
Host smart-a6b5e84d-6020-4209-a356-ceff64b62896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25080
82005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2508082005
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2474626533
Short name T663
Test name
Test status
Simulation time 294519281003 ps
CPU time 4493.37 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 02:37:23 PM PDT 24
Peak memory 297296 kb
Host smart-5d8929be-e813-494f-9285-4d5aef54a487
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474626533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2474626533
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3574347963
Short name T238
Test name
Test status
Simulation time 61618054036 ps
CPU time 5727.78 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 02:57:55 PM PDT 24
Peak memory 346652 kb
Host smart-63546c38-97e7-4c82-8add-531f0170569c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574347963 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3574347963
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3494660733
Short name T203
Test name
Test status
Simulation time 42957259 ps
CPU time 2.13 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 01:22:40 PM PDT 24
Peak memory 248932 kb
Host smart-fc68cc7f-5f62-453d-90aa-b61201a6b4ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3494660733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3494660733
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2692589958
Short name T617
Test name
Test status
Simulation time 50357414742 ps
CPU time 1475.22 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:47:02 PM PDT 24
Peak memory 273216 kb
Host smart-5b62b8a9-4257-43b5-9d3d-f212b3ffda6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692589958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2692589958
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.4009806112
Short name T60
Test name
Test status
Simulation time 159032282 ps
CPU time 9.97 seconds
Started May 26 01:22:22 PM PDT 24
Finished May 26 01:22:32 PM PDT 24
Peak memory 248920 kb
Host smart-4c60586e-8b8c-4400-b3b4-72c7498f1b8b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4009806112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4009806112
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.895568989
Short name T626
Test name
Test status
Simulation time 2495162175 ps
CPU time 157.29 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:25:03 PM PDT 24
Peak memory 256860 kb
Host smart-c05ffe23-38c1-437e-b2a5-ea4f2d07bc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89556
8989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.895568989
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2426861463
Short name T583
Test name
Test status
Simulation time 284959114 ps
CPU time 25.01 seconds
Started May 26 01:22:22 PM PDT 24
Finished May 26 01:22:48 PM PDT 24
Peak memory 248740 kb
Host smart-ba5e1ecf-9161-46dc-988b-71702b82b705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24268
61463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2426861463
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2651742202
Short name T212
Test name
Test status
Simulation time 28298167259 ps
CPU time 1119.35 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:41:07 PM PDT 24
Peak memory 273300 kb
Host smart-042e514e-7e6b-4c63-898d-662d6d3a9054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651742202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2651742202
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.810488353
Short name T350
Test name
Test status
Simulation time 91254665195 ps
CPU time 1406.31 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:45:52 PM PDT 24
Peak memory 269392 kb
Host smart-4c59b453-a645-4abd-b52a-b3a01b2e15b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810488353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.810488353
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1762389550
Short name T288
Test name
Test status
Simulation time 51409834498 ps
CPU time 511.86 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:30:58 PM PDT 24
Peak memory 248156 kb
Host smart-5791d286-629d-45e0-8b06-e4598e66128d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762389550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1762389550
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2109615388
Short name T434
Test name
Test status
Simulation time 234708281 ps
CPU time 20.19 seconds
Started May 26 01:22:20 PM PDT 24
Finished May 26 01:22:40 PM PDT 24
Peak memory 248708 kb
Host smart-da730c9f-d6b8-4488-afbd-c1d0f5c4171c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21096
15388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2109615388
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.694632539
Short name T43
Test name
Test status
Simulation time 285575970 ps
CPU time 25.86 seconds
Started May 26 01:22:18 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 248840 kb
Host smart-26a8c21f-6dd9-485a-a374-0026c3cac1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69463
2539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.694632539
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1864820565
Short name T415
Test name
Test status
Simulation time 5899052336 ps
CPU time 45.63 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:23:12 PM PDT 24
Peak memory 256172 kb
Host smart-c2b994be-5ece-4eeb-bb7e-9675e2c29ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
20565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1864820565
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1915535394
Short name T578
Test name
Test status
Simulation time 6618979245 ps
CPU time 34.13 seconds
Started May 26 01:22:23 PM PDT 24
Finished May 26 01:22:58 PM PDT 24
Peak memory 248836 kb
Host smart-5ab533c5-b16d-428a-9cc9-372a93ad52ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19155
35394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1915535394
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1116944915
Short name T90
Test name
Test status
Simulation time 16105610360 ps
CPU time 62.01 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:23:27 PM PDT 24
Peak memory 256908 kb
Host smart-a5e739eb-552b-4a9d-8aca-ae1a08349713
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116944915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1116944915
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1703150763
Short name T201
Test name
Test status
Simulation time 17094440 ps
CPU time 2.74 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:22:34 PM PDT 24
Peak memory 248892 kb
Host smart-ff03119d-c482-43ef-9937-bffe225834ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1703150763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1703150763
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.708476602
Short name T705
Test name
Test status
Simulation time 53443617400 ps
CPU time 1366.81 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:45:15 PM PDT 24
Peak memory 281632 kb
Host smart-53757d2f-c2eb-4880-8a8e-681a95d4afc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708476602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.708476602
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1750786452
Short name T503
Test name
Test status
Simulation time 273910815 ps
CPU time 8.2 seconds
Started May 26 01:22:42 PM PDT 24
Finished May 26 01:22:52 PM PDT 24
Peak memory 248748 kb
Host smart-e98a5534-dc63-462a-84b7-d475ebd53d4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1750786452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1750786452
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3317193474
Short name T606
Test name
Test status
Simulation time 5418833231 ps
CPU time 92.37 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:24:00 PM PDT 24
Peak memory 256700 kb
Host smart-f0ca4d13-8ab1-4636-adbd-937cd0f4d446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
93474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3317193474
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3448080599
Short name T240
Test name
Test status
Simulation time 460011488 ps
CPU time 36.6 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:23:04 PM PDT 24
Peak memory 256020 kb
Host smart-a4294be2-58d7-4b37-8bc9-aafd43581581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34480
80599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3448080599
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.479262943
Short name T316
Test name
Test status
Simulation time 32515638488 ps
CPU time 1709.09 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:50:56 PM PDT 24
Peak memory 273412 kb
Host smart-e6b0c055-7127-4599-bf52-cced8baf761c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479262943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.479262943
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3146588084
Short name T386
Test name
Test status
Simulation time 366856720648 ps
CPU time 1713.11 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:51:05 PM PDT 24
Peak memory 289524 kb
Host smart-f20d8a74-1fcd-4499-9001-98844055051e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146588084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3146588084
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1898262051
Short name T64
Test name
Test status
Simulation time 16685461323 ps
CPU time 178.12 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:25:25 PM PDT 24
Peak memory 248036 kb
Host smart-df143378-cc4f-4878-8883-18384b60d467
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898262051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1898262051
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2920181708
Short name T349
Test name
Test status
Simulation time 2957257896 ps
CPU time 43.13 seconds
Started May 26 01:22:37 PM PDT 24
Finished May 26 01:23:21 PM PDT 24
Peak memory 256916 kb
Host smart-f35b0698-9be2-4f16-b956-1bb72e096bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
81708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2920181708
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1824686414
Short name T31
Test name
Test status
Simulation time 432540044 ps
CPU time 11.16 seconds
Started May 26 01:22:24 PM PDT 24
Finished May 26 01:22:37 PM PDT 24
Peak memory 255948 kb
Host smart-681d72d9-1c8d-478f-8e2a-e95227c051b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18246
86414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1824686414
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3309686639
Short name T74
Test name
Test status
Simulation time 313920140 ps
CPU time 18.75 seconds
Started May 26 01:22:37 PM PDT 24
Finished May 26 01:22:56 PM PDT 24
Peak memory 248692 kb
Host smart-38d320c3-2606-4e05-b3f8-110e963a0dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33096
86639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3309686639
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1633210330
Short name T21
Test name
Test status
Simulation time 331251542 ps
CPU time 17.71 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:22:44 PM PDT 24
Peak memory 248788 kb
Host smart-ee779bef-a0fd-416e-985c-b1219861fed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16332
10330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1633210330
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2436020212
Short name T604
Test name
Test status
Simulation time 741138568 ps
CPU time 55.62 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:23:27 PM PDT 24
Peak memory 255184 kb
Host smart-dbc779a9-f33f-4c43-bbf8-565ce60f9208
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436020212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2436020212
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2805087994
Short name T465
Test name
Test status
Simulation time 30877754109 ps
CPU time 2661.56 seconds
Started May 26 01:22:27 PM PDT 24
Finished May 26 02:06:51 PM PDT 24
Peak memory 289680 kb
Host smart-dce2fcbe-2009-4a9e-ba19-a58e5b025116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805087994 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2805087994
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2504186492
Short name T198
Test name
Test status
Simulation time 41862937 ps
CPU time 3.56 seconds
Started May 26 01:22:39 PM PDT 24
Finished May 26 01:22:44 PM PDT 24
Peak memory 249084 kb
Host smart-276d9b79-890b-4426-9424-44d4f66256a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2504186492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2504186492
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.171634766
Short name T505
Test name
Test status
Simulation time 163251003212 ps
CPU time 1812.51 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:52:44 PM PDT 24
Peak memory 273444 kb
Host smart-bedac2a6-3d48-4b4b-bfab-b4fd9357e67b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171634766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.171634766
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2837247804
Short name T580
Test name
Test status
Simulation time 694615226 ps
CPU time 10.31 seconds
Started May 26 01:22:35 PM PDT 24
Finished May 26 01:22:47 PM PDT 24
Peak memory 252392 kb
Host smart-fb33549f-6a96-47c1-a5f7-723020c72fe7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2837247804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2837247804
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3862467103
Short name T652
Test name
Test status
Simulation time 9484696083 ps
CPU time 127.64 seconds
Started May 26 01:22:25 PM PDT 24
Finished May 26 01:24:34 PM PDT 24
Peak memory 256920 kb
Host smart-059f11c0-2572-4809-927e-5511074ccb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
67103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3862467103
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.777175745
Short name T404
Test name
Test status
Simulation time 775265472 ps
CPU time 26.22 seconds
Started May 26 01:22:38 PM PDT 24
Finished May 26 01:23:05 PM PDT 24
Peak memory 248768 kb
Host smart-bf3d72fd-bbb5-4317-b7fe-671a8ab2535a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77717
5745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.777175745
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1414114161
Short name T302
Test name
Test status
Simulation time 327194543760 ps
CPU time 1325.34 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:44:38 PM PDT 24
Peak memory 284864 kb
Host smart-6ade6b88-4173-4463-9682-89af7cc8081e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414114161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1414114161
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3029593958
Short name T420
Test name
Test status
Simulation time 11810679432 ps
CPU time 1175.61 seconds
Started May 26 01:22:30 PM PDT 24
Finished May 26 01:42:08 PM PDT 24
Peak memory 289104 kb
Host smart-c5c5d39e-1e0b-4050-b19b-4ff9732d8ca9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029593958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3029593958
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.970440011
Short name T371
Test name
Test status
Simulation time 1709008496 ps
CPU time 44.72 seconds
Started May 26 01:22:37 PM PDT 24
Finished May 26 01:23:23 PM PDT 24
Peak memory 248676 kb
Host smart-83a51587-527d-4eb4-be45-ca5d1e0389a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97044
0011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.970440011
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1501529758
Short name T446
Test name
Test status
Simulation time 70242292 ps
CPU time 5.45 seconds
Started May 26 01:22:28 PM PDT 24
Finished May 26 01:22:36 PM PDT 24
Peak memory 247512 kb
Host smart-7731e21e-f986-4935-95db-d3b83a022939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15015
29758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1501529758
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3702454350
Short name T88
Test name
Test status
Simulation time 3826895472 ps
CPU time 61.64 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:23:30 PM PDT 24
Peak memory 248764 kb
Host smart-1c5c2af9-a189-48cd-9bc1-fef899a98a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37024
54350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3702454350
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2892028912
Short name T432
Test name
Test status
Simulation time 1217614202 ps
CPU time 16.78 seconds
Started May 26 01:22:26 PM PDT 24
Finished May 26 01:22:45 PM PDT 24
Peak memory 248708 kb
Host smart-73b24a82-4d9c-468e-a7e2-8e6480dfb359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28920
28912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2892028912
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1344914850
Short name T91
Test name
Test status
Simulation time 47871578255 ps
CPU time 1390.72 seconds
Started May 26 01:22:29 PM PDT 24
Finished May 26 01:45:42 PM PDT 24
Peak memory 288984 kb
Host smart-6a2a8405-88ad-4adc-a243-9e6a37bf77b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344914850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1344914850
Directory /workspace/9.alert_handler_stress_all/latest
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