Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	111182	1			T3	3		T6	2		T11	94
class_i[0x1]	71104	1			T1	4		T3	1		T6	4
class_i[0x2]	58004	1			T1	5		T3	6		T15	81
class_i[0x3]	39889	1			T3	27		T6	1		T7	7

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	72481	1			T1	3		T3	1		T15	17
alert[0x1]	68684	1			T1	1		T15	33		T7	6
alert[0x2]	69061	1			T3	20		T15	15		T6	1
alert[0x3]	69953	1			T1	5		T3	16		T15	16

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

279905

1

T1

5

T3

37

T15

81

esc_ping_fail

274

1

T1

4

T6

3

T7

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	72402	1			T1	2		T3	1		T15	17
esc_integrity_fail	alert[0x1]	68612	1			T15	33		T7	4		T11	1232
esc_integrity_fail	alert[0x2]	69006	1			T3	20		T15	15		T11	1142
esc_integrity_fail	alert[0x3]	69885	1			T1	3		T3	16		T15	16
esc_ping_fail	alert[0x0]	79	1			T1	1		T6	1		T239	1
esc_ping_fail	alert[0x1]	72	1			T1	1		T7	2		T239	1
esc_ping_fail	alert[0x2]	55	1			T6	1		T21	1		T239	1
esc_ping_fail	alert[0x3]	68	1			T1	2		T6	1		T7	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	111125	1			T3	3		T11	94		T14	10
esc_integrity_fail	class_i[0x1]	71063	1			T3	1		T6	4		T19	2529
esc_integrity_fail	class_i[0x2]	57911	1			T1	5		T3	6		T15	81
esc_integrity_fail	class_i[0x3]	39806	1			T3	27		T7	7		T19	17
esc_ping_fail	class_i[0x0]	57	1			T6	2		T297	6		T300	1
esc_ping_fail	class_i[0x1]	41	1			T1	4		T239	3		T101	2
esc_ping_fail	class_i[0x2]	93	1			T7	3		T21	1		T239	1
esc_ping_fail	class_i[0x3]	83	1			T6	1		T101	1		T105	2