Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	68	1			T18	1		T72	1		T42	2
class_index[0x1]	76	1			T3	1		T11	1		T18	1
class_index[0x2]	61	1			T75	1		T81	1		T48	1
class_index[0x3]	57	1			T59	1		T22	2		T75	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	101	1			T59	1		T18	1		T20	1
intr_timeout_cnt[1]	54	1			T43	1		T22	1		T77	1
intr_timeout_cnt[2]	21	1			T75	1		T79	1		T24	1
intr_timeout_cnt[3]	25	1			T11	1		T22	1		T45	1
intr_timeout_cnt[4]	21	1			T42	1		T45	1		T86	1
intr_timeout_cnt[5]	3	1			T72	1		T80	1		T107	1
intr_timeout_cnt[6]	9	1			T72	1		T24	1		T48	1
intr_timeout_cnt[7]	13	1			T18	1		T22	1		T80	1
intr_timeout_cnt[8]	9	1			T3	1		T90	1		T274	1
intr_timeout_cnt[9]	6	1			T22	1		T79	1		T107	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T18	1		T42	1		T74	1
class_index[0x0]	intr_timeout_cnt[1]	10	1			T75	1		T275	1		T54	1
class_index[0x0]	intr_timeout_cnt[2]	3	1			T276	1		T247	1		T277	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T226	1		T98	1		T278	1
class_index[0x0]	intr_timeout_cnt[4]	11	1			T42	1		T183	1		T247	2
class_index[0x0]	intr_timeout_cnt[5]	2	1			T72	1		T80	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T24	1		T279	1		T280	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T22	1		T281	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T89	1		T282	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T79	1		T107	1		T283	1
class_index[0x1]	intr_timeout_cnt[0]	34	1			T20	1		T78	2		T45	4
class_index[0x1]	intr_timeout_cnt[1]	13	1			T43	1		T77	1		T284	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T82	1		T285	1		T286	1
class_index[0x1]	intr_timeout_cnt[3]	10	1			T11	1		T22	1		T49	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T45	1		T287	1		T95	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T72	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T18	1		T86	1		T288	1
class_index[0x1]	intr_timeout_cnt[8]	5	1			T3	1		T289	1		T290	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T107	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	26	1			T81	1		T82	1		T97	2
class_index[0x2]	intr_timeout_cnt[1]	17	1			T49	1		T108	1		T99	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T75	1		T98	1		T291	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T180	2		T189	1		T292	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T89	2		T293	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T107	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	4	1			T48	1		T280	1		T290	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T289	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T90	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T246	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	15	1			T59	1		T117	1		T82	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T22	1		T75	1		T107	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T79	1		T24	1		T294	3
class_index[0x3]	intr_timeout_cnt[3]	5	1			T45	1		T49	1		T295	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T86	1		T98	2		T278	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T54	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	7	1			T80	1		T116	4		T89	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T274	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T22	1		-	-		-	-