Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361353	1			T1	31		T2	1997		T3	14
all_values[1]	361353	1			T1	31		T2	1997		T3	14
all_values[2]	361353	1			T1	31		T2	1997		T3	14
all_values[3]	361353	1			T1	31		T2	1997		T3	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

720137

1

T2

3968

T3

24

T4

2237

auto[1]

725275

1

T1

124

T2

4020

T3

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

861287

1

T1

106

T2

5833

T3

12

auto[1]

584125

1

T1

18

T2

2155

T3

44

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103495	1			T2	717		T3	1		T4	385
all_values[0]	auto[0]	auto[1]	76716	1			T2	268		T3	3		T4	133
all_values[0]	auto[1]	auto[0]	104337	1			T1	20		T2	754		T3	3
all_values[0]	auto[1]	auto[1]	76805	1			T1	11		T2	258		T3	7
all_values[1]	auto[0]	auto[0]	106961	1			T2	561		T3	2		T4	348
all_values[1]	auto[0]	auto[1]	72338	1			T2	435		T3	5		T4	217
all_values[1]	auto[1]	auto[0]	108891	1			T1	27		T2	554		T3	2
all_values[1]	auto[1]	auto[1]	73163	1			T1	4		T2	447		T3	5
all_values[2]	auto[0]	auto[0]	108523	1			T2	1008		T3	1		T4	605
all_values[2]	auto[0]	auto[1]	71725	1			T2	2		T3	8		T15	4
all_values[2]	auto[1]	auto[0]	109429	1			T1	28		T2	987		T3	1
all_values[2]	auto[1]	auto[1]	71676	1			T1	3		T3	4		T15	9
all_values[3]	auto[0]	auto[0]	109485	1			T2	622		T4	350		T15	7
all_values[3]	auto[0]	auto[1]	70894	1			T2	355		T3	4		T4	199
all_values[3]	auto[1]	auto[0]	110166	1			T1	31		T2	630		T3	2
all_values[3]	auto[1]	auto[1]	70808	1			T2	390		T3	8		T4	210