Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361353	1			T1	31		T2	1997		T3	14
all_pins[1]	361353	1			T1	31		T2	1997		T3	14
all_pins[2]	361353	1			T1	31		T2	1997		T3	14
all_pins[3]	361353	1			T1	31		T2	1997		T3	14

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1152960	1			T1	106		T2	6893		T3	32
values[0x1]	292452	1			T1	18		T2	1095		T3	24
transitions[0x0=>0x1]	194149	1			T1	14		T2	968		T3	12
transitions[0x1=>0x0]	194388	1			T1	15		T2	968		T3	13

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	284548	1			T1	20		T2	1739		T3	7
all_pins[0]	values[0x1]	76805	1			T1	11		T2	258		T3	7
all_pins[0]	transitions[0x0=>0x1]	76161	1			T1	10		T2	258		T3	2
all_pins[0]	transitions[0x1=>0x0]	70403	1			T2	390		T3	4		T4	210
all_pins[1]	values[0x0]	288190	1			T1	27		T2	1550		T3	9
all_pins[1]	values[0x1]	73163	1			T1	4		T2	447		T3	5
all_pins[1]	transitions[0x0=>0x1]	40044	1			T1	4		T2	320		T3	1
all_pins[1]	transitions[0x1=>0x0]	43686	1			T1	11		T2	131		T3	3
all_pins[2]	values[0x0]	289677	1			T1	28		T2	1997		T3	10
all_pins[2]	values[0x1]	71676	1			T1	3		T3	4		T15	9
all_pins[2]	transitions[0x0=>0x1]	39087	1			T3	3		T15	6		T16	3
all_pins[2]	transitions[0x1=>0x0]	40574	1			T1	1		T2	447		T3	4
all_pins[3]	values[0x0]	290545	1			T1	31		T2	1607		T3	6
all_pins[3]	values[0x1]	70808	1			T2	390		T3	8		T4	210
all_pins[3]	transitions[0x0=>0x1]	38857	1			T2	390		T3	6		T4	210
all_pins[3]	transitions[0x1=>0x0]	39725	1			T1	3		T3	2		T15	5