Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T159	4		T230	7		T232	4
all_values[1]	269	1			T159	4		T230	7		T232	4
all_values[2]	269	1			T159	4		T230	7		T232	4
all_values[3]	269	1			T159	4		T230	7		T232	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571

1

T159

9

T230

11

T232

9

auto[1]

505

1

T159

7

T230

17

T232

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

436

1

T159

4

T230

10

T232

7

auto[1]

640

1

T159

12

T230

18

T232

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

627

1

T159

7

T230

12

T232

11

auto[1]

449

1

T159

9

T230

16

T232

5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

61

1

T159

1

T230

1

T232

1

all_values[0]

auto[0]

auto[0]

auto[1]

26

1

T159

2

T344

1

T345

1

all_values[0]

auto[0]

auto[1]

auto[0]

50

1

T230

1

T232

3

T231

1

all_values[0]

auto[0]

auto[1]

auto[1]

28

1

T231

1

T344

1

T346

1

all_values[0]

auto[1]

auto[0]

auto[1]

46

1

T159

1

T230

3

T344

2

all_values[0]

auto[1]

auto[1]

auto[1]

58

1

T230

2

T231

1

T344

1

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T159

1

T230

1

T232

2

all_values[1]

auto[0]

auto[0]

auto[1]

16

1

T347

1

T344

1

T346

1

all_values[1]

auto[0]

auto[1]

auto[0]

49

1

T230

4

T232

1

T231

4

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T348

1

T349

1

T350

3

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T159

2

T230

2

T347

1

all_values[1]

auto[1]

auto[1]

auto[1]

50

1

T159

1

T232

1

T344

3

all_values[2]

auto[0]

auto[0]

auto[0]

52

1

T230

1

T347

1

T231

1

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T230

1

T232

2

T344

1

all_values[2]

auto[0]

auto[1]

auto[0]

55

1

T231

1

T351

1

T352

1

all_values[2]

auto[0]

auto[1]

auto[1]

19

1

T159

1

T347

1

T231

1

all_values[2]

auto[1]

auto[0]

auto[1]

54

1

T159

1

T344

1

T345

2

all_values[2]

auto[1]

auto[1]

auto[1]

60

1

T159

2

T230

5

T232

2

all_values[3]

auto[0]

auto[0]

auto[0]

70

1

T159

1

T230

1

T347

1

all_values[3]

auto[0]

auto[0]

auto[1]

23

1

T232

2

T345

1

T346

1

all_values[3]

auto[0]

auto[1]

auto[0]

38

1

T159

1

T230

1

T344

1

all_values[3]

auto[0]

auto[1]

auto[1]

22

1

T230

1

T347

2

T344

1

all_values[3]

auto[1]

auto[0]

auto[1]

68

1

T230

1

T232

2

T344

1

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T159

2

T230

3

T347

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal