Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82557	1			T5	545		T11	985		T12	353
accum_cnt_1000	235739	1			T4	627		T5	525		T11	1786
accum_cnt_100	29395	1			T4	92		T15	4		T16	2
accum_cnt_50	74025	1			T3	13		T4	69		T15	5
accum_cnt_10	189700	1			T1	14		T2	1463		T3	27
accum_cnt_0	411798	1			T1	94		T2	4429		T3	48

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	266272	1			T1	27		T2	1473		T3	22
class_index[0x1]	266272	1			T1	27		T2	1473		T3	22
class_index[0x2]	266272	1			T1	27		T2	1473		T3	22
class_index[0x3]	266272	1			T1	27		T2	1473		T3	22

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	17881	1			T14	136		T18	1318		T25	76
class_index[0x0]	accum_cnt_1000	57197	1			T11	199		T12	694		T13	757
class_index[0x0]	accum_cnt_100	8647	1			T11	25		T12	43		T13	170
class_index[0x0]	accum_cnt_50	18095	1			T11	66		T12	39		T13	109
class_index[0x0]	accum_cnt_10	62589	1			T1	14		T2	1462		T4	800
class_index[0x0]	accum_cnt_0	89060	1			T1	13		T2	11		T3	22
class_index[0x1]	accum_cnt_2000	22153	1			T11	354		T19	261		T18	286
class_index[0x1]	accum_cnt_1000	62834	1			T11	1038		T13	881		T19	224
class_index[0x1]	accum_cnt_100	7230	1			T15	4		T11	76		T13	89
class_index[0x1]	accum_cnt_50	17225	1			T15	4		T16	13		T11	63
class_index[0x1]	accum_cnt_10	36595	1			T2	1		T3	22		T4	800
class_index[0x1]	accum_cnt_0	109363	1			T1	27		T2	1472		T4	8
class_index[0x2]	accum_cnt_2000	21646	1			T5	545		T12	353		T18	331
class_index[0x2]	accum_cnt_1000	59817	1			T5	525		T12	396		T13	766
class_index[0x2]	accum_cnt_100	7159	1			T16	2		T5	38		T12	25
class_index[0x2]	accum_cnt_50	20217	1			T3	13		T16	16		T5	27
class_index[0x2]	accum_cnt_10	43148	1			T3	5		T16	6		T6	8
class_index[0x2]	accum_cnt_0	105991	1			T1	27		T2	1473		T3	4
class_index[0x3]	accum_cnt_2000	20877	1			T11	631		T83	497		T43	431
class_index[0x3]	accum_cnt_1000	55891	1			T4	627		T11	549		T14	625
class_index[0x3]	accum_cnt_100	6359	1			T4	92		T11	26		T14	53
class_index[0x3]	accum_cnt_50	18488	1			T4	69		T15	1		T26	4
class_index[0x3]	accum_cnt_10	47368	1			T4	10		T15	11		T7	19
class_index[0x3]	accum_cnt_0	107384	1			T1	27		T2	1473		T3	22