Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	10630	1			T3	2		T6	1		T19	2
alert[0x1]	8341	1			T1	1		T7	1		T11	2
alert[0x2]	6559	1			T1	1		T11	13		T61	19
alert[0x3]	8497	1			T7	1		T19	22		T61	1
alert[0x4]	14798	1			T1	1		T19	39		T18	5
alert[0x5]	6370	1			T7	1		T18	137		T62	3
alert[0x6]	11552	1			T20	760		T43	6158		T234	13
alert[0x7]	2948	1			T15	1		T18	4		T236	1
alert[0x8]	3051	1			T14	318		T19	61		T18	5
alert[0x9]	4870	1			T7	1		T14	1540		T73	2
alert[0xa]	6443	1			T19	190		T18	270		T74	4
alert[0xb]	7433	1			T18	134		T62	6		T43	175
alert[0xc]	5992	1			T3	2		T18	9		T61	3
alert[0xd]	5081	1			T14	93		T19	44		T25	120
alert[0xe]	3791	1			T7	1		T18	87		T20	2
alert[0xf]	9052	1			T61	39		T20	3		T25	6
alert[0x10]	7696	1			T20	163		T43	459		T22	99
alert[0x11]	12355	1			T15	28		T6	1		T14	157
alert[0x12]	13535	1			T11	7		T19	168		T72	1
alert[0x13]	4567	1			T15	1		T20	61		T25	81
alert[0x14]	4518	1			T20	759		T74	19		T22	12
alert[0x15]	3957	1			T1	1		T14	13		T19	11
alert[0x16]	3320	1			T2	1		T19	78		T20	15
alert[0x17]	3816	1			T19	379		T18	13		T61	146
alert[0x18]	3551	1			T14	4		T19	355		T25	58
alert[0x19]	10501	1			T1	1		T15	33		T18	3
alert[0x1a]	7042	1			T1	1		T19	214		T62	17
alert[0x1b]	12101	1			T14	2227		T19	184		T25	42
alert[0x1c]	13600	1			T11	1		T13	1		T18	6
alert[0x1d]	4076	1			T15	1		T11	1		T234	1
alert[0x1e]	5373	1			T14	13		T72	4		T297	1
alert[0x1f]	3889	1			T15	1		T19	124		T18	829
alert[0x20]	4144	1			T18	274		T62	4		T20	120
alert[0x21]	13694	1			T70	1		T102	1		T48	168
alert[0x22]	9147	1			T6	1		T20	711		T25	6
alert[0x23]	5859	1			T15	7		T61	34		T25	109
alert[0x24]	1296	1			T62	2		T74	57		T22	3
alert[0x25]	1878	1			T18	16		T61	3		T25	10
alert[0x26]	6968	1			T15	1		T7	1		T14	46
alert[0x27]	2627	1			T18	35		T21	1		T74	8
alert[0x28]	4891	1			T19	45		T18	105		T20	1
alert[0x29]	13617	1			T7	1		T20	983		T25	20
alert[0x2a]	15146	1			T7	2		T14	87		T19	85
alert[0x2b]	2636	1			T7	1		T20	304		T25	69
alert[0x2c]	2894	1			T15	4		T14	191		T18	285
alert[0x2d]	5152	1			T3	4		T14	28		T18	226
alert[0x2e]	2352	1			T1	1		T15	1		T6	1
alert[0x2f]	3119	1			T1	3		T2	2		T18	98
alert[0x30]	3628	1			T1	1		T4	1		T25	7
alert[0x31]	3409	1			T3	1		T15	2		T43	32
alert[0x32]	3694	1			T7	2		T11	13		T25	22
alert[0x33]	10206	1			T25	102		T43	36		T79	3
alert[0x34]	3566	1			T18	12		T25	116		T72	1
alert[0x35]	4594	1			T14	103		T18	43		T25	3
alert[0x36]	4254	1			T20	94		T25	56		T22	2
alert[0x37]	8815	1			T19	45		T20	3145		T25	72
alert[0x38]	4432	1			T14	63		T20	140		T25	90
alert[0x39]	11979	1			T18	19		T20	109		T43	5
alert[0x3a]	9733	1			T25	187		T22	17		T70	1
alert[0x3b]	6753	1			T20	146		T25	502		T43	90
alert[0x3c]	4404	1			T14	23		T20	71		T25	93
alert[0x3d]	6291	1			T15	1		T11	4		T14	26
alert[0x3e]	4339	1			T15	2		T11	5		T18	25
alert[0x3f]	5560	1			T3	1		T14	128		T19	858
alert[0x40]	2882	1			T7	1		T25	18		T43	14

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	114999	1			T1	11		T2	3		T15	1
class_i[0x1]	106184	1			T3	6		T4	1		T15	82
class_i[0x2]	98141	1			T6	1		T13	1		T14	7
class_i[0x3]	103940	1			T3	4		T7	13		T11	46

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

422579

1

T3

10

T15

83

T11

46

alert_ping_fail

685

1

T1

11

T2

3

T4

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	10622	1			T3	2		T19	2		T20	18
alert_integrity_fail	alert[0x1]	8327	1			T11	2		T18	14		T62	46
alert_integrity_fail	alert[0x2]	6547	1			T11	13		T61	19		T62	31
alert_integrity_fail	alert[0x3]	8489	1			T19	22		T61	1		T20	15
alert_integrity_fail	alert[0x4]	14790	1			T19	39		T18	5		T25	7
alert_integrity_fail	alert[0x5]	6356	1			T18	137		T62	3		T20	207
alert_integrity_fail	alert[0x6]	11542	1			T20	760		T43	6158		T234	13
alert_integrity_fail	alert[0x7]	2931	1			T15	1		T18	4		T22	5
alert_integrity_fail	alert[0x8]	3040	1			T14	318		T19	61		T18	5
alert_integrity_fail	alert[0x9]	4858	1			T14	1540		T73	2		T80	3
alert_integrity_fail	alert[0xa]	6432	1			T19	190		T18	270		T74	4
alert_integrity_fail	alert[0xb]	7423	1			T18	134		T62	6		T43	175
alert_integrity_fail	alert[0xc]	5983	1			T3	2		T18	9		T61	3
alert_integrity_fail	alert[0xd]	5064	1			T14	93		T19	44		T25	120
alert_integrity_fail	alert[0xe]	3781	1			T18	87		T20	2		T25	468
alert_integrity_fail	alert[0xf]	9043	1			T61	39		T20	3		T25	6
alert_integrity_fail	alert[0x10]	7690	1			T20	163		T43	459		T22	99
alert_integrity_fail	alert[0x11]	12346	1			T15	28		T14	157		T18	511
alert_integrity_fail	alert[0x12]	13528	1			T11	7		T19	168		T72	1
alert_integrity_fail	alert[0x13]	4556	1			T15	1		T20	61		T25	81
alert_integrity_fail	alert[0x14]	4500	1			T20	759		T74	19		T22	12
alert_integrity_fail	alert[0x15]	3946	1			T14	13		T19	11		T18	5
alert_integrity_fail	alert[0x16]	3309	1			T19	78		T20	15		T25	20
alert_integrity_fail	alert[0x17]	3807	1			T19	379		T18	13		T61	146
alert_integrity_fail	alert[0x18]	3542	1			T14	4		T19	355		T25	58
alert_integrity_fail	alert[0x19]	10495	1			T15	33		T18	3		T20	564
alert_integrity_fail	alert[0x1a]	7031	1			T19	214		T62	17		T20	425
alert_integrity_fail	alert[0x1b]	12094	1			T14	2227		T19	184		T25	42
alert_integrity_fail	alert[0x1c]	13589	1			T11	1		T18	6		T62	46
alert_integrity_fail	alert[0x1d]	4058	1			T15	1		T11	1		T234	1
alert_integrity_fail	alert[0x1e]	5364	1			T14	13		T72	4		T48	419
alert_integrity_fail	alert[0x1f]	3874	1			T15	1		T19	124		T18	829
alert_integrity_fail	alert[0x20]	4130	1			T18	274		T62	4		T20	120
alert_integrity_fail	alert[0x21]	13684	1			T48	168		T49	43		T274	1
alert_integrity_fail	alert[0x22]	9134	1			T20	711		T25	6		T43	2945
alert_integrity_fail	alert[0x23]	5848	1			T15	7		T61	34		T25	109
alert_integrity_fail	alert[0x24]	1292	1			T62	2		T74	57		T22	3
alert_integrity_fail	alert[0x25]	1867	1			T18	16		T61	3		T25	10
alert_integrity_fail	alert[0x26]	6956	1			T15	1		T14	46		T18	79
alert_integrity_fail	alert[0x27]	2615	1			T18	35		T74	8		T84	95
alert_integrity_fail	alert[0x28]	4879	1			T19	45		T18	105		T20	1
alert_integrity_fail	alert[0x29]	13603	1			T20	983		T25	20		T43	696
alert_integrity_fail	alert[0x2a]	15132	1			T14	87		T19	85		T25	17
alert_integrity_fail	alert[0x2b]	2625	1			T20	304		T25	69		T43	1135
alert_integrity_fail	alert[0x2c]	2880	1			T15	4		T14	191		T18	285
alert_integrity_fail	alert[0x2d]	5138	1			T3	4		T14	28		T18	226
alert_integrity_fail	alert[0x2e]	2337	1			T15	1		T61	1		T77	3
alert_integrity_fail	alert[0x2f]	3103	1			T18	98		T61	3		T25	15
alert_integrity_fail	alert[0x30]	3614	1			T25	7		T43	56		T22	6
alert_integrity_fail	alert[0x31]	3401	1			T3	1		T15	2		T43	32
alert_integrity_fail	alert[0x32]	3683	1			T11	13		T25	22		T22	2
alert_integrity_fail	alert[0x33]	10201	1			T25	102		T43	36		T79	3
alert_integrity_fail	alert[0x34]	3558	1			T18	12		T25	116		T72	1
alert_integrity_fail	alert[0x35]	4583	1			T14	103		T18	43		T25	3
alert_integrity_fail	alert[0x36]	4246	1			T20	94		T25	56		T22	2
alert_integrity_fail	alert[0x37]	8807	1			T19	45		T20	3145		T25	72
alert_integrity_fail	alert[0x38]	4429	1			T14	63		T20	140		T25	90
alert_integrity_fail	alert[0x39]	11972	1			T18	19		T20	109		T43	5
alert_integrity_fail	alert[0x3a]	9722	1			T25	187		T22	17		T24	10
alert_integrity_fail	alert[0x3b]	6740	1			T20	146		T25	502		T43	90
alert_integrity_fail	alert[0x3c]	4398	1			T14	23		T20	71		T25	93
alert_integrity_fail	alert[0x3d]	6282	1			T15	1		T11	4		T14	26
alert_integrity_fail	alert[0x3e]	4329	1			T15	2		T11	5		T18	25
alert_integrity_fail	alert[0x3f]	5557	1			T3	1		T14	128		T19	858
alert_integrity_fail	alert[0x40]	2877	1			T25	18		T43	14		T45	4
alert_ping_fail	alert[0x0]	8	1			T6	1		T239	1		T298	1
alert_ping_fail	alert[0x1]	14	1			T1	1		T7	1		T70	1
alert_ping_fail	alert[0x2]	12	1			T1	1		T299	1		T298	1
alert_ping_fail	alert[0x3]	8	1			T7	1		T300	1		T301	1
alert_ping_fail	alert[0x4]	8	1			T1	1		T70	1		T102	1
alert_ping_fail	alert[0x5]	14	1			T7	1		T236	1		T102	1
alert_ping_fail	alert[0x6]	10	1			T298	1		T302	1		T303	1
alert_ping_fail	alert[0x7]	17	1			T236	1		T239	1		T70	1
alert_ping_fail	alert[0x8]	11	1			T239	1		T301	2		T304	1
alert_ping_fail	alert[0x9]	12	1			T7	1		T299	1		T31	1
alert_ping_fail	alert[0xa]	11	1			T70	1		T305	1		T306	1
alert_ping_fail	alert[0xb]	10	1			T70	1		T297	1		T299	1
alert_ping_fail	alert[0xc]	9	1			T299	1		T306	2		T307	1
alert_ping_fail	alert[0xd]	17	1			T101	1		T102	2		T297	1
alert_ping_fail	alert[0xe]	10	1			T7	1		T31	1		T308	2
alert_ping_fail	alert[0xf]	9	1			T102	1		T105	1		T298	1
alert_ping_fail	alert[0x10]	6	1			T70	1		T105	1		T304	1
alert_ping_fail	alert[0x11]	9	1			T6	1		T299	1		T305	1
alert_ping_fail	alert[0x12]	7	1			T21	2		T298	1		T306	1
alert_ping_fail	alert[0x13]	11	1			T102	2		T299	1		T298	1
alert_ping_fail	alert[0x14]	18	1			T102	1		T105	2		T298	1
alert_ping_fail	alert[0x15]	11	1			T1	1		T299	1		T305	1
alert_ping_fail	alert[0x16]	11	1			T2	1		T297	1		T301	1
alert_ping_fail	alert[0x17]	9	1			T300	2		T309	1		T310	1
alert_ping_fail	alert[0x18]	9	1			T105	1		T306	1		T300	1
alert_ping_fail	alert[0x19]	6	1			T1	1		T101	1		T105	1
alert_ping_fail	alert[0x1a]	11	1			T1	1		T102	1		T298	1
alert_ping_fail	alert[0x1b]	7	1			T311	1		T312	3		T313	2
alert_ping_fail	alert[0x1c]	11	1			T13	1		T102	1		T186	1
alert_ping_fail	alert[0x1d]	18	1			T314	1		T315	1		T301	1
alert_ping_fail	alert[0x1e]	9	1			T297	1		T305	1		T314	1
alert_ping_fail	alert[0x1f]	15	1			T101	1		T316	2		T307	1
alert_ping_fail	alert[0x20]	14	1			T101	2		T305	1		T317	1
alert_ping_fail	alert[0x21]	10	1			T70	1		T102	1		T301	2
alert_ping_fail	alert[0x22]	13	1			T6	1		T101	1		T102	1
alert_ping_fail	alert[0x23]	11	1			T239	1		T105	1		T314	1
alert_ping_fail	alert[0x24]	4	1			T308	1		T310	1		T318	1
alert_ping_fail	alert[0x25]	11	1			T297	1		T305	1		T319	1
alert_ping_fail	alert[0x26]	12	1			T7	1		T70	1		T102	1
alert_ping_fail	alert[0x27]	12	1			T21	1		T102	1		T314	1
alert_ping_fail	alert[0x28]	12	1			T70	1		T102	1		T320	1
alert_ping_fail	alert[0x29]	14	1			T7	1		T70	1		T105	1
alert_ping_fail	alert[0x2a]	14	1			T7	2		T299	1		T304	1
alert_ping_fail	alert[0x2b]	11	1			T7	1		T321	1		T304	1
alert_ping_fail	alert[0x2c]	14	1			T305	1		T306	1		T300	2
alert_ping_fail	alert[0x2d]	14	1			T102	1		T298	1		T306	1
alert_ping_fail	alert[0x2e]	15	1			T1	1		T6	1		T70	1
alert_ping_fail	alert[0x2f]	16	1			T1	3		T2	2		T297	1
alert_ping_fail	alert[0x30]	14	1			T1	1		T4	1		T299	1
alert_ping_fail	alert[0x31]	8	1			T297	1		T299	1		T314	1
alert_ping_fail	alert[0x32]	11	1			T7	2		T305	1		T301	1
alert_ping_fail	alert[0x33]	5	1			T297	1		T322	1		T312	1
alert_ping_fail	alert[0x34]	8	1			T323	1		T271	1		T318	1
alert_ping_fail	alert[0x35]	11	1			T306	2		T300	1		T314	1
alert_ping_fail	alert[0x36]	8	1			T101	1		T297	1		T323	1
alert_ping_fail	alert[0x37]	8	1			T70	1		T105	1		T305	1
alert_ping_fail	alert[0x38]	3	1			T186	1		T322	1		T318	1
alert_ping_fail	alert[0x39]	7	1			T70	1		T297	1		T324	1
alert_ping_fail	alert[0x3a]	11	1			T70	1		T101	2		T305	1
alert_ping_fail	alert[0x3b]	13	1			T102	1		T105	1		T298	1
alert_ping_fail	alert[0x3c]	6	1			T102	1		T105	1		T297	1
alert_ping_fail	alert[0x3d]	9	1			T321	1		T301	1		T323	2
alert_ping_fail	alert[0x3e]	10	1			T21	1		T105	1		T299	1
alert_ping_fail	alert[0x3f]	3	1			T320	1		T325	1		T326	1
alert_ping_fail	alert[0x40]	5	1			T7	1		T299	1		T317	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	114813	1			T15	1		T14	5053		T18	1907
alert_integrity_fail	class_i[0x1]	105986	1			T3	6		T15	82		T19	18
alert_integrity_fail	class_i[0x2]	97994	1			T14	7		T19	2884		T18	1338
alert_integrity_fail	class_i[0x3]	103786	1			T3	4		T11	46		T19	2
alert_ping_fail	class_i[0x0]	186	1			T1	11		T2	3		T6	2
alert_ping_fail	class_i[0x1]	198	1			T4	1		T6	1		T21	2
alert_ping_fail	class_i[0x2]	147	1			T6	1		T13	1		T101	3
alert_ping_fail	class_i[0x3]	154	1			T7	13		T21	2		T239	2