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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.67 99.99 98.72 100.00 100.00 100.00 99.38 99.60


Total test records in report: 833
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T773 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1119454712 May 28 01:46:17 PM PDT 24 May 28 01:46:48 PM PDT 24 540032916 ps
T774 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1542545045 May 28 01:44:16 PM PDT 24 May 28 01:44:24 PM PDT 24 1510856508 ps
T775 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.270001075 May 28 01:44:32 PM PDT 24 May 28 01:44:35 PM PDT 24 9557470 ps
T776 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2133282975 May 28 01:46:14 PM PDT 24 May 28 01:48:24 PM PDT 24 6685955231 ps
T141 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3243846463 May 28 01:44:17 PM PDT 24 May 28 01:48:00 PM PDT 24 6471676107 ps
T777 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.594676841 May 28 01:44:18 PM PDT 24 May 28 01:44:21 PM PDT 24 7510677 ps
T176 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2563238374 May 28 01:44:17 PM PDT 24 May 28 01:44:44 PM PDT 24 156133561 ps
T154 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1889125418 May 28 01:44:17 PM PDT 24 May 28 01:49:34 PM PDT 24 17236002673 ps
T168 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4101271143 May 28 01:44:15 PM PDT 24 May 28 01:44:21 PM PDT 24 116554917 ps
T778 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3576316565 May 28 01:44:33 PM PDT 24 May 28 01:44:36 PM PDT 24 7670357 ps
T133 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2772153994 May 28 01:44:17 PM PDT 24 May 28 01:54:35 PM PDT 24 4314349516 ps
T779 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2204831151 May 28 01:44:20 PM PDT 24 May 28 01:44:47 PM PDT 24 257874428 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2470960330 May 28 01:46:16 PM PDT 24 May 28 01:46:58 PM PDT 24 191564538 ps
T781 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.888457960 May 28 01:44:29 PM PDT 24 May 28 01:44:32 PM PDT 24 19965394 ps
T782 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.286360443 May 28 01:44:19 PM PDT 24 May 28 01:44:49 PM PDT 24 357010897 ps
T174 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1772775490 May 28 01:46:12 PM PDT 24 May 28 01:46:52 PM PDT 24 245567962 ps
T783 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2015350173 May 28 01:44:16 PM PDT 24 May 28 01:44:27 PM PDT 24 206721067 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.217118157 May 28 01:44:18 PM PDT 24 May 28 01:44:38 PM PDT 24 425963427 ps
T785 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1269193036 May 28 01:44:17 PM PDT 24 May 28 01:44:29 PM PDT 24 66983011 ps
T786 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4275622210 May 28 01:44:29 PM PDT 24 May 28 01:44:32 PM PDT 24 11643788 ps
T787 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1103027820 May 28 01:44:29 PM PDT 24 May 28 01:44:33 PM PDT 24 10729706 ps
T788 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4088915117 May 28 01:44:29 PM PDT 24 May 28 01:44:33 PM PDT 24 9592879 ps
T789 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.416041211 May 28 01:44:32 PM PDT 24 May 28 01:44:37 PM PDT 24 213923833 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1694401777 May 28 01:44:17 PM PDT 24 May 28 01:44:33 PM PDT 24 573828696 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3919301940 May 28 01:46:17 PM PDT 24 May 28 01:46:43 PM PDT 24 119877690 ps
T792 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1763724662 May 28 01:44:20 PM PDT 24 May 28 01:44:24 PM PDT 24 10435433 ps
T793 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2818285275 May 28 01:44:32 PM PDT 24 May 28 01:44:35 PM PDT 24 21506155 ps
T794 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.910427153 May 28 01:46:15 PM PDT 24 May 28 01:46:42 PM PDT 24 129027311 ps
T167 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3485195525 May 28 01:44:19 PM PDT 24 May 28 01:45:03 PM PDT 24 2382966966 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.924973553 May 28 01:46:02 PM PDT 24 May 28 01:46:17 PM PDT 24 166039446 ps
T796 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.641789108 May 28 01:46:20 PM PDT 24 May 28 01:46:52 PM PDT 24 187087807 ps
T150 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1974842868 May 28 01:44:19 PM PDT 24 May 28 01:47:22 PM PDT 24 25666695268 ps
T797 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1539434353 May 28 01:44:19 PM PDT 24 May 28 01:44:34 PM PDT 24 760776276 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1167161350 May 28 01:44:19 PM PDT 24 May 28 01:44:32 PM PDT 24 82157407 ps
T799 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4160202278 May 28 01:44:31 PM PDT 24 May 28 01:44:35 PM PDT 24 57647216 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1017511603 May 28 01:46:15 PM PDT 24 May 28 01:46:41 PM PDT 24 648602746 ps
T801 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3091266845 May 28 01:44:20 PM PDT 24 May 28 01:44:30 PM PDT 24 102726668 ps
T802 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.46656934 May 28 01:44:29 PM PDT 24 May 28 01:44:33 PM PDT 24 10486640 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2143120523 May 28 01:44:28 PM PDT 24 May 28 01:44:41 PM PDT 24 893725152 ps
T804 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1705891280 May 28 01:44:15 PM PDT 24 May 28 01:44:21 PM PDT 24 178667094 ps
T172 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.154596029 May 28 01:46:14 PM PDT 24 May 28 01:46:38 PM PDT 24 63748299 ps
T805 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.84225165 May 28 01:44:19 PM PDT 24 May 28 01:44:23 PM PDT 24 6743671 ps
T806 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.862208527 May 28 01:46:16 PM PDT 24 May 28 01:49:02 PM PDT 24 2255795534 ps
T807 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.251540008 May 28 01:44:18 PM PDT 24 May 28 01:44:32 PM PDT 24 503357831 ps
T143 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1209285208 May 28 01:44:33 PM PDT 24 May 28 01:48:10 PM PDT 24 7160636255 ps
T171 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2094440643 May 28 01:46:15 PM PDT 24 May 28 01:47:18 PM PDT 24 2478214559 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.315416744 May 28 01:44:22 PM PDT 24 May 28 01:44:33 PM PDT 24 62546830 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.527237085 May 28 01:44:22 PM PDT 24 May 28 01:44:32 PM PDT 24 52099339 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2359401848 May 28 01:46:14 PM PDT 24 May 28 01:46:46 PM PDT 24 259623264 ps
T811 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3861526183 May 28 01:46:21 PM PDT 24 May 28 01:46:45 PM PDT 24 63541308 ps
T812 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2739354769 May 28 01:44:14 PM PDT 24 May 28 01:44:25 PM PDT 24 672642621 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2485906834 May 28 01:46:03 PM PDT 24 May 28 01:46:21 PM PDT 24 58155556 ps
T151 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3849115715 May 28 01:44:14 PM PDT 24 May 28 01:49:34 PM PDT 24 11262903420 ps
T814 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3409944654 May 28 01:46:17 PM PDT 24 May 28 01:46:46 PM PDT 24 533582872 ps
T815 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4077903383 May 28 01:46:20 PM PDT 24 May 28 01:46:41 PM PDT 24 26704315 ps
T816 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3655299062 May 28 01:44:14 PM PDT 24 May 28 01:44:21 PM PDT 24 64293144 ps
T166 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2617460014 May 28 01:44:30 PM PDT 24 May 28 01:44:36 PM PDT 24 801232592 ps
T817 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2982945865 May 28 01:44:29 PM PDT 24 May 28 01:44:33 PM PDT 24 11767546 ps
T818 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3854797857 May 28 01:44:29 PM PDT 24 May 28 01:44:37 PM PDT 24 181215985 ps
T152 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2578642037 May 28 01:44:16 PM PDT 24 May 28 01:46:02 PM PDT 24 3018874373 ps
T358 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.786381106 May 28 01:44:18 PM PDT 24 May 28 01:52:10 PM PDT 24 7832705606 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2407353199 May 28 01:44:18 PM PDT 24 May 28 01:45:35 PM PDT 24 1198992735 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4034620311 May 28 01:46:10 PM PDT 24 May 28 01:46:32 PM PDT 24 19986970 ps
T820 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3413597303 May 28 01:44:20 PM PDT 24 May 28 01:44:37 PM PDT 24 224247842 ps
T821 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1032127675 May 28 01:44:16 PM PDT 24 May 28 01:44:23 PM PDT 24 53580967 ps
T161 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4149249356 May 28 01:45:36 PM PDT 24 May 28 01:47:01 PM PDT 24 4774775952 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3274431347 May 28 01:46:16 PM PDT 24 May 28 01:46:42 PM PDT 24 169320384 ps
T823 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2937650118 May 28 01:45:22 PM PDT 24 May 28 01:45:33 PM PDT 24 222275389 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1413727167 May 28 01:46:10 PM PDT 24 May 28 01:46:53 PM PDT 24 184825560 ps
T825 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2733658295 May 28 01:46:16 PM PDT 24 May 28 01:52:37 PM PDT 24 5702552907 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2375444842 May 28 01:44:33 PM PDT 24 May 28 01:44:43 PM PDT 24 589795461 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2284515965 May 28 01:46:10 PM PDT 24 May 28 01:46:40 PM PDT 24 166987668 ps
T828 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1088811604 May 28 01:44:31 PM PDT 24 May 28 01:44:58 PM PDT 24 184686738 ps
T829 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3858816520 May 28 01:46:18 PM PDT 24 May 28 01:46:41 PM PDT 24 8381417 ps
T169 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1509024354 May 28 01:44:15 PM PDT 24 May 28 01:44:19 PM PDT 24 72994458 ps
T830 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.717642142 May 28 01:44:20 PM PDT 24 May 28 01:49:37 PM PDT 24 17902143739 ps
T357 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.674203295 May 28 01:44:20 PM PDT 24 May 28 01:52:08 PM PDT 24 6331816915 ps
T153 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3046373573 May 28 01:44:18 PM PDT 24 May 28 02:02:05 PM PDT 24 16579627086 ps
T356 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3640629104 May 28 01:46:13 PM PDT 24 May 28 01:56:06 PM PDT 24 23752435598 ps
T831 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.245586572 May 28 01:44:17 PM PDT 24 May 28 01:44:20 PM PDT 24 14175073 ps
T832 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2984772600 May 28 01:46:15 PM PDT 24 May 28 01:57:17 PM PDT 24 9915372283 ps
T833 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1453563128 May 28 01:46:13 PM PDT 24 May 28 01:47:16 PM PDT 24 2340234853 ps
T164 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1386173631 May 28 01:46:16 PM PDT 24 May 28 01:46:59 PM PDT 24 287269276 ps

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3174045267
Short name T15
Test name
Test status
Simulation time 4188206397 ps
CPU time 37.66 seconds
Started May 28 02:01:01 PM PDT 24
Finished May 28 02:01:42 PM PDT 24
Peak memory 255208 kb
Host smart-bd2ade7d-ca0b-46c8-bf0a-9d420fa915d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31740
45267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3174045267
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3695638643
Short name T18
Test name
Test status
Simulation time 163166947092 ps
CPU time 9748.34 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 04:42:05 PM PDT 24
Peak memory 387168 kb
Host smart-99f9e4bd-ef57-48d2-a0fe-b049d39f5ba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695638643 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3695638643
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1978178229
Short name T5
Test name
Test status
Simulation time 460149911708 ps
CPU time 1940.66 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:32:17 PM PDT 24
Peak memory 281612 kb
Host smart-483318fe-8266-4011-a36d-b5b0fea05387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978178229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1978178229
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.732465114
Short name T8
Test name
Test status
Simulation time 2252484670 ps
CPU time 11.35 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 01:58:27 PM PDT 24
Peak memory 278700 kb
Host smart-16bad17a-e7c3-443f-8f2d-1c29eebb114a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=732465114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.732465114
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3799131487
Short name T122
Test name
Test status
Simulation time 18028367138 ps
CPU time 1170.6 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 02:06:06 PM PDT 24
Peak memory 265084 kb
Host smart-1b4faa32-4ecf-469c-b9bd-7f332cca1833
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799131487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3799131487
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.4019684112
Short name T48
Test name
Test status
Simulation time 56231389180 ps
CPU time 2767.46 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 02:44:40 PM PDT 24
Peak memory 289308 kb
Host smart-9e102aec-5134-4c40-b5e7-997adde91d7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019684112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.4019684112
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2364969084
Short name T20
Test name
Test status
Simulation time 209860303795 ps
CPU time 6481.19 seconds
Started May 28 02:00:25 PM PDT 24
Finished May 28 03:48:31 PM PDT 24
Peak memory 349060 kb
Host smart-ec6b37e8-fa17-49cd-8cd8-53e8c2409067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364969084 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2364969084
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1792771465
Short name T177
Test name
Test status
Simulation time 1698967756 ps
CPU time 61.55 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:45:19 PM PDT 24
Peak memory 239380 kb
Host smart-120398ab-3747-403c-a649-550a2cc7ed67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1792771465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1792771465
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2222971984
Short name T579
Test name
Test status
Simulation time 242671763250 ps
CPU time 6433.05 seconds
Started May 28 01:59:02 PM PDT 24
Finished May 28 03:46:17 PM PDT 24
Peak memory 354968 kb
Host smart-66725ff7-e6c8-43fd-9bba-1df676624ee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222971984 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2222971984
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3402951009
Short name T24
Test name
Test status
Simulation time 90630774431 ps
CPU time 5444.34 seconds
Started May 28 01:58:48 PM PDT 24
Finished May 28 03:29:35 PM PDT 24
Peak memory 370836 kb
Host smart-2eb9f1a2-5597-49d1-8e68-5b06a6ee6452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402951009 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3402951009
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3083528219
Short name T236
Test name
Test status
Simulation time 558570265277 ps
CPU time 2712.04 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:45:51 PM PDT 24
Peak memory 289020 kb
Host smart-c1cf2b4a-0ef7-4cc3-93c5-3b8ae1e244db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083528219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3083528219
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.524201543
Short name T137
Test name
Test status
Simulation time 4757749457 ps
CPU time 298.59 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:51:32 PM PDT 24
Peak memory 265388 kb
Host smart-26d9e3d4-f9e9-4cb6-84a8-e4bf227d1f62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=524201543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.524201543
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1631096335
Short name T246
Test name
Test status
Simulation time 149834535365 ps
CPU time 3564.59 seconds
Started May 28 02:01:09 PM PDT 24
Finished May 28 03:00:36 PM PDT 24
Peak memory 339100 kb
Host smart-ba49ab3d-c101-455c-a6b4-a2522490d3ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631096335 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1631096335
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1169757932
Short name T233
Test name
Test status
Simulation time 168735597 ps
CPU time 9.57 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 248756 kb
Host smart-ce8a1e5c-ced8-4038-84a5-97f9e24619b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1169757932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1169757932
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2810063591
Short name T126
Test name
Test status
Simulation time 48034046391 ps
CPU time 929.29 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 02:02:02 PM PDT 24
Peak memory 265032 kb
Host smart-99d906fc-559e-42fc-a071-c90ca784f7fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810063591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2810063591
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3637273693
Short name T120
Test name
Test status
Simulation time 48368271347 ps
CPU time 856.73 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 02:00:53 PM PDT 24
Peak memory 265020 kb
Host smart-f3210c56-0b7f-4796-92c2-b9fe29081f95
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637273693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3637273693
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1809796222
Short name T13
Test name
Test status
Simulation time 67075439446 ps
CPU time 1922.6 seconds
Started May 28 02:01:02 PM PDT 24
Finished May 28 02:33:09 PM PDT 24
Peak memory 282724 kb
Host smart-fc46ec76-9942-465b-a67f-a778a664f156
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809796222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1809796222
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2486575957
Short name T344
Test name
Test status
Simulation time 10514835 ps
CPU time 1.56 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:17 PM PDT 24
Peak memory 236616 kb
Host smart-c1944f6b-9123-4dde-872e-8442ac594ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2486575957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2486575957
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1619695473
Short name T131
Test name
Test status
Simulation time 6427668107 ps
CPU time 204.68 seconds
Started May 28 01:46:09 PM PDT 24
Finished May 28 01:49:52 PM PDT 24
Peak memory 265128 kb
Host smart-66ee3a04-5e07-4f51-a5b7-da9315510906
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1619695473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1619695473
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1381743064
Short name T297
Test name
Test status
Simulation time 22490220775 ps
CPU time 478.63 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 02:06:03 PM PDT 24
Peak memory 248356 kb
Host smart-3505e770-2d8f-447e-93d9-84f82c5014ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381743064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1381743064
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1884236071
Short name T22
Test name
Test status
Simulation time 64691876709 ps
CPU time 4177.99 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 03:10:06 PM PDT 24
Peak memory 306284 kb
Host smart-69532330-396e-46c6-824e-251f8328eca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884236071 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1884236071
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2956519658
Short name T111
Test name
Test status
Simulation time 160010456833 ps
CPU time 2314.62 seconds
Started May 28 01:59:19 PM PDT 24
Finished May 28 02:37:55 PM PDT 24
Peak memory 286728 kb
Host smart-f14dd6ca-a51b-476f-98fa-d7d90e588245
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956519658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2956519658
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2990060810
Short name T121
Test name
Test status
Simulation time 6047328069 ps
CPU time 196.29 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:47:39 PM PDT 24
Peak memory 265288 kb
Host smart-8afb3262-ac47-498f-a846-11177fef6c75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2990060810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2990060810
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4264219190
Short name T298
Test name
Test status
Simulation time 9038491760 ps
CPU time 383.98 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:06:22 PM PDT 24
Peak memory 248136 kb
Host smart-c4e01fca-02a8-470d-9d61-2ea8237538b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264219190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4264219190
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.363718036
Short name T7
Test name
Test status
Simulation time 13902150948 ps
CPU time 296.02 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:04:20 PM PDT 24
Peak memory 248020 kb
Host smart-f2df2ba0-ea30-4b45-93fb-1b84c9cb4b72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363718036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.363718036
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1974842868
Short name T150
Test name
Test status
Simulation time 25666695268 ps
CPU time 179.63 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:47:22 PM PDT 24
Peak memory 270364 kb
Host smart-f8839bd2-543c-4d96-9165-c24852357d3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1974842868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1974842868
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3489210604
Short name T337
Test name
Test status
Simulation time 58819800636 ps
CPU time 3210.6 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 02:52:21 PM PDT 24
Peak memory 289180 kb
Host smart-402fd269-3d99-428f-abc8-f2fad8a78a3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489210604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3489210604
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2153322756
Short name T98
Test name
Test status
Simulation time 48954972128 ps
CPU time 1084.93 seconds
Started May 28 01:57:55 PM PDT 24
Finished May 28 02:16:01 PM PDT 24
Peak memory 273212 kb
Host smart-b6c0a337-cb60-4861-b031-55b665cea715
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153322756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2153322756
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2083910692
Short name T323
Test name
Test status
Simulation time 66167100789 ps
CPU time 668.67 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 02:09:37 PM PDT 24
Peak memory 247100 kb
Host smart-06321727-a6ae-40c7-a05f-c8f56a9fb622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083910692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2083910692
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3046373573
Short name T153
Test name
Test status
Simulation time 16579627086 ps
CPU time 1063.79 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 02:02:05 PM PDT 24
Peak memory 273316 kb
Host smart-a04a41e5-fe95-4451-9694-acc104460274
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046373573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3046373573
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3598299829
Short name T307
Test name
Test status
Simulation time 154258992812 ps
CPU time 2452.68 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 02:39:30 PM PDT 24
Peak memory 281612 kb
Host smart-049923f2-cd2b-451d-a30c-1569329f0128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598299829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3598299829
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.198263140
Short name T116
Test name
Test status
Simulation time 46225026668 ps
CPU time 2498.4 seconds
Started May 28 01:59:03 PM PDT 24
Finished May 28 02:40:43 PM PDT 24
Peak memory 289400 kb
Host smart-2d04a892-dea0-46cc-9395-6ff9e5eba365
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198263140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.198263140
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.575086065
Short name T105
Test name
Test status
Simulation time 41377396261 ps
CPU time 427.48 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 02:05:55 PM PDT 24
Peak memory 247876 kb
Host smart-9a31f421-235e-49ce-b9ee-5fad33fb355b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575086065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.575086065
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3050226326
Short name T145
Test name
Test status
Simulation time 4342347051 ps
CPU time 310.67 seconds
Started May 28 01:44:33 PM PDT 24
Finished May 28 01:49:45 PM PDT 24
Peak memory 269296 kb
Host smart-66db0234-aee2-4ac6-bcee-e508e129d9fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3050226326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3050226326
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.755375707
Short name T61
Test name
Test status
Simulation time 3079499761 ps
CPU time 54.87 seconds
Started May 28 01:58:38 PM PDT 24
Finished May 28 01:59:34 PM PDT 24
Peak memory 248568 kb
Host smart-9e92cdb1-328b-49ad-973c-5f12f16218e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75537
5707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.755375707
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.823566264
Short name T107
Test name
Test status
Simulation time 1570943567 ps
CPU time 22.64 seconds
Started May 28 01:58:04 PM PDT 24
Finished May 28 01:58:30 PM PDT 24
Peak memory 255960 kb
Host smart-417ee03d-d865-45f7-bc78-25ad9a654f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82356
6264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.823566264
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2743015805
Short name T4
Test name
Test status
Simulation time 40045613439 ps
CPU time 967.99 seconds
Started May 28 01:58:17 PM PDT 24
Finished May 28 02:14:26 PM PDT 24
Peak memory 267440 kb
Host smart-ecf7635f-b572-4ff4-b42d-e1709d39abf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743015805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2743015805
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.432930149
Short name T9
Test name
Test status
Simulation time 547968856 ps
CPU time 11.08 seconds
Started May 28 01:57:52 PM PDT 24
Finished May 28 01:58:05 PM PDT 24
Peak memory 270256 kb
Host smart-49dcb27d-9df3-4eab-a8e1-9908faa6faa0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=432930149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.432930149
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.29576751
Short name T348
Test name
Test status
Simulation time 7251417 ps
CPU time 1.46 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 236572 kb
Host smart-51fbbad2-8774-4db9-ab7e-a8dbadab3538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=29576751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.29576751
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3240261883
Short name T89
Test name
Test status
Simulation time 106424190102 ps
CPU time 3451.3 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:57:30 PM PDT 24
Peak memory 299048 kb
Host smart-ea0d7f36-1ed5-4c76-b3c6-5120631e96ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240261883 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3240261883
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1378251134
Short name T310
Test name
Test status
Simulation time 8953529288 ps
CPU time 397.82 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:07:42 PM PDT 24
Peak memory 247892 kb
Host smart-33d68c5c-7d19-43bd-b743-1b8f5741b655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378251134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1378251134
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.62889841
Short name T45
Test name
Test status
Simulation time 40453137883 ps
CPU time 2652.87 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:44:12 PM PDT 24
Peak memory 289588 kb
Host smart-3655312b-08b8-4012-870b-7d15364ddec7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62889841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_hand
ler_stress_all.62889841
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3081755429
Short name T196
Test name
Test status
Simulation time 34189958 ps
CPU time 5.14 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:46:36 PM PDT 24
Peak memory 235632 kb
Host smart-2a5e4b36-808b-494a-8ea2-035d01fba9dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3081755429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3081755429
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3640629104
Short name T356
Test name
Test status
Simulation time 23752435598 ps
CPU time 572.58 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:56:06 PM PDT 24
Peak memory 273240 kb
Host smart-1fb76d16-aa83-47a8-9666-5556af721b7b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640629104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3640629104
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.982197400
Short name T320
Test name
Test status
Simulation time 40877808020 ps
CPU time 218.54 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 02:02:08 PM PDT 24
Peak memory 254796 kb
Host smart-cba1b008-ceeb-4db1-aa5e-6daf44a9d342
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982197400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.982197400
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3201752690
Short name T56
Test name
Test status
Simulation time 56477045715 ps
CPU time 2498.14 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:41:51 PM PDT 24
Peak memory 305484 kb
Host smart-112b2ba0-cb49-46eb-ac39-eb51cfc2fdfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201752690 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3201752690
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3327813719
Short name T609
Test name
Test status
Simulation time 150195057575 ps
CPU time 1883.76 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:31:40 PM PDT 24
Peak memory 272868 kb
Host smart-c2a60a76-f6ec-4d2b-8189-0fc9b62b26a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327813719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3327813719
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2070204167
Short name T72
Test name
Test status
Simulation time 1541120275 ps
CPU time 26.16 seconds
Started May 28 01:58:36 PM PDT 24
Finished May 28 01:59:04 PM PDT 24
Peak memory 248772 kb
Host smart-5a71bade-4567-4589-8c17-e16b3a2b7c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
04167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2070204167
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.989384731
Short name T147
Test name
Test status
Simulation time 48364706737 ps
CPU time 1004.23 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 02:03:19 PM PDT 24
Peak memory 265104 kb
Host smart-8d969c7c-c7c8-4898-9aac-afdd9d92e524
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989384731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.989384731
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.562102477
Short name T208
Test name
Test status
Simulation time 20279982 ps
CPU time 2.52 seconds
Started May 28 01:57:51 PM PDT 24
Finished May 28 01:57:55 PM PDT 24
Peak memory 248804 kb
Host smart-078b5093-0076-4ad3-a077-4ef9f5753321
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=562102477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.562102477
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2826551955
Short name T206
Test name
Test status
Simulation time 44866658 ps
CPU time 3.73 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:07 PM PDT 24
Peak memory 248940 kb
Host smart-170fc39e-985c-40b8-9cab-2d77c3284891
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2826551955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2826551955
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1732048863
Short name T213
Test name
Test status
Simulation time 16407230 ps
CPU time 2.42 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 01:58:35 PM PDT 24
Peak memory 248932 kb
Host smart-07b6e551-79d7-4109-ab0a-696f1726fb75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1732048863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1732048863
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3470633432
Short name T220
Test name
Test status
Simulation time 22744317 ps
CPU time 2.2 seconds
Started May 28 01:58:41 PM PDT 24
Finished May 28 01:58:45 PM PDT 24
Peak memory 248952 kb
Host smart-7713bdb7-88de-4ad1-8494-70f8d53f4b05
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3470633432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3470633432
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3849115715
Short name T151
Test name
Test status
Simulation time 11262903420 ps
CPU time 317.93 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 265076 kb
Host smart-9fa69bad-8dba-4aee-8167-4e25b3393a3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3849115715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3849115715
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2958979480
Short name T54
Test name
Test status
Simulation time 213525862308 ps
CPU time 3148.08 seconds
Started May 28 01:58:39 PM PDT 24
Finished May 28 02:51:08 PM PDT 24
Peak memory 289352 kb
Host smart-039aa568-ba1b-423e-8982-0f2165e73717
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958979480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2958979480
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.321220992
Short name T335
Test name
Test status
Simulation time 26306045694 ps
CPU time 1473.86 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 02:23:23 PM PDT 24
Peak memory 273344 kb
Host smart-ee448c25-d70a-4dc7-a966-e69d36722418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321220992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.321220992
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2783135351
Short name T648
Test name
Test status
Simulation time 42306449314 ps
CPU time 2490.05 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:41:06 PM PDT 24
Peak memory 305656 kb
Host smart-b6ca26c8-a00e-44d8-8daf-7c83291adcc6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783135351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2783135351
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3550596213
Short name T292
Test name
Test status
Simulation time 52268648223 ps
CPU time 2622.95 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:43:19 PM PDT 24
Peak memory 289876 kb
Host smart-11b05d0b-fab1-4cb5-b47e-517d7bb62ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550596213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3550596213
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1064118158
Short name T318
Test name
Test status
Simulation time 30004503001 ps
CPU time 590.66 seconds
Started May 28 02:00:28 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 247868 kb
Host smart-1cb5646b-725b-48d0-b1f4-9aa0dc864ae9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064118158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1064118158
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1514297484
Short name T46
Test name
Test status
Simulation time 21013091184 ps
CPU time 349.28 seconds
Started May 28 01:58:12 PM PDT 24
Finished May 28 02:04:02 PM PDT 24
Peak memory 253272 kb
Host smart-0edebd44-0025-4dd1-8bdb-ef4f3c959f1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514297484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1514297484
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1958872066
Short name T247
Test name
Test status
Simulation time 66697583517 ps
CPU time 6225.84 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 03:44:37 PM PDT 24
Peak memory 346964 kb
Host smart-5f04f53a-5c1e-4c90-ab2a-f154d854428a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958872066 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1958872066
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1708306325
Short name T77
Test name
Test status
Simulation time 48301901948 ps
CPU time 2444.9 seconds
Started May 28 01:59:44 PM PDT 24
Finished May 28 02:40:31 PM PDT 24
Peak memory 288996 kb
Host smart-9a52d6fd-ef3a-4f8c-9530-8fc5987be950
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708306325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1708306325
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3986342125
Short name T312
Test name
Test status
Simulation time 16673508176 ps
CPU time 728.96 seconds
Started May 28 01:58:37 PM PDT 24
Finished May 28 02:10:48 PM PDT 24
Peak memory 254648 kb
Host smart-2bc58c0a-723f-4d80-ae43-a70e9867ccb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986342125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3986342125
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2740627577
Short name T162
Test name
Test status
Simulation time 134117225 ps
CPU time 6.3 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 236380 kb
Host smart-5a1c7d98-84fe-4845-8dd8-572fe606eb60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2740627577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2740627577
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1209285208
Short name T143
Test name
Test status
Simulation time 7160636255 ps
CPU time 216.05 seconds
Started May 28 01:44:33 PM PDT 24
Finished May 28 01:48:10 PM PDT 24
Peak memory 273236 kb
Host smart-56742d70-5f67-4e23-81d2-6a2d68f49051
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1209285208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1209285208
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2240055744
Short name T351
Test name
Test status
Simulation time 8944212 ps
CPU time 1.3 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 234640 kb
Host smart-989c632b-7193-4474-95a1-e023989e7a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2240055744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2240055744
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1353529285
Short name T53
Test name
Test status
Simulation time 133966222863 ps
CPU time 1646.64 seconds
Started May 28 01:59:02 PM PDT 24
Finished May 28 02:26:30 PM PDT 24
Peak memory 273404 kb
Host smart-e41371c5-aab5-4d99-8efe-b94c0cc9ce6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353529285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1353529285
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3940354867
Short name T115
Test name
Test status
Simulation time 79100322186 ps
CPU time 2215.93 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:36:20 PM PDT 24
Peak memory 288448 kb
Host smart-198aacf0-1a06-458a-9b7d-1971d3164d48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940354867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3940354867
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.822602163
Short name T339
Test name
Test status
Simulation time 37501944933 ps
CPU time 2084.13 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:34:21 PM PDT 24
Peak memory 285492 kb
Host smart-b121d3ae-636a-4032-8a98-ed7aa5f6511e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822602163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.822602163
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.675013485
Short name T256
Test name
Test status
Simulation time 7244295884 ps
CPU time 128.52 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:01:44 PM PDT 24
Peak memory 256992 kb
Host smart-30e8ce44-9a8f-4fce-bf0c-288f3bb4247a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67501
3485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.675013485
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1261986188
Short name T90
Test name
Test status
Simulation time 105333778094 ps
CPU time 528.64 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:09:03 PM PDT 24
Peak memory 256960 kb
Host smart-fc60e6dc-f2fc-41d1-9320-a92216f1abba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261986188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1261986188
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4148625431
Short name T289
Test name
Test status
Simulation time 138269286034 ps
CPU time 2045.61 seconds
Started May 28 02:01:42 PM PDT 24
Finished May 28 02:35:49 PM PDT 24
Peak memory 289160 kb
Host smart-6ed98e60-bf55-40cf-baa0-12973f9a07e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148625431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4148625431
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2478094709
Short name T274
Test name
Test status
Simulation time 713125138 ps
CPU time 19.12 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 01:58:35 PM PDT 24
Peak memory 254868 kb
Host smart-27e50a90-490e-41cc-b4e1-eb7ccab60e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24780
94709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2478094709
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3286369105
Short name T93
Test name
Test status
Simulation time 52043304962 ps
CPU time 963.1 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 02:14:52 PM PDT 24
Peak memory 273088 kb
Host smart-c41fb464-3f7c-4f8a-baeb-96b2247ff6ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286369105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3286369105
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4149249356
Short name T161
Test name
Test status
Simulation time 4774775952 ps
CPU time 84.08 seconds
Started May 28 01:45:36 PM PDT 24
Finished May 28 01:47:01 PM PDT 24
Peak memory 239516 kb
Host smart-1a1f5744-9281-4a60-a495-f90d80ad699f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4149249356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4149249356
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2407353199
Short name T165
Test name
Test status
Simulation time 1198992735 ps
CPU time 74.34 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:45:35 PM PDT 24
Peak memory 239436 kb
Host smart-87939b15-133b-4522-9825-c4cf8360521f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2407353199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2407353199
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4101271143
Short name T168
Test name
Test status
Simulation time 116554917 ps
CPU time 4.58 seconds
Started May 28 01:44:15 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 236588 kb
Host smart-5b1efb9b-72a7-4d8c-bb6c-6cb7234e0e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4101271143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4101271143
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1386173631
Short name T164
Test name
Test status
Simulation time 287269276 ps
CPU time 21.99 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:59 PM PDT 24
Peak memory 240068 kb
Host smart-c562a184-edc0-42cf-a65d-f0e382aefc08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1386173631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1386173631
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2582970985
Short name T135
Test name
Test status
Simulation time 15932708594 ps
CPU time 216.24 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:50:08 PM PDT 24
Peak memory 265148 kb
Host smart-fd36f09e-3afa-4775-8aee-9266b03d3be0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2582970985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2582970985
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3485195525
Short name T167
Test name
Test status
Simulation time 2382966966 ps
CPU time 41.33 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:45:03 PM PDT 24
Peak memory 236772 kb
Host smart-7b9ee56b-22a0-44c0-ba66-edb965d06e91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3485195525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3485195525
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1816313028
Short name T157
Test name
Test status
Simulation time 212314798 ps
CPU time 4.46 seconds
Started May 28 01:44:30 PM PDT 24
Finished May 28 01:44:36 PM PDT 24
Peak memory 236624 kb
Host smart-6f356170-3df8-4484-aea0-8c57fc92c6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1816313028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1816313028
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.154596029
Short name T172
Test name
Test status
Simulation time 63748299 ps
CPU time 4.3 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:38 PM PDT 24
Peak memory 236664 kb
Host smart-014432ad-2aff-4421-8580-e0408c44768a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=154596029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.154596029
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1301480686
Short name T163
Test name
Test status
Simulation time 231790517 ps
CPU time 4.42 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 236428 kb
Host smart-27fc56b8-0f21-453e-a3d6-5b39f5046633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1301480686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1301480686
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2563238374
Short name T176
Test name
Test status
Simulation time 156133561 ps
CPU time 25.06 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:44:44 PM PDT 24
Peak memory 244896 kb
Host smart-faeb8f00-64dc-4984-958d-1891cc0e7ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2563238374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2563238374
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1772775490
Short name T174
Test name
Test status
Simulation time 245567962 ps
CPU time 20.53 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:52 PM PDT 24
Peak memory 240124 kb
Host smart-592b1a88-f7ae-461f-b0f3-08563f0ae783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1772775490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1772775490
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2094440643
Short name T171
Test name
Test status
Simulation time 2478214559 ps
CPU time 41.85 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:47:18 PM PDT 24
Peak memory 244740 kb
Host smart-9e8012a3-1f56-41cd-a334-4887e26e15a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2094440643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2094440643
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1509024354
Short name T169
Test name
Test status
Simulation time 72994458 ps
CPU time 3 seconds
Started May 28 01:44:15 PM PDT 24
Finished May 28 01:44:19 PM PDT 24
Peak memory 236588 kb
Host smart-55fa8eeb-c7e8-4a62-a51a-eb102fddf1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1509024354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1509024354
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.727909820
Short name T170
Test name
Test status
Simulation time 1103370267 ps
CPU time 37.91 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:45:00 PM PDT 24
Peak memory 240124 kb
Host smart-d651b4e2-8242-43b2-8433-7e2b0791e9f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=727909820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.727909820
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2617460014
Short name T166
Test name
Test status
Simulation time 801232592 ps
CPU time 3.44 seconds
Started May 28 01:44:30 PM PDT 24
Finished May 28 01:44:36 PM PDT 24
Peak memory 236376 kb
Host smart-836c81bd-cba7-4074-8d47-8183d0fe7482
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2617460014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2617460014
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2381546740
Short name T155
Test name
Test status
Simulation time 155560147 ps
CPU time 5.91 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 236628 kb
Host smart-cd96ca56-82e6-455d-968d-98843a36307a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2381546740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2381546740
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4197495892
Short name T156
Test name
Test status
Simulation time 93518958 ps
CPU time 3.63 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:19 PM PDT 24
Peak memory 236588 kb
Host smart-35f461aa-c1a6-4eff-b8ea-8736c1b75f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4197495892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4197495892
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1866869469
Short name T19
Test name
Test status
Simulation time 59379925579 ps
CPU time 1700.52 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 02:26:26 PM PDT 24
Peak memory 266320 kb
Host smart-f124d7dc-19d8-43a8-a6f9-ad3e7c399f5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866869469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1866869469
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1668731585
Short name T191
Test name
Test status
Simulation time 4195681498 ps
CPU time 241.14 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:50:34 PM PDT 24
Peak memory 240312 kb
Host smart-d6dfcc40-a320-411a-a055-9b4045b9c6e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1668731585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1668731585
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1130235945
Short name T768
Test name
Test status
Simulation time 18420403711 ps
CPU time 364.43 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:50:38 PM PDT 24
Peak memory 236636 kb
Host smart-f00dd4c4-06c2-46fe-8bbc-5350c35be09a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1130235945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1130235945
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3919301940
Short name T791
Test name
Test status
Simulation time 119877690 ps
CPU time 5.47 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:46:43 PM PDT 24
Peak memory 240072 kb
Host smart-9798457f-0bd4-4073-8fc5-14e709aca5bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3919301940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3919301940
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.865172745
Short name T175
Test name
Test status
Simulation time 130466935 ps
CPU time 11.63 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 250512 kb
Host smart-650b695a-21e7-44c4-ac33-cb7c169a4088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865172745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.865172745
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2450071672
Short name T345
Test name
Test status
Simulation time 9310248 ps
CPU time 1.54 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:33 PM PDT 24
Peak memory 236576 kb
Host smart-27d0bccd-63f6-403c-b692-33ee1727955b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2450071672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2450071672
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2347717172
Short name T198
Test name
Test status
Simulation time 1290436374 ps
CPU time 36.09 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:47:10 PM PDT 24
Peak memory 248316 kb
Host smart-e7deb8d9-4f3f-4c57-a975-9faa4485e879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2347717172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2347717172
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2921193210
Short name T123
Test name
Test status
Simulation time 10430648173 ps
CPU time 161.34 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:46:38 PM PDT 24
Peak memory 265132 kb
Host smart-aa3e47c1-550b-4dbf-bffd-5a853fa375a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2921193210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2921193210
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3520746709
Short name T142
Test name
Test status
Simulation time 30851153581 ps
CPU time 453.22 seconds
Started May 28 01:43:54 PM PDT 24
Finished May 28 01:51:30 PM PDT 24
Peak memory 267616 kb
Host smart-51f99218-b9c9-4345-8223-1ee798550857
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520746709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3520746709
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.673420635
Short name T729
Test name
Test status
Simulation time 3309972401 ps
CPU time 17.02 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:50 PM PDT 24
Peak memory 253212 kb
Host smart-cbda2d5a-228c-4025-bab8-55dbbb927c47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=673420635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.673420635
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2133282975
Short name T776
Test name
Test status
Simulation time 6685955231 ps
CPU time 109.54 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:48:24 PM PDT 24
Peak memory 240136 kb
Host smart-2a8d6e03-15b2-41cb-8692-c8c6b6e6b3e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2133282975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2133282975
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2733658295
Short name T825
Test name
Test status
Simulation time 5702552907 ps
CPU time 360.63 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:52:37 PM PDT 24
Peak memory 236600 kb
Host smart-4919ef46-71f4-4359-8cab-e28df2215345
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2733658295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2733658295
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1017511603
Short name T800
Test name
Test status
Simulation time 648602746 ps
CPU time 5.41 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 240004 kb
Host smart-1f20ae30-5fdf-43d0-9f4b-1962083a39f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1017511603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1017511603
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.910427153
Short name T794
Test name
Test status
Simulation time 129027311 ps
CPU time 5.85 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 240280 kb
Host smart-e3b7c8df-774a-4de0-8c15-15eef6221ee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910427153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.910427153
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3274431347
Short name T822
Test name
Test status
Simulation time 169320384 ps
CPU time 4.68 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 235512 kb
Host smart-e184b824-a78a-45fb-bef6-5e5630dc3faa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3274431347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3274431347
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3350115826
Short name T765
Test name
Test status
Simulation time 11138248 ps
CPU time 1.52 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:38 PM PDT 24
Peak memory 236488 kb
Host smart-735dbb8a-7ccc-431a-a9da-c6dbc9d95359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3350115826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3350115826
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1119454712
Short name T773
Test name
Test status
Simulation time 540032916 ps
CPU time 10.35 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:46:48 PM PDT 24
Peak memory 243788 kb
Host smart-5f9ab062-1ca5-4315-b6e3-5f67dae119ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1119454712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1119454712
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1077846111
Short name T761
Test name
Test status
Simulation time 395172945 ps
CPU time 23.65 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:47:00 PM PDT 24
Peak memory 247752 kb
Host smart-0138752b-e626-4852-a4be-6023d5140d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077846111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1077846111
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3303652127
Short name T354
Test name
Test status
Simulation time 65487171 ps
CPU time 5.11 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:28 PM PDT 24
Peak memory 239012 kb
Host smart-5bd7f434-0067-477a-bc28-59867916b091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303652127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3303652127
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1032127675
Short name T821
Test name
Test status
Simulation time 53580967 ps
CPU time 4.92 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 236504 kb
Host smart-c26db105-bc7d-4310-9849-d1681966b705
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1032127675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1032127675
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4093969319
Short name T197
Test name
Test status
Simulation time 1196918755 ps
CPU time 20.08 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:38 PM PDT 24
Peak memory 243800 kb
Host smart-260f70a7-c677-4f7d-a4d0-cfa9634195aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4093969319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4093969319
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1552046371
Short name T132
Test name
Test status
Simulation time 23930560748 ps
CPU time 311.86 seconds
Started May 28 01:44:15 PM PDT 24
Finished May 28 01:49:28 PM PDT 24
Peak memory 265156 kb
Host smart-8698c3f9-764d-48ce-90c6-1cc522bd52c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1552046371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1552046371
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2772153994
Short name T133
Test name
Test status
Simulation time 4314349516 ps
CPU time 615.98 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:54:35 PM PDT 24
Peak memory 273316 kb
Host smart-4aaef595-1130-46a7-9358-4a4c4ec678fe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772153994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2772153994
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3413597303
Short name T820
Test name
Test status
Simulation time 224247842 ps
CPU time 14.19 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 248388 kb
Host smart-7e670908-228f-4375-9f39-30f8f4bdad01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3413597303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3413597303
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2015350173
Short name T783
Test name
Test status
Simulation time 206721067 ps
CPU time 9.56 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:27 PM PDT 24
Peak memory 248376 kb
Host smart-118beb12-c22b-4a4d-a076-17be435cfb9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015350173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2015350173
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1710282192
Short name T194
Test name
Test status
Simulation time 50279510 ps
CPU time 5.05 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:22 PM PDT 24
Peak memory 239400 kb
Host smart-b66249ac-ee0b-4741-a4d3-5d0c3d880cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1710282192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1710282192
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2726572299
Short name T722
Test name
Test status
Simulation time 8216505 ps
CPU time 1.49 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:44:20 PM PDT 24
Peak memory 236604 kb
Host smart-bb9d3e1d-a65a-490d-b181-35d47cd7f8a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726572299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2726572299
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2687413705
Short name T770
Test name
Test status
Simulation time 1244377424 ps
CPU time 44.78 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:45:06 PM PDT 24
Peak memory 243756 kb
Host smart-3bcae564-71bc-45b2-9848-526abfc9a148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2687413705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2687413705
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1889125418
Short name T154
Test name
Test status
Simulation time 17236002673 ps
CPU time 315.87 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:49:34 PM PDT 24
Peak memory 265220 kb
Host smart-dbaf75dd-513f-4b8a-8a2d-fceb5b507dbc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889125418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1889125418
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.22652734
Short name T734
Test name
Test status
Simulation time 240372972 ps
CPU time 16.24 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:31 PM PDT 24
Peak memory 248316 kb
Host smart-bfd2fe74-555c-4286-a1f3-a62086896b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=22652734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.22652734
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2810995151
Short name T741
Test name
Test status
Simulation time 67325563 ps
CPU time 6.12 seconds
Started May 28 01:44:21 PM PDT 24
Finished May 28 01:44:29 PM PDT 24
Peak memory 242672 kb
Host smart-822fd006-dbd7-401c-880c-967dd6b1c515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810995151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2810995151
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1953536254
Short name T772
Test name
Test status
Simulation time 35426693 ps
CPU time 5.78 seconds
Started May 28 01:44:15 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 240096 kb
Host smart-5f5b9072-c6a2-489d-a06e-80ece1185c50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1953536254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1953536254
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1763724662
Short name T792
Test name
Test status
Simulation time 10435433 ps
CPU time 1.31 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:24 PM PDT 24
Peak memory 234656 kb
Host smart-9be2628b-9fa4-40b9-8348-2fb439b9cced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763724662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1763724662
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1167161350
Short name T798
Test name
Test status
Simulation time 82157407 ps
CPU time 9.81 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 243836 kb
Host smart-61d45658-d7dd-4759-926f-39a9c7c9d0d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1167161350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1167161350
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2711811101
Short name T140
Test name
Test status
Simulation time 7547230748 ps
CPU time 133.55 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:46:35 PM PDT 24
Peak memory 265092 kb
Host smart-1ceb8370-ba1c-41b4-9e99-d1c1e64d7e88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2711811101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2711811101
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2615720693
Short name T128
Test name
Test status
Simulation time 12970393387 ps
CPU time 965.12 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 02:00:23 PM PDT 24
Peak memory 265104 kb
Host smart-e1a736bd-8322-47dc-ba50-0f7251c40cab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615720693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2615720693
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2494286711
Short name T727
Test name
Test status
Simulation time 53365158 ps
CPU time 5.07 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:27 PM PDT 24
Peak memory 248308 kb
Host smart-e5955a2d-04ba-4d2e-95f8-64546d5a2a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2494286711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2494286711
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3091266845
Short name T801
Test name
Test status
Simulation time 102726668 ps
CPU time 7.62 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:30 PM PDT 24
Peak memory 239948 kb
Host smart-4be8324c-a086-489b-9841-e72af97d3f82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091266845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3091266845
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.251540008
Short name T807
Test name
Test status
Simulation time 503357831 ps
CPU time 10.21 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 236492 kb
Host smart-d27d282b-08de-4b53-9fad-177e61757bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=251540008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.251540008
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.245586572
Short name T831
Test name
Test status
Simulation time 14175073 ps
CPU time 1.36 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:44:20 PM PDT 24
Peak memory 234668 kb
Host smart-6a51d323-f8c2-42c7-8119-632db0c706b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=245586572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.245586572
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1175633450
Short name T752
Test name
Test status
Simulation time 519466281 ps
CPU time 33.22 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:56 PM PDT 24
Peak memory 244772 kb
Host smart-e5816d24-800d-4293-bedb-71e7cb0f7581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1175633450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1175633450
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2578642037
Short name T152
Test name
Test status
Simulation time 3018874373 ps
CPU time 104.55 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:46:02 PM PDT 24
Peak memory 265132 kb
Host smart-107d9fd9-dcec-4ad8-8f5e-6036c2b2fde1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2578642037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2578642037
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3208501202
Short name T149
Test name
Test status
Simulation time 2204272025 ps
CPU time 294.74 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:49:17 PM PDT 24
Peak memory 265188 kb
Host smart-769e0b10-9274-43ac-b1e6-ccc82ce0298a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208501202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3208501202
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2739354769
Short name T812
Test name
Test status
Simulation time 672642621 ps
CPU time 10.06 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:25 PM PDT 24
Peak memory 247664 kb
Host smart-2f6b49c1-34b8-4e27-8068-82766b9519cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2739354769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2739354769
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1694401777
Short name T790
Test name
Test status
Simulation time 573828696 ps
CPU time 13.45 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 243232 kb
Host smart-a03b4ded-b0e9-4fae-8ade-6850a5d7a0e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694401777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1694401777
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1705891280
Short name T804
Test name
Test status
Simulation time 178667094 ps
CPU time 4.48 seconds
Started May 28 01:44:15 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 239256 kb
Host smart-742b2b36-d309-42b9-8816-818bd508d5f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1705891280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1705891280
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2379042442
Short name T762
Test name
Test status
Simulation time 13488045 ps
CPU time 1.47 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 235616 kb
Host smart-33b8de4c-89e5-4fc1-848e-d3bd4449e6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2379042442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2379042442
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.715995347
Short name T740
Test name
Test status
Simulation time 353873694 ps
CPU time 10.46 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 243708 kb
Host smart-98189980-f44b-4367-9d06-e466f6accc5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=715995347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.715995347
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.717642142
Short name T830
Test name
Test status
Simulation time 17902143739 ps
CPU time 314.3 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:49:37 PM PDT 24
Peak memory 264868 kb
Host smart-7e8e50e0-70ed-4233-b9bc-3f1c59230798
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=717642142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.717642142
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3027926247
Short name T129
Test name
Test status
Simulation time 12477127871 ps
CPU time 997.95 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 02:00:57 PM PDT 24
Peak memory 272324 kb
Host smart-a191476e-8038-4a65-bc99-94949f010b77
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027926247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3027926247
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.217118157
Short name T784
Test name
Test status
Simulation time 425963427 ps
CPU time 16.88 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:38 PM PDT 24
Peak memory 248328 kb
Host smart-45de529a-d932-457e-8f0c-65e1050e45ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=217118157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.217118157
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.305145606
Short name T755
Test name
Test status
Simulation time 59909928 ps
CPU time 5.22 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 239932 kb
Host smart-f8f5fe8d-e3d0-496a-9768-72f63f9e4b7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305145606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.305145606
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1548878819
Short name T764
Test name
Test status
Simulation time 65213108 ps
CPU time 3.46 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:26 PM PDT 24
Peak memory 239160 kb
Host smart-f6f85acc-bd97-4cc9-a007-564399eb7a4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1548878819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1548878819
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2769438706
Short name T732
Test name
Test status
Simulation time 11874127 ps
CPU time 1.27 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 235596 kb
Host smart-a599914a-4dde-4c90-8076-ace44df57218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2769438706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2769438706
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2204831151
Short name T779
Test name
Test status
Simulation time 257874428 ps
CPU time 23.45 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:44:47 PM PDT 24
Peak memory 248292 kb
Host smart-4624f1e5-5f6c-4fcb-9844-8b2b13880c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2204831151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2204831151
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3243846463
Short name T141
Test name
Test status
Simulation time 6471676107 ps
CPU time 221.15 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:48:00 PM PDT 24
Peak memory 272792 kb
Host smart-6430e9cb-b529-4168-9321-08b2e2406d61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3243846463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3243846463
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1449897401
Short name T138
Test name
Test status
Simulation time 6689088490 ps
CPU time 341.26 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:50:03 PM PDT 24
Peak memory 265172 kb
Host smart-00ff29ed-8380-40c3-8ab3-11f24f0fd902
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449897401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1449897401
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2410441296
Short name T721
Test name
Test status
Simulation time 536598239 ps
CPU time 21.54 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:43 PM PDT 24
Peak memory 248328 kb
Host smart-82d495e0-e63c-48d9-8339-546c049cacfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2410441296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2410441296
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.523536719
Short name T766
Test name
Test status
Simulation time 51186693 ps
CPU time 2.58 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:24 PM PDT 24
Peak memory 236392 kb
Host smart-1eaf83f2-d813-4ee2-a878-7083950320e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=523536719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.523536719
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.315416744
Short name T808
Test name
Test status
Simulation time 62546830 ps
CPU time 9.82 seconds
Started May 28 01:44:22 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 244276 kb
Host smart-50b32c48-4169-4d3f-ae1c-7ddc0c00ac8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315416744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.315416744
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3361769823
Short name T731
Test name
Test status
Simulation time 22547325 ps
CPU time 3.63 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:26 PM PDT 24
Peak memory 236536 kb
Host smart-94add03d-ddd2-4a9f-ab02-fa344d8ba972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3361769823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3361769823
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.286360443
Short name T782
Test name
Test status
Simulation time 357010897 ps
CPU time 26.41 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:49 PM PDT 24
Peak memory 248316 kb
Host smart-1634c12e-c1b9-4791-b342-aef4dac83ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=286360443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.286360443
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3608378971
Short name T127
Test name
Test status
Simulation time 27866857775 ps
CPU time 312.85 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:49:36 PM PDT 24
Peak memory 265112 kb
Host smart-1070de0f-be00-43f5-a969-4b3c6f7e3928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3608378971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3608378971
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.674203295
Short name T357
Test name
Test status
Simulation time 6331816915 ps
CPU time 465.38 seconds
Started May 28 01:44:20 PM PDT 24
Finished May 28 01:52:08 PM PDT 24
Peak memory 269620 kb
Host smart-c9de8189-f61a-4d6a-8ba0-c0d0c1a69bc5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674203295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.674203295
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1539434353
Short name T797
Test name
Test status
Simulation time 760776276 ps
CPU time 12.74 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:34 PM PDT 24
Peak memory 248280 kb
Host smart-0a9041a1-27be-4490-bcdd-92adf7d88876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1539434353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1539434353
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.527237085
Short name T809
Test name
Test status
Simulation time 52099339 ps
CPU time 8.62 seconds
Started May 28 01:44:22 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 250528 kb
Host smart-003917ca-6e28-469b-814f-3efcb9d8aa94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527237085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.527237085
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.790937695
Short name T192
Test name
Test status
Simulation time 91249457 ps
CPU time 8.09 seconds
Started May 28 01:44:22 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 236440 kb
Host smart-7a9e25c1-06e7-43f2-9f22-a01dd2b2f99e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=790937695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.790937695
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.84225165
Short name T805
Test name
Test status
Simulation time 6743671 ps
CPU time 1.61 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 235620 kb
Host smart-d27763ea-7931-45a3-ae76-ea2f4ee5c5d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=84225165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.84225165
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.431767216
Short name T173
Test name
Test status
Simulation time 534167453 ps
CPU time 18.15 seconds
Started May 28 01:44:22 PM PDT 24
Finished May 28 01:44:42 PM PDT 24
Peak memory 239996 kb
Host smart-32b1842d-6e34-4381-a872-77258cb5e94d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=431767216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.431767216
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4239874651
Short name T746
Test name
Test status
Simulation time 76437263 ps
CPU time 9.31 seconds
Started May 28 01:44:19 PM PDT 24
Finished May 28 01:44:31 PM PDT 24
Peak memory 248296 kb
Host smart-43d35b40-c662-4b91-aa86-7d3ae1960eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4239874651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.4239874651
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3925281553
Short name T749
Test name
Test status
Simulation time 568027942 ps
CPU time 11.65 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:42 PM PDT 24
Peak memory 248372 kb
Host smart-9e322727-546f-4cd8-a636-d05767522955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925281553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3925281553
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.416041211
Short name T789
Test name
Test status
Simulation time 213923833 ps
CPU time 3.13 seconds
Started May 28 01:44:32 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 235496 kb
Host smart-0be26155-4405-4ce2-be4c-5b37fba6c210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=416041211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.416041211
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4277070881
Short name T753
Test name
Test status
Simulation time 8540461 ps
CPU time 1.46 seconds
Started May 28 01:44:27 PM PDT 24
Finished May 28 01:44:29 PM PDT 24
Peak memory 236556 kb
Host smart-cdf0eb48-2aea-4303-b8b2-8927afbd3c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4277070881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4277070881
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2143120523
Short name T803
Test name
Test status
Simulation time 893725152 ps
CPU time 12.06 seconds
Started May 28 01:44:28 PM PDT 24
Finished May 28 01:44:41 PM PDT 24
Peak memory 244772 kb
Host smart-945f506b-89d9-49a4-9e9c-0da830c139b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2143120523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2143120523
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.786381106
Short name T358
Test name
Test status
Simulation time 7832705606 ps
CPU time 468.29 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:52:10 PM PDT 24
Peak memory 265132 kb
Host smart-873aebc7-f5d9-462d-8e43-57c35775d07f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786381106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.786381106
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4279725370
Short name T717
Test name
Test status
Simulation time 75855609 ps
CPU time 9.85 seconds
Started May 28 01:44:27 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 247344 kb
Host smart-112e46f5-ffbf-4d32-857a-ec5885ce4abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4279725370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4279725370
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3854797857
Short name T818
Test name
Test status
Simulation time 181215985 ps
CPU time 5.25 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 240140 kb
Host smart-721bb611-9d83-400b-9f6e-3913e4988800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854797857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3854797857
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2375444842
Short name T826
Test name
Test status
Simulation time 589795461 ps
CPU time 8.39 seconds
Started May 28 01:44:33 PM PDT 24
Finished May 28 01:44:43 PM PDT 24
Peak memory 236512 kb
Host smart-1d557ddc-cc25-4d71-9c9d-78a7effdab91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2375444842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2375444842
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1103027820
Short name T787
Test name
Test status
Simulation time 10729706 ps
CPU time 1.57 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 234628 kb
Host smart-2959ad14-a8db-448c-a66f-021f6096470e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1103027820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1103027820
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1088811604
Short name T828
Test name
Test status
Simulation time 184686738 ps
CPU time 25.02 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:44:58 PM PDT 24
Peak memory 244728 kb
Host smart-5e8bcad4-2dec-4ef4-8711-f980ccb52e27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1088811604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1088811604
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.295694423
Short name T148
Test name
Test status
Simulation time 16123572230 ps
CPU time 1150.9 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 02:03:44 PM PDT 24
Peak memory 265188 kb
Host smart-7d8cc21d-ffcb-4c41-84e4-afe09e2aa3b5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295694423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.295694423
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4205896102
Short name T737
Test name
Test status
Simulation time 274497573 ps
CPU time 10.98 seconds
Started May 28 01:44:30 PM PDT 24
Finished May 28 01:44:43 PM PDT 24
Peak memory 248344 kb
Host smart-e1ebf668-4071-44a3-8d2e-b92cac6c8beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4205896102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4205896102
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.862208527
Short name T806
Test name
Test status
Simulation time 2255795534 ps
CPU time 145.41 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:49:02 PM PDT 24
Peak memory 240100 kb
Host smart-63c36e0e-d62e-4743-b6c3-0a0c6b9eb424
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=862208527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.862208527
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.679190603
Short name T359
Test name
Test status
Simulation time 1637187020 ps
CPU time 211.34 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:50:05 PM PDT 24
Peak memory 240092 kb
Host smart-d01fc5e6-b507-43f7-a787-31e530971798
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=679190603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.679190603
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2935290401
Short name T160
Test name
Test status
Simulation time 53717214 ps
CPU time 5.35 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:39 PM PDT 24
Peak memory 240116 kb
Host smart-d06b74e3-9d86-4af0-8e3e-f92930e26bbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2935290401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2935290401
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2485906834
Short name T813
Test name
Test status
Simulation time 58155556 ps
CPU time 9.46 seconds
Started May 28 01:46:03 PM PDT 24
Finished May 28 01:46:21 PM PDT 24
Peak memory 251620 kb
Host smart-c6878bba-6fce-400b-98a2-14cdb338734b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485906834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2485906834
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3409944654
Short name T814
Test name
Test status
Simulation time 533582872 ps
CPU time 7.77 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 240032 kb
Host smart-494bd884-e878-4e2b-8df9-5108b6e3cf46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3409944654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3409944654
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4077903383
Short name T815
Test name
Test status
Simulation time 26704315 ps
CPU time 1.43 seconds
Started May 28 01:46:20 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 235656 kb
Host smart-d24543da-42ce-461d-8ce1-0613407bd9ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4077903383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4077903383
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2025797361
Short name T195
Test name
Test status
Simulation time 190675490 ps
CPU time 24.71 seconds
Started May 28 01:45:32 PM PDT 24
Finished May 28 01:45:58 PM PDT 24
Peak memory 244788 kb
Host smart-ed1ff16e-d70f-4fb4-a78d-781ef678361d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2025797361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2025797361
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.341837835
Short name T130
Test name
Test status
Simulation time 1589173584 ps
CPU time 98.56 seconds
Started May 28 01:46:21 PM PDT 24
Finished May 28 01:48:19 PM PDT 24
Peak memory 256856 kb
Host smart-2c59e9ae-d1ee-46f0-bd42-12b0f6e2ce95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=341837835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.341837835
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2984772600
Short name T832
Test name
Test status
Simulation time 9915372283 ps
CPU time 641.51 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:57:17 PM PDT 24
Peak memory 265156 kb
Host smart-86069c22-0667-4706-9362-54cc8e830af0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984772600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2984772600
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.641789108
Short name T796
Test name
Test status
Simulation time 187087807 ps
CPU time 11.99 seconds
Started May 28 01:46:20 PM PDT 24
Finished May 28 01:46:52 PM PDT 24
Peak memory 248324 kb
Host smart-d32c4e68-c841-4ae7-a2a5-780f90a34061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=641789108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.641789108
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.902302710
Short name T739
Test name
Test status
Simulation time 10945035 ps
CPU time 1.67 seconds
Started May 28 01:44:25 PM PDT 24
Finished May 28 01:44:27 PM PDT 24
Peak memory 236556 kb
Host smart-836c6f90-65dc-4325-9b96-e41a0f59ee17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=902302710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.902302710
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4275622210
Short name T786
Test name
Test status
Simulation time 11643788 ps
CPU time 1.37 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 235636 kb
Host smart-6fd12798-a786-472b-884b-609a395faac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4275622210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4275622210
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4160202278
Short name T799
Test name
Test status
Simulation time 57647216 ps
CPU time 1.35 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 234568 kb
Host smart-b5892a1d-959b-43ec-b508-78bc4375fd00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4160202278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4160202278
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4102324245
Short name T758
Test name
Test status
Simulation time 15051409 ps
CPU time 1.37 seconds
Started May 28 01:44:28 PM PDT 24
Finished May 28 01:44:30 PM PDT 24
Peak memory 236604 kb
Host smart-55289376-8118-4010-b7e4-0692ce2e8344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4102324245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4102324245
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.551618126
Short name T763
Test name
Test status
Simulation time 8486021 ps
CPU time 1.5 seconds
Started May 28 01:44:28 PM PDT 24
Finished May 28 01:44:31 PM PDT 24
Peak memory 234848 kb
Host smart-133a6d8b-b182-41d1-a6bf-4de04b7206f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=551618126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.551618126
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.888457960
Short name T781
Test name
Test status
Simulation time 19965394 ps
CPU time 1.46 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 236572 kb
Host smart-a696805c-0b1d-440e-821e-d4055322b408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=888457960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.888457960
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4142127869
Short name T232
Test name
Test status
Simulation time 10489187 ps
CPU time 1.25 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:31 PM PDT 24
Peak memory 236788 kb
Host smart-f41b43d2-a513-4230-9840-12e9da48c0a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4142127869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4142127869
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2982945865
Short name T817
Test name
Test status
Simulation time 11767546 ps
CPU time 1.33 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 236792 kb
Host smart-fc5cfcba-2d68-4560-b683-6e5cf3212540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2982945865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2982945865
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3307156324
Short name T735
Test name
Test status
Simulation time 24868782 ps
CPU time 1.44 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 236572 kb
Host smart-1d2d6547-ad59-446b-8084-9f5bf06f0165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3307156324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3307156324
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2161995707
Short name T346
Test name
Test status
Simulation time 7392321 ps
CPU time 1.41 seconds
Started May 28 01:44:30 PM PDT 24
Finished May 28 01:44:34 PM PDT 24
Peak memory 235596 kb
Host smart-cb531a14-5ad8-4e08-8d10-28ec21bafe4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161995707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2161995707
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3956085066
Short name T199
Test name
Test status
Simulation time 20950077853 ps
CPU time 293.72 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:51:09 PM PDT 24
Peak memory 240548 kb
Host smart-ee305673-2b00-4f17-a296-73a576100ab0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3956085066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3956085066
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1195264708
Short name T769
Test name
Test status
Simulation time 3270081865 ps
CPU time 80.65 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:47:49 PM PDT 24
Peak memory 240208 kb
Host smart-5a7ab4e8-b624-476c-8b17-f59a93b5fffc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1195264708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1195264708
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.919291591
Short name T158
Test name
Test status
Simulation time 93943072 ps
CPU time 5.64 seconds
Started May 28 01:46:05 PM PDT 24
Finished May 28 01:46:22 PM PDT 24
Peak memory 240076 kb
Host smart-f3ab36ef-8e73-4d98-a5f2-0a8f5868cb97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=919291591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.919291591
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2228197584
Short name T353
Test name
Test status
Simulation time 62837153 ps
CPU time 5.22 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:34 PM PDT 24
Peak memory 237660 kb
Host smart-9744b0e8-77bb-4366-8426-56a5fcf17fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228197584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2228197584
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4034620311
Short name T819
Test name
Test status
Simulation time 19986970 ps
CPU time 3.47 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:32 PM PDT 24
Peak memory 235632 kb
Host smart-b2efed74-6102-49c1-9c6b-292303e2f0e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4034620311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4034620311
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.508481470
Short name T759
Test name
Test status
Simulation time 11006582 ps
CPU time 1.65 seconds
Started May 28 01:46:02 PM PDT 24
Finished May 28 01:46:10 PM PDT 24
Peak memory 236528 kb
Host smart-ebe86a35-fa82-458c-a297-22f0231f7617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508481470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.508481470
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1413727167
Short name T824
Test name
Test status
Simulation time 184825560 ps
CPU time 24.2 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:53 PM PDT 24
Peak memory 248292 kb
Host smart-6efd1f57-fa50-4a53-a3ef-060ab8895421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1413727167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1413727167
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3437827229
Short name T124
Test name
Test status
Simulation time 13591664876 ps
CPU time 145.27 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:49:02 PM PDT 24
Peak memory 265092 kb
Host smart-51d78118-f060-43c3-9370-d3f137aa6ecb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3437827229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3437827229
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1326532298
Short name T754
Test name
Test status
Simulation time 148509010 ps
CPU time 10.11 seconds
Started May 28 01:46:04 PM PDT 24
Finished May 28 01:46:23 PM PDT 24
Peak memory 248388 kb
Host smart-84e9edcc-a0fc-4e2b-b68f-42ca3ec7e846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1326532298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1326532298
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.590121190
Short name T352
Test name
Test status
Simulation time 8035950 ps
CPU time 1.45 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:44:34 PM PDT 24
Peak memory 235596 kb
Host smart-348d57d1-63e2-46e3-8dad-52620f53f7e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=590121190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.590121190
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4088915117
Short name T788
Test name
Test status
Simulation time 9592879 ps
CPU time 1.4 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 236788 kb
Host smart-8a1e56ea-30a7-4b37-ade8-a0f4453706f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4088915117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4088915117
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3049881074
Short name T231
Test name
Test status
Simulation time 10365985 ps
CPU time 1.32 seconds
Started May 28 01:44:30 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 236584 kb
Host smart-0ba680a4-4986-4024-aa8d-cfcd24313563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3049881074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3049881074
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3260170072
Short name T725
Test name
Test status
Simulation time 93968741 ps
CPU time 1.47 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 236436 kb
Host smart-c1ad1338-0ae1-4db8-b79a-2fef24a87618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3260170072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3260170072
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1221690537
Short name T350
Test name
Test status
Simulation time 15792995 ps
CPU time 1.6 seconds
Started May 28 01:44:32 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 236604 kb
Host smart-9ea9d47d-923a-431b-87c4-804022f3ac58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1221690537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1221690537
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3052077426
Short name T723
Test name
Test status
Simulation time 16497746 ps
CPU time 1.34 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:44:34 PM PDT 24
Peak memory 236608 kb
Host smart-51fad46a-a234-4732-880d-ba32c065664d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3052077426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3052077426
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1414917902
Short name T767
Test name
Test status
Simulation time 18353263 ps
CPU time 1.34 seconds
Started May 28 01:44:28 PM PDT 24
Finished May 28 01:44:30 PM PDT 24
Peak memory 234668 kb
Host smart-db5e4d98-12ad-43d9-b7fc-497242899ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1414917902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1414917902
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2818285275
Short name T793
Test name
Test status
Simulation time 21506155 ps
CPU time 1.43 seconds
Started May 28 01:44:32 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 235668 kb
Host smart-d017573f-6a37-494e-9660-25c019753dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818285275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2818285275
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.270001075
Short name T775
Test name
Test status
Simulation time 9557470 ps
CPU time 1.52 seconds
Started May 28 01:44:32 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 235672 kb
Host smart-8a7b72d2-a858-44a7-ae96-6d92394bbc73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=270001075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.270001075
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3481165811
Short name T743
Test name
Test status
Simulation time 6499890977 ps
CPU time 116.87 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:48:28 PM PDT 24
Peak memory 236652 kb
Host smart-dc9c978a-547c-4b09-8dc9-bf5d7c99329d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3481165811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3481165811
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.747474163
Short name T751
Test name
Test status
Simulation time 51842943715 ps
CPU time 358.93 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:52:32 PM PDT 24
Peak memory 240116 kb
Host smart-cf3b8403-0411-4616-b5b0-d40e952f95b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=747474163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.747474163
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1211589412
Short name T719
Test name
Test status
Simulation time 844878702 ps
CPU time 9.08 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 240076 kb
Host smart-88153eb4-353d-432a-82ba-4cd9c8bcace0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1211589412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1211589412
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2937650118
Short name T823
Test name
Test status
Simulation time 222275389 ps
CPU time 9.03 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:45:33 PM PDT 24
Peak memory 252268 kb
Host smart-241f1007-0c57-4b76-8fea-2dbcda64befc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937650118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2937650118
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.924973553
Short name T795
Test name
Test status
Simulation time 166039446 ps
CPU time 8.97 seconds
Started May 28 01:46:02 PM PDT 24
Finished May 28 01:46:17 PM PDT 24
Peak memory 236572 kb
Host smart-e47d4f68-9fd8-40f5-b619-0658408260cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=924973553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.924973553
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.303332676
Short name T744
Test name
Test status
Simulation time 6779470 ps
CPU time 1.41 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:31 PM PDT 24
Peak memory 235640 kb
Host smart-60addf38-2100-49b7-9894-e399b5aa273d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=303332676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.303332676
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1453563128
Short name T833
Test name
Test status
Simulation time 2340234853 ps
CPU time 42.62 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:47:16 PM PDT 24
Peak memory 244792 kb
Host smart-9adab22a-1f43-4afc-9cc5-35febfaa4314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1453563128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1453563128
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2284515965
Short name T827
Test name
Test status
Simulation time 166987668 ps
CPU time 11.71 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:40 PM PDT 24
Peak memory 248148 kb
Host smart-d003f229-ae1c-4fa1-bb18-18c0c74e346e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2284515965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2284515965
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3764284673
Short name T742
Test name
Test status
Simulation time 58236794 ps
CPU time 2.08 seconds
Started May 28 01:46:10 PM PDT 24
Finished May 28 01:46:30 PM PDT 24
Peak memory 236972 kb
Host smart-0a456b3f-1210-4dff-80e7-317d963987a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3764284673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3764284673
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1876140143
Short name T159
Test name
Test status
Simulation time 18294280 ps
CPU time 1.46 seconds
Started May 28 01:44:32 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 234628 kb
Host smart-dcc0f46c-26e8-4472-8b01-d31068ab85ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1876140143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1876140143
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.46656934
Short name T802
Test name
Test status
Simulation time 10486640 ps
CPU time 1.27 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:33 PM PDT 24
Peak memory 236608 kb
Host smart-1032b382-7927-4df4-b21d-e5be3efff319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=46656934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.46656934
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3842018126
Short name T726
Test name
Test status
Simulation time 7116745 ps
CPU time 1.47 seconds
Started May 28 01:44:28 PM PDT 24
Finished May 28 01:44:30 PM PDT 24
Peak memory 235672 kb
Host smart-e7bf99cc-9f5e-416d-8d80-4e64d35204c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3842018126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3842018126
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.135394424
Short name T230
Test name
Test status
Simulation time 26876442 ps
CPU time 1.53 seconds
Started May 28 01:44:32 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 236608 kb
Host smart-15398384-bf47-4b7b-83bb-f7f711a9f666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=135394424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.135394424
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3376989280
Short name T347
Test name
Test status
Simulation time 15774608 ps
CPU time 1.4 seconds
Started May 28 01:44:35 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 235624 kb
Host smart-5a5de594-384f-4ebb-b76d-1a93bb1e9ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3376989280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3376989280
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3871344078
Short name T750
Test name
Test status
Simulation time 12419324 ps
CPU time 1.35 seconds
Started May 28 01:44:29 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 236608 kb
Host smart-6b44aa74-7113-45c1-9454-9f81e720ab2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3871344078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3871344078
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3158485196
Short name T756
Test name
Test status
Simulation time 8888822 ps
CPU time 1.56 seconds
Started May 28 01:44:33 PM PDT 24
Finished May 28 01:44:36 PM PDT 24
Peak memory 236552 kb
Host smart-a7d67d26-8a73-4bb6-af78-777393fb721c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3158485196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3158485196
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3801700865
Short name T771
Test name
Test status
Simulation time 79790574 ps
CPU time 1.45 seconds
Started May 28 01:44:35 PM PDT 24
Finished May 28 01:44:38 PM PDT 24
Peak memory 236408 kb
Host smart-bcae1288-087f-4938-8695-e924522dcbb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3801700865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3801700865
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3576316565
Short name T778
Test name
Test status
Simulation time 7670357 ps
CPU time 1.48 seconds
Started May 28 01:44:33 PM PDT 24
Finished May 28 01:44:36 PM PDT 24
Peak memory 236544 kb
Host smart-ab9294d6-170c-48fc-8611-84a10dd0b3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3576316565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3576316565
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2048932072
Short name T760
Test name
Test status
Simulation time 6534767 ps
CPU time 1.44 seconds
Started May 28 01:44:31 PM PDT 24
Finished May 28 01:44:35 PM PDT 24
Peak memory 236608 kb
Host smart-73d1e2e1-0eb7-4a7f-bba5-b4454661afa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2048932072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2048932072
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4257471123
Short name T355
Test name
Test status
Simulation time 58553214 ps
CPU time 9.02 seconds
Started May 28 01:46:13 PM PDT 24
Finished May 28 01:46:42 PM PDT 24
Peak memory 250428 kb
Host smart-d96334f5-061e-4739-ab0c-7c75da06faf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257471123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4257471123
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.55322160
Short name T745
Test name
Test status
Simulation time 223056530 ps
CPU time 8.5 seconds
Started May 28 01:46:12 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 240064 kb
Host smart-44bdd7b5-bbcf-441a-bdb1-c4983d596179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=55322160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.55322160
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2085986590
Short name T349
Test name
Test status
Simulation time 7542023 ps
CPU time 1.39 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:45:26 PM PDT 24
Peak memory 236592 kb
Host smart-cbf22027-5da1-4acf-8367-ab97935c9275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2085986590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2085986590
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3985519107
Short name T720
Test name
Test status
Simulation time 581181974 ps
CPU time 18.82 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:53 PM PDT 24
Peak memory 243844 kb
Host smart-e807dd94-88dc-44f6-8dab-5a8a3c4b19c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3985519107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3985519107
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.64707748
Short name T125
Test name
Test status
Simulation time 2465623888 ps
CPU time 171.3 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:49:30 PM PDT 24
Peak memory 265152 kb
Host smart-cd9d6052-ab98-4230-a2ec-d44e95beec2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=64707748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors
.64707748
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3402089669
Short name T144
Test name
Test status
Simulation time 7585013071 ps
CPU time 471.62 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:54:30 PM PDT 24
Peak memory 265204 kb
Host smart-0b863413-e196-4157-aa1f-c5e225a5c9be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402089669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3402089669
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3750665124
Short name T730
Test name
Test status
Simulation time 237708134 ps
CPU time 9.34 seconds
Started May 28 01:46:11 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 248300 kb
Host smart-2e22e2f3-be7f-4012-8485-f12e56b05e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3750665124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3750665124
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2359401848
Short name T810
Test name
Test status
Simulation time 259623264 ps
CPU time 11.39 seconds
Started May 28 01:46:14 PM PDT 24
Finished May 28 01:46:46 PM PDT 24
Peak memory 248320 kb
Host smart-b9757b70-9c34-482c-a86c-7807bb39ec24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359401848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2359401848
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2517043577
Short name T193
Test name
Test status
Simulation time 73253906 ps
CPU time 5.64 seconds
Started May 28 01:46:17 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 236516 kb
Host smart-fc3a7645-f426-4490-90b0-dfcb5d87d5ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2517043577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2517043577
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.124637357
Short name T748
Test name
Test status
Simulation time 16385468 ps
CPU time 1.49 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:37 PM PDT 24
Peak memory 236412 kb
Host smart-c3b91434-c7b3-4b19-98e4-5f590fdb4ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=124637357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.124637357
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2470960330
Short name T780
Test name
Test status
Simulation time 191564538 ps
CPU time 21.2 seconds
Started May 28 01:46:16 PM PDT 24
Finished May 28 01:46:58 PM PDT 24
Peak memory 243724 kb
Host smart-3d8adfca-a493-45c3-b046-48223532f0b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2470960330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2470960330
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3974691043
Short name T728
Test name
Test status
Simulation time 363751834 ps
CPU time 7.61 seconds
Started May 28 01:46:15 PM PDT 24
Finished May 28 01:46:44 PM PDT 24
Peak memory 251312 kb
Host smart-e0af6009-ff04-4e72-bcac-26608762499e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3974691043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3974691043
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3358934159
Short name T733
Test name
Test status
Simulation time 853206055 ps
CPU time 12.07 seconds
Started May 28 01:44:13 PM PDT 24
Finished May 28 01:44:26 PM PDT 24
Peak memory 250404 kb
Host smart-4bec6ac8-2657-4cc3-9df8-9a4b8ff828ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358934159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3358934159
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3861526183
Short name T811
Test name
Test status
Simulation time 63541308 ps
CPU time 5.05 seconds
Started May 28 01:46:21 PM PDT 24
Finished May 28 01:46:45 PM PDT 24
Peak memory 236548 kb
Host smart-5d62a9ad-4f72-4c52-bf48-71b5c3c38e61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3861526183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3861526183
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3858816520
Short name T829
Test name
Test status
Simulation time 8381417 ps
CPU time 1.44 seconds
Started May 28 01:46:18 PM PDT 24
Finished May 28 01:46:41 PM PDT 24
Peak memory 235640 kb
Host smart-2e405e01-5baa-40f5-a62e-9653041f93f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3858816520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3858816520
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1606223489
Short name T736
Test name
Test status
Simulation time 1005673484 ps
CPU time 22.68 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 244728 kb
Host smart-a71032f6-f992-4739-a1aa-8dbaa53cefa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1606223489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1606223489
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3514721493
Short name T134
Test name
Test status
Simulation time 3150393697 ps
CPU time 193.47 seconds
Started May 28 01:45:22 PM PDT 24
Finished May 28 01:48:38 PM PDT 24
Peak memory 265196 kb
Host smart-14aa2cad-67a3-4e14-bc4c-f214ca19bced
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3514721493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3514721493
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2257524269
Short name T718
Test name
Test status
Simulation time 1068872617 ps
CPU time 22.62 seconds
Started May 28 01:44:34 PM PDT 24
Finished May 28 01:44:57 PM PDT 24
Peak memory 253476 kb
Host smart-d3e65ae7-6e4d-43bf-b70b-1ce29486cb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2257524269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2257524269
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1269193036
Short name T785
Test name
Test status
Simulation time 66983011 ps
CPU time 10.39 seconds
Started May 28 01:44:17 PM PDT 24
Finished May 28 01:44:29 PM PDT 24
Peak memory 252332 kb
Host smart-80ee70b1-3fc0-40dd-b4c7-5927ecdd7e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269193036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1269193036
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1579958489
Short name T747
Test name
Test status
Simulation time 268049500 ps
CPU time 5.24 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 236568 kb
Host smart-24e0fdf3-b986-4b74-83fa-b93e0b7d4432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1579958489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1579958489
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3066434361
Short name T724
Test name
Test status
Simulation time 9885332 ps
CPU time 1.54 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:20 PM PDT 24
Peak memory 235652 kb
Host smart-6f5f9db3-ece8-4e0b-bf9b-cbeddae0b78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3066434361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3066434361
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1766651831
Short name T738
Test name
Test status
Simulation time 999673710 ps
CPU time 18.95 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:37 PM PDT 24
Peak memory 248308 kb
Host smart-2891edca-9bdb-4670-bd71-4c7cc3d9c54a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1766651831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1766651831
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1644189205
Short name T146
Test name
Test status
Simulation time 2277837496 ps
CPU time 326.27 seconds
Started May 28 01:44:13 PM PDT 24
Finished May 28 01:49:40 PM PDT 24
Peak memory 265332 kb
Host smart-ec05f608-c7b1-47ee-9a1b-857095698233
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644189205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1644189205
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1542545045
Short name T774
Test name
Test status
Simulation time 1510856508 ps
CPU time 6.8 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:24 PM PDT 24
Peak memory 249352 kb
Host smart-285ce85c-94a6-4de3-85b9-c625e1b09905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542545045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1542545045
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3655299062
Short name T816
Test name
Test status
Simulation time 64293144 ps
CPU time 5.24 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 248400 kb
Host smart-032d5efe-2221-4db1-8231-a0d25fc89e5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655299062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3655299062
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3256267025
Short name T757
Test name
Test status
Simulation time 36328268 ps
CPU time 5.38 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:44:23 PM PDT 24
Peak memory 236564 kb
Host smart-39e318f9-3b3e-4204-a194-2457dabe2f3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3256267025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3256267025
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.594676841
Short name T777
Test name
Test status
Simulation time 7510677 ps
CPU time 1.45 seconds
Started May 28 01:44:18 PM PDT 24
Finished May 28 01:44:21 PM PDT 24
Peak memory 236608 kb
Host smart-91f78f64-e967-469a-a367-877293e58b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=594676841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.594676841
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1381109840
Short name T190
Test name
Test status
Simulation time 250970571 ps
CPU time 16.28 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:32 PM PDT 24
Peak memory 248296 kb
Host smart-4c5972d8-fc84-4b27-a220-cfd71fd3e7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1381109840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1381109840
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.366543083
Short name T136
Test name
Test status
Simulation time 4984821424 ps
CPU time 86.95 seconds
Started May 28 01:44:16 PM PDT 24
Finished May 28 01:45:44 PM PDT 24
Peak memory 265036 kb
Host smart-2804b784-217d-41ae-8868-52ca30c2eb33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=366543083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.366543083
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2332403445
Short name T139
Test name
Test status
Simulation time 12129483896 ps
CPU time 483.26 seconds
Started May 28 01:44:15 PM PDT 24
Finished May 28 01:52:19 PM PDT 24
Peak memory 269732 kb
Host smart-3f83e553-0cc5-40dd-b612-cac250cd4738
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332403445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2332403445
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.266764418
Short name T244
Test name
Test status
Simulation time 133173396 ps
CPU time 9.17 seconds
Started May 28 01:44:14 PM PDT 24
Finished May 28 01:44:25 PM PDT 24
Peak memory 252068 kb
Host smart-77a74c17-b0a2-4187-9025-52c596078382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=266764418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.266764418
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2734579576
Short name T254
Test name
Test status
Simulation time 31978278110 ps
CPU time 1749.09 seconds
Started May 28 01:57:51 PM PDT 24
Finished May 28 02:27:02 PM PDT 24
Peak memory 273460 kb
Host smart-ea93968c-17a8-4a83-bc82-2506c4d4da12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734579576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2734579576
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1625665959
Short name T533
Test name
Test status
Simulation time 922514272 ps
CPU time 42.08 seconds
Started May 28 01:57:54 PM PDT 24
Finished May 28 01:58:37 PM PDT 24
Peak memory 248772 kb
Host smart-bdc9b169-5d73-459b-bf14-9fd163565658
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1625665959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1625665959
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1329791930
Short name T486
Test name
Test status
Simulation time 22600158584 ps
CPU time 321.2 seconds
Started May 28 01:57:51 PM PDT 24
Finished May 28 02:03:15 PM PDT 24
Peak memory 256980 kb
Host smart-52229ec2-a45d-42e0-8b34-c8232bb22422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13297
91930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1329791930
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2795617033
Short name T284
Test name
Test status
Simulation time 13052914240 ps
CPU time 50.47 seconds
Started May 28 01:57:51 PM PDT 24
Finished May 28 01:58:44 PM PDT 24
Peak memory 248904 kb
Host smart-7b2c60de-2897-4ac3-86b7-ea9a2fd5f972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27956
17033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2795617033
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1634244708
Short name T334
Test name
Test status
Simulation time 73782472959 ps
CPU time 2446.09 seconds
Started May 28 01:57:51 PM PDT 24
Finished May 28 02:38:39 PM PDT 24
Peak memory 288684 kb
Host smart-5b161d15-cccd-4d18-a7f5-5e35960cc0f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634244708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1634244708
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.954832739
Short name T643
Test name
Test status
Simulation time 178050796815 ps
CPU time 1529.07 seconds
Started May 28 01:57:52 PM PDT 24
Finished May 28 02:23:23 PM PDT 24
Peak memory 273336 kb
Host smart-f23a24b2-96cc-4fa7-b090-624d3c8e79eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954832739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.954832739
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2295237622
Short name T301
Test name
Test status
Simulation time 12998869999 ps
CPU time 493.16 seconds
Started May 28 01:57:50 PM PDT 24
Finished May 28 02:06:04 PM PDT 24
Peak memory 248116 kb
Host smart-03c0d8b5-f736-4e2a-b802-4f18f94917d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295237622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2295237622
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.218095387
Short name T109
Test name
Test status
Simulation time 180869371 ps
CPU time 7.02 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 01:58:09 PM PDT 24
Peak memory 248760 kb
Host smart-2b7cc6c1-1d2c-4b66-b763-3a1acc429be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21809
5387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.218095387
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.85138293
Short name T483
Test name
Test status
Simulation time 693071947 ps
CPU time 42.15 seconds
Started May 28 01:57:55 PM PDT 24
Finished May 28 01:58:38 PM PDT 24
Peak memory 255944 kb
Host smart-f85693fa-ea43-4575-a8a0-6f60c00716b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85138
293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.85138293
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3699016803
Short name T642
Test name
Test status
Simulation time 739575907 ps
CPU time 14.35 seconds
Started May 28 01:57:52 PM PDT 24
Finished May 28 01:58:08 PM PDT 24
Peak memory 248780 kb
Host smart-f2df6406-8389-419d-9a48-9eeed2404009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36990
16803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3699016803
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3639185032
Short name T674
Test name
Test status
Simulation time 742825862 ps
CPU time 45.92 seconds
Started May 28 01:57:55 PM PDT 24
Finished May 28 01:58:42 PM PDT 24
Peak memory 248756 kb
Host smart-46e4612b-da1f-4fb2-9c87-1c7eab8fb8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36391
85032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3639185032
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2691253530
Short name T255
Test name
Test status
Simulation time 38696708999 ps
CPU time 3937.33 seconds
Started May 28 01:57:55 PM PDT 24
Finished May 28 03:03:33 PM PDT 24
Peak memory 321944 kb
Host smart-faade1da-16fe-46ce-a2c7-29fe6a679c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691253530 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2691253530
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3478611573
Short name T662
Test name
Test status
Simulation time 69343563810 ps
CPU time 1452.11 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 02:22:18 PM PDT 24
Peak memory 289572 kb
Host smart-7e4fddb5-095b-4fdb-a27e-aba1487967ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478611573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3478611573
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.699955820
Short name T645
Test name
Test status
Simulation time 254887766 ps
CPU time 10.94 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:15 PM PDT 24
Peak memory 251444 kb
Host smart-52340e1f-dd05-45dd-8fd9-fd124e72350e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=699955820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.699955820
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2316697698
Short name T574
Test name
Test status
Simulation time 2979610959 ps
CPU time 60.57 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:59:05 PM PDT 24
Peak memory 256944 kb
Host smart-355ec020-ef52-4cdf-99d3-2e6571e7d359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23166
97698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2316697698
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3389517429
Short name T58
Test name
Test status
Simulation time 9693979523 ps
CPU time 40.59 seconds
Started May 28 01:58:04 PM PDT 24
Finished May 28 01:58:48 PM PDT 24
Peak memory 254616 kb
Host smart-34f78d7c-b7c5-4e04-9155-940c1caf0327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
17429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3389517429
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1687269365
Short name T316
Test name
Test status
Simulation time 104623628030 ps
CPU time 1656.73 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 02:25:43 PM PDT 24
Peak memory 289036 kb
Host smart-6486a707-3610-42c9-b1d6-216910c0e030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687269365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1687269365
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3026736319
Short name T599
Test name
Test status
Simulation time 81731615611 ps
CPU time 1462.03 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 02:22:26 PM PDT 24
Peak memory 273392 kb
Host smart-65971bb9-4326-451e-b527-77ff14c8f2df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026736319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3026736319
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.568308805
Short name T657
Test name
Test status
Simulation time 28052642 ps
CPU time 4.02 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:08 PM PDT 24
Peak memory 240544 kb
Host smart-36bf19c7-bba9-43fc-a700-6babe30b4127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56830
8805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.568308805
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3025091515
Short name T30
Test name
Test status
Simulation time 686958087 ps
CPU time 31.37 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:37 PM PDT 24
Peak memory 248412 kb
Host smart-d11541af-4084-42dd-94f5-0671696b51ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
91515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3025091515
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.222062134
Short name T28
Test name
Test status
Simulation time 1151714937 ps
CPU time 45.46 seconds
Started May 28 01:58:05 PM PDT 24
Finished May 28 01:58:53 PM PDT 24
Peak memory 270200 kb
Host smart-182b9e0a-a1fc-4213-bed2-be43f9b2f2ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=222062134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.222062134
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2443621858
Short name T282
Test name
Test status
Simulation time 294339156 ps
CPU time 17.2 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:23 PM PDT 24
Peak memory 247560 kb
Host smart-1b3d76a3-12d2-48d1-86fb-725cc7288c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24436
21858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2443621858
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.550914819
Short name T368
Test name
Test status
Simulation time 61172597 ps
CPU time 4.56 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:09 PM PDT 24
Peak memory 248784 kb
Host smart-1662bccf-33bc-4a38-ae35-eb3b2425f2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55091
4819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.550914819
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3995007988
Short name T671
Test name
Test status
Simulation time 51601551854 ps
CPU time 790.78 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 273180 kb
Host smart-cc9e16ad-b42c-4419-8ea4-ede2d3d13070
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995007988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3995007988
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1140626787
Short name T711
Test name
Test status
Simulation time 9895532427 ps
CPU time 859.88 seconds
Started May 28 01:58:32 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 273028 kb
Host smart-893e0867-ae2d-4354-b219-e9dc6196198a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140626787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1140626787
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1261433843
Short name T420
Test name
Test status
Simulation time 651136236 ps
CPU time 28.9 seconds
Started May 28 01:58:32 PM PDT 24
Finished May 28 01:59:02 PM PDT 24
Peak memory 248716 kb
Host smart-7ba797f0-3a4c-45d5-9c77-573d3d7c2e15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1261433843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1261433843
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2380861747
Short name T685
Test name
Test status
Simulation time 11006351258 ps
CPU time 211.78 seconds
Started May 28 01:58:28 PM PDT 24
Finished May 28 02:02:03 PM PDT 24
Peak memory 250856 kb
Host smart-95fb603c-b1e2-4319-8c9f-a2001aa04924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23808
61747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2380861747
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1572486089
Short name T587
Test name
Test status
Simulation time 1944955588 ps
CPU time 36.38 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 01:59:08 PM PDT 24
Peak memory 255944 kb
Host smart-572323eb-77e0-41ae-88fa-5e31a4dec679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15724
86089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1572486089
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1703541904
Short name T540
Test name
Test status
Simulation time 38202401123 ps
CPU time 870.08 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 266296 kb
Host smart-4625f805-34fc-4680-9bfa-74ed414d654e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703541904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1703541904
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.184920230
Short name T461
Test name
Test status
Simulation time 12752444742 ps
CPU time 1341.74 seconds
Started May 28 01:58:29 PM PDT 24
Finished May 28 02:20:53 PM PDT 24
Peak memory 289680 kb
Host smart-49567473-858b-4f95-ab31-a5ff0fffca53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184920230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.184920230
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3608636784
Short name T592
Test name
Test status
Simulation time 324630557 ps
CPU time 24.51 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:58:51 PM PDT 24
Peak memory 248780 kb
Host smart-04f57c24-901f-4039-b4ba-c1820c032e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36086
36784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3608636784
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3354674291
Short name T52
Test name
Test status
Simulation time 668003179 ps
CPU time 41.81 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 01:59:10 PM PDT 24
Peak memory 256184 kb
Host smart-ea7d7dff-cacb-4b14-ba31-3b2b97357ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33546
74291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3354674291
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.931722622
Short name T286
Test name
Test status
Simulation time 251417340 ps
CPU time 21.29 seconds
Started May 28 01:58:28 PM PDT 24
Finished May 28 01:58:53 PM PDT 24
Peak memory 248748 kb
Host smart-02ef9b02-3814-414e-8676-c29acdbae2b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93172
2622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.931722622
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2555712027
Short name T680
Test name
Test status
Simulation time 1906079568 ps
CPU time 36.08 seconds
Started May 28 01:58:28 PM PDT 24
Finished May 28 01:59:07 PM PDT 24
Peak memory 248748 kb
Host smart-16606119-3933-4f37-9790-48f02ee7277b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25557
12027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2555712027
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.935578076
Short name T495
Test name
Test status
Simulation time 17799380832 ps
CPU time 1374.53 seconds
Started May 28 01:58:32 PM PDT 24
Finished May 28 02:21:28 PM PDT 24
Peak memory 289472 kb
Host smart-56b2a1cf-9a8d-41fd-a3bf-f4b2d01f7c95
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935578076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.935578076
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3749040207
Short name T707
Test name
Test status
Simulation time 118974951739 ps
CPU time 1947.57 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 02:31:04 PM PDT 24
Peak memory 289872 kb
Host smart-0649d4e4-97c1-463b-8445-e6d60657c66b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749040207 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3749040207
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3992983915
Short name T219
Test name
Test status
Simulation time 37672524 ps
CPU time 3.52 seconds
Started May 28 01:58:36 PM PDT 24
Finished May 28 01:58:41 PM PDT 24
Peak memory 248928 kb
Host smart-a85896ac-0a84-4f67-8b42-ae427a62289d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3992983915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3992983915
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2305136426
Short name T25
Test name
Test status
Simulation time 101708444218 ps
CPU time 1256.49 seconds
Started May 28 01:58:44 PM PDT 24
Finished May 28 02:19:42 PM PDT 24
Peak memory 272908 kb
Host smart-3d43a5f9-81e4-4632-a7be-73bf66a98597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305136426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2305136426
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1703189068
Short name T693
Test name
Test status
Simulation time 9854938429 ps
CPU time 102.61 seconds
Started May 28 01:58:38 PM PDT 24
Finished May 28 02:00:22 PM PDT 24
Peak memory 248816 kb
Host smart-148f3b9a-9324-4189-b7c0-88395addbdf3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1703189068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1703189068
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.949744550
Short name T450
Test name
Test status
Simulation time 1254302667 ps
CPU time 26.19 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 01:59:03 PM PDT 24
Peak memory 256008 kb
Host smart-2d16fcba-9ef3-421e-9040-87df637895e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94974
4550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.949744550
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.771488511
Short name T229
Test name
Test status
Simulation time 603396968 ps
CPU time 20.54 seconds
Started May 28 01:58:39 PM PDT 24
Finished May 28 01:59:01 PM PDT 24
Peak memory 248560 kb
Host smart-4b04450d-d4b4-4d5d-a903-d97c8ed11755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77148
8511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.771488511
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3299902123
Short name T683
Test name
Test status
Simulation time 50419776053 ps
CPU time 2771.4 seconds
Started May 28 01:58:41 PM PDT 24
Finished May 28 02:44:53 PM PDT 24
Peak memory 281596 kb
Host smart-140cbe3f-c119-456f-a012-c951b6eaac9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299902123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3299902123
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.782697834
Short name T314
Test name
Test status
Simulation time 44614858592 ps
CPU time 460.82 seconds
Started May 28 01:58:36 PM PDT 24
Finished May 28 02:06:18 PM PDT 24
Peak memory 247088 kb
Host smart-6af02ff0-564c-45e9-b1b2-bc288b805cfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782697834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.782697834
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1135104610
Short name T400
Test name
Test status
Simulation time 143744420 ps
CPU time 14.59 seconds
Started May 28 01:58:41 PM PDT 24
Finished May 28 01:58:56 PM PDT 24
Peak memory 248776 kb
Host smart-ae5e91e2-1174-4ee3-a8c4-d8430fc72137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
04610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1135104610
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2939966038
Short name T285
Test name
Test status
Simulation time 918663701 ps
CPU time 28.72 seconds
Started May 28 01:58:41 PM PDT 24
Finished May 28 01:59:11 PM PDT 24
Peak memory 248768 kb
Host smart-1b941349-3582-44f6-a845-17e0f9e86b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29399
66038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2939966038
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.304397608
Short name T623
Test name
Test status
Simulation time 4870579507 ps
CPU time 29.07 seconds
Started May 28 01:58:37 PM PDT 24
Finished May 28 01:59:08 PM PDT 24
Peak memory 248808 kb
Host smart-4c489041-4630-46e5-b0d7-fe6feb8e95db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30439
7608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.304397608
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2944357499
Short name T651
Test name
Test status
Simulation time 108729715222 ps
CPU time 10363.2 seconds
Started May 28 01:58:37 PM PDT 24
Finished May 28 04:51:23 PM PDT 24
Peak memory 393024 kb
Host smart-6801efe5-8dd5-4ff5-b96a-b0abfea6a6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944357499 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2944357499
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2319331891
Short name T497
Test name
Test status
Simulation time 345879309336 ps
CPU time 1809.48 seconds
Started May 28 01:58:36 PM PDT 24
Finished May 28 02:28:48 PM PDT 24
Peak memory 271364 kb
Host smart-6f80b9e7-f0ee-4898-a8ca-46e74d629778
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319331891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2319331891
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2182813056
Short name T659
Test name
Test status
Simulation time 408554568 ps
CPU time 11.55 seconds
Started May 28 01:58:37 PM PDT 24
Finished May 28 01:58:50 PM PDT 24
Peak memory 248752 kb
Host smart-48c5bcd6-5693-4e66-87e8-798310335cd6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2182813056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2182813056
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2664051077
Short name T221
Test name
Test status
Simulation time 1860859115 ps
CPU time 109.37 seconds
Started May 28 01:58:39 PM PDT 24
Finished May 28 02:00:30 PM PDT 24
Peak memory 256628 kb
Host smart-7c27501d-e7c5-44ce-8e9c-b7a50147bed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26640
51077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2664051077
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3848719792
Short name T676
Test name
Test status
Simulation time 958444700 ps
CPU time 26.23 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 01:59:02 PM PDT 24
Peak memory 248800 kb
Host smart-7ce15f2f-d601-49c7-9125-ad2b98436c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38487
19792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3848719792
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3956707563
Short name T41
Test name
Test status
Simulation time 10518324920 ps
CPU time 860.83 seconds
Started May 28 01:58:38 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 265228 kb
Host smart-868481ae-98ed-4d72-88c5-941c2ea57127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956707563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3956707563
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2667417611
Short name T492
Test name
Test status
Simulation time 31681244612 ps
CPU time 1291.35 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 02:20:08 PM PDT 24
Peak memory 273428 kb
Host smart-0a230d78-d3a1-4540-b07a-616808cb5b65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667417611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2667417611
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1568978986
Short name T465
Test name
Test status
Simulation time 289123236 ps
CPU time 10.97 seconds
Started May 28 01:58:36 PM PDT 24
Finished May 28 01:58:48 PM PDT 24
Peak memory 249008 kb
Host smart-eb696334-3110-4855-b275-f09177b86486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15689
78986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1568978986
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2126832340
Short name T669
Test name
Test status
Simulation time 415687118 ps
CPU time 29.48 seconds
Started May 28 01:58:44 PM PDT 24
Finished May 28 01:59:14 PM PDT 24
Peak memory 256332 kb
Host smart-e8237d13-b984-49ad-9fc1-42a6837cc875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21268
32340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2126832340
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2540706844
Short name T374
Test name
Test status
Simulation time 3437257614 ps
CPU time 54.23 seconds
Started May 28 01:58:37 PM PDT 24
Finished May 28 01:59:33 PM PDT 24
Peak memory 255696 kb
Host smart-82ddd609-0cbe-43ac-b6f1-3cbf3a439f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25407
06844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2540706844
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3935060756
Short name T442
Test name
Test status
Simulation time 2378949296 ps
CPU time 20.5 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 01:58:57 PM PDT 24
Peak memory 248828 kb
Host smart-1469a739-a0c3-420b-88a5-1b2b609366c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39350
60756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3935060756
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3689738840
Short name T293
Test name
Test status
Simulation time 48472992379 ps
CPU time 2916.52 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 02:47:13 PM PDT 24
Peak memory 303608 kb
Host smart-97080e51-1252-4113-8432-81324e41f5d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689738840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3689738840
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1356942402
Short name T216
Test name
Test status
Simulation time 337552171 ps
CPU time 3.32 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 01:58:52 PM PDT 24
Peak memory 248932 kb
Host smart-194e7201-e497-4dcb-8f90-abc108b106b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1356942402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1356942402
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3725696619
Short name T639
Test name
Test status
Simulation time 6784180411 ps
CPU time 770.12 seconds
Started May 28 01:58:44 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 268348 kb
Host smart-3c16e25c-2748-4c6f-9bd7-c0bbfb2aedd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725696619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3725696619
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.211121088
Short name T640
Test name
Test status
Simulation time 374982346 ps
CPU time 17.1 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 01:59:05 PM PDT 24
Peak memory 248660 kb
Host smart-37fb3bf1-3400-4505-a043-b943a81c6143
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=211121088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.211121088
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2075555156
Short name T387
Test name
Test status
Simulation time 2334712343 ps
CPU time 63.98 seconds
Started May 28 01:58:44 PM PDT 24
Finished May 28 01:59:49 PM PDT 24
Peak memory 255600 kb
Host smart-0a566b83-ecab-4939-8880-3c5d3a6d2694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20755
55156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2075555156
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2460415
Short name T603
Test name
Test status
Simulation time 8833946226 ps
CPU time 43.74 seconds
Started May 28 01:58:44 PM PDT 24
Finished May 28 01:59:29 PM PDT 24
Peak memory 256248 kb
Host smart-2d81db42-35ab-4df0-a3e0-2b66b9bb859b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24604
15 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2460415
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2914321938
Short name T702
Test name
Test status
Simulation time 7507417108 ps
CPU time 599.54 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 02:08:47 PM PDT 24
Peak memory 272444 kb
Host smart-62b2e335-9fcf-4d85-a128-3b5cd3cde0b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914321938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2914321938
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.93471174
Short name T695
Test name
Test status
Simulation time 124519893622 ps
CPU time 2043.75 seconds
Started May 28 01:58:45 PM PDT 24
Finished May 28 02:32:51 PM PDT 24
Peak memory 281592 kb
Host smart-818ff13b-77bb-47a4-afad-8e9c91317216
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93471174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.93471174
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1185116003
Short name T571
Test name
Test status
Simulation time 561925726 ps
CPU time 29.68 seconds
Started May 28 01:58:36 PM PDT 24
Finished May 28 01:59:08 PM PDT 24
Peak memory 248752 kb
Host smart-a8f21271-2e24-4a20-a9d6-d83daff0d05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
16003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1185116003
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2736204077
Short name T518
Test name
Test status
Simulation time 667271881 ps
CPU time 12.93 seconds
Started May 28 01:58:37 PM PDT 24
Finished May 28 01:58:52 PM PDT 24
Peak memory 254392 kb
Host smart-f3293437-2894-4677-ad1f-58d841495280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27362
04077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2736204077
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.675111464
Short name T364
Test name
Test status
Simulation time 1024728530 ps
CPU time 38.39 seconds
Started May 28 01:58:35 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 248760 kb
Host smart-baa20f50-ebf8-4ee6-96a7-06c4ff3b8a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67511
1464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.675111464
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3957772085
Short name T591
Test name
Test status
Simulation time 5032325122 ps
CPU time 308.65 seconds
Started May 28 01:58:48 PM PDT 24
Finished May 28 02:03:59 PM PDT 24
Peak memory 256956 kb
Host smart-ea894c61-6ecc-4bc6-8688-c33690d4579f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957772085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3957772085
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2039490236
Short name T212
Test name
Test status
Simulation time 18710074 ps
CPU time 2.9 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:58:52 PM PDT 24
Peak memory 248916 kb
Host smart-b7b8ecf6-20b5-44ef-82c6-de02e55ace23
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2039490236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2039490236
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2223870198
Short name T527
Test name
Test status
Simulation time 91233640948 ps
CPU time 2957.51 seconds
Started May 28 01:58:48 PM PDT 24
Finished May 28 02:48:08 PM PDT 24
Peak memory 288696 kb
Host smart-ba970fa0-9932-40ae-a265-7fec38c911d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223870198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2223870198
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.4003845955
Short name T694
Test name
Test status
Simulation time 259600200 ps
CPU time 14.14 seconds
Started May 28 01:58:45 PM PDT 24
Finished May 28 01:59:00 PM PDT 24
Peak memory 248784 kb
Host smart-2a570dba-6f39-4f1d-a879-d72a0b618d90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4003845955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.4003845955
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2845661438
Short name T696
Test name
Test status
Simulation time 3648726600 ps
CPU time 98.24 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 02:00:26 PM PDT 24
Peak memory 250896 kb
Host smart-d3f472ec-d5f4-4b03-81f9-4a98ec463758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
61438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2845661438
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.690620726
Short name T621
Test name
Test status
Simulation time 571130631 ps
CPU time 38.52 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 01:59:27 PM PDT 24
Peak memory 249016 kb
Host smart-82a3af38-7f2f-48ed-9be1-8902dac32305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69062
0726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.690620726
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3788805102
Short name T541
Test name
Test status
Simulation time 69851349207 ps
CPU time 2100.88 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 02:33:52 PM PDT 24
Peak memory 273428 kb
Host smart-d3c80a1c-1387-4ef2-b907-45c51915cfe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788805102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3788805102
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2752302392
Short name T300
Test name
Test status
Simulation time 17183166833 ps
CPU time 397.76 seconds
Started May 28 01:58:45 PM PDT 24
Finished May 28 02:05:24 PM PDT 24
Peak memory 247044 kb
Host smart-53b14ff4-9fe0-4c76-bb7f-d17100f3f7df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752302392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2752302392
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2749841380
Short name T363
Test name
Test status
Simulation time 3641657806 ps
CPU time 49.95 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 01:59:41 PM PDT 24
Peak memory 256968 kb
Host smart-4497ffa9-e83e-4e2f-af2e-ae635dc353b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
41380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2749841380
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.762960701
Short name T78
Test name
Test status
Simulation time 287463628 ps
CPU time 18.65 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 01:59:06 PM PDT 24
Peak memory 254224 kb
Host smart-0593f323-ecf0-4d7c-80d7-e9ae43e215c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76296
0701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.762960701
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.727801106
Short name T279
Test name
Test status
Simulation time 799885806 ps
CPU time 49.57 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 01:59:40 PM PDT 24
Peak memory 248536 kb
Host smart-76b2bc0e-13cb-46dc-b9e8-301e7766fec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72780
1106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.727801106
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.14608208
Short name T404
Test name
Test status
Simulation time 508982097 ps
CPU time 38.74 seconds
Started May 28 01:58:48 PM PDT 24
Finished May 28 01:59:29 PM PDT 24
Peak memory 249004 kb
Host smart-bddc7739-8157-42cc-af45-ce51ca3a2750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.14608208
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3072034683
Short name T43
Test name
Test status
Simulation time 133883844266 ps
CPU time 2120.66 seconds
Started May 28 01:58:52 PM PDT 24
Finished May 28 02:34:13 PM PDT 24
Peak memory 289696 kb
Host smart-8496daed-4afa-4435-bf3d-97153dfbb1ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072034683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3072034683
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1085867119
Short name T241
Test name
Test status
Simulation time 16254041111 ps
CPU time 248.46 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 02:02:59 PM PDT 24
Peak memory 272440 kb
Host smart-9044bbe2-964f-43c1-9374-66a9683a3bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085867119 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1085867119
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3347565891
Short name T110
Test name
Test status
Simulation time 69227928 ps
CPU time 2.48 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:58:52 PM PDT 24
Peak memory 248932 kb
Host smart-07206dee-7775-4195-bd82-f4d0c9ba93a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3347565891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3347565891
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2494153482
Short name T235
Test name
Test status
Simulation time 233662128284 ps
CPU time 3117.72 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 02:50:49 PM PDT 24
Peak memory 289512 kb
Host smart-14b18a84-bba8-4f23-afba-c97e79b31ab3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494153482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2494153482
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4162159184
Short name T530
Test name
Test status
Simulation time 185909858 ps
CPU time 10.39 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 01:59:01 PM PDT 24
Peak memory 240520 kb
Host smart-b2ac973b-c4e8-4720-8a17-09a582fca577
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4162159184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4162159184
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3534435177
Short name T650
Test name
Test status
Simulation time 4193206311 ps
CPU time 36.55 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:59:26 PM PDT 24
Peak memory 248968 kb
Host smart-3e10be50-3a20-42dc-a04f-d1e05497f138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
35177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3534435177
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1796820528
Short name T710
Test name
Test status
Simulation time 1033156706 ps
CPU time 36.36 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 01:59:24 PM PDT 24
Peak memory 248784 kb
Host smart-6cf743e6-2f14-4e8d-9311-51a2d563d195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17968
20528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1796820528
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3052648370
Short name T315
Test name
Test status
Simulation time 40807478873 ps
CPU time 722.46 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 02:10:50 PM PDT 24
Peak memory 265268 kb
Host smart-21e81da6-e626-48c6-b140-3f435914a746
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052648370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3052648370
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1757866518
Short name T471
Test name
Test status
Simulation time 6482594245 ps
CPU time 708.3 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 273044 kb
Host smart-2c3005d3-349f-4f4d-984d-e4d522f7ad39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757866518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1757866518
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4057621070
Short name T319
Test name
Test status
Simulation time 82368267057 ps
CPU time 585.02 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 02:08:35 PM PDT 24
Peak memory 247064 kb
Host smart-cf945f1b-7763-4615-846c-9b55e0687d32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057621070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4057621070
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1345982879
Short name T500
Test name
Test status
Simulation time 14985519211 ps
CPU time 49.13 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:59:39 PM PDT 24
Peak memory 248836 kb
Host smart-74090ec1-ade5-43f7-ac45-2046fe1af002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
82879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1345982879
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3108637578
Short name T586
Test name
Test status
Simulation time 1174309953 ps
CPU time 60.89 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 01:59:52 PM PDT 24
Peak memory 248856 kb
Host smart-c0427356-745d-426f-b1df-5465aa7bff5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31086
37578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3108637578
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3517199113
Short name T536
Test name
Test status
Simulation time 439420687 ps
CPU time 26.49 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 247580 kb
Host smart-b6154632-a89c-4a70-a8a8-1d25e9909b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35171
99113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3517199113
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2036906282
Short name T396
Test name
Test status
Simulation time 1001632011 ps
CPU time 25.14 seconds
Started May 28 01:58:45 PM PDT 24
Finished May 28 01:59:12 PM PDT 24
Peak memory 248772 kb
Host smart-2a583f53-527c-436f-be3c-15d6b8aa8df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20369
06282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2036906282
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2561158877
Short name T214
Test name
Test status
Simulation time 59889434 ps
CPU time 3.76 seconds
Started May 28 01:59:07 PM PDT 24
Finished May 28 01:59:12 PM PDT 24
Peak memory 248932 kb
Host smart-5e0b57af-77db-4321-bcdc-920d698ad627
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2561158877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2561158877
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3611897253
Short name T633
Test name
Test status
Simulation time 18723569694 ps
CPU time 1552.69 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 02:24:41 PM PDT 24
Peak memory 289100 kb
Host smart-876db6b5-dd00-4fd7-9ad2-6d1cbbd6b287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611897253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3611897253
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.670843085
Short name T556
Test name
Test status
Simulation time 974718575 ps
CPU time 12.77 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:18 PM PDT 24
Peak memory 248788 kb
Host smart-b5a05e1d-6b7e-4d67-b568-adf1b2e3b263
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=670843085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.670843085
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2161717089
Short name T472
Test name
Test status
Simulation time 14167016574 ps
CPU time 241.7 seconds
Started May 28 01:58:46 PM PDT 24
Finished May 28 02:02:49 PM PDT 24
Peak memory 256996 kb
Host smart-4d38b021-68e8-4066-90a9-e3549df5f39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
17089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2161717089
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.657489898
Short name T548
Test name
Test status
Simulation time 2371204135 ps
CPU time 33.24 seconds
Started May 28 01:58:49 PM PDT 24
Finished May 28 01:59:24 PM PDT 24
Peak memory 255988 kb
Host smart-0bca8b0e-34e0-40f0-b760-d86a65f57859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65748
9898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.657489898
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3852009443
Short name T419
Test name
Test status
Simulation time 106645860402 ps
CPU time 1953.83 seconds
Started May 28 01:59:02 PM PDT 24
Finished May 28 02:31:37 PM PDT 24
Peak memory 282712 kb
Host smart-5e705f17-8bfd-4aad-bb38-483716ecfe09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852009443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3852009443
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.671606365
Short name T305
Test name
Test status
Simulation time 183936542883 ps
CPU time 435.86 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 02:06:05 PM PDT 24
Peak memory 247988 kb
Host smart-3638847f-a624-4a56-90c0-7900cddc4199
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671606365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.671606365
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3492548385
Short name T383
Test name
Test status
Simulation time 868214116 ps
CPU time 15.57 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:59:04 PM PDT 24
Peak memory 248772 kb
Host smart-0a0d8304-5e81-4fee-bc92-fc96fa6989dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34925
48385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3492548385
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.752809168
Short name T117
Test name
Test status
Simulation time 156334379 ps
CPU time 7.24 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:58:57 PM PDT 24
Peak memory 253056 kb
Host smart-60f6a838-63c2-41fb-a409-635118873cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75280
9168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.752809168
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4174834609
Short name T97
Test name
Test status
Simulation time 3314119323 ps
CPU time 58.36 seconds
Started May 28 01:58:48 PM PDT 24
Finished May 28 01:59:48 PM PDT 24
Peak memory 255700 kb
Host smart-3a4216b3-629e-4b01-a87c-7e3e3c5aab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
34609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4174834609
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1548209326
Short name T549
Test name
Test status
Simulation time 141386018 ps
CPU time 13.04 seconds
Started May 28 01:58:47 PM PDT 24
Finished May 28 01:59:02 PM PDT 24
Peak memory 248752 kb
Host smart-5d5ef9dc-4d34-4361-88d4-d2f65d27fe9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15482
09326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1548209326
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2729096839
Short name T469
Test name
Test status
Simulation time 22689786399 ps
CPU time 1931.26 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 02:31:17 PM PDT 24
Peak memory 305376 kb
Host smart-d55804e3-b905-45cf-a5f3-3aa7fa100fbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729096839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2729096839
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1767686974
Short name T51
Test name
Test status
Simulation time 60546088299 ps
CPU time 5555.72 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 03:31:42 PM PDT 24
Peak memory 371148 kb
Host smart-4170c45e-a544-44e8-a00f-d60f705daffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767686974 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1767686974
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3792601883
Short name T207
Test name
Test status
Simulation time 86795448 ps
CPU time 4.02 seconds
Started May 28 01:59:02 PM PDT 24
Finished May 28 01:59:07 PM PDT 24
Peak memory 248936 kb
Host smart-98d55dc4-7c78-4c16-8fa2-327eb3f4d71c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3792601883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3792601883
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3641577401
Short name T462
Test name
Test status
Simulation time 143401653 ps
CPU time 8.52 seconds
Started May 28 01:59:05 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 248772 kb
Host smart-b9857a50-7129-4d27-81cc-71100dbd793a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3641577401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3641577401
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2452143489
Short name T182
Test name
Test status
Simulation time 17021800409 ps
CPU time 272.25 seconds
Started May 28 01:59:03 PM PDT 24
Finished May 28 02:03:36 PM PDT 24
Peak memory 257000 kb
Host smart-0325512d-421f-462a-bf96-47f6a6ff00d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
43489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2452143489
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3424861521
Short name T71
Test name
Test status
Simulation time 105149301 ps
CPU time 13.3 seconds
Started May 28 01:59:02 PM PDT 24
Finished May 28 01:59:17 PM PDT 24
Peak memory 254260 kb
Host smart-32e83ec6-e4a9-4dc5-bbff-d5ee1175d4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
61521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3424861521
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2032910783
Short name T713
Test name
Test status
Simulation time 57075349396 ps
CPU time 1522.7 seconds
Started May 28 01:59:07 PM PDT 24
Finished May 28 02:24:31 PM PDT 24
Peak memory 289344 kb
Host smart-47db0c6f-afe7-4bc4-85cb-e703dfeb4a7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032910783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2032910783
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1475922711
Short name T379
Test name
Test status
Simulation time 20644340894 ps
CPU time 1414.03 seconds
Started May 28 01:59:03 PM PDT 24
Finished May 28 02:22:38 PM PDT 24
Peak memory 272944 kb
Host smart-14988bae-2ee0-4d66-923e-862f1bc56e7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475922711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1475922711
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4269561181
Short name T299
Test name
Test status
Simulation time 31678637345 ps
CPU time 459.69 seconds
Started May 28 01:59:05 PM PDT 24
Finished May 28 02:06:46 PM PDT 24
Peak memory 248112 kb
Host smart-4c073298-6c19-4cc0-b239-c804d9911422
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269561181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4269561181
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2388070881
Short name T375
Test name
Test status
Simulation time 1579114283 ps
CPU time 33.56 seconds
Started May 28 01:59:07 PM PDT 24
Finished May 28 01:59:42 PM PDT 24
Peak memory 248768 kb
Host smart-7f158600-9bbb-40f2-9b50-7ccba433ce6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
70881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2388070881
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2452417151
Short name T705
Test name
Test status
Simulation time 1324366007 ps
CPU time 14.2 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:20 PM PDT 24
Peak memory 253220 kb
Host smart-042a981e-d99b-457c-850d-96f69768231b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24524
17151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2452417151
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2687886994
Short name T250
Test name
Test status
Simulation time 177043934 ps
CPU time 7.5 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:13 PM PDT 24
Peak memory 247432 kb
Host smart-d9ff5b10-2490-4503-b6ac-3ded59eb2084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26878
86994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2687886994
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.892370105
Short name T473
Test name
Test status
Simulation time 2200760799 ps
CPU time 60.98 seconds
Started May 28 01:59:02 PM PDT 24
Finished May 28 02:00:04 PM PDT 24
Peak memory 248964 kb
Host smart-891e175a-a094-4f2e-9a61-56692c099797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89237
0105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.892370105
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3758847764
Short name T211
Test name
Test status
Simulation time 16340077 ps
CPU time 2.6 seconds
Started May 28 01:59:06 PM PDT 24
Finished May 28 01:59:09 PM PDT 24
Peak memory 248932 kb
Host smart-153e914f-446b-42c3-91bc-1e3a2dadb0ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3758847764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3758847764
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.319242385
Short name T261
Test name
Test status
Simulation time 12544946218 ps
CPU time 1213.11 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 02:19:19 PM PDT 24
Peak memory 288068 kb
Host smart-d1a36aa5-9436-46cc-a0c1-4ef90013780b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319242385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.319242385
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1686265736
Short name T477
Test name
Test status
Simulation time 694959774 ps
CPU time 67.69 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 02:00:13 PM PDT 24
Peak memory 256808 kb
Host smart-8a8d982b-4c1f-447a-bf45-655018b19ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16862
65736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1686265736
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3494661138
Short name T626
Test name
Test status
Simulation time 742179238 ps
CPU time 34.21 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:40 PM PDT 24
Peak memory 248756 kb
Host smart-61e00bfd-5fad-46f2-975f-c6d6ecfaf4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
61138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3494661138
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.348701252
Short name T691
Test name
Test status
Simulation time 17268921201 ps
CPU time 749.94 seconds
Started May 28 01:59:05 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 270676 kb
Host smart-897490bc-db9d-4801-b5fe-6b8b699e5f63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348701252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.348701252
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1868848193
Short name T83
Test name
Test status
Simulation time 26695531589 ps
CPU time 1304.88 seconds
Started May 28 01:59:03 PM PDT 24
Finished May 28 02:20:49 PM PDT 24
Peak memory 281584 kb
Host smart-703a1ee3-3f9e-43a4-b6dd-7f7bdebde241
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868848193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1868848193
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1813461600
Short name T239
Test name
Test status
Simulation time 3126208410 ps
CPU time 63.64 seconds
Started May 28 01:59:03 PM PDT 24
Finished May 28 02:00:08 PM PDT 24
Peak memory 248268 kb
Host smart-298bdb23-41cf-4a1a-baca-5d33aa45dac7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813461600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1813461600
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3310954135
Short name T654
Test name
Test status
Simulation time 314534483 ps
CPU time 21.97 seconds
Started May 28 01:59:06 PM PDT 24
Finished May 28 01:59:29 PM PDT 24
Peak memory 256924 kb
Host smart-e34743fa-9403-42f8-b535-ad4d6184328a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33109
54135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3310954135
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3613498238
Short name T371
Test name
Test status
Simulation time 1343823280 ps
CPU time 55.2 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 02:00:00 PM PDT 24
Peak memory 248752 kb
Host smart-013b3552-d1f7-4ce5-9bbb-50dc3c749f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36134
98238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3613498238
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2053245282
Short name T555
Test name
Test status
Simulation time 727262704 ps
CPU time 21.84 seconds
Started May 28 01:59:07 PM PDT 24
Finished May 28 01:59:30 PM PDT 24
Peak memory 256304 kb
Host smart-5fbdff5a-bc82-45fc-b438-7b37bcf742dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20532
45282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2053245282
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1123980838
Short name T361
Test name
Test status
Simulation time 291979961 ps
CPU time 14.43 seconds
Started May 28 01:59:05 PM PDT 24
Finished May 28 01:59:21 PM PDT 24
Peak memory 248776 kb
Host smart-4fa6c905-472c-4b57-9548-aeca349e00c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11239
80838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1123980838
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1794675502
Short name T75
Test name
Test status
Simulation time 10896959639 ps
CPU time 213.74 seconds
Started May 28 01:59:07 PM PDT 24
Finished May 28 02:02:42 PM PDT 24
Peak memory 256104 kb
Host smart-ad794536-9b61-4ee4-8608-d6501e8380d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794675502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1794675502
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1467621696
Short name T205
Test name
Test status
Simulation time 166967531 ps
CPU time 3.3 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:26 PM PDT 24
Peak memory 248916 kb
Host smart-1a5a9941-85f1-4779-a081-e1a240d38410
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1467621696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1467621696
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.560490836
Short name T441
Test name
Test status
Simulation time 13306052823 ps
CPU time 1269.21 seconds
Started May 28 01:59:22 PM PDT 24
Finished May 28 02:20:34 PM PDT 24
Peak memory 288832 kb
Host smart-e405b98d-b110-4bba-a885-02835ad00fd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560490836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.560490836
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1948664767
Short name T200
Test name
Test status
Simulation time 815517573 ps
CPU time 13.37 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 01:59:38 PM PDT 24
Peak memory 248752 kb
Host smart-84b83523-2f38-4a58-b424-0ec276933b03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1948664767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1948664767
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.103519294
Short name T660
Test name
Test status
Simulation time 15020406113 ps
CPU time 117.34 seconds
Started May 28 01:59:19 PM PDT 24
Finished May 28 02:01:18 PM PDT 24
Peak memory 256180 kb
Host smart-08e274be-9c1a-429c-bb26-feac13525954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10351
9294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.103519294
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2175126717
Short name T259
Test name
Test status
Simulation time 167806816 ps
CPU time 7.53 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:30 PM PDT 24
Peak memory 249196 kb
Host smart-206820d3-c688-4cf7-9d90-bdc266fadd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
26717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2175126717
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.969472420
Short name T410
Test name
Test status
Simulation time 37919907382 ps
CPU time 842.47 seconds
Started May 28 01:59:18 PM PDT 24
Finished May 28 02:13:22 PM PDT 24
Peak memory 272860 kb
Host smart-c2a57c32-4475-427f-931c-b4226b3074bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969472420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.969472420
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.4004458922
Short name T322
Test name
Test status
Simulation time 12547793850 ps
CPU time 502.55 seconds
Started May 28 01:59:19 PM PDT 24
Finished May 28 02:07:44 PM PDT 24
Peak memory 248328 kb
Host smart-cac7af54-005c-438e-a512-7bdccbc87b49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004458922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.4004458922
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.569542222
Short name T366
Test name
Test status
Simulation time 1268264580 ps
CPU time 21.62 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:27 PM PDT 24
Peak memory 256908 kb
Host smart-17938089-0501-4e96-ae05-2d3a81620c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56954
2222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.569542222
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.374648518
Short name T522
Test name
Test status
Simulation time 1172356877 ps
CPU time 26.07 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:49 PM PDT 24
Peak memory 248808 kb
Host smart-94bab84d-9579-4fcd-ad6d-fd926f5ab751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464
8518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.374648518
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1347655339
Short name T287
Test name
Test status
Simulation time 2293217025 ps
CPU time 43.02 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 02:00:05 PM PDT 24
Peak memory 248832 kb
Host smart-54d9d3a8-0b16-44ad-b9bc-d2dd8b7eca25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13476
55339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1347655339
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.394830400
Short name T412
Test name
Test status
Simulation time 661455652 ps
CPU time 19.96 seconds
Started May 28 01:59:04 PM PDT 24
Finished May 28 01:59:25 PM PDT 24
Peak memory 256224 kb
Host smart-b9de8b5b-776f-47ad-98ad-e5fab27852c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
0400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.394830400
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2362804570
Short name T646
Test name
Test status
Simulation time 59069925162 ps
CPU time 1233.1 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:19:57 PM PDT 24
Peak memory 288836 kb
Host smart-d5759091-7c46-47fc-a7bd-d1b1e082dee7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362804570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2362804570
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.746851334
Short name T179
Test name
Test status
Simulation time 280324222498 ps
CPU time 3678.6 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 03:00:41 PM PDT 24
Peak memory 322144 kb
Host smart-f43b1781-f542-45d9-b5b8-e0b29c661a92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746851334 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.746851334
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.647823860
Short name T210
Test name
Test status
Simulation time 51667176 ps
CPU time 3.77 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:09 PM PDT 24
Peak memory 248920 kb
Host smart-fa2a34ac-b5b4-4dd5-ba72-1d0bcdc7ae90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=647823860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.647823860
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1902518622
Short name T658
Test name
Test status
Simulation time 779912074 ps
CPU time 10.6 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:15 PM PDT 24
Peak memory 248796 kb
Host smart-40e6196c-e3ad-483e-aebe-0fdfbca767da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1902518622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1902518622
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3400630621
Short name T637
Test name
Test status
Simulation time 3654115460 ps
CPU time 128.17 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 02:00:11 PM PDT 24
Peak memory 256956 kb
Host smart-d104bf7c-25fb-4325-93fa-0cfbfaa08844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34006
30621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3400630621
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2616305753
Short name T631
Test name
Test status
Simulation time 2771754247 ps
CPU time 22.78 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:28 PM PDT 24
Peak memory 254828 kb
Host smart-0c840d49-e50e-4664-ab37-2ab41be3c997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26163
05753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2616305753
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4040735380
Short name T2
Test name
Test status
Simulation time 618662706629 ps
CPU time 2800.1 seconds
Started May 28 01:58:04 PM PDT 24
Finished May 28 02:44:48 PM PDT 24
Peak memory 289384 kb
Host smart-56983594-c6dc-428e-9249-eda30a3e1a87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040735380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4040735380
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2147711796
Short name T36
Test name
Test status
Simulation time 12614305529 ps
CPU time 1326.24 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 02:20:12 PM PDT 24
Peak memory 289556 kb
Host smart-1c9cd2ac-1a3f-42d5-b6af-16f020c9b180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147711796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2147711796
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.769321581
Short name T260
Test name
Test status
Simulation time 33179415355 ps
CPU time 321.42 seconds
Started May 28 01:57:59 PM PDT 24
Finished May 28 02:03:22 PM PDT 24
Peak memory 248344 kb
Host smart-dd515090-f5e9-4f6a-afb8-e1668910ad95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769321581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.769321581
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1027067183
Short name T604
Test name
Test status
Simulation time 152426512 ps
CPU time 6.43 seconds
Started May 28 01:58:03 PM PDT 24
Finished May 28 01:58:13 PM PDT 24
Peak memory 240580 kb
Host smart-e20ec893-13bb-4345-b5a6-2888e189f733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
67183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1027067183
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4184999111
Short name T34
Test name
Test status
Simulation time 1015536022 ps
CPU time 11.01 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:17 PM PDT 24
Peak memory 247316 kb
Host smart-c0a94402-5157-4c43-abaf-d5d86a9aef97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41849
99111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4184999111
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4137015811
Short name T27
Test name
Test status
Simulation time 1171844195 ps
CPU time 53.27 seconds
Started May 28 01:58:03 PM PDT 24
Finished May 28 01:59:00 PM PDT 24
Peak memory 270860 kb
Host smart-84dd32d6-86cd-4337-bcee-e963ccf5e4ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4137015811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4137015811
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3055113114
Short name T65
Test name
Test status
Simulation time 105602146 ps
CPU time 7.52 seconds
Started May 28 01:58:09 PM PDT 24
Finished May 28 01:58:18 PM PDT 24
Peak memory 249472 kb
Host smart-210d687a-69ab-479d-828a-d0121f2c0c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
13114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3055113114
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2192980330
Short name T388
Test name
Test status
Simulation time 2130828436 ps
CPU time 34.46 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 01:58:37 PM PDT 24
Peak memory 255960 kb
Host smart-8e31f4c3-ed69-446c-826d-7538cdf161e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
80330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2192980330
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1772730622
Short name T629
Test name
Test status
Simulation time 208807329321 ps
CPU time 2692.12 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 02:42:55 PM PDT 24
Peak memory 298068 kb
Host smart-272ff0bb-0160-4f74-b165-c1571b504013
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772730622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1772730622
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.4216153323
Short name T118
Test name
Test status
Simulation time 570995021612 ps
CPU time 9854.65 seconds
Started May 28 01:58:00 PM PDT 24
Finished May 28 04:42:19 PM PDT 24
Peak memory 338276 kb
Host smart-030adb5c-e6df-451c-9b30-1f148ec1eb8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216153323 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.4216153323
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1474428944
Short name T245
Test name
Test status
Simulation time 5410108915 ps
CPU time 155.61 seconds
Started May 28 01:59:19 PM PDT 24
Finished May 28 02:01:57 PM PDT 24
Peak memory 256788 kb
Host smart-e7a8d0f3-ec9b-4a91-8b83-c5e885f555c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
28944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1474428944
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.471264623
Short name T575
Test name
Test status
Simulation time 1235727528 ps
CPU time 19.89 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:42 PM PDT 24
Peak memory 254756 kb
Host smart-e27d68c7-9ac8-4096-be92-3ff8a8125e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47126
4623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.471264623
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2912167600
Short name T184
Test name
Test status
Simulation time 17161566191 ps
CPU time 1364.23 seconds
Started May 28 01:59:18 PM PDT 24
Finished May 28 02:22:04 PM PDT 24
Peak memory 289200 kb
Host smart-4616d750-cd98-4f8c-afa4-cc5db7ea663d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912167600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2912167600
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1987284193
Short name T417
Test name
Test status
Simulation time 34535583885 ps
CPU time 1444.3 seconds
Started May 28 01:59:23 PM PDT 24
Finished May 28 02:23:30 PM PDT 24
Peak memory 289700 kb
Host smart-d6ca6239-d0cd-4c48-8db5-f95639add524
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987284193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1987284193
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1068716469
Short name T6
Test name
Test status
Simulation time 12728343607 ps
CPU time 137.28 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:01:42 PM PDT 24
Peak memory 247100 kb
Host smart-329d1f5b-cad0-46b8-ba11-afeeac215ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068716469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1068716469
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3188921588
Short name T528
Test name
Test status
Simulation time 1569403416 ps
CPU time 33.35 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:56 PM PDT 24
Peak memory 248716 kb
Host smart-b6b7f206-9269-4ca3-863e-99f123dd3be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31889
21588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3188921588
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2519188273
Short name T389
Test name
Test status
Simulation time 55553048 ps
CPU time 4.78 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:27 PM PDT 24
Peak memory 248756 kb
Host smart-7d6675d6-fbf1-41d7-bba3-c4e8b02073ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25191
88273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2519188273
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1312802450
Short name T542
Test name
Test status
Simulation time 221659991 ps
CPU time 15.14 seconds
Started May 28 01:59:23 PM PDT 24
Finished May 28 01:59:40 PM PDT 24
Peak memory 254920 kb
Host smart-33afbfbb-b782-4c2e-b7b1-98533dc64b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13128
02450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1312802450
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2578290682
Short name T365
Test name
Test status
Simulation time 101760427 ps
CPU time 12.26 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 01:59:35 PM PDT 24
Peak memory 248752 kb
Host smart-01a116e2-c95b-4468-b49c-1807694f6c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
90682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2578290682
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1174139662
Short name T630
Test name
Test status
Simulation time 3651239156 ps
CPU time 94.05 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 02:00:57 PM PDT 24
Peak memory 255244 kb
Host smart-b95f63ed-21a7-4a33-8cd6-04076f328aa6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174139662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1174139662
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3698319381
Short name T291
Test name
Test status
Simulation time 228376521529 ps
CPU time 5417.84 seconds
Started May 28 01:59:22 PM PDT 24
Finished May 28 03:29:43 PM PDT 24
Peak memory 338536 kb
Host smart-39ea1046-16bf-49a1-a02f-55820ba906be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698319381 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3698319381
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1361635223
Short name T464
Test name
Test status
Simulation time 42110281763 ps
CPU time 2565.32 seconds
Started May 28 01:59:18 PM PDT 24
Finished May 28 02:42:05 PM PDT 24
Peak memory 289824 kb
Host smart-6e12cca3-9bec-4cf4-9532-6b319acf6843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361635223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1361635223
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2812073242
Short name T641
Test name
Test status
Simulation time 19114431495 ps
CPU time 290.58 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 02:04:13 PM PDT 24
Peak memory 256904 kb
Host smart-9dd494e0-3986-42fc-9fb8-27dfc00a71da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28120
73242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2812073242
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1323849858
Short name T590
Test name
Test status
Simulation time 230323959 ps
CPU time 16.23 seconds
Started May 28 01:59:22 PM PDT 24
Finished May 28 01:59:41 PM PDT 24
Peak memory 255588 kb
Host smart-c4030ca5-0556-47e8-95e5-d7cdf1b2783a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13238
49858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1323849858
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3654290273
Short name T303
Test name
Test status
Simulation time 29981663345 ps
CPU time 1278.08 seconds
Started May 28 01:59:19 PM PDT 24
Finished May 28 02:20:40 PM PDT 24
Peak memory 286652 kb
Host smart-56b1a3a0-3c2f-4c03-984b-dab700e86952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654290273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3654290273
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3270556811
Short name T593
Test name
Test status
Simulation time 10514483285 ps
CPU time 925.28 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:14:49 PM PDT 24
Peak memory 273436 kb
Host smart-d609df44-5493-403c-9953-89f789d02bdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270556811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3270556811
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.366158904
Short name T386
Test name
Test status
Simulation time 1018873898 ps
CPU time 13.95 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 01:59:38 PM PDT 24
Peak memory 248568 kb
Host smart-ba31e425-adf3-469e-ae96-25c7cad81b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
8904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.366158904
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4041858894
Short name T55
Test name
Test status
Simulation time 1230742199 ps
CPU time 16.96 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 01:59:41 PM PDT 24
Peak memory 255820 kb
Host smart-cf2da765-c034-4274-9b4a-b115e39a2fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40418
58894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4041858894
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4101043883
Short name T706
Test name
Test status
Simulation time 789698887 ps
CPU time 25.07 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:47 PM PDT 24
Peak memory 256516 kb
Host smart-cda472f6-02a7-48a1-82ec-94fad23a15fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41010
43883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4101043883
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1573191486
Short name T578
Test name
Test status
Simulation time 1305533782 ps
CPU time 28.55 seconds
Started May 28 01:59:22 PM PDT 24
Finished May 28 01:59:53 PM PDT 24
Peak memory 256052 kb
Host smart-00e12a5a-c73d-468b-8d79-2da750150f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
91486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1573191486
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2328529189
Short name T11
Test name
Test status
Simulation time 24435138162 ps
CPU time 1834.41 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:29:58 PM PDT 24
Peak memory 302848 kb
Host smart-9a10def0-ca59-453f-8ee7-38d28967b57f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328529189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2328529189
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2389148773
Short name T280
Test name
Test status
Simulation time 21898322751 ps
CPU time 2077.7 seconds
Started May 28 01:59:23 PM PDT 24
Finished May 28 02:34:03 PM PDT 24
Peak memory 305700 kb
Host smart-81740405-e485-48eb-9fae-cd1792a84c17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389148773 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2389148773
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1529590255
Short name T265
Test name
Test status
Simulation time 50139328012 ps
CPU time 1501.82 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 02:24:24 PM PDT 24
Peak memory 273424 kb
Host smart-c81ec818-2dcf-4923-bbbf-33b165a11ec7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529590255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1529590255
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1461371743
Short name T203
Test name
Test status
Simulation time 1306655465 ps
CPU time 84.71 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 02:00:47 PM PDT 24
Peak memory 256540 kb
Host smart-dcbbf410-4aa4-4b06-a13c-22a0b317f489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14613
71743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1461371743
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.485817142
Short name T613
Test name
Test status
Simulation time 2536713562 ps
CPU time 39.86 seconds
Started May 28 01:59:18 PM PDT 24
Finished May 28 01:59:59 PM PDT 24
Peak memory 248824 kb
Host smart-551a38df-7ba3-4300-b8b2-a497fc9cdfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48581
7142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.485817142
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1779045631
Short name T342
Test name
Test status
Simulation time 50395525206 ps
CPU time 2651.52 seconds
Started May 28 01:59:23 PM PDT 24
Finished May 28 02:43:37 PM PDT 24
Peak memory 286704 kb
Host smart-7717ef78-bafb-44a1-9714-73bdd0eae889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779045631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1779045631
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2549270368
Short name T679
Test name
Test status
Simulation time 15750238350 ps
CPU time 1410.62 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 02:22:52 PM PDT 24
Peak memory 281604 kb
Host smart-699f6010-f01e-4ebc-b26b-beb054279c1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549270368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2549270368
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1414226536
Short name T504
Test name
Test status
Simulation time 2373218505 ps
CPU time 91.42 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 02:00:55 PM PDT 24
Peak memory 248364 kb
Host smart-850752d7-101f-45fd-aa79-548951c7b2e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414226536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1414226536
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3921201438
Short name T479
Test name
Test status
Simulation time 533294863 ps
CPU time 8.3 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 01:59:32 PM PDT 24
Peak memory 240824 kb
Host smart-838a698b-043b-4091-aa6f-dcbbf7f3b57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39212
01438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3921201438
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3219981135
Short name T380
Test name
Test status
Simulation time 974317187 ps
CPU time 17.78 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:41 PM PDT 24
Peak memory 255112 kb
Host smart-7db00ae3-c427-41b0-ac8b-0074d4608fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32199
81135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3219981135
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2527928542
Short name T73
Test name
Test status
Simulation time 1442034830 ps
CPU time 25.98 seconds
Started May 28 01:59:20 PM PDT 24
Finished May 28 01:59:49 PM PDT 24
Peak memory 255388 kb
Host smart-bcc02aae-2705-4b6a-937d-5569ba70cf17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
28542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2527928542
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3270726350
Short name T638
Test name
Test status
Simulation time 84539776 ps
CPU time 6.21 seconds
Started May 28 01:59:22 PM PDT 24
Finished May 28 01:59:31 PM PDT 24
Peak memory 248740 kb
Host smart-83a4a7ff-70f7-435c-9ee0-32c46f8167d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32707
26350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3270726350
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4241298070
Short name T82
Test name
Test status
Simulation time 58681364249 ps
CPU time 3151.49 seconds
Started May 28 01:59:23 PM PDT 24
Finished May 28 02:51:57 PM PDT 24
Peak memory 289008 kb
Host smart-a6d3c003-ce5f-4ce4-ac7e-7b6a72979382
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241298070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4241298070
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2996334051
Short name T278
Test name
Test status
Simulation time 74060754503 ps
CPU time 1941.31 seconds
Started May 28 01:59:18 PM PDT 24
Finished May 28 02:31:41 PM PDT 24
Peak memory 306000 kb
Host smart-00679356-9263-4453-8ed9-9deb80f25aa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996334051 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2996334051
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.4023204070
Short name T407
Test name
Test status
Simulation time 9841402227 ps
CPU time 983.37 seconds
Started May 28 01:59:32 PM PDT 24
Finished May 28 02:15:57 PM PDT 24
Peak memory 286500 kb
Host smart-4ea461ec-8f0f-45f3-a488-b0d610f7dd6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023204070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.4023204070
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.4102737715
Short name T457
Test name
Test status
Simulation time 17276077711 ps
CPU time 274.27 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:04:11 PM PDT 24
Peak memory 256556 kb
Host smart-81f43ca4-6c97-486f-ba1a-adc56ea7094b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41027
37715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.4102737715
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.997436295
Short name T262
Test name
Test status
Simulation time 321685529 ps
CPU time 33.96 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:00:09 PM PDT 24
Peak memory 255964 kb
Host smart-cb5da628-7fca-4af3-8416-7650e740e3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99743
6295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.997436295
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.510843916
Short name T240
Test name
Test status
Simulation time 7405667582 ps
CPU time 717 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:11:32 PM PDT 24
Peak memory 267512 kb
Host smart-596a80e8-e242-4794-9a8e-088b448827f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510843916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.510843916
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.680563916
Short name T692
Test name
Test status
Simulation time 10654238442 ps
CPU time 452.5 seconds
Started May 28 01:59:30 PM PDT 24
Finished May 28 02:07:04 PM PDT 24
Peak memory 247084 kb
Host smart-b1ad5fcb-16af-4c44-a80a-22e3957aed49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680563916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.680563916
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1164573841
Short name T681
Test name
Test status
Simulation time 658178709 ps
CPU time 46 seconds
Started May 28 01:59:30 PM PDT 24
Finished May 28 02:00:18 PM PDT 24
Peak memory 248752 kb
Host smart-15d174dd-a2f9-4099-8f27-2760c4191eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
73841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1164573841
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1025292095
Short name T595
Test name
Test status
Simulation time 122858282 ps
CPU time 6.54 seconds
Started May 28 01:59:31 PM PDT 24
Finished May 28 01:59:39 PM PDT 24
Peak memory 252936 kb
Host smart-e83b1f3a-b06c-408a-a195-bc11f0c02a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10252
92095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1025292095
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.955821909
Short name T3
Test name
Test status
Simulation time 6050535414 ps
CPU time 52.75 seconds
Started May 28 01:59:30 PM PDT 24
Finished May 28 02:00:24 PM PDT 24
Peak memory 248840 kb
Host smart-ed6b973e-726f-482b-a42a-4257d4781502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95582
1909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.955821909
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.981723084
Short name T39
Test name
Test status
Simulation time 317170180 ps
CPU time 4.56 seconds
Started May 28 01:59:21 PM PDT 24
Finished May 28 01:59:28 PM PDT 24
Peak memory 240576 kb
Host smart-d7cde5b8-c392-4b77-9806-07af869c8172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98172
3084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.981723084
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3688190573
Short name T572
Test name
Test status
Simulation time 27594030700 ps
CPU time 699.72 seconds
Started May 28 01:59:30 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 269416 kb
Host smart-5ae79d5f-7c28-4b34-ab42-f263d9d46f4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688190573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3688190573
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.981833869
Short name T573
Test name
Test status
Simulation time 529036987 ps
CPU time 18.12 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 01:59:54 PM PDT 24
Peak memory 255312 kb
Host smart-075a1948-3593-4198-a188-fdbf53069317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98183
3869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.981833869
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3636860864
Short name T332
Test name
Test status
Simulation time 127263554296 ps
CPU time 1894.64 seconds
Started May 28 01:59:35 PM PDT 24
Finished May 28 02:31:12 PM PDT 24
Peak memory 269180 kb
Host smart-490efb7e-7c60-43b9-a259-f2f817dcb3dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636860864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3636860864
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1936903042
Short name T596
Test name
Test status
Simulation time 21553232384 ps
CPU time 1264.9 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:20:41 PM PDT 24
Peak memory 289396 kb
Host smart-a3ef45d4-b564-4c06-b678-a35de0bdefd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936903042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1936903042
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1837308018
Short name T311
Test name
Test status
Simulation time 2716903249 ps
CPU time 101.51 seconds
Started May 28 01:59:31 PM PDT 24
Finished May 28 02:01:14 PM PDT 24
Peak memory 248244 kb
Host smart-83844967-a2e0-4040-911b-fb78f9cdc42b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837308018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1837308018
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.4092104821
Short name T425
Test name
Test status
Simulation time 908940282 ps
CPU time 13.49 seconds
Started May 28 01:59:30 PM PDT 24
Finished May 28 01:59:44 PM PDT 24
Peak memory 248760 kb
Host smart-38b6d2a0-5ae2-4577-a7d8-f8c31a8809eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
04821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.4092104821
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3493999582
Short name T563
Test name
Test status
Simulation time 302442360 ps
CPU time 23.99 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 01:59:59 PM PDT 24
Peak memory 256420 kb
Host smart-a741b534-5c65-4f74-9e46-318f1680fde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
99582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3493999582
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1239887794
Short name T458
Test name
Test status
Simulation time 2080859174 ps
CPU time 43.73 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:00:20 PM PDT 24
Peak memory 247708 kb
Host smart-a8f875e0-da56-44c9-bd3a-15f2803329a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12398
87794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1239887794
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2180645427
Short name T667
Test name
Test status
Simulation time 313794329 ps
CPU time 9.57 seconds
Started May 28 01:59:36 PM PDT 24
Finished May 28 01:59:47 PM PDT 24
Peak memory 248776 kb
Host smart-a486c709-b8bc-430f-b4f5-3942d143e53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21806
45427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2180645427
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.421456586
Short name T488
Test name
Test status
Simulation time 7603351253 ps
CPU time 416.99 seconds
Started May 28 01:59:31 PM PDT 24
Finished May 28 02:06:30 PM PDT 24
Peak memory 254672 kb
Host smart-e78d854b-df31-44a3-bcc1-c9e6a4be2103
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421456586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.421456586
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3393591781
Short name T94
Test name
Test status
Simulation time 8773790707 ps
CPU time 762.43 seconds
Started May 28 01:59:36 PM PDT 24
Finished May 28 02:12:20 PM PDT 24
Peak memory 272708 kb
Host smart-bf3b96d2-b2a2-4154-b2ed-a0654345f48b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393591781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3393591781
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3555086935
Short name T40
Test name
Test status
Simulation time 5225309322 ps
CPU time 135.88 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:01:52 PM PDT 24
Peak memory 256936 kb
Host smart-5c8addad-e03d-4677-ba4a-5a3e6b7e5754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
86935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3555086935
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3462187331
Short name T468
Test name
Test status
Simulation time 522567631 ps
CPU time 12.87 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 01:59:49 PM PDT 24
Peak memory 248748 kb
Host smart-0cacb371-b985-4bbc-a27d-d09046840266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34621
87331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3462187331
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2932460725
Short name T338
Test name
Test status
Simulation time 10852763804 ps
CPU time 800.39 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 272472 kb
Host smart-5c5f2e45-3510-4c77-bdb0-bada02e0475d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932460725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2932460725
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2721118572
Short name T619
Test name
Test status
Simulation time 71702092919 ps
CPU time 2335.91 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:38:32 PM PDT 24
Peak memory 289704 kb
Host smart-831284af-9d12-4b5f-9c00-6bb8114d47f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721118572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2721118572
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.986697251
Short name T309
Test name
Test status
Simulation time 23928119852 ps
CPU time 496.87 seconds
Started May 28 01:59:32 PM PDT 24
Finished May 28 02:07:52 PM PDT 24
Peak memory 254832 kb
Host smart-6f9708d7-ace7-4b82-a146-42ce8575067b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986697251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.986697251
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2550971300
Short name T625
Test name
Test status
Simulation time 450365489 ps
CPU time 27.06 seconds
Started May 28 01:59:31 PM PDT 24
Finished May 28 01:59:59 PM PDT 24
Peak memory 248764 kb
Host smart-e35a494e-548a-4274-b030-81167b89f8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25509
71300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2550971300
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1541630166
Short name T38
Test name
Test status
Simulation time 1067740567 ps
CPU time 32.74 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:00:08 PM PDT 24
Peak memory 248780 kb
Host smart-1b373c06-1a9f-41a6-bfa7-60412fd63752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
30166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1541630166
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2645630692
Short name T474
Test name
Test status
Simulation time 86010169 ps
CPU time 10.91 seconds
Started May 28 01:59:36 PM PDT 24
Finished May 28 01:59:49 PM PDT 24
Peak memory 255008 kb
Host smart-333f3daf-0470-4395-8d02-90a22bf76a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26456
30692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2645630692
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2778643195
Short name T204
Test name
Test status
Simulation time 164432115 ps
CPU time 21.53 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 01:59:57 PM PDT 24
Peak memory 249036 kb
Host smart-77b9a65b-1068-45f9-a6e8-fd2b0bd1790f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786
43195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2778643195
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2308708046
Short name T647
Test name
Test status
Simulation time 133517688320 ps
CPU time 2083.84 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:34:20 PM PDT 24
Peak memory 284552 kb
Host smart-a7af3673-59a0-4e0a-be14-d1d56dcdab5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308708046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2308708046
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.885581840
Short name T709
Test name
Test status
Simulation time 62949305429 ps
CPU time 2181.68 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:35:58 PM PDT 24
Peak memory 287016 kb
Host smart-ce112abd-fe40-42ac-ab6e-9e0541885030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885581840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.885581840
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.4122170498
Short name T269
Test name
Test status
Simulation time 8096833499 ps
CPU time 193.33 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:02:50 PM PDT 24
Peak memory 256872 kb
Host smart-9fa0a150-8229-4c17-812e-ae55415d32d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41221
70498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4122170498
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4256423631
Short name T627
Test name
Test status
Simulation time 1309845640 ps
CPU time 29.11 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 02:00:05 PM PDT 24
Peak memory 248784 kb
Host smart-84ce0cad-263d-4ea7-82c9-8b6ef1ce094c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42564
23631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4256423631
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.837392285
Short name T331
Test name
Test status
Simulation time 14887405660 ps
CPU time 1196.28 seconds
Started May 28 01:59:35 PM PDT 24
Finished May 28 02:19:34 PM PDT 24
Peak memory 282180 kb
Host smart-91017103-af9f-4845-9301-3c1c8f711057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837392285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.837392285
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3557910547
Short name T437
Test name
Test status
Simulation time 36332162937 ps
CPU time 2042.8 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:33:47 PM PDT 24
Peak memory 281660 kb
Host smart-5bb09585-4ce4-4601-a21b-e6d3f62f1d37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557910547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3557910547
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3156182537
Short name T324
Test name
Test status
Simulation time 12808730489 ps
CPU time 535.8 seconds
Started May 28 01:59:32 PM PDT 24
Finished May 28 02:08:31 PM PDT 24
Peak memory 248072 kb
Host smart-f2edc371-4aea-4f3d-8be2-782deaeb8757
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156182537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3156182537
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.468202609
Short name T403
Test name
Test status
Simulation time 780448691 ps
CPU time 44.91 seconds
Started May 28 01:59:32 PM PDT 24
Finished May 28 02:00:19 PM PDT 24
Peak memory 248780 kb
Host smart-bffc6029-78a8-4ab2-a3c1-a54a9e653a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46820
2609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.468202609
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2413614750
Short name T670
Test name
Test status
Simulation time 2436053293 ps
CPU time 37.1 seconds
Started May 28 01:59:30 PM PDT 24
Finished May 28 02:00:09 PM PDT 24
Peak memory 248808 kb
Host smart-5663fa18-99b9-4b1b-90c2-a69daee339c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24136
14750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2413614750
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2315058901
Short name T598
Test name
Test status
Simulation time 152616388 ps
CPU time 6.42 seconds
Started May 28 01:59:33 PM PDT 24
Finished May 28 01:59:42 PM PDT 24
Peak memory 247456 kb
Host smart-68d90877-94bf-4d84-9537-56981e4e4be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23150
58901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2315058901
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1489587193
Short name T502
Test name
Test status
Simulation time 2329688264 ps
CPU time 35.92 seconds
Started May 28 01:59:34 PM PDT 24
Finished May 28 02:00:12 PM PDT 24
Peak memory 256992 kb
Host smart-b1695045-4d89-482c-a709-99e5485d9058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
87193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1489587193
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2927711928
Short name T62
Test name
Test status
Simulation time 23940683058 ps
CPU time 293.51 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:04:39 PM PDT 24
Peak memory 257012 kb
Host smart-297f9f61-09ee-4247-ae8b-05bce1957f1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927711928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2927711928
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.867582128
Short name T557
Test name
Test status
Simulation time 117842870841 ps
CPU time 1901.01 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 02:31:24 PM PDT 24
Peak memory 286372 kb
Host smart-1b9ae5ee-7929-433a-a8ef-8aa514e7325b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867582128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.867582128
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.534811323
Short name T624
Test name
Test status
Simulation time 3737787976 ps
CPU time 260.04 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 02:04:03 PM PDT 24
Peak memory 256964 kb
Host smart-2294cadb-38ff-4679-850c-d573d946707f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53481
1323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.534811323
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2382065455
Short name T508
Test name
Test status
Simulation time 1818901943 ps
CPU time 57.39 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:00:41 PM PDT 24
Peak memory 255328 kb
Host smart-d99f09a8-530d-4cc1-9f26-47226544ccda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
65455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2382065455
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3032798003
Short name T336
Test name
Test status
Simulation time 13256852258 ps
CPU time 996.45 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 02:16:19 PM PDT 24
Peak memory 288820 kb
Host smart-b4ef3569-71b4-447e-be02-0bb04a559f5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032798003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3032798003
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2340581931
Short name T499
Test name
Test status
Simulation time 138927922648 ps
CPU time 2053.44 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 02:33:57 PM PDT 24
Peak memory 289776 kb
Host smart-9c017156-d15c-4be5-9ace-e70c9d647865
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340581931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2340581931
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2670462613
Short name T304
Test name
Test status
Simulation time 6102845780 ps
CPU time 241.12 seconds
Started May 28 01:59:44 PM PDT 24
Finished May 28 02:03:47 PM PDT 24
Peak memory 248184 kb
Host smart-955aedfc-1f69-4385-931a-c51704c0d053
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670462613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2670462613
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.771008097
Short name T367
Test name
Test status
Simulation time 747806664 ps
CPU time 6.67 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 01:59:50 PM PDT 24
Peak memory 248772 kb
Host smart-0c7f06f5-4b8b-4920-92b0-ddb95e0aeba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77100
8097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.771008097
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1765143036
Short name T435
Test name
Test status
Simulation time 182484584 ps
CPU time 16.12 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:00:02 PM PDT 24
Peak memory 254952 kb
Host smart-53149cd9-26e4-47f9-ae03-1cece4b157dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17651
43036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1765143036
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2769170186
Short name T114
Test name
Test status
Simulation time 167247405 ps
CPU time 11.25 seconds
Started May 28 01:59:41 PM PDT 24
Finished May 28 01:59:53 PM PDT 24
Peak memory 248776 kb
Host smart-967b6e5d-7085-4181-96d5-333b44cbf3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27691
70186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2769170186
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1607514019
Short name T564
Test name
Test status
Simulation time 816676343 ps
CPU time 30.52 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:00:16 PM PDT 24
Peak memory 248832 kb
Host smart-f29ba362-c6df-4cbe-a0c6-39785d2a5f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16075
14019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1607514019
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.957241177
Short name T95
Test name
Test status
Simulation time 119372998351 ps
CPU time 1901.09 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 02:31:25 PM PDT 24
Peak memory 282732 kb
Host smart-af9020c7-a6c3-4c46-bcda-f74949fd1d0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957241177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.957241177
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3107631333
Short name T119
Test name
Test status
Simulation time 103471040451 ps
CPU time 1280.48 seconds
Started May 28 01:59:45 PM PDT 24
Finished May 28 02:21:07 PM PDT 24
Peak memory 281608 kb
Host smart-d56f003f-b4b0-4af5-95fd-d8fa46b14022
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107631333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3107631333
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2335377787
Short name T385
Test name
Test status
Simulation time 1912750026 ps
CPU time 160.16 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 02:02:23 PM PDT 24
Peak memory 256912 kb
Host smart-e8eb9ade-e223-45f3-97e8-91800513d4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23353
77787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2335377787
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.850322986
Short name T108
Test name
Test status
Simulation time 832625864 ps
CPU time 47.13 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:00:31 PM PDT 24
Peak memory 248788 kb
Host smart-476ae0d2-2f27-42ab-abfe-bee981d99614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85032
2986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.850322986
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.4048152014
Short name T330
Test name
Test status
Simulation time 48789422777 ps
CPU time 1171.48 seconds
Started May 28 01:59:46 PM PDT 24
Finished May 28 02:19:19 PM PDT 24
Peak memory 289696 kb
Host smart-e2046047-ab31-466e-b043-5abb1b054c56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048152014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4048152014
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1093309771
Short name T12
Test name
Test status
Simulation time 98300825849 ps
CPU time 1448.08 seconds
Started May 28 01:59:44 PM PDT 24
Finished May 28 02:23:54 PM PDT 24
Peak memory 273292 kb
Host smart-7c094f30-d730-410f-8f0f-f7443722d96e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093309771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1093309771
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3447615520
Short name T1
Test name
Test status
Simulation time 41599612661 ps
CPU time 287.67 seconds
Started May 28 01:59:44 PM PDT 24
Finished May 28 02:04:34 PM PDT 24
Peak memory 254524 kb
Host smart-b085909e-91df-4c41-be01-94ba1f11a41a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447615520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3447615520
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.931110954
Short name T701
Test name
Test status
Simulation time 1332581542 ps
CPU time 66.73 seconds
Started May 28 01:59:46 PM PDT 24
Finished May 28 02:00:54 PM PDT 24
Peak memory 248772 kb
Host smart-374ce276-c252-478a-ab1c-c888978d83e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93111
0954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.931110954
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4183786534
Short name T489
Test name
Test status
Simulation time 1580458894 ps
CPU time 31.98 seconds
Started May 28 01:59:44 PM PDT 24
Finished May 28 02:00:18 PM PDT 24
Peak memory 248780 kb
Host smart-6332dbc5-3e53-4d6f-b220-00555d8fe52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41837
86534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4183786534
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4147910093
Short name T588
Test name
Test status
Simulation time 8526015976 ps
CPU time 72.89 seconds
Started May 28 01:59:46 PM PDT 24
Finished May 28 02:01:01 PM PDT 24
Peak memory 256500 kb
Host smart-f9eabff7-5511-4682-b91a-b7926f4324ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41479
10093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4147910093
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1415363096
Short name T605
Test name
Test status
Simulation time 201506974 ps
CPU time 19.02 seconds
Started May 28 01:59:41 PM PDT 24
Finished May 28 02:00:01 PM PDT 24
Peak memory 248764 kb
Host smart-7e2ad9f4-b8e9-4877-b559-1ced95da4567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
63096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1415363096
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.98865974
Short name T524
Test name
Test status
Simulation time 248652212523 ps
CPU time 2732.93 seconds
Started May 28 01:59:46 PM PDT 24
Finished May 28 02:45:21 PM PDT 24
Peak memory 338524 kb
Host smart-8e064864-a9ef-4646-9f67-73aa312627fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98865974 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.98865974
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3109967267
Short name T480
Test name
Test status
Simulation time 29279975732 ps
CPU time 1909.92 seconds
Started May 28 01:59:59 PM PDT 24
Finished May 28 02:31:51 PM PDT 24
Peak memory 281604 kb
Host smart-36fac790-2b4c-46a9-afd8-88e8d12c29c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109967267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3109967267
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1315128098
Short name T429
Test name
Test status
Simulation time 11581946078 ps
CPU time 320.49 seconds
Started May 28 01:59:40 PM PDT 24
Finished May 28 02:05:02 PM PDT 24
Peak memory 251444 kb
Host smart-71f18d3f-26b8-4993-83c7-61ff34534800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13151
28098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1315128098
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3869950026
Short name T551
Test name
Test status
Simulation time 63155207 ps
CPU time 3.08 seconds
Started May 28 01:59:46 PM PDT 24
Finished May 28 01:59:50 PM PDT 24
Peak memory 240584 kb
Host smart-3ba9e9b8-ae43-482c-b4e1-933ae49dfeb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699
50026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3869950026
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3771126913
Short name T328
Test name
Test status
Simulation time 19088554101 ps
CPU time 1231.52 seconds
Started May 28 01:59:58 PM PDT 24
Finished May 28 02:20:32 PM PDT 24
Peak memory 273368 kb
Host smart-5bb60805-bd17-4ce7-8e1f-494619614f71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771126913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3771126913
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3242847417
Short name T418
Test name
Test status
Simulation time 10338293361 ps
CPU time 1113.35 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:18:31 PM PDT 24
Peak memory 272668 kb
Host smart-a8602beb-d00a-48b3-96a6-d14681fae102
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242847417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3242847417
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1168033911
Short name T21
Test name
Test status
Simulation time 2499818119 ps
CPU time 100.8 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:01:39 PM PDT 24
Peak memory 247904 kb
Host smart-c16a5f7d-c9d6-48f8-8f61-52811b10912a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168033911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1168033911
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.884254233
Short name T708
Test name
Test status
Simulation time 292302683 ps
CPU time 3.06 seconds
Started May 28 01:59:42 PM PDT 24
Finished May 28 01:59:46 PM PDT 24
Peak memory 240580 kb
Host smart-6b8ce71e-7425-4022-bc9b-f281c1603da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88425
4233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.884254233
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3196441167
Short name T91
Test name
Test status
Simulation time 671518119 ps
CPU time 42 seconds
Started May 28 01:59:43 PM PDT 24
Finished May 28 02:00:27 PM PDT 24
Peak memory 254868 kb
Host smart-d6adfec5-914a-4a5f-8d40-dbf854a31b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964
41167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3196441167
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1164130489
Short name T79
Test name
Test status
Simulation time 190636772 ps
CPU time 14.09 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:00:13 PM PDT 24
Peak memory 247456 kb
Host smart-debd29e6-6a62-4202-94bb-b137fd790838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11641
30489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1164130489
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.865635162
Short name T432
Test name
Test status
Simulation time 171254507 ps
CPU time 8.33 seconds
Started May 28 01:59:46 PM PDT 24
Finished May 28 01:59:56 PM PDT 24
Peak memory 252640 kb
Host smart-4451e6e0-0d35-4399-8136-bc36d61442e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86563
5162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.865635162
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1813365601
Short name T616
Test name
Test status
Simulation time 15347433805 ps
CPU time 891.58 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:14:50 PM PDT 24
Peak memory 265196 kb
Host smart-2c755584-19a1-4db3-bf84-95f5211e2002
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813365601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1813365601
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4286404236
Short name T180
Test name
Test status
Simulation time 230300893844 ps
CPU time 6305.6 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 03:45:04 PM PDT 24
Peak memory 322044 kb
Host smart-8e64dfbb-b849-4d38-969b-ecb2bd49a7c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286404236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4286404236
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1262293288
Short name T218
Test name
Test status
Simulation time 27820123 ps
CPU time 2.4 seconds
Started May 28 01:58:04 PM PDT 24
Finished May 28 01:58:09 PM PDT 24
Peak memory 248932 kb
Host smart-b7de4e28-db28-4539-848d-92ce19e3e26c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1262293288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1262293288
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1595297436
Short name T421
Test name
Test status
Simulation time 31015933609 ps
CPU time 1796.08 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 02:28:02 PM PDT 24
Peak memory 273412 kb
Host smart-64f907bb-a8d6-4458-a3f1-a2f3f335d804
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595297436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1595297436
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2914192734
Short name T582
Test name
Test status
Simulation time 163587868 ps
CPU time 9.81 seconds
Started May 28 01:58:09 PM PDT 24
Finished May 28 01:58:20 PM PDT 24
Peak memory 240420 kb
Host smart-c7ad20cc-5c47-4bf2-a6eb-f3725693b978
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2914192734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2914192734
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.4226057830
Short name T467
Test name
Test status
Simulation time 841523697 ps
CPU time 48.59 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:55 PM PDT 24
Peak memory 256804 kb
Host smart-27fbe4c5-350a-4791-ac5a-a366b82e5c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
57830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.4226057830
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3236784186
Short name T566
Test name
Test status
Simulation time 4185114083 ps
CPU time 67.06 seconds
Started May 28 01:58:03 PM PDT 24
Finished May 28 01:59:14 PM PDT 24
Peak memory 248840 kb
Host smart-47c87785-9725-4eac-a0cb-78160a8e255d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32367
84186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3236784186
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2652905276
Short name T606
Test name
Test status
Simulation time 50418152413 ps
CPU time 1255.31 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 02:19:01 PM PDT 24
Peak memory 281484 kb
Host smart-e9815588-222c-4cc4-b2d1-162d7bf9a682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652905276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2652905276
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.685463047
Short name T543
Test name
Test status
Simulation time 12158684151 ps
CPU time 1148.79 seconds
Started May 28 01:58:03 PM PDT 24
Finished May 28 02:17:15 PM PDT 24
Peak memory 287112 kb
Host smart-fad520a7-0d3f-4816-93ed-2d55aa271129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685463047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.685463047
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1133258681
Short name T602
Test name
Test status
Simulation time 48495672942 ps
CPU time 216.83 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 02:01:43 PM PDT 24
Peak memory 254460 kb
Host smart-1dfa85b2-85f2-4fd4-9838-e7406d0436c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133258681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1133258681
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3099128868
Short name T428
Test name
Test status
Simulation time 1450648096 ps
CPU time 23.63 seconds
Started May 28 01:57:59 PM PDT 24
Finished May 28 01:58:24 PM PDT 24
Peak memory 248756 kb
Host smart-b38fd500-78b5-438c-94d6-be8fca428946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30991
28868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3099128868
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3389237610
Short name T50
Test name
Test status
Simulation time 2587507669 ps
CPU time 48.76 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:53 PM PDT 24
Peak memory 255696 kb
Host smart-07ac5cbc-badd-44eb-86dd-6a41afac8838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33892
37610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3389237610
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1889208514
Short name T10
Test name
Test status
Simulation time 1737902788 ps
CPU time 25.1 seconds
Started May 28 01:58:09 PM PDT 24
Finished May 28 01:58:35 PM PDT 24
Peak memory 278536 kb
Host smart-46351bb1-0cf3-4af9-9efb-2e82eea4eaf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1889208514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1889208514
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.4003990904
Short name T185
Test name
Test status
Simulation time 991652191 ps
CPU time 53.31 seconds
Started May 28 01:58:01 PM PDT 24
Finished May 28 01:58:58 PM PDT 24
Peak memory 256380 kb
Host smart-41da20ef-b7be-4e9a-853d-57394f004f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40039
90904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4003990904
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3680493314
Short name T398
Test name
Test status
Simulation time 32340004 ps
CPU time 4.07 seconds
Started May 28 01:58:03 PM PDT 24
Finished May 28 01:58:11 PM PDT 24
Peak memory 248756 kb
Host smart-d8c0d4d2-f81d-414b-93ae-605d57ac1a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36804
93314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3680493314
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.369795739
Short name T652
Test name
Test status
Simulation time 73662260154 ps
CPU time 2033.55 seconds
Started May 28 01:58:03 PM PDT 24
Finished May 28 02:32:00 PM PDT 24
Peak memory 289408 kb
Host smart-80c97138-f420-4b07-abfc-c158fc95e941
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369795739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.369795739
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1043787957
Short name T584
Test name
Test status
Simulation time 31781818684 ps
CPU time 1279.04 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:21:18 PM PDT 24
Peak memory 265240 kb
Host smart-8eea4fdf-de98-46d5-a73b-b21c383abdb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043787957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1043787957
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3628951946
Short name T248
Test name
Test status
Simulation time 3057718980 ps
CPU time 119.91 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:01:59 PM PDT 24
Peak memory 256928 kb
Host smart-810e73f8-c18f-4f52-9c77-69d49c494ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
51946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3628951946
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3403856402
Short name T438
Test name
Test status
Simulation time 1874633869 ps
CPU time 51.76 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:00:51 PM PDT 24
Peak memory 248780 kb
Host smart-07f9b350-3d41-4246-9177-d15b0fd84313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
56402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3403856402
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1908288797
Short name T327
Test name
Test status
Simulation time 20193449717 ps
CPU time 1499.63 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:24:58 PM PDT 24
Peak memory 289784 kb
Host smart-855a1b20-89c6-43b3-8075-97a9818e2660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908288797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1908288797
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1849777216
Short name T266
Test name
Test status
Simulation time 390859635433 ps
CPU time 2270.95 seconds
Started May 28 02:00:03 PM PDT 24
Finished May 28 02:37:55 PM PDT 24
Peak memory 289152 kb
Host smart-47b70980-56c3-4e80-86c2-03b556e3c8e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849777216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1849777216
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3864451065
Short name T321
Test name
Test status
Simulation time 9340052198 ps
CPU time 118.47 seconds
Started May 28 02:00:02 PM PDT 24
Finished May 28 02:02:01 PM PDT 24
Peak memory 248568 kb
Host smart-49089c56-5195-4064-a2be-a6c0d56a04a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864451065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3864451065
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4003297591
Short name T394
Test name
Test status
Simulation time 731431986 ps
CPU time 22.38 seconds
Started May 28 01:59:58 PM PDT 24
Finished May 28 02:00:23 PM PDT 24
Peak memory 248752 kb
Host smart-3cd87a4a-3c40-4fa9-8ede-2d47732518c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40032
97591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4003297591
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1326123424
Short name T16
Test name
Test status
Simulation time 391316831 ps
CPU time 27.3 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:00:24 PM PDT 24
Peak memory 256056 kb
Host smart-45fa23b5-fbc3-4020-8e37-4dfc0f65b335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13261
23424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1326123424
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1341549393
Short name T482
Test name
Test status
Simulation time 127032439 ps
CPU time 9.95 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:00:08 PM PDT 24
Peak memory 249176 kb
Host smart-3ace9c23-adf9-44e6-932a-5424c2e9517e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13415
49393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1341549393
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3757113725
Short name T249
Test name
Test status
Simulation time 2895654443 ps
CPU time 74.52 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:01:13 PM PDT 24
Peak memory 248836 kb
Host smart-f90952ff-5162-4906-a086-cc6981e44e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
13725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3757113725
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2223063856
Short name T277
Test name
Test status
Simulation time 2049152460 ps
CPU time 133.16 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:02:11 PM PDT 24
Peak memory 256912 kb
Host smart-3b085a30-4ee0-4589-9cb8-7b2e298faa86
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223063856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2223063856
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2381604735
Short name T270
Test name
Test status
Simulation time 34648459755 ps
CPU time 1201.38 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:20:00 PM PDT 24
Peak memory 273392 kb
Host smart-da946139-3324-46b4-87f4-b4958b983904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381604735 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2381604735
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.4247212903
Short name T440
Test name
Test status
Simulation time 24238503950 ps
CPU time 1078.25 seconds
Started May 28 02:00:02 PM PDT 24
Finished May 28 02:18:02 PM PDT 24
Peak memory 288900 kb
Host smart-43210b68-4359-4e2a-ac1a-b8cfc397377a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247212903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4247212903
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3626172078
Short name T636
Test name
Test status
Simulation time 1359336740 ps
CPU time 33.77 seconds
Started May 28 01:59:58 PM PDT 24
Finished May 28 02:00:33 PM PDT 24
Peak memory 248708 kb
Host smart-19f4fdc8-ab3d-42ed-b580-02c10156f937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
72078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3626172078
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1215757555
Short name T490
Test name
Test status
Simulation time 2198871440 ps
CPU time 20.11 seconds
Started May 28 01:59:58 PM PDT 24
Finished May 28 02:00:20 PM PDT 24
Peak memory 256084 kb
Host smart-fc35e24a-5c69-4533-b285-f85ac9c22eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12157
57555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1215757555
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1674924627
Short name T341
Test name
Test status
Simulation time 35376324268 ps
CPU time 1296.78 seconds
Started May 28 01:59:58 PM PDT 24
Finished May 28 02:21:37 PM PDT 24
Peak memory 289028 kb
Host smart-7a9dc695-8b36-4b23-b2df-1b0263cfb85d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674924627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1674924627
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3159471360
Short name T463
Test name
Test status
Simulation time 64762631 ps
CPU time 5.72 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:00:04 PM PDT 24
Peak memory 240580 kb
Host smart-d07bd343-4f6c-4275-9340-48db9b0a7a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31594
71360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3159471360
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.319963356
Short name T634
Test name
Test status
Simulation time 112254505 ps
CPU time 5.38 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:00:05 PM PDT 24
Peak memory 239260 kb
Host smart-a54aafae-3fcd-4a90-af6c-c6b7c724ed99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31996
3356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.319963356
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.494197235
Short name T68
Test name
Test status
Simulation time 10126010931 ps
CPU time 63.73 seconds
Started May 28 01:59:58 PM PDT 24
Finished May 28 02:01:04 PM PDT 24
Peak memory 256856 kb
Host smart-08b71e16-4d62-45d6-8ecc-071e102bf536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49419
7235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.494197235
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2453197864
Short name T485
Test name
Test status
Simulation time 920535988 ps
CPU time 13.99 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:00:10 PM PDT 24
Peak memory 248756 kb
Host smart-b428ceb4-0eeb-4e42-a5ff-aacc497faf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24531
97864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2453197864
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2558709917
Short name T663
Test name
Test status
Simulation time 387397309984 ps
CPU time 2595.23 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:43:29 PM PDT 24
Peak memory 281572 kb
Host smart-897bca50-1e3d-49f4-9ed2-fe5faf7f58a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558709917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2558709917
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1055752031
Short name T362
Test name
Test status
Simulation time 5118600252 ps
CPU time 303.17 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:05:17 PM PDT 24
Peak memory 256964 kb
Host smart-f227dfac-d4d8-477f-b634-7949ea11bdff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10557
52031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1055752031
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2710945573
Short name T618
Test name
Test status
Simulation time 821326344 ps
CPU time 22.42 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:00:36 PM PDT 24
Peak memory 255528 kb
Host smart-9d6df0c6-bf6d-4fe5-a152-1b38dc989ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27109
45573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2710945573
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.193803861
Short name T503
Test name
Test status
Simulation time 95570294434 ps
CPU time 1461 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:24:36 PM PDT 24
Peak memory 273388 kb
Host smart-a73a1fad-c020-44ed-a956-30b0b972ca28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193803861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.193803861
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.359365039
Short name T699
Test name
Test status
Simulation time 54229712239 ps
CPU time 1895.02 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:31:47 PM PDT 24
Peak memory 270560 kb
Host smart-b1131a12-7cc3-47a9-b974-edc3334d75fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359365039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.359365039
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.421609460
Short name T326
Test name
Test status
Simulation time 10767080408 ps
CPU time 452.94 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:07:45 PM PDT 24
Peak memory 254608 kb
Host smart-d51390c7-2bc5-4a3d-a119-f7719ade18f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421609460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.421609460
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3478070267
Short name T369
Test name
Test status
Simulation time 1408364859 ps
CPU time 21.7 seconds
Started May 28 01:59:57 PM PDT 24
Finished May 28 02:00:21 PM PDT 24
Peak memory 248816 kb
Host smart-28eb108d-ffd0-4775-83f8-c5e88481599a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
70267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3478070267
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1528182706
Short name T628
Test name
Test status
Simulation time 162534766 ps
CPU time 4.78 seconds
Started May 28 01:59:56 PM PDT 24
Finished May 28 02:00:02 PM PDT 24
Peak memory 239256 kb
Host smart-1220e7e4-dc60-4864-92f6-e87c1bca6b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15281
82706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1528182706
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.529381956
Short name T668
Test name
Test status
Simulation time 4639680039 ps
CPU time 53.57 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:01:06 PM PDT 24
Peak memory 256284 kb
Host smart-cda477af-0476-4908-9566-d3c80c691897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52938
1956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.529381956
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3884739310
Short name T678
Test name
Test status
Simulation time 2747693278 ps
CPU time 41.69 seconds
Started May 28 01:59:59 PM PDT 24
Finished May 28 02:00:42 PM PDT 24
Peak memory 248808 kb
Host smart-8cd63f6e-5110-4abd-935f-883cbf7a655a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38847
39310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3884739310
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1197546829
Short name T620
Test name
Test status
Simulation time 34489871091 ps
CPU time 2024.53 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:33:58 PM PDT 24
Peak memory 269860 kb
Host smart-b1263ebf-3423-42a1-b97f-2cbdb82db089
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197546829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1197546829
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2088174028
Short name T189
Test name
Test status
Simulation time 286776893524 ps
CPU time 3806.59 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 03:03:43 PM PDT 24
Peak memory 305780 kb
Host smart-38b2ef8f-fd45-4e58-b61c-1b97cfae6c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088174028 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2088174028
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.263658487
Short name T14
Test name
Test status
Simulation time 32202155818 ps
CPU time 1283.62 seconds
Started May 28 02:00:14 PM PDT 24
Finished May 28 02:21:40 PM PDT 24
Peak memory 273052 kb
Host smart-ad8368ef-12ab-48a4-85b9-e99409cd1d2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263658487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.263658487
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1462875046
Short name T222
Test name
Test status
Simulation time 15065712212 ps
CPU time 192.69 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:03:26 PM PDT 24
Peak memory 249908 kb
Host smart-d69ac620-74e6-46ba-a3c9-a0cd60c31fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14628
75046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1462875046
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1672113049
Short name T423
Test name
Test status
Simulation time 1081304148 ps
CPU time 68.79 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:01:25 PM PDT 24
Peak memory 248772 kb
Host smart-26188f54-0d33-4434-8c40-f4bb03825866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16721
13049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1672113049
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1665247705
Short name T340
Test name
Test status
Simulation time 20127045679 ps
CPU time 1096.49 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:18:32 PM PDT 24
Peak memory 272612 kb
Host smart-d088adb8-6687-474d-92b6-5f8dc8098483
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665247705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1665247705
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2784913865
Short name T470
Test name
Test status
Simulation time 111474606690 ps
CPU time 1769.68 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:29:45 PM PDT 24
Peak memory 273080 kb
Host smart-838e4607-e3b5-4a94-9dc4-dc7b4bce204c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784913865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2784913865
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1691862768
Short name T537
Test name
Test status
Simulation time 10302316298 ps
CPU time 220.92 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:03:55 PM PDT 24
Peak memory 254888 kb
Host smart-29862daa-1319-47cd-ad49-04af22266871
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691862768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1691862768
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3253062879
Short name T360
Test name
Test status
Simulation time 2088905448 ps
CPU time 37.35 seconds
Started May 28 02:00:19 PM PDT 24
Finished May 28 02:00:57 PM PDT 24
Peak memory 248984 kb
Host smart-857d51c5-0739-432e-b385-9bd2f9bd3a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32530
62879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3253062879
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3680060180
Short name T87
Test name
Test status
Simulation time 133620984 ps
CPU time 9.81 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:00:24 PM PDT 24
Peak memory 250712 kb
Host smart-54b775d8-a128-466b-bbe2-a103fc72b3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36800
60180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3680060180
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.4092299697
Short name T409
Test name
Test status
Simulation time 194197611 ps
CPU time 20.36 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:00:36 PM PDT 24
Peak memory 248772 kb
Host smart-80afeb5f-f524-408e-a834-62284f0667da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
99697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.4092299697
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4249379933
Short name T552
Test name
Test status
Simulation time 624924117 ps
CPU time 33.17 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:00:46 PM PDT 24
Peak memory 256740 kb
Host smart-a2245617-e58c-475a-a680-859b707669ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
79933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4249379933
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.394842446
Short name T448
Test name
Test status
Simulation time 138465563374 ps
CPU time 2021.39 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:33:55 PM PDT 24
Peak memory 273420 kb
Host smart-c3e07e41-48cd-4a1d-9c7e-afed05cb34d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394842446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.394842446
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.750791815
Short name T493
Test name
Test status
Simulation time 935429837 ps
CPU time 19.83 seconds
Started May 28 02:00:13 PM PDT 24
Finished May 28 02:00:36 PM PDT 24
Peak memory 248772 kb
Host smart-6ba93388-7f8f-4469-a471-bdcc490c47c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75079
1815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.750791815
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1379568260
Short name T372
Test name
Test status
Simulation time 76163352 ps
CPU time 5.65 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:00:22 PM PDT 24
Peak memory 248748 kb
Host smart-ee2a36a9-5978-459d-8017-faf7cc6b6cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13795
68260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1379568260
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.564206347
Short name T452
Test name
Test status
Simulation time 18842562014 ps
CPU time 662.05 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 272156 kb
Host smart-d00f30ae-4332-458c-a4fc-7c237c1acc87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564206347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.564206347
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3657944532
Short name T672
Test name
Test status
Simulation time 185009255721 ps
CPU time 2659.4 seconds
Started May 28 02:00:09 PM PDT 24
Finished May 28 02:44:30 PM PDT 24
Peak memory 289468 kb
Host smart-a6234bc9-197c-4d12-8bf4-432522f4d0b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657944532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3657944532
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2367056566
Short name T597
Test name
Test status
Simulation time 44569799247 ps
CPU time 480.66 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:08:16 PM PDT 24
Peak memory 254820 kb
Host smart-5b055cea-ff83-491c-a5d4-ffe33a57ea9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367056566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2367056566
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.78960554
Short name T401
Test name
Test status
Simulation time 40083068 ps
CPU time 6.51 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:00:22 PM PDT 24
Peak memory 248776 kb
Host smart-5fa4209b-572a-4ec5-8d1c-a9ebe66875e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78960
554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.78960554
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.956171591
Short name T35
Test name
Test status
Simulation time 3609084272 ps
CPU time 42.52 seconds
Started May 28 02:00:19 PM PDT 24
Finished May 28 02:01:03 PM PDT 24
Peak memory 256176 kb
Host smart-47d00e49-32e0-46b6-b2a5-6deb33d0d122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95617
1591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.956171591
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1554405643
Short name T86
Test name
Test status
Simulation time 2629479199 ps
CPU time 69.59 seconds
Started May 28 02:00:19 PM PDT 24
Finished May 28 02:01:30 PM PDT 24
Peak memory 255868 kb
Host smart-c4d20242-50c0-42d2-958d-847bc5199301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544
05643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1554405643
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2940543370
Short name T104
Test name
Test status
Simulation time 245052194 ps
CPU time 5.27 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:00:20 PM PDT 24
Peak memory 240564 kb
Host smart-9dfdfb6d-a548-4bb5-8220-71b256f81c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
43370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2940543370
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3690022948
Short name T568
Test name
Test status
Simulation time 58571255733 ps
CPU time 1555.55 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:26:12 PM PDT 24
Peak memory 298452 kb
Host smart-7846ba7e-6e9c-4b2f-b77b-4e4c2c7e702e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690022948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3690022948
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1476296954
Short name T47
Test name
Test status
Simulation time 23988047523 ps
CPU time 1488.53 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:25:02 PM PDT 24
Peak memory 289728 kb
Host smart-b81cf480-6469-475c-bd52-a5d3000ca604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476296954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1476296954
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2961772497
Short name T476
Test name
Test status
Simulation time 1405200811 ps
CPU time 89.86 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:01:45 PM PDT 24
Peak memory 249176 kb
Host smart-109cd085-24ec-4f85-9d53-de7b773ba515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29617
72497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2961772497
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4227813494
Short name T594
Test name
Test status
Simulation time 1429038443 ps
CPU time 25.4 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:00:40 PM PDT 24
Peak memory 248768 kb
Host smart-0ec74497-a344-4bd3-8883-c8ace005a7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278
13494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4227813494
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.92159867
Short name T539
Test name
Test status
Simulation time 18237107410 ps
CPU time 1237.13 seconds
Started May 28 02:00:13 PM PDT 24
Finished May 28 02:20:53 PM PDT 24
Peak memory 288796 kb
Host smart-b90de8d0-2ca7-406c-a786-d40685f335b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92159867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.92159867
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4069668232
Short name T101
Test name
Test status
Simulation time 24595533608 ps
CPU time 255.79 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:04:30 PM PDT 24
Peak memory 254820 kb
Host smart-b1781cbe-0f2b-4583-a927-b7a9135456c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069668232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4069668232
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1552334961
Short name T267
Test name
Test status
Simulation time 730061626 ps
CPU time 31.34 seconds
Started May 28 02:00:12 PM PDT 24
Finished May 28 02:00:47 PM PDT 24
Peak memory 248760 kb
Host smart-67137663-c94e-4aec-b9ec-e9d405d1816e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
34961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1552334961
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2901744157
Short name T585
Test name
Test status
Simulation time 735344214 ps
CPU time 43.09 seconds
Started May 28 02:00:14 PM PDT 24
Finished May 28 02:01:00 PM PDT 24
Peak memory 248752 kb
Host smart-499b3703-9bd0-4a14-9c09-e3f4badabaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29017
44157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2901744157
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3065602759
Short name T42
Test name
Test status
Simulation time 1039254528 ps
CPU time 62.3 seconds
Started May 28 02:00:18 PM PDT 24
Finished May 28 02:01:21 PM PDT 24
Peak memory 255816 kb
Host smart-5e99cd29-496b-4916-9738-43cbf6b4b511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30656
02759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3065602759
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.145934513
Short name T384
Test name
Test status
Simulation time 1019913230 ps
CPU time 13.61 seconds
Started May 28 02:00:11 PM PDT 24
Finished May 28 02:00:28 PM PDT 24
Peak memory 255220 kb
Host smart-45725bfb-c3f9-4f67-ae8e-d9133ef8a45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14593
4513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.145934513
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2148727690
Short name T547
Test name
Test status
Simulation time 112453997366 ps
CPU time 1759.13 seconds
Started May 28 02:00:10 PM PDT 24
Finished May 28 02:29:33 PM PDT 24
Peak memory 289748 kb
Host smart-1ae1fa55-eb4b-4128-a632-c21354c5618e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148727690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2148727690
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1426703755
Short name T276
Test name
Test status
Simulation time 13823751421 ps
CPU time 922.91 seconds
Started May 28 02:00:22 PM PDT 24
Finished May 28 02:15:48 PM PDT 24
Peak memory 268676 kb
Host smart-3c7f9997-dc20-403c-bc55-b83dc5aff426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426703755 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1426703755
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2881034075
Short name T484
Test name
Test status
Simulation time 69797432727 ps
CPU time 1407.11 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:23:56 PM PDT 24
Peak memory 265220 kb
Host smart-16dfbb1e-0d6e-476b-83b7-b028d61025d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881034075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2881034075
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.506818307
Short name T716
Test name
Test status
Simulation time 2987933701 ps
CPU time 173.11 seconds
Started May 28 02:00:25 PM PDT 24
Finished May 28 02:03:22 PM PDT 24
Peak memory 257012 kb
Host smart-559a73e0-cd11-4c15-9cae-4214f9822336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50681
8307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.506818307
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3837159792
Short name T649
Test name
Test status
Simulation time 723520711 ps
CPU time 10.51 seconds
Started May 28 02:00:27 PM PDT 24
Finished May 28 02:00:41 PM PDT 24
Peak memory 254156 kb
Host smart-436deb9f-2728-41b9-855e-fdfa247ad61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38371
59792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3837159792
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1205188439
Short name T106
Test name
Test status
Simulation time 33924187879 ps
CPU time 1781.09 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:30:10 PM PDT 24
Peak memory 273420 kb
Host smart-4711c4b2-8074-4c27-81c3-37ea227fd95d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205188439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1205188439
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.655076172
Short name T433
Test name
Test status
Simulation time 31879846490 ps
CPU time 951.2 seconds
Started May 28 02:00:25 PM PDT 24
Finished May 28 02:16:20 PM PDT 24
Peak memory 288668 kb
Host smart-4d02fe52-ed98-4ec0-8d42-d8a014a49564
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655076172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.655076172
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3372265632
Short name T70
Test name
Test status
Simulation time 9568377914 ps
CPU time 406.1 seconds
Started May 28 02:00:22 PM PDT 24
Finished May 28 02:07:11 PM PDT 24
Peak memory 248264 kb
Host smart-927b5504-6a60-4e6b-a158-12cdc65c8631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372265632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3372265632
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2524489265
Short name T512
Test name
Test status
Simulation time 4775053346 ps
CPU time 58.34 seconds
Started May 28 02:00:26 PM PDT 24
Finished May 28 02:01:28 PM PDT 24
Peak memory 256988 kb
Host smart-59bac2fc-17d1-4bd2-978d-52891cacc63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25244
89265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2524489265
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3547763705
Short name T427
Test name
Test status
Simulation time 2029489261 ps
CPU time 35.12 seconds
Started May 28 02:00:27 PM PDT 24
Finished May 28 02:01:06 PM PDT 24
Peak memory 249216 kb
Host smart-760a4493-c659-4a1f-831f-dd7319ee3949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35477
63705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3547763705
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1118641908
Short name T226
Test name
Test status
Simulation time 654703432 ps
CPU time 19.9 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:00:48 PM PDT 24
Peak memory 248780 kb
Host smart-7f796857-fd57-4417-9bf3-cae493094e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11186
41908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1118641908
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4188776705
Short name T516
Test name
Test status
Simulation time 2223162161 ps
CPU time 64.61 seconds
Started May 28 02:00:25 PM PDT 24
Finished May 28 02:01:33 PM PDT 24
Peak memory 256060 kb
Host smart-d8c8045d-c238-4476-a18c-a634c8d257da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41887
76705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4188776705
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2396102906
Short name T295
Test name
Test status
Simulation time 127537942768 ps
CPU time 4326.41 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 03:12:36 PM PDT 24
Peak memory 322492 kb
Host smart-6c67e5b3-5b8b-42e9-865b-67c624b3a04b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396102906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2396102906
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2705883353
Short name T612
Test name
Test status
Simulation time 25125680098 ps
CPU time 1558.06 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:26:26 PM PDT 24
Peak memory 273340 kb
Host smart-c4290fae-a5d7-4be7-a413-65e12fd8fc03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705883353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2705883353
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1225588145
Short name T443
Test name
Test status
Simulation time 5222249413 ps
CPU time 118.98 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:02:26 PM PDT 24
Peak memory 249852 kb
Host smart-e586f333-98dc-405b-b21a-cdf4f4330b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12255
88145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1225588145
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2852757930
Short name T686
Test name
Test status
Simulation time 330823412 ps
CPU time 23.85 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 02:00:50 PM PDT 24
Peak memory 255552 kb
Host smart-1acb45f6-9732-4a1a-ac91-4b4eed0bf727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28527
57930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2852757930
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.682610962
Short name T544
Test name
Test status
Simulation time 215217394530 ps
CPU time 3183.55 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 02:53:30 PM PDT 24
Peak memory 286564 kb
Host smart-129acb31-85f9-42c4-b4cf-5ef9f3ff7a64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682610962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.682610962
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3825234798
Short name T263
Test name
Test status
Simulation time 95538977902 ps
CPU time 1557.48 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:26:26 PM PDT 24
Peak memory 273404 kb
Host smart-dc6e47cd-d174-44fb-94e5-eb4a5569260d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825234798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3825234798
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2924968893
Short name T534
Test name
Test status
Simulation time 585969925 ps
CPU time 36.69 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 02:01:04 PM PDT 24
Peak memory 248752 kb
Host smart-2f634579-9c17-46ec-8629-86df5ca0ce74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29249
68893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2924968893
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3926389679
Short name T406
Test name
Test status
Simulation time 8191062252 ps
CPU time 57.98 seconds
Started May 28 02:00:22 PM PDT 24
Finished May 28 02:01:23 PM PDT 24
Peak memory 248816 kb
Host smart-57d9dace-71b4-4899-b5ea-ae9f00728bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39263
89679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3926389679
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.923501538
Short name T378
Test name
Test status
Simulation time 1694180765 ps
CPU time 31.48 seconds
Started May 28 02:00:22 PM PDT 24
Finished May 28 02:00:57 PM PDT 24
Peak memory 249060 kb
Host smart-d0469260-9557-40ee-b7fe-c07fbd3547c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92350
1538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.923501538
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3406974653
Short name T494
Test name
Test status
Simulation time 1474678754 ps
CPU time 38.87 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:01:08 PM PDT 24
Peak memory 256272 kb
Host smart-f12fe6b9-b4b4-41ba-b956-b8b18e13edc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
74653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3406974653
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1155393381
Short name T635
Test name
Test status
Simulation time 602923638682 ps
CPU time 2523.37 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 02:42:30 PM PDT 24
Peak memory 289144 kb
Host smart-cdec28fb-4454-4a6e-bd21-9579e868b804
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155393381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1155393381
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2667283478
Short name T445
Test name
Test status
Simulation time 14170209897 ps
CPU time 1287.31 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:21:56 PM PDT 24
Peak memory 289208 kb
Host smart-ce1a2283-96f6-4791-a4db-11c1a3a93950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667283478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2667283478
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3029685816
Short name T523
Test name
Test status
Simulation time 14348628037 ps
CPU time 163.9 seconds
Started May 28 02:00:26 PM PDT 24
Finished May 28 02:03:13 PM PDT 24
Peak memory 256976 kb
Host smart-dbc60ec1-e67c-4de4-a798-f029d17f336b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30296
85816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3029685816
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.558810343
Short name T656
Test name
Test status
Simulation time 1212036233 ps
CPU time 25.55 seconds
Started May 28 02:00:25 PM PDT 24
Finished May 28 02:00:55 PM PDT 24
Peak memory 248876 kb
Host smart-abd515ff-a774-404f-a8f8-91315a064752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55881
0343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.558810343
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1325332888
Short name T187
Test name
Test status
Simulation time 65972205657 ps
CPU time 771.11 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 02:13:19 PM PDT 24
Peak memory 265236 kb
Host smart-356348eb-6c81-4a28-8b4d-62b6bb1ef988
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325332888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1325332888
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1713139703
Short name T224
Test name
Test status
Simulation time 27203995513 ps
CPU time 784.44 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:13:33 PM PDT 24
Peak memory 267288 kb
Host smart-c1e804df-19e8-476c-98d5-f2da8b016eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713139703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1713139703
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2289460234
Short name T600
Test name
Test status
Simulation time 6153159759 ps
CPU time 130.74 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:02:39 PM PDT 24
Peak memory 248344 kb
Host smart-b407afc0-9111-46b2-af4c-7d7d68989239
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289460234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2289460234
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2190803365
Short name T661
Test name
Test status
Simulation time 682533278 ps
CPU time 23.05 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:00:51 PM PDT 24
Peak memory 254676 kb
Host smart-d2b5afcd-ca76-4e3d-ac6a-e6dddf6bd683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21908
03365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2190803365
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2061666743
Short name T611
Test name
Test status
Simulation time 534526027 ps
CPU time 33.41 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:01:01 PM PDT 24
Peak memory 255780 kb
Host smart-92a1eb46-7a32-4a78-99a1-dff604371959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616
66743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2061666743
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2286881637
Short name T281
Test name
Test status
Simulation time 3815704073 ps
CPU time 33.23 seconds
Started May 28 02:00:24 PM PDT 24
Finished May 28 02:01:01 PM PDT 24
Peak memory 256876 kb
Host smart-061fd01a-5f5b-4a79-a9c7-043b3b2d02de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22868
81637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2286881637
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3976203109
Short name T32
Test name
Test status
Simulation time 1242412099 ps
CPU time 77.02 seconds
Started May 28 02:00:23 PM PDT 24
Finished May 28 02:01:43 PM PDT 24
Peak memory 248776 kb
Host smart-0fc456ce-149e-4530-8e66-37fb77981779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39762
03109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3976203109
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1112910113
Short name T44
Test name
Test status
Simulation time 20232627486 ps
CPU time 1798.92 seconds
Started May 28 02:00:25 PM PDT 24
Finished May 28 02:30:28 PM PDT 24
Peak memory 304904 kb
Host smart-ac7a284b-c0fe-40ec-bba5-82b8cb674a67
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112910113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1112910113
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1016967019
Short name T234
Test name
Test status
Simulation time 42741742647 ps
CPU time 1404.65 seconds
Started May 28 02:00:37 PM PDT 24
Finished May 28 02:24:04 PM PDT 24
Peak memory 273404 kb
Host smart-9195d3d3-7ef9-4e92-9fd3-7cf0553de9b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016967019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1016967019
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1004000685
Short name T257
Test name
Test status
Simulation time 17465165883 ps
CPU time 272.8 seconds
Started May 28 02:00:40 PM PDT 24
Finished May 28 02:05:14 PM PDT 24
Peak memory 257004 kb
Host smart-5e735583-feca-44ff-a2ef-b5c2ddc1a05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10040
00685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1004000685
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2065919667
Short name T529
Test name
Test status
Simulation time 645211488 ps
CPU time 32.47 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:01:09 PM PDT 24
Peak memory 256592 kb
Host smart-bb32b7a5-3415-4a10-b62e-89fc6466c5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659
19667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2065919667
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3057590134
Short name T715
Test name
Test status
Simulation time 11549315464 ps
CPU time 789.26 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:13:46 PM PDT 24
Peak memory 272008 kb
Host smart-8bbffa12-72d4-4693-b9a0-30cd3ecf7072
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057590134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3057590134
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1276362195
Short name T507
Test name
Test status
Simulation time 58167517453 ps
CPU time 1787.3 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:30:26 PM PDT 24
Peak memory 273240 kb
Host smart-4d355267-fdcc-4dea-a691-89138bb9540e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276362195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1276362195
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3402641448
Short name T31
Test name
Test status
Simulation time 12605108791 ps
CPU time 239.81 seconds
Started May 28 02:00:39 PM PDT 24
Finished May 28 02:04:40 PM PDT 24
Peak memory 248004 kb
Host smart-6f3690d5-9116-4533-942d-6f62ea9dde50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402641448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3402641448
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4039184701
Short name T392
Test name
Test status
Simulation time 146930034 ps
CPU time 4.7 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:00:41 PM PDT 24
Peak memory 240580 kb
Host smart-86c1db2c-710c-4e81-bfb4-adb8222fc7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40391
84701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4039184701
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3838781391
Short name T26
Test name
Test status
Simulation time 477004530 ps
CPU time 14.7 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:00:52 PM PDT 24
Peak memory 248760 kb
Host smart-2a04f6fd-02b3-4c74-b304-cf3fea404c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38387
81391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3838781391
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3605076140
Short name T80
Test name
Test status
Simulation time 173768117 ps
CPU time 13.3 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:00:52 PM PDT 24
Peak memory 248764 kb
Host smart-73b64b3d-5864-48cc-aa5e-4112d45b8553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36050
76140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3605076140
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1756624983
Short name T644
Test name
Test status
Simulation time 5352753856 ps
CPU time 66.32 seconds
Started May 28 02:00:39 PM PDT 24
Finished May 28 02:01:47 PM PDT 24
Peak memory 256316 kb
Host smart-01b86f2c-8b79-4307-b466-c0a33426536a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17566
24983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1756624983
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3470100971
Short name T183
Test name
Test status
Simulation time 191729763147 ps
CPU time 1006.16 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:17:24 PM PDT 24
Peak memory 283712 kb
Host smart-fead4292-5e43-4f73-8a3c-246aa3abc4ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470100971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3470100971
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3894210239
Short name T85
Test name
Test status
Simulation time 215626979642 ps
CPU time 4006.56 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 03:07:25 PM PDT 24
Peak memory 319452 kb
Host smart-1af87b0e-bd94-4e90-887e-15e356b91215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894210239 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3894210239
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2946985572
Short name T37
Test name
Test status
Simulation time 210975568 ps
CPU time 3.95 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 01:58:20 PM PDT 24
Peak memory 249136 kb
Host smart-aa25fecf-c526-4bfd-9ef0-ea3dfce4e7cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2946985572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2946985572
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1996175591
Short name T617
Test name
Test status
Simulation time 57368571323 ps
CPU time 1642.82 seconds
Started May 28 01:58:15 PM PDT 24
Finished May 28 02:25:39 PM PDT 24
Peak memory 266380 kb
Host smart-71428209-1958-465f-8a63-b67eef3fa062
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996175591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1996175591
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3105834277
Short name T580
Test name
Test status
Simulation time 428362534 ps
CPU time 20.39 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 01:58:38 PM PDT 24
Peak memory 248720 kb
Host smart-7c038dc7-a69e-4a44-94c4-f50bdc6635df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3105834277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3105834277
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2883492162
Short name T201
Test name
Test status
Simulation time 16231096936 ps
CPU time 117.36 seconds
Started May 28 01:58:06 PM PDT 24
Finished May 28 02:00:05 PM PDT 24
Peak memory 256888 kb
Host smart-dfe4f0a1-7305-4bfb-8fde-bd00700cac1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28834
92162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2883492162
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2960853126
Short name T382
Test name
Test status
Simulation time 305345335 ps
CPU time 12.71 seconds
Started May 28 01:58:04 PM PDT 24
Finished May 28 01:58:20 PM PDT 24
Peak memory 252952 kb
Host smart-3c274550-e944-4b7c-98a8-1fe5f6482799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29608
53126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2960853126
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4039165674
Short name T446
Test name
Test status
Simulation time 56691036325 ps
CPU time 1898.25 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 02:29:54 PM PDT 24
Peak memory 281624 kb
Host smart-86a956ae-cd8e-4132-8aca-66dd2e65ea35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039165674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4039165674
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.303800803
Short name T306
Test name
Test status
Simulation time 26349175757 ps
CPU time 281.35 seconds
Started May 28 01:58:13 PM PDT 24
Finished May 28 02:02:56 PM PDT 24
Peak memory 255056 kb
Host smart-25c7c758-c0dc-42ed-b866-63534c1da58a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303800803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.303800803
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1324656982
Short name T395
Test name
Test status
Simulation time 730810259 ps
CPU time 42.6 seconds
Started May 28 01:58:09 PM PDT 24
Finished May 28 01:58:52 PM PDT 24
Peak memory 248780 kb
Host smart-2cbad74a-cedf-4b50-b079-802cf2bd8758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13246
56982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1324656982
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.351643491
Short name T69
Test name
Test status
Simulation time 432966814 ps
CPU time 13.64 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:19 PM PDT 24
Peak memory 252972 kb
Host smart-a5ca3b79-e46d-43da-984b-1f006eb7c17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35164
3491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.351643491
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3133559923
Short name T57
Test name
Test status
Simulation time 292210647 ps
CPU time 25.08 seconds
Started May 28 01:58:02 PM PDT 24
Finished May 28 01:58:31 PM PDT 24
Peak memory 248784 kb
Host smart-ac89fdcb-6c74-480f-b3a0-a4c0472660e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31335
59923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3133559923
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2817733521
Short name T227
Test name
Test status
Simulation time 27995622907 ps
CPU time 1617.59 seconds
Started May 28 02:00:38 PM PDT 24
Finished May 28 02:27:38 PM PDT 24
Peak memory 268316 kb
Host smart-60967567-8ef6-42a4-be30-fba03f2ec4ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817733521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2817733521
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.137071370
Short name T455
Test name
Test status
Simulation time 1720499025 ps
CPU time 138.81 seconds
Started May 28 02:00:34 PM PDT 24
Finished May 28 02:02:54 PM PDT 24
Peak memory 250928 kb
Host smart-64ccaa30-dbcd-4910-9ccc-a3c32c5830a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13707
1370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.137071370
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4255717709
Short name T545
Test name
Test status
Simulation time 298759395 ps
CPU time 28.29 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:01:05 PM PDT 24
Peak memory 256132 kb
Host smart-1d0411f5-6219-4476-824f-038aaec5819e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42557
17709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4255717709
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1810047286
Short name T553
Test name
Test status
Simulation time 126904956231 ps
CPU time 3450.32 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:58:08 PM PDT 24
Peak memory 289212 kb
Host smart-436add8d-2653-4d97-afcf-1e9cf8c04c79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810047286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1810047286
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4254377986
Short name T526
Test name
Test status
Simulation time 380983335885 ps
CPU time 1260.25 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:21:38 PM PDT 24
Peak memory 265220 kb
Host smart-a7cdb481-9d3a-443b-893a-c943ddb686be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254377986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4254377986
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.198056316
Short name T308
Test name
Test status
Simulation time 9029857195 ps
CPU time 354.6 seconds
Started May 28 02:00:40 PM PDT 24
Finished May 28 02:06:36 PM PDT 24
Peak memory 248068 kb
Host smart-d9ade3b6-ffde-4c29-b3d5-0171d044b1d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198056316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.198056316
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3969731749
Short name T589
Test name
Test status
Simulation time 264039182 ps
CPU time 23.22 seconds
Started May 28 02:00:38 PM PDT 24
Finished May 28 02:01:03 PM PDT 24
Peak memory 248784 kb
Host smart-012a7a28-ffd3-4b0e-a8da-ee4d274e28c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39697
31749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3969731749
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1010559441
Short name T601
Test name
Test status
Simulation time 322444446 ps
CPU time 5.42 seconds
Started May 28 02:00:37 PM PDT 24
Finished May 28 02:00:44 PM PDT 24
Peak memory 240576 kb
Host smart-76b6f333-d9e8-4fad-93f0-39f5ab117cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10105
59441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1010559441
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3858396033
Short name T675
Test name
Test status
Simulation time 523739845 ps
CPU time 32.31 seconds
Started May 28 02:00:40 PM PDT 24
Finished May 28 02:01:13 PM PDT 24
Peak memory 247648 kb
Host smart-334992db-bca0-469a-9efd-23a0844ef30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38583
96033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3858396033
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1239258759
Short name T17
Test name
Test status
Simulation time 541198478 ps
CPU time 7.51 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:00:45 PM PDT 24
Peak memory 248756 kb
Host smart-8c67bf08-1787-4961-ae22-a5c8eb654a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12392
58759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1239258759
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.697756961
Short name T283
Test name
Test status
Simulation time 256277748810 ps
CPU time 3514.83 seconds
Started May 28 02:00:37 PM PDT 24
Finished May 28 02:59:14 PM PDT 24
Peak memory 289828 kb
Host smart-a663b57f-9796-4237-87f3-ba49ce5ede3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697756961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.697756961
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.240890628
Short name T99
Test name
Test status
Simulation time 49447154926 ps
CPU time 256.59 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:04:55 PM PDT 24
Peak memory 265348 kb
Host smart-33b8de8f-3869-48fd-ab79-4748087b1d73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240890628 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.240890628
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.200880783
Short name T478
Test name
Test status
Simulation time 102781273378 ps
CPU time 2903.1 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:49:01 PM PDT 24
Peak memory 289528 kb
Host smart-82dcc579-fbd6-4318-8f00-30320a0dde6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200880783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.200880783
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3970533410
Short name T377
Test name
Test status
Simulation time 2422166830 ps
CPU time 37.71 seconds
Started May 28 02:00:39 PM PDT 24
Finished May 28 02:01:18 PM PDT 24
Peak memory 248804 kb
Host smart-b3919a13-1283-451d-975a-779e1a14b586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
33410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3970533410
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.215976074
Short name T517
Test name
Test status
Simulation time 4503167684 ps
CPU time 70.01 seconds
Started May 28 02:00:40 PM PDT 24
Finished May 28 02:01:52 PM PDT 24
Peak memory 256124 kb
Host smart-243ad989-1f01-4683-9cee-2e45e6a30891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
6074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.215976074
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2408336375
Short name T607
Test name
Test status
Simulation time 112851059016 ps
CPU time 1874.55 seconds
Started May 28 02:00:48 PM PDT 24
Finished May 28 02:32:04 PM PDT 24
Peak memory 281660 kb
Host smart-b22c5578-5063-40cf-af63-65b936752ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408336375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2408336375
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2316126297
Short name T186
Test name
Test status
Simulation time 14665677494 ps
CPU time 149.6 seconds
Started May 28 02:00:37 PM PDT 24
Finished May 28 02:03:09 PM PDT 24
Peak memory 248268 kb
Host smart-2414850c-1abb-463f-a296-f50291df981a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316126297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2316126297
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2059610497
Short name T567
Test name
Test status
Simulation time 607615735 ps
CPU time 22.17 seconds
Started May 28 02:00:36 PM PDT 24
Finished May 28 02:01:00 PM PDT 24
Peak memory 255900 kb
Host smart-a51ed377-599d-47b6-9b3d-3f3bbe7531f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20596
10497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2059610497
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2199616515
Short name T413
Test name
Test status
Simulation time 287334209 ps
CPU time 27.74 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:01:03 PM PDT 24
Peak memory 247764 kb
Host smart-362febe4-b56e-4e91-8328-214441f74b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21996
16515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2199616515
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3893017804
Short name T505
Test name
Test status
Simulation time 39030022 ps
CPU time 4.76 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:00:42 PM PDT 24
Peak memory 252384 kb
Host smart-e6aa15e7-50e8-4f20-8507-c8d2c88c2ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38930
17804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3893017804
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2418476955
Short name T514
Test name
Test status
Simulation time 347100291 ps
CPU time 43.79 seconds
Started May 28 02:00:35 PM PDT 24
Finished May 28 02:01:21 PM PDT 24
Peak memory 248724 kb
Host smart-139e5d69-7b5d-4fb8-ba8a-af82a23cae9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24184
76955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2418476955
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.300590819
Short name T451
Test name
Test status
Simulation time 17732717034 ps
CPU time 1618.68 seconds
Started May 28 02:00:52 PM PDT 24
Finished May 28 02:27:53 PM PDT 24
Peak memory 289756 kb
Host smart-4ed54640-0b94-4839-a35c-cb8171fb425e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300590819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.300590819
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1785155309
Short name T436
Test name
Test status
Simulation time 30489081631 ps
CPU time 1651.47 seconds
Started May 28 02:00:51 PM PDT 24
Finished May 28 02:28:24 PM PDT 24
Peak memory 273400 kb
Host smart-78a0ba37-7f67-4e02-b1b3-faee77ef6d68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785155309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1785155309
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2223242189
Short name T561
Test name
Test status
Simulation time 462753446 ps
CPU time 51.31 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:42 PM PDT 24
Peak memory 248780 kb
Host smart-d4cdf506-931e-48c5-b79c-10635b6d163b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22232
42189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2223242189
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1252734596
Short name T509
Test name
Test status
Simulation time 2431196778 ps
CPU time 12.25 seconds
Started May 28 02:00:50 PM PDT 24
Finished May 28 02:01:04 PM PDT 24
Peak memory 254508 kb
Host smart-b5073f5b-9c0c-46bd-8a69-cfc8ee5b631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
34596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1252734596
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3924271933
Short name T689
Test name
Test status
Simulation time 79614612165 ps
CPU time 1607.42 seconds
Started May 28 02:00:50 PM PDT 24
Finished May 28 02:27:39 PM PDT 24
Peak memory 289548 kb
Host smart-da44460e-615a-4e9e-b1b4-3eed77235996
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924271933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3924271933
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2697497403
Short name T237
Test name
Test status
Simulation time 75810114586 ps
CPU time 2242.78 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:38:13 PM PDT 24
Peak memory 289788 kb
Host smart-35c46535-8f0f-4780-95be-6a790895488d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697497403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2697497403
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2343674302
Short name T577
Test name
Test status
Simulation time 6128275665 ps
CPU time 255.07 seconds
Started May 28 02:00:50 PM PDT 24
Finished May 28 02:05:07 PM PDT 24
Peak memory 248108 kb
Host smart-1c72ee30-0f0f-4a60-a84d-7588cae4f56f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343674302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2343674302
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1840505893
Short name T100
Test name
Test status
Simulation time 18135554 ps
CPU time 2.96 seconds
Started May 28 02:00:51 PM PDT 24
Finished May 28 02:00:56 PM PDT 24
Peak memory 240584 kb
Host smart-2070b413-956e-49f8-b893-46c4a2cdea0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18405
05893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1840505893
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.228416359
Short name T268
Test name
Test status
Simulation time 71228036 ps
CPU time 9.09 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:00:59 PM PDT 24
Peak memory 247432 kb
Host smart-d8d82a48-c71e-4f58-8959-c47f6f270273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22841
6359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.228416359
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2425361865
Short name T712
Test name
Test status
Simulation time 1331939618 ps
CPU time 9.14 seconds
Started May 28 02:00:54 PM PDT 24
Finished May 28 02:01:04 PM PDT 24
Peak memory 249036 kb
Host smart-941a5679-24cb-48ad-b7d9-98b50ba4b452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24253
61865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2425361865
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2090823418
Short name T456
Test name
Test status
Simulation time 752928185 ps
CPU time 19.54 seconds
Started May 28 02:00:50 PM PDT 24
Finished May 28 02:01:11 PM PDT 24
Peak memory 255728 kb
Host smart-78a91c4c-8a22-4795-9121-34fa3eb642e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20908
23418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2090823418
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2853271475
Short name T84
Test name
Test status
Simulation time 11458692765 ps
CPU time 896.07 seconds
Started May 28 02:00:55 PM PDT 24
Finished May 28 02:15:53 PM PDT 24
Peak memory 272728 kb
Host smart-06ea7d4e-b674-4bc8-98c7-67955dd66d8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853271475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2853271475
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1269223227
Short name T665
Test name
Test status
Simulation time 20561729952 ps
CPU time 1333.49 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:23:04 PM PDT 24
Peak memory 273456 kb
Host smart-d902e100-d423-4939-ae2e-afc212bc33ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269223227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1269223227
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3193843181
Short name T431
Test name
Test status
Simulation time 917578085 ps
CPU time 66.94 seconds
Started May 28 02:00:51 PM PDT 24
Finished May 28 02:02:00 PM PDT 24
Peak memory 256928 kb
Host smart-32d663e9-a81f-451a-bedc-57fc8a5ce825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
43181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3193843181
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.720635607
Short name T673
Test name
Test status
Simulation time 671221207 ps
CPU time 10.69 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:01 PM PDT 24
Peak memory 252020 kb
Host smart-f63ac5da-86f7-4490-8abe-e53e71a2f2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72063
5607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.720635607
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1421678879
Short name T329
Test name
Test status
Simulation time 106768400264 ps
CPU time 1833.36 seconds
Started May 28 02:00:56 PM PDT 24
Finished May 28 02:31:30 PM PDT 24
Peak memory 289068 kb
Host smart-1631aac3-6b97-4ea9-b1e7-03c2a8f7cedd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421678879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1421678879
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1412369194
Short name T103
Test name
Test status
Simulation time 30721043893 ps
CPU time 1581.35 seconds
Started May 28 02:00:52 PM PDT 24
Finished May 28 02:27:15 PM PDT 24
Peak memory 272796 kb
Host smart-eb9a47e3-6dc4-42a5-b7d5-0562db4ca6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412369194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1412369194
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1052764053
Short name T271
Test name
Test status
Simulation time 7799458335 ps
CPU time 112.49 seconds
Started May 28 02:00:56 PM PDT 24
Finished May 28 02:02:50 PM PDT 24
Peak memory 248240 kb
Host smart-f654e039-1905-4b44-a88d-6c388cec1510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052764053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1052764053
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.274213066
Short name T449
Test name
Test status
Simulation time 1549019502 ps
CPU time 28.21 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:20 PM PDT 24
Peak memory 248760 kb
Host smart-f8be4986-361d-4498-83f6-f7a33d564ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
3066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.274213066
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3022077015
Short name T583
Test name
Test status
Simulation time 634515772 ps
CPU time 46.06 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:36 PM PDT 24
Peak memory 254900 kb
Host smart-80d94215-c103-4cf6-9afe-6b95774dc3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
77015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3022077015
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1013471580
Short name T251
Test name
Test status
Simulation time 3035879565 ps
CPU time 50.86 seconds
Started May 28 02:00:48 PM PDT 24
Finished May 28 02:01:41 PM PDT 24
Peak memory 248896 kb
Host smart-dd90ba4a-d860-46cd-99f4-b8cd0539beac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10134
71580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1013471580
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.770863313
Short name T538
Test name
Test status
Simulation time 649543208 ps
CPU time 22.69 seconds
Started May 28 02:00:48 PM PDT 24
Finished May 28 02:01:12 PM PDT 24
Peak memory 248752 kb
Host smart-de0ab250-6b8c-4893-b6c9-cef23c279485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77086
3313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.770863313
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.438543423
Short name T414
Test name
Test status
Simulation time 6926470775 ps
CPU time 192.15 seconds
Started May 28 02:00:52 PM PDT 24
Finished May 28 02:04:06 PM PDT 24
Peak memory 256988 kb
Host smart-4951871a-811a-4da4-9709-362ce98fa9a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438543423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.438543423
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.4189058440
Short name T411
Test name
Test status
Simulation time 93100332284 ps
CPU time 1452.15 seconds
Started May 28 02:00:54 PM PDT 24
Finished May 28 02:25:07 PM PDT 24
Peak memory 273460 kb
Host smart-c3ac61ed-9c31-4dde-8549-35437c0c62e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189058440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.4189058440
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.624391760
Short name T405
Test name
Test status
Simulation time 1294756407 ps
CPU time 81.52 seconds
Started May 28 02:00:56 PM PDT 24
Finished May 28 02:02:19 PM PDT 24
Peak memory 248864 kb
Host smart-79fff75f-6a20-4cf8-8ea7-ae8d95e04a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62439
1760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.624391760
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.216265404
Short name T416
Test name
Test status
Simulation time 930590065 ps
CPU time 23.24 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:14 PM PDT 24
Peak memory 255948 kb
Host smart-51a2af4a-ad21-405c-86ee-677ae4bd8b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21626
5404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.216265404
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3159291224
Short name T704
Test name
Test status
Simulation time 165564821670 ps
CPU time 2444.24 seconds
Started May 28 02:00:59 PM PDT 24
Finished May 28 02:41:46 PM PDT 24
Peak memory 289136 kb
Host smart-170fe8c0-c893-4a92-bdc8-3dea2deeaefc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159291224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3159291224
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4183325774
Short name T546
Test name
Test status
Simulation time 135426428197 ps
CPU time 2070.49 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:35:34 PM PDT 24
Peak memory 273420 kb
Host smart-d631aacb-1ba5-4725-a14e-ef709bd9a647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183325774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4183325774
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1670535065
Short name T698
Test name
Test status
Simulation time 6620960901 ps
CPU time 267.35 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:05:31 PM PDT 24
Peak memory 248140 kb
Host smart-f7ca4850-be66-476b-aebd-0552c1cb3c7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670535065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1670535065
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.419211807
Short name T391
Test name
Test status
Simulation time 324835442 ps
CPU time 24.51 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:16 PM PDT 24
Peak memory 248800 kb
Host smart-018447d8-ca8b-4142-9c98-7e0d448ce824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41921
1807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.419211807
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1170194993
Short name T264
Test name
Test status
Simulation time 421876107 ps
CPU time 29.36 seconds
Started May 28 02:00:49 PM PDT 24
Finished May 28 02:01:19 PM PDT 24
Peak memory 249188 kb
Host smart-59c1eab5-bdac-4549-82a3-9e4259b5f135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
94993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1170194993
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4207910083
Short name T402
Test name
Test status
Simulation time 955786330 ps
CPU time 32.42 seconds
Started May 28 02:00:53 PM PDT 24
Finished May 28 02:01:27 PM PDT 24
Peak memory 255632 kb
Host smart-087de7f4-993a-4d20-b372-ef88e9e6e76f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42079
10083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4207910083
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.361099332
Short name T697
Test name
Test status
Simulation time 2222720502 ps
CPU time 32.68 seconds
Started May 28 02:00:50 PM PDT 24
Finished May 28 02:01:24 PM PDT 24
Peak memory 256164 kb
Host smart-080abb9f-22c7-4bce-94b8-3f2e20ecae41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
9332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.361099332
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1824601926
Short name T23
Test name
Test status
Simulation time 627298495132 ps
CPU time 2136.55 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:36:41 PM PDT 24
Peak memory 287736 kb
Host smart-5455f6d1-197a-4601-b753-106868010668
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824601926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1824601926
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2089588286
Short name T81
Test name
Test status
Simulation time 25903266319 ps
CPU time 1437.89 seconds
Started May 28 02:01:01 PM PDT 24
Finished May 28 02:25:04 PM PDT 24
Peak memory 272460 kb
Host smart-ddc83573-e44c-4871-b340-97b21ab94b70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089588286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2089588286
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3870214987
Short name T690
Test name
Test status
Simulation time 430049423 ps
CPU time 29.31 seconds
Started May 28 02:00:59 PM PDT 24
Finished May 28 02:01:32 PM PDT 24
Peak memory 248788 kb
Host smart-2c718b71-318c-4d5a-95c6-9f642f354d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38702
14987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3870214987
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.892736119
Short name T664
Test name
Test status
Simulation time 298930729 ps
CPU time 24.83 seconds
Started May 28 02:01:03 PM PDT 24
Finished May 28 02:01:31 PM PDT 24
Peak memory 254928 kb
Host smart-ead6050f-bceb-4f36-aada-829fd4eba437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89273
6119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.892736119
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2458651678
Short name T688
Test name
Test status
Simulation time 56384649316 ps
CPU time 1696.83 seconds
Started May 28 02:01:02 PM PDT 24
Finished May 28 02:29:23 PM PDT 24
Peak memory 267284 kb
Host smart-0f99e998-440c-493e-8ae5-c95408d55299
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458651678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2458651678
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1203129872
Short name T714
Test name
Test status
Simulation time 277127893 ps
CPU time 18.89 seconds
Started May 28 02:01:01 PM PDT 24
Finished May 28 02:01:24 PM PDT 24
Peak memory 248748 kb
Host smart-07289eb3-4d7a-4f81-bb09-d45e73a49b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12031
29872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1203129872
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3048823818
Short name T520
Test name
Test status
Simulation time 3333830090 ps
CPU time 43.5 seconds
Started May 28 02:01:02 PM PDT 24
Finished May 28 02:01:49 PM PDT 24
Peak memory 248028 kb
Host smart-1fbada09-5a6a-4df9-9c83-0d8020402689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
23818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3048823818
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3710468457
Short name T390
Test name
Test status
Simulation time 346421590 ps
CPU time 12.63 seconds
Started May 28 02:01:02 PM PDT 24
Finished May 28 02:01:19 PM PDT 24
Peak memory 248988 kb
Host smart-7f141c41-9992-4f5b-a046-a30630aa3722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37104
68457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3710468457
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3077388702
Short name T399
Test name
Test status
Simulation time 275662874 ps
CPU time 16.88 seconds
Started May 28 02:01:01 PM PDT 24
Finished May 28 02:01:22 PM PDT 24
Peak memory 248664 kb
Host smart-3c3b335b-feec-42ad-a345-fb66c5148b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
88702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3077388702
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3480488644
Short name T88
Test name
Test status
Simulation time 36415815111 ps
CPU time 951.35 seconds
Started May 28 02:00:59 PM PDT 24
Finished May 28 02:16:54 PM PDT 24
Peak memory 283720 kb
Host smart-fd3f82cc-c7fe-4abf-8d1e-734c27ee59b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480488644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3480488644
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2385746836
Short name T454
Test name
Test status
Simulation time 35996155179 ps
CPU time 1739.38 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:30:03 PM PDT 24
Peak memory 272800 kb
Host smart-198ce3ed-318d-40c4-b346-1ddd3985e920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385746836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2385746836
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3346450638
Short name T560
Test name
Test status
Simulation time 6819883932 ps
CPU time 154.67 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:03:39 PM PDT 24
Peak memory 250860 kb
Host smart-0180b304-e53b-43cc-919c-366b52394c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33464
50638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3346450638
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.962593209
Short name T33
Test name
Test status
Simulation time 210860126 ps
CPU time 16.2 seconds
Started May 28 02:01:01 PM PDT 24
Finished May 28 02:01:22 PM PDT 24
Peak memory 255824 kb
Host smart-af617b3a-bc01-4e4c-b41a-c64d1a2bd353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96259
3209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.962593209
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3945730508
Short name T223
Test name
Test status
Simulation time 18990879576 ps
CPU time 1224.69 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:21:29 PM PDT 24
Peak memory 272376 kb
Host smart-e5d1e295-12e8-45b2-ae4d-ce81630621e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945730508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3945730508
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2036244943
Short name T273
Test name
Test status
Simulation time 370061798669 ps
CPU time 1960.34 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:33:44 PM PDT 24
Peak memory 268696 kb
Host smart-30ed9479-abaa-461f-8089-82409694312c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036244943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2036244943
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3424650030
Short name T325
Test name
Test status
Simulation time 22942514009 ps
CPU time 498.02 seconds
Started May 28 02:01:02 PM PDT 24
Finished May 28 02:09:24 PM PDT 24
Peak memory 247120 kb
Host smart-002b90b5-48e9-4207-8481-588dac8976ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424650030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3424650030
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1671730945
Short name T252
Test name
Test status
Simulation time 1100735377 ps
CPU time 24.54 seconds
Started May 28 02:01:01 PM PDT 24
Finished May 28 02:01:29 PM PDT 24
Peak memory 248764 kb
Host smart-56aa08ad-94f2-44b1-b92b-cb2f238e7921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16717
30945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1671730945
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4259530585
Short name T76
Test name
Test status
Simulation time 307804156 ps
CPU time 4.43 seconds
Started May 28 02:00:59 PM PDT 24
Finished May 28 02:01:07 PM PDT 24
Peak memory 250516 kb
Host smart-f803882c-8e5b-4c25-8c09-80a64a6ddad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42595
30585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4259530585
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.110247376
Short name T608
Test name
Test status
Simulation time 464994930 ps
CPU time 31.16 seconds
Started May 28 02:01:00 PM PDT 24
Finished May 28 02:01:35 PM PDT 24
Peak memory 248788 kb
Host smart-4ceac553-9664-4ba9-9778-896bb0eae4cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11024
7376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.110247376
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1064492081
Short name T290
Test name
Test status
Simulation time 240169398298 ps
CPU time 3767.26 seconds
Started May 28 02:01:15 PM PDT 24
Finished May 28 03:04:04 PM PDT 24
Peak memory 289088 kb
Host smart-5cbcd90c-ba3f-4a7e-a141-03c4dc5dc4e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064492081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1064492081
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3715470721
Short name T615
Test name
Test status
Simulation time 33747636874 ps
CPU time 1952.79 seconds
Started May 28 02:01:15 PM PDT 24
Finished May 28 02:33:48 PM PDT 24
Peak memory 289132 kb
Host smart-6a1f6894-64ba-4416-82d7-557d70020d7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715470721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3715470721
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2648861042
Short name T703
Test name
Test status
Simulation time 4028611830 ps
CPU time 229.19 seconds
Started May 28 02:01:11 PM PDT 24
Finished May 28 02:05:03 PM PDT 24
Peak memory 249840 kb
Host smart-03fee001-aa28-4bd7-a513-c00df9c9ea28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26488
61042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2648861042
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1403231086
Short name T565
Test name
Test status
Simulation time 219741982 ps
CPU time 4.69 seconds
Started May 28 02:01:10 PM PDT 24
Finished May 28 02:01:17 PM PDT 24
Peak memory 250480 kb
Host smart-538b6a51-ee84-4cee-a80d-9c17bdcdfb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
31086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1403231086
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.189955126
Short name T302
Test name
Test status
Simulation time 40824649310 ps
CPU time 817.67 seconds
Started May 28 02:01:10 PM PDT 24
Finished May 28 02:14:50 PM PDT 24
Peak memory 271860 kb
Host smart-f070fcb1-06e1-44af-8981-038cb6567f4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189955126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.189955126
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.809752600
Short name T682
Test name
Test status
Simulation time 35978298369 ps
CPU time 1400.98 seconds
Started May 28 02:01:15 PM PDT 24
Finished May 28 02:24:37 PM PDT 24
Peak memory 267504 kb
Host smart-2b68fbd5-04ae-4bce-bc4b-6e43af42f8e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809752600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.809752600
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3127272648
Short name T558
Test name
Test status
Simulation time 48347114483 ps
CPU time 291.56 seconds
Started May 28 02:01:11 PM PDT 24
Finished May 28 02:06:05 PM PDT 24
Peak memory 254436 kb
Host smart-64aed388-d166-44eb-bbac-f73c805d818d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127272648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3127272648
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2989238774
Short name T408
Test name
Test status
Simulation time 1344413248 ps
CPU time 18.83 seconds
Started May 28 02:01:10 PM PDT 24
Finished May 28 02:01:31 PM PDT 24
Peak memory 248780 kb
Host smart-ee0ec041-cd38-48db-ac7c-a7ce1972ded6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29892
38774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2989238774
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2428635903
Short name T622
Test name
Test status
Simulation time 2566039140 ps
CPU time 38.98 seconds
Started May 28 02:01:11 PM PDT 24
Finished May 28 02:01:52 PM PDT 24
Peak memory 256284 kb
Host smart-739b5911-e548-432d-9253-eea645e14a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24286
35903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2428635903
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3426628295
Short name T511
Test name
Test status
Simulation time 3519884379 ps
CPU time 37.33 seconds
Started May 28 02:01:12 PM PDT 24
Finished May 28 02:01:51 PM PDT 24
Peak memory 247448 kb
Host smart-6a3cf497-6b40-4a46-8aba-cab4f36d5b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34266
28295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3426628295
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1377707648
Short name T501
Test name
Test status
Simulation time 213897219 ps
CPU time 21.26 seconds
Started May 28 02:01:10 PM PDT 24
Finished May 28 02:01:33 PM PDT 24
Peak memory 248772 kb
Host smart-84861ff8-88da-435c-8998-ee8a23f93217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13777
07648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1377707648
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.829152907
Short name T113
Test name
Test status
Simulation time 9133126141 ps
CPU time 534.57 seconds
Started May 28 02:01:17 PM PDT 24
Finished May 28 02:10:12 PM PDT 24
Peak memory 257020 kb
Host smart-87c42fd0-a18b-4ee1-b0be-b74707423c2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829152907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.829152907
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1926087208
Short name T74
Test name
Test status
Simulation time 19504145827 ps
CPU time 2057.3 seconds
Started May 28 02:01:10 PM PDT 24
Finished May 28 02:35:30 PM PDT 24
Peak memory 305596 kb
Host smart-42b9d24e-c57f-4484-a7f4-f659a6eea8f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926087208 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1926087208
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2382585752
Short name T506
Test name
Test status
Simulation time 578141641229 ps
CPU time 2318.29 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:40:08 PM PDT 24
Peak memory 288908 kb
Host smart-f1172941-d4a7-4769-981d-016fd2f824f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382585752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2382585752
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3537954777
Short name T373
Test name
Test status
Simulation time 329825876 ps
CPU time 9.33 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:01:38 PM PDT 24
Peak memory 254364 kb
Host smart-f040e6b7-0887-4e2e-a1ed-f0db5dbca0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35379
54777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3537954777
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2651439321
Short name T453
Test name
Test status
Simulation time 6186326383 ps
CPU time 37.32 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:02:06 PM PDT 24
Peak memory 248828 kb
Host smart-7db10cda-b8bd-45e5-8e5b-bcd15dff7b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
39321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2651439321
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1178555462
Short name T426
Test name
Test status
Simulation time 54528819016 ps
CPU time 678.76 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:12:48 PM PDT 24
Peak memory 265248 kb
Host smart-db851d6a-0a14-463a-80ad-c9a94f8bea04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178555462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1178555462
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2331026788
Short name T381
Test name
Test status
Simulation time 30825653012 ps
CPU time 1426 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:25:14 PM PDT 24
Peak memory 288816 kb
Host smart-1af72f00-515b-44ce-a547-7ece61e5a194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331026788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2331026788
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3292794350
Short name T102
Test name
Test status
Simulation time 13557514297 ps
CPU time 541.16 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:10:30 PM PDT 24
Peak memory 255300 kb
Host smart-481aa329-9f1b-41b0-ae5d-4d13d3ed9817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292794350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3292794350
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.383278236
Short name T430
Test name
Test status
Simulation time 3510091277 ps
CPU time 72.21 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:02:40 PM PDT 24
Peak memory 256264 kb
Host smart-23035cc9-3950-44d4-b639-12ad4d727a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38327
8236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.383278236
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3277642198
Short name T569
Test name
Test status
Simulation time 1586482122 ps
CPU time 24.71 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:01:52 PM PDT 24
Peak memory 248784 kb
Host smart-938f0827-3248-4dc0-b36e-73439b0f0fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32776
42198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3277642198
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1233644440
Short name T444
Test name
Test status
Simulation time 385397427 ps
CPU time 11.88 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:01:42 PM PDT 24
Peak memory 248772 kb
Host smart-73016c9b-50fe-4053-bbab-bb029c96c3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12336
44440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1233644440
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.738129942
Short name T554
Test name
Test status
Simulation time 78258836 ps
CPU time 6.47 seconds
Started May 28 02:01:11 PM PDT 24
Finished May 28 02:01:19 PM PDT 24
Peak memory 248772 kb
Host smart-dde26a35-2b12-4a4e-896b-10fe77055304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73812
9942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.738129942
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3422323325
Short name T29
Test name
Test status
Simulation time 76825325232 ps
CPU time 1520.02 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:26:50 PM PDT 24
Peak memory 288884 kb
Host smart-8cf40437-a51d-4fff-807d-3557950681c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422323325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3422323325
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.879703155
Short name T614
Test name
Test status
Simulation time 130455859437 ps
CPU time 5552.65 seconds
Started May 28 02:01:25 PM PDT 24
Finished May 28 03:34:00 PM PDT 24
Peak memory 332924 kb
Host smart-c623aba8-c51b-4553-b471-524b1d94264c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879703155 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.879703155
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2684376005
Short name T67
Test name
Test status
Simulation time 33654517726 ps
CPU time 929.06 seconds
Started May 28 02:01:47 PM PDT 24
Finished May 28 02:17:19 PM PDT 24
Peak memory 269756 kb
Host smart-63c63cc1-aa67-4d7f-aeeb-e863a816eee0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684376005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2684376005
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.865463384
Short name T228
Test name
Test status
Simulation time 1080522598 ps
CPU time 85.63 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:02:55 PM PDT 24
Peak memory 256956 kb
Host smart-2bf1f15b-5550-4f82-aaee-31f9ea117a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86546
3384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.865463384
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.854941780
Short name T525
Test name
Test status
Simulation time 1285915415 ps
CPU time 72.21 seconds
Started May 28 02:01:27 PM PDT 24
Finished May 28 02:02:42 PM PDT 24
Peak memory 256068 kb
Host smart-f98d0bf0-8588-400a-b9b7-68d2e72b9573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85494
1780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.854941780
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3040488609
Short name T333
Test name
Test status
Simulation time 75105932584 ps
CPU time 969.36 seconds
Started May 28 02:01:44 PM PDT 24
Finished May 28 02:17:56 PM PDT 24
Peak memory 266244 kb
Host smart-c280bd37-4fcc-4b11-9c44-3f35091296cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040488609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3040488609
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2183975580
Short name T496
Test name
Test status
Simulation time 565180812231 ps
CPU time 1642.79 seconds
Started May 28 02:01:44 PM PDT 24
Finished May 28 02:29:09 PM PDT 24
Peak memory 282984 kb
Host smart-874cf47c-ac60-42de-85f3-29cda0858a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183975580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2183975580
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.579980870
Short name T313
Test name
Test status
Simulation time 12863325454 ps
CPU time 537.83 seconds
Started May 28 02:01:43 PM PDT 24
Finished May 28 02:10:42 PM PDT 24
Peak memory 248780 kb
Host smart-0d4fd7b9-b686-4ba1-8e24-9cc951f05e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579980870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.579980870
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3819424070
Short name T532
Test name
Test status
Simulation time 1134537462 ps
CPU time 43.72 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:02:11 PM PDT 24
Peak memory 256048 kb
Host smart-ff1d52be-30be-48b6-999e-282d230e0133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38194
24070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3819424070
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1915602887
Short name T498
Test name
Test status
Simulation time 3785452291 ps
CPU time 56.06 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:02:25 PM PDT 24
Peak memory 248952 kb
Host smart-b6efc76e-1f05-44c3-a429-5250c4a29a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19156
02887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1915602887
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1783125724
Short name T447
Test name
Test status
Simulation time 563425768 ps
CPU time 32.94 seconds
Started May 28 02:01:26 PM PDT 24
Finished May 28 02:02:00 PM PDT 24
Peak memory 249216 kb
Host smart-b0072bde-92e8-4bd2-ab24-889829b8b47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17831
25724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1783125724
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.760064729
Short name T487
Test name
Test status
Simulation time 1326598283 ps
CPU time 37.62 seconds
Started May 28 02:01:28 PM PDT 24
Finished May 28 02:02:08 PM PDT 24
Peak memory 248860 kb
Host smart-b2f02868-5245-406c-97ee-4e9b65f97278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76006
4729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.760064729
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3767949187
Short name T49
Test name
Test status
Simulation time 287408523668 ps
CPU time 3120.82 seconds
Started May 28 02:01:44 PM PDT 24
Finished May 28 02:53:47 PM PDT 24
Peak memory 305792 kb
Host smart-03f6faac-f411-43fe-b683-3ca301084bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767949187 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3767949187
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.405174366
Short name T215
Test name
Test status
Simulation time 46033750 ps
CPU time 3.79 seconds
Started May 28 01:58:13 PM PDT 24
Finished May 28 01:58:18 PM PDT 24
Peak memory 248964 kb
Host smart-af446306-6317-4346-94ba-581411bac308
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=405174366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.405174366
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.289938020
Short name T677
Test name
Test status
Simulation time 418449894089 ps
CPU time 1709.31 seconds
Started May 28 01:58:13 PM PDT 24
Finished May 28 02:26:44 PM PDT 24
Peak memory 273248 kb
Host smart-3964f357-bed2-447e-a220-41057044e22e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289938020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.289938020
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1033973352
Short name T570
Test name
Test status
Simulation time 654178930 ps
CPU time 13.37 seconds
Started May 28 01:58:15 PM PDT 24
Finished May 28 01:58:30 PM PDT 24
Peak memory 248760 kb
Host smart-e5fe2fe9-79e0-4306-aa7c-9d53c82b5a72
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1033973352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1033973352
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.866220893
Short name T535
Test name
Test status
Simulation time 1172634158 ps
CPU time 29.27 seconds
Started May 28 01:58:13 PM PDT 24
Finished May 28 01:58:44 PM PDT 24
Peak memory 249256 kb
Host smart-1738c418-7ace-43f7-a1c1-bc77eb03c499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86622
0893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.866220893
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3424842289
Short name T59
Test name
Test status
Simulation time 315132787 ps
CPU time 29.45 seconds
Started May 28 01:58:15 PM PDT 24
Finished May 28 01:58:46 PM PDT 24
Peak memory 248784 kb
Host smart-ef691a94-6db6-4acc-bb70-6783c094a875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
42289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3424842289
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1607316300
Short name T510
Test name
Test status
Simulation time 117207263303 ps
CPU time 1781.07 seconds
Started May 28 01:58:12 PM PDT 24
Finished May 28 02:27:54 PM PDT 24
Peak memory 267304 kb
Host smart-67602283-d7c4-4753-8bf0-7169775b55b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607316300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1607316300
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1633211552
Short name T92
Test name
Test status
Simulation time 111783389260 ps
CPU time 1884.61 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 02:29:42 PM PDT 24
Peak memory 289308 kb
Host smart-85262d2a-f977-4259-ad66-35713d55ee61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633211552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1633211552
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.181298803
Short name T272
Test name
Test status
Simulation time 8207517875 ps
CPU time 338.92 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 02:03:57 PM PDT 24
Peak memory 248236 kb
Host smart-3fe5005c-b236-4301-8742-e8571da5aaa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181298803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.181298803
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3235396091
Short name T393
Test name
Test status
Simulation time 813869683 ps
CPU time 26.21 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 01:58:44 PM PDT 24
Peak memory 249104 kb
Host smart-afdfd4ed-fa74-41cb-9f4b-9add29131501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32353
96091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3235396091
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2429046736
Short name T225
Test name
Test status
Simulation time 1787396940 ps
CPU time 44.53 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 01:59:02 PM PDT 24
Peak memory 256796 kb
Host smart-ecc2f9cd-cf63-4c1c-b846-8c2dd0084c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290
46736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2429046736
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3263423189
Short name T466
Test name
Test status
Simulation time 915178945 ps
CPU time 49.72 seconds
Started May 28 01:58:18 PM PDT 24
Finished May 28 01:59:09 PM PDT 24
Peak memory 248756 kb
Host smart-0dc95881-ac01-4249-a39e-bcbceec6844d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32634
23189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3263423189
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1989965031
Short name T581
Test name
Test status
Simulation time 6155681496 ps
CPU time 87.66 seconds
Started May 28 01:58:12 PM PDT 24
Finished May 28 01:59:41 PM PDT 24
Peak memory 256996 kb
Host smart-9215f09e-5564-4d6e-9ab5-29a03f4d6e29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989965031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1989965031
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.999893221
Short name T178
Test name
Test status
Simulation time 96097837500 ps
CPU time 2401.62 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 02:38:17 PM PDT 24
Peak memory 306264 kb
Host smart-7698e8a1-9d7b-4a8b-af29-b11b80425b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999893221 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.999893221
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4039975835
Short name T217
Test name
Test status
Simulation time 94238107 ps
CPU time 3.28 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 01:58:18 PM PDT 24
Peak memory 248932 kb
Host smart-90d2c615-d718-401a-9a1f-c859ef783ff3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4039975835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4039975835
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1046321530
Short name T397
Test name
Test status
Simulation time 127201276817 ps
CPU time 1599.51 seconds
Started May 28 01:58:18 PM PDT 24
Finished May 28 02:24:58 PM PDT 24
Peak memory 273276 kb
Host smart-6dc44952-294a-4e1e-995d-40f7b51b30dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046321530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1046321530
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1151847607
Short name T519
Test name
Test status
Simulation time 608211153 ps
CPU time 10.11 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 01:58:25 PM PDT 24
Peak memory 248792 kb
Host smart-deb045b1-0cda-404e-8591-46a2db9c2f6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1151847607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1151847607
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.363153903
Short name T550
Test name
Test status
Simulation time 1151019920 ps
CPU time 101.64 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 01:59:59 PM PDT 24
Peak memory 256820 kb
Host smart-4bdf217c-8c1f-4966-ada4-5c0589a21dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36315
3903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.363153903
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2283369028
Short name T491
Test name
Test status
Simulation time 1288740356 ps
CPU time 43.4 seconds
Started May 28 01:58:17 PM PDT 24
Finished May 28 01:59:02 PM PDT 24
Peak memory 255924 kb
Host smart-cf5ace0b-309a-4e78-bff7-b3476e1584bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833
69028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2283369028
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.473502328
Short name T531
Test name
Test status
Simulation time 113906861619 ps
CPU time 979.92 seconds
Started May 28 01:58:18 PM PDT 24
Finished May 28 02:14:39 PM PDT 24
Peak memory 270368 kb
Host smart-b7eac749-e145-4ba7-91bd-0f9b6855dd71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473502328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.473502328
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.755222509
Short name T460
Test name
Test status
Simulation time 104146230704 ps
CPU time 1604.41 seconds
Started May 28 01:58:18 PM PDT 24
Finished May 28 02:25:04 PM PDT 24
Peak memory 289368 kb
Host smart-78d2c6c3-0046-47a6-bf20-a49fd61ce7cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755222509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.755222509
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2533705094
Short name T317
Test name
Test status
Simulation time 6372965286 ps
CPU time 256.73 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 02:02:34 PM PDT 24
Peak memory 248260 kb
Host smart-ef4e8780-089f-4c1b-9199-745d06dafcc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533705094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2533705094
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2199653400
Short name T370
Test name
Test status
Simulation time 178080130 ps
CPU time 4.86 seconds
Started May 28 01:58:15 PM PDT 24
Finished May 28 01:58:21 PM PDT 24
Peak memory 240584 kb
Host smart-f9d0f444-8b16-44ba-86c7-6c03043e9fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21996
53400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2199653400
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1393525375
Short name T562
Test name
Test status
Simulation time 46676948 ps
CPU time 4.83 seconds
Started May 28 01:58:15 PM PDT 24
Finished May 28 01:58:21 PM PDT 24
Peak memory 251984 kb
Host smart-6840f71f-9b53-48ff-93bc-4dad2ce48ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13935
25375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1393525375
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1232379407
Short name T655
Test name
Test status
Simulation time 357694834 ps
CPU time 19.66 seconds
Started May 28 01:58:14 PM PDT 24
Finished May 28 01:58:35 PM PDT 24
Peak memory 248776 kb
Host smart-2a4adaf6-35cc-4ce0-a28a-f76f37d6a312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
79407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1232379407
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.453633538
Short name T376
Test name
Test status
Simulation time 4855330453 ps
CPU time 66.16 seconds
Started May 28 01:58:17 PM PDT 24
Finished May 28 01:59:25 PM PDT 24
Peak memory 248840 kb
Host smart-84dd4e6c-a87a-42e6-ab65-3c42ccb48d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45363
3538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.453633538
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1999269334
Short name T439
Test name
Test status
Simulation time 844072843 ps
CPU time 47.98 seconds
Started May 28 01:58:16 PM PDT 24
Finished May 28 01:59:06 PM PDT 24
Peak memory 255656 kb
Host smart-a667146e-c51e-43da-b420-ff22ee9c134e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999269334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1999269334
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3405886982
Short name T209
Test name
Test status
Simulation time 73883484 ps
CPU time 3.51 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 01:58:29 PM PDT 24
Peak memory 248916 kb
Host smart-8af8924e-e032-47cc-86d0-91162898b5c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3405886982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3405886982
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1246545730
Short name T610
Test name
Test status
Simulation time 9464983981 ps
CPU time 758.59 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 272624 kb
Host smart-4f932713-84e6-408f-ba1d-e8ab8094b001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246545730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1246545730
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.373695208
Short name T238
Test name
Test status
Simulation time 9556716494 ps
CPU time 57.99 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:59:25 PM PDT 24
Peak memory 240624 kb
Host smart-b0818466-80c4-46ed-8cde-e9acf1dccb62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=373695208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.373695208
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.739438963
Short name T415
Test name
Test status
Simulation time 7418917223 ps
CPU time 262.81 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 02:02:55 PM PDT 24
Peak memory 251980 kb
Host smart-1526edd1-6fa9-4ac4-a0f1-97e848245442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73943
8963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.739438963
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2322793880
Short name T243
Test name
Test status
Simulation time 115190485 ps
CPU time 3.74 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:58:31 PM PDT 24
Peak memory 239204 kb
Host smart-cc489b57-86d7-4ba4-a2f5-f5942cb29865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23227
93880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2322793880
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3609087569
Short name T343
Test name
Test status
Simulation time 49136354146 ps
CPU time 1222.24 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:18:52 PM PDT 24
Peak memory 286788 kb
Host smart-04d13c27-ff3a-451a-8494-bee2a80ea5e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609087569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3609087569
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2795550044
Short name T253
Test name
Test status
Simulation time 16967260050 ps
CPU time 726.6 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 02:10:35 PM PDT 24
Peak memory 265276 kb
Host smart-d5f8723b-8029-4a1a-80a9-63a1631bac00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795550044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2795550044
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1988791231
Short name T521
Test name
Test status
Simulation time 7401264571 ps
CPU time 299.09 seconds
Started May 28 01:58:29 PM PDT 24
Finished May 28 02:03:31 PM PDT 24
Peak memory 248260 kb
Host smart-d226b8e4-a43a-4b2f-98ca-d9a0028163a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988791231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1988791231
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3373747324
Short name T202
Test name
Test status
Simulation time 4203028184 ps
CPU time 39.51 seconds
Started May 28 01:58:29 PM PDT 24
Finished May 28 01:59:11 PM PDT 24
Peak memory 248844 kb
Host smart-71bb38e0-f0f5-438c-9d06-9bc24413e6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33737
47324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3373747324
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3719142762
Short name T181
Test name
Test status
Simulation time 5201688118 ps
CPU time 65.66 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 01:59:34 PM PDT 24
Peak memory 255900 kb
Host smart-fdde1e0d-0ac6-4b7a-9ad2-b5b79c91c333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37191
42762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3719142762
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.536887404
Short name T459
Test name
Test status
Simulation time 230747417 ps
CPU time 7.03 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 01:58:32 PM PDT 24
Peak memory 248792 kb
Host smart-42207d73-63e6-45e4-a6f8-ec957ec0dda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53688
7404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.536887404
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3499765566
Short name T258
Test name
Test status
Simulation time 286676348 ps
CPU time 22.75 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 01:58:48 PM PDT 24
Peak memory 248800 kb
Host smart-c501be58-f137-4bba-996d-8f7d4cc7f1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34997
65566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3499765566
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3769164310
Short name T288
Test name
Test status
Simulation time 58284679826 ps
CPU time 1655.06 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:26:05 PM PDT 24
Peak memory 289824 kb
Host smart-d4594a8e-8eee-4e30-a3e3-9991e8d90104
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769164310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3769164310
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1569131524
Short name T63
Test name
Test status
Simulation time 20939197 ps
CPU time 2.86 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 01:58:33 PM PDT 24
Peak memory 248936 kb
Host smart-e49b0dc7-355f-4a4b-a0bf-74229e5589fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1569131524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1569131524
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.274638311
Short name T96
Test name
Test status
Simulation time 15659171090 ps
CPU time 1360.89 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 02:21:09 PM PDT 24
Peak memory 281668 kb
Host smart-a3d64560-603c-4663-a616-bba66e346a8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274638311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.274638311
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.609184207
Short name T700
Test name
Test status
Simulation time 380186254 ps
CPU time 6.37 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 01:58:32 PM PDT 24
Peak memory 240576 kb
Host smart-dfbebdf0-df67-43d1-a470-1a7d31906ab0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=609184207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.609184207
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.881144671
Short name T559
Test name
Test status
Simulation time 4381588132 ps
CPU time 230.39 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:02:20 PM PDT 24
Peak memory 249888 kb
Host smart-e7a225ef-71d6-4ddb-93fa-781bdcbcbc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88114
4671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.881144671
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3370340052
Short name T294
Test name
Test status
Simulation time 14133433452 ps
CPU time 69.74 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 01:59:42 PM PDT 24
Peak memory 256072 kb
Host smart-1e2d17bd-0e24-4f1b-8f6a-4514cfe362a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703
40052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3370340052
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3941224572
Short name T296
Test name
Test status
Simulation time 66976580524 ps
CPU time 1502.99 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 02:23:29 PM PDT 24
Peak memory 288996 kb
Host smart-ac285e8a-cbe5-47ac-b94f-33b2002f484a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941224572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3941224572
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2315542910
Short name T434
Test name
Test status
Simulation time 11733240070 ps
CPU time 1238.96 seconds
Started May 28 01:58:32 PM PDT 24
Finished May 28 02:19:13 PM PDT 24
Peak memory 281596 kb
Host smart-9aca0bff-a0fe-46c2-85a5-14bafb3a99cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315542910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2315542910
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4240016474
Short name T666
Test name
Test status
Simulation time 10940986074 ps
CPU time 451.93 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 02:06:04 PM PDT 24
Peak memory 255768 kb
Host smart-a248e26c-7ee1-4f66-8048-9f8873099aa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240016474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4240016474
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2729099500
Short name T576
Test name
Test status
Simulation time 950835638 ps
CPU time 7.48 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:58:35 PM PDT 24
Peak memory 249124 kb
Host smart-be4f261e-c5e7-46a7-ab65-e67b3aaee58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27290
99500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2729099500
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.190356290
Short name T112
Test name
Test status
Simulation time 955335993 ps
CPU time 65.74 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:59:33 PM PDT 24
Peak memory 255624 kb
Host smart-335cd1c7-61f3-49da-937b-bbc1c3d5d130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19035
6290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.190356290
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3485717551
Short name T424
Test name
Test status
Simulation time 505879868 ps
CPU time 14.63 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 01:58:43 PM PDT 24
Peak memory 247660 kb
Host smart-1c8946c0-8f82-4f9b-8b5a-aeb83d4c0135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34857
17551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3485717551
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3376176128
Short name T687
Test name
Test status
Simulation time 456235467 ps
CPU time 12.75 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 01:58:41 PM PDT 24
Peak memory 248768 kb
Host smart-ebb60761-ab21-4e9f-9a1a-9d0d6605885c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33761
76128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3376176128
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.491146662
Short name T481
Test name
Test status
Simulation time 16534768259 ps
CPU time 228.38 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 02:02:14 PM PDT 24
Peak memory 256992 kb
Host smart-9fdf13c1-0aff-448d-9947-d677e612cb9e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491146662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.491146662
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.402819244
Short name T242
Test name
Test status
Simulation time 26637738202 ps
CPU time 1657.65 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:26:07 PM PDT 24
Peak memory 288760 kb
Host smart-af2456e2-35ec-4812-b77e-510779b9ec60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402819244 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.402819244
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3474256105
Short name T60
Test name
Test status
Simulation time 37924965 ps
CPU time 2.3 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 01:58:35 PM PDT 24
Peak memory 248932 kb
Host smart-88a92d44-8369-4b50-81ea-6c67c98a1702
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3474256105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3474256105
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.889640993
Short name T422
Test name
Test status
Simulation time 36588021426 ps
CPU time 1529.9 seconds
Started May 28 01:58:24 PM PDT 24
Finished May 28 02:23:56 PM PDT 24
Peak memory 289488 kb
Host smart-981a1df4-8ed7-4201-8083-5bb482200056
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889640993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.889640993
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3538693905
Short name T513
Test name
Test status
Simulation time 1352723491 ps
CPU time 13.17 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 01:58:42 PM PDT 24
Peak memory 248788 kb
Host smart-04da80d9-a095-4f2c-8cdf-3d32264d1a21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3538693905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3538693905
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.193381262
Short name T515
Test name
Test status
Simulation time 30389606889 ps
CPU time 263.35 seconds
Started May 28 01:58:30 PM PDT 24
Finished May 28 02:02:55 PM PDT 24
Peak memory 250344 kb
Host smart-f3cf35ba-f85c-4420-a0d5-022aa8245c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
1262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.193381262
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3244992911
Short name T275
Test name
Test status
Simulation time 130431761 ps
CPU time 9.03 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 01:58:37 PM PDT 24
Peak memory 248836 kb
Host smart-79a0af74-4095-4b4a-826c-16b7e37ac87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449
92911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3244992911
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.429624743
Short name T188
Test name
Test status
Simulation time 178247147420 ps
CPU time 808.67 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 265192 kb
Host smart-8ecbe7b8-11dd-4f73-a7df-0564335d9588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429624743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.429624743
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2625509541
Short name T632
Test name
Test status
Simulation time 104138532745 ps
CPU time 921.58 seconds
Started May 28 01:58:26 PM PDT 24
Finished May 28 02:13:50 PM PDT 24
Peak memory 273404 kb
Host smart-3c9f7fb9-f959-4fc1-be92-dde306271155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625509541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2625509541
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1248147496
Short name T653
Test name
Test status
Simulation time 3063561699 ps
CPU time 52.67 seconds
Started May 28 01:58:28 PM PDT 24
Finished May 28 01:59:24 PM PDT 24
Peak memory 248836 kb
Host smart-9bc5738d-1eb3-44f0-b10b-6b55bd648f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
47496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1248147496
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1582564012
Short name T66
Test name
Test status
Simulation time 300256658 ps
CPU time 6.34 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:58:33 PM PDT 24
Peak memory 251360 kb
Host smart-5236bbed-60ab-4bd4-9740-a2df373c7a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
64012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1582564012
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2657547978
Short name T475
Test name
Test status
Simulation time 828365310 ps
CPU time 15.37 seconds
Started May 28 01:58:28 PM PDT 24
Finished May 28 01:58:46 PM PDT 24
Peak memory 255096 kb
Host smart-5279b563-5444-4697-819a-21df6c722576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26575
47978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2657547978
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1202331260
Short name T64
Test name
Test status
Simulation time 1733514055 ps
CPU time 48.14 seconds
Started May 28 01:58:25 PM PDT 24
Finished May 28 01:59:15 PM PDT 24
Peak memory 256664 kb
Host smart-84608abd-a790-4b31-bb6b-a64c4390b2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023
31260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1202331260
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2787643941
Short name T684
Test name
Test status
Simulation time 26824695948 ps
CPU time 3161.41 seconds
Started May 28 01:58:27 PM PDT 24
Finished May 28 02:51:12 PM PDT 24
Peak memory 321328 kb
Host smart-7e345bb3-6d21-4b0f-8eeb-533c9ee8c1be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787643941 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2787643941
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%