Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	105789	1			T18	225		T12	27		T13	1929
class_i[0x1]	79635	1			T2	1		T18	1252		T8	9
class_i[0x2]	41696	1			T3	10		T7	29		T18	1
class_i[0x3]	84817	1			T4	8		T18	1348		T12	4569

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	78546	1			T3	4		T4	3		T7	12
alert[0x1]	79113	1			T2	1		T3	2		T7	7
alert[0x2]	77554	1			T3	2		T7	4		T18	753
alert[0x3]	76724	1			T3	2		T4	5		T7	6

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

311639

1

T2

1

T4

5

T7

29

esc_ping_fail

298

1

T3

10

T4

3

T8

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	78465	1			T4	2		T7	12		T18	1369
esc_integrity_fail	alert[0x1]	79040	1			T2	1		T7	7		T18	704
esc_integrity_fail	alert[0x2]	77478	1			T7	4		T18	753		T12	1058
esc_integrity_fail	alert[0x3]	76656	1			T4	3		T7	6		T12	1153
esc_ping_fail	alert[0x0]	81	1			T3	4		T4	1		T8	1
esc_ping_fail	alert[0x1]	73	1			T3	2		T8	3		T79	1
esc_ping_fail	alert[0x2]	76	1			T3	2		T8	2		T79	1
esc_ping_fail	alert[0x3]	68	1			T3	2		T4	2		T8	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	105727	1			T18	225		T12	27		T13	1929
esc_integrity_fail	class_i[0x1]	79573	1			T2	1		T18	1252		T45	152
esc_integrity_fail	class_i[0x2]	41597	1			T7	29		T18	1		T12	8
esc_integrity_fail	class_i[0x3]	84742	1			T4	5		T18	1348		T12	4569
esc_ping_fail	class_i[0x0]	62	1			T37	6		T283	6		T288	1
esc_ping_fail	class_i[0x1]	62	1			T8	9		T223	5		T286	2
esc_ping_fail	class_i[0x2]	99	1			T3	10		T79	8		T308	4
esc_ping_fail	class_i[0x3]	75	1			T4	3		T182	8		T213	1