Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	68	1			T16	1		T18	1		T45	1
class_index[0x1]	68	1			T2	2		T7	1		T13	1
class_index[0x2]	54	1			T7	1		T24	1		T73	3
class_index[0x3]	53	1			T7	1		T84	1		T105	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	96	1			T2	1		T13	1		T75	2
intr_timeout_cnt[1]	72	1			T2	1		T7	1		T16	1
intr_timeout_cnt[2]	17	1			T84	1		T86	1		T236	1
intr_timeout_cnt[3]	8	1			T7	1		T45	1		T85	1
intr_timeout_cnt[4]	13	1			T105	1		T87	1		T215	1
intr_timeout_cnt[5]	13	1			T80	1		T47	1		T25	2
intr_timeout_cnt[6]	8	1			T7	1		T24	1		T23	1
intr_timeout_cnt[7]	4	1			T23	1		T87	1		T237	1
intr_timeout_cnt[8]	10	1			T18	1		T84	1		T85	1
intr_timeout_cnt[9]	2	1			T238	1		T239	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	32	1			T23	1		T38	3		T240	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T16	1		T76	1		T84	2
class_index[0x0]	intr_timeout_cnt[2]	4	1			T84	1		T236	1		T241	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T45	1		T184	1		T239	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T87	1		T59	1		T242	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T80	1		T47	1		T243	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T228	1		T244	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T18	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T238	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	32	1			T2	1		T13	1		T75	2
class_index[0x1]	intr_timeout_cnt[1]	16	1			T2	1		T7	1		T68	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T245	1		T246	1		T95	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T237	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T247	1		T248	2		-	-
class_index[0x1]	intr_timeout_cnt[5]	4	1			T25	2		T95	2		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T23	1		T249	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T87	1		T250	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T85	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	15	1			T84	1		T104	1		T58	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T73	3		T80	1		T68	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T86	1		T57	2		T241	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T7	1		T85	1		T243	1
class_index[0x2]	intr_timeout_cnt[4]	4	1			T215	1		T60	1		T251	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T252	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T24	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T23	1		T237	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	4	1			T84	1		T110	2		T228	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T239	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	17	1			T116	1		T57	2		T58	2
class_index[0x3]	intr_timeout_cnt[1]	24	1			T84	1		T57	2		T118	1
class_index[0x3]	intr_timeout_cnt[2]	1	1			T107	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T105	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T115	1		T253	1		T227	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T7	1		T117	1		T254	1
class_index[0x3]	intr_timeout_cnt[8]	4	1			T241	1		T255	1		T22	2