Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	378826	1			T1	31		T2	2817		T3	53
all_values[1]	378826	1			T1	31		T2	2817		T3	53
all_values[2]	378826	1			T1	31		T2	2817		T3	53
all_values[3]	378826	1			T1	31		T2	2817		T3	53

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

755419

1

T1

82

T2

5656

T7

3151

auto[1]

759885

1

T1

42

T2

5612

T3

212

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

903018

1

T1

117

T2

6696

T3

185

auto[1]

612286

1

T1

7

T2

4572

T3

27

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	108415	1			T1	18		T2	843		T7	409
all_values[0]	auto[0]	auto[1]	80584	1			T1	5		T2	569		T7	397
all_values[0]	auto[1]	auto[0]	109517	1			T1	6		T2	873		T3	53
all_values[0]	auto[1]	auto[1]	80310	1			T1	2		T2	532		T4	2
all_values[1]	auto[0]	auto[0]	112715	1			T1	25		T2	837		T7	410
all_values[1]	auto[0]	auto[1]	76302	1			T2	532		T7	398		T5	431
all_values[1]	auto[1]	auto[0]	113699	1			T1	6		T2	892		T3	52
all_values[1]	auto[1]	auto[1]	76110	1			T2	556		T3	1		T4	6
all_values[2]	auto[0]	auto[0]	113528	1			T1	16		T2	820		T7	382
all_values[2]	auto[0]	auto[1]	75410	1			T2	588		T7	377		T5	433
all_values[2]	auto[1]	auto[0]	114684	1			T1	15		T2	835		T3	43
all_values[2]	auto[1]	auto[1]	75204	1			T2	574		T3	10		T4	3
all_values[3]	auto[0]	auto[0]	114344	1			T1	18		T2	835		T7	395
all_values[3]	auto[0]	auto[1]	74121	1			T2	632		T7	383		T5	430
all_values[3]	auto[1]	auto[0]	116116	1			T1	13		T2	761		T3	37
all_values[3]	auto[1]	auto[1]	74245	1			T2	589		T3	16		T4	3