Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	378826	1			T1	31		T2	2817		T3	53
all_pins[1]	378826	1			T1	31		T2	2817		T3	53
all_pins[2]	378826	1			T1	31		T2	2817		T3	53
all_pins[3]	378826	1			T1	31		T2	2817		T3	53

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1209435	1			T1	122		T2	9017		T3	185
values[0x1]	305869	1			T1	2		T2	2251		T3	27
transitions[0x0=>0x1]	204016	1			T1	2		T2	1472		T3	27
transitions[0x1=>0x0]	204288	1			T1	2		T2	1473		T3	27

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	298516	1			T1	29		T2	2285		T3	53
all_pins[0]	values[0x1]	80310	1			T1	2		T2	532		T4	2
all_pins[0]	transitions[0x0=>0x1]	79656	1			T1	2		T2	530		T4	2
all_pins[0]	transitions[0x1=>0x0]	73863	1			T2	588		T3	16		T4	3
all_pins[1]	values[0x0]	302716	1			T1	31		T2	2261		T3	52
all_pins[1]	values[0x1]	76110	1			T2	556		T3	1		T4	6
all_pins[1]	transitions[0x0=>0x1]	42339	1			T2	326		T3	1		T4	6
all_pins[1]	transitions[0x1=>0x0]	46539	1			T1	2		T2	302		T4	2
all_pins[2]	values[0x0]	303622	1			T1	31		T2	2243		T3	43
all_pins[2]	values[0x1]	75204	1			T2	574		T3	10		T4	3
all_pins[2]	transitions[0x0=>0x1]	41093	1			T2	299		T3	10		T4	3
all_pins[2]	transitions[0x1=>0x0]	41999	1			T2	281		T3	1		T4	6
all_pins[3]	values[0x0]	304581	1			T1	31		T2	2228		T3	37
all_pins[3]	values[0x1]	74245	1			T2	589		T3	16		T4	3
all_pins[3]	transitions[0x0=>0x1]	40928	1			T2	317		T3	16		T4	3
all_pins[3]	transitions[0x1=>0x0]	41887	1			T2	302		T3	10		T4	3