Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	98151	1			T2	848		T7	514		T5	1243
accum_cnt_1000	241161	1			T2	2337		T7	480		T5	1081
accum_cnt_100	29837	1			T2	213		T7	53		T5	50
accum_cnt_50	80866	1			T2	207		T7	166		T5	47
accum_cnt_10	193005	1			T2	1054		T3	25		T4	23
accum_cnt_0	430550	1			T1	88		T2	3281		T3	115

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	279427	1			T1	22		T2	1985		T3	35
class_index[0x1]	279427	1			T1	22		T2	1985		T3	35
class_index[0x2]	279427	1			T1	22		T2	1985		T3	35
class_index[0x3]	279427	1			T1	22		T2	1985		T3	35

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26596	1			T2	199		T13	243		T45	194
class_index[0x0]	accum_cnt_1000	60005	1			T2	1142		T43	2		T13	550
class_index[0x0]	accum_cnt_100	8636	1			T2	99		T7	1		T42	7
class_index[0x0]	accum_cnt_50	20932	1			T2	114		T7	32		T12	2
class_index[0x0]	accum_cnt_10	55843	1			T2	227		T7	1053		T16	1
class_index[0x0]	accum_cnt_0	89472	1			T1	22		T2	204		T3	35
class_index[0x1]	accum_cnt_2000	25954	1			T5	619		T12	672		T14	505
class_index[0x1]	accum_cnt_1000	61151	1			T5	545		T17	45		T18	1
class_index[0x1]	accum_cnt_100	7580	1			T5	26		T17	23		T12	10
class_index[0x1]	accum_cnt_50	12262	1			T7	59		T5	26		T17	23
class_index[0x1]	accum_cnt_10	50557	1			T2	749		T3	1		T4	14
class_index[0x1]	accum_cnt_0	113486	1			T1	22		T2	1236		T3	34
class_index[0x2]	accum_cnt_2000	24064	1			T2	348		T7	514		T5	624
class_index[0x2]	accum_cnt_1000	62589	1			T2	586		T7	471		T5	536
class_index[0x2]	accum_cnt_100	6949	1			T2	57		T7	38		T5	24
class_index[0x2]	accum_cnt_50	23764	1			T2	51		T7	47		T5	21
class_index[0x2]	accum_cnt_10	40563	1			T2	27		T3	24		T4	9
class_index[0x2]	accum_cnt_0	113782	1			T1	22		T2	916		T3	11
class_index[0x3]	accum_cnt_2000	21537	1			T2	301		T12	223		T13	138
class_index[0x3]	accum_cnt_1000	57416	1			T2	609		T7	9		T17	64
class_index[0x3]	accum_cnt_100	6672	1			T2	57		T7	14		T17	17
class_index[0x3]	accum_cnt_50	23908	1			T2	42		T7	28		T17	15
class_index[0x3]	accum_cnt_10	46042	1			T2	51		T7	1065		T17	2
class_index[0x3]	accum_cnt_0	113810	1			T1	22		T2	925		T3	35