Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	5397	1			T4	1		T7	89		T21	33
alert[0x1]	4587	1			T7	45		T46	8		T27	11
alert[0x2]	7407	1			T3	1		T7	69		T8	1
alert[0x3]	12055	1			T4	1		T7	2969		T45	8
alert[0x4]	8024	1			T2	15		T13	1		T45	1
alert[0x5]	2871	1			T8	1		T27	15		T76	11
alert[0x6]	2696	1			T4	1		T76	64		T68	37
alert[0x7]	6395	1			T3	1		T7	3833		T68	75
alert[0x8]	7678	1			T2	9		T46	43		T76	24
alert[0x9]	3397	1			T46	51		T71	121		T47	4
alert[0xa]	3184	1			T7	1011		T46	181		T76	2
alert[0xb]	3875	1			T46	18		T182	1		T283	1
alert[0xc]	4079	1			T2	179		T7	50		T76	40
alert[0xd]	5037	1			T8	1		T45	1		T46	23
alert[0xe]	4920	1			T45	28		T24	21		T46	221
alert[0xf]	3549	1			T3	1		T4	1		T45	5
alert[0x10]	7940	1			T3	1		T8	1		T27	14
alert[0x11]	5075	1			T24	1		T68	1		T71	1679
alert[0x12]	3685	1			T3	1		T7	56		T45	69
alert[0x13]	6527	1			T4	1		T7	175		T12	1
alert[0x14]	2527	1			T3	1		T8	2		T45	7
alert[0x15]	4763	1			T3	1		T7	69		T8	1
alert[0x16]	6084	1			T4	1		T12	1		T46	75
alert[0x17]	5331	1			T7	32		T46	199		T27	227
alert[0x18]	5962	1			T3	1		T12	5		T46	390
alert[0x19]	6084	1			T2	9		T45	15		T27	3
alert[0x1a]	3005	1			T2	10		T7	13		T8	1
alert[0x1b]	7071	1			T7	2035		T45	27		T69	326
alert[0x1c]	4463	1			T2	203		T3	1		T12	16
alert[0x1d]	6467	1			T2	32		T3	1		T4	1
alert[0x1e]	3306	1			T2	121		T3	1		T8	3
alert[0x1f]	4123	1			T12	159		T68	783		T69	23
alert[0x20]	2931	1			T7	102		T45	2		T46	69
alert[0x21]	5602	1			T2	9		T46	24		T76	19
alert[0x22]	4243	1			T45	10		T46	12		T21	20
alert[0x23]	3880	1			T2	2		T68	132		T71	953
alert[0x24]	9481	1			T2	12		T3	1		T7	204
alert[0x25]	2973	1			T8	1		T76	27		T68	4
alert[0x26]	4436	1			T2	16		T45	55		T76	54
alert[0x27]	8274	1			T2	1		T3	1		T4	1
alert[0x28]	8312	1			T45	38		T46	158		T76	3403
alert[0x29]	4580	1			T2	5		T4	1		T7	31
alert[0x2a]	7160	1			T2	2		T7	19		T45	176
alert[0x2b]	8139	1			T7	21		T27	135		T71	350
alert[0x2c]	9426	1			T2	94		T7	114		T45	47
alert[0x2d]	4654	1			T12	4		T76	44		T69	134
alert[0x2e]	3599	1			T3	1		T46	442		T68	1
alert[0x2f]	5480	1			T2	1		T27	1		T76	13
alert[0x30]	3470	1			T3	1		T12	4		T8	1
alert[0x31]	8270	1			T37	1		T225	122		T86	1028
alert[0x32]	4931	1			T2	3		T7	1692		T45	7
alert[0x33]	6517	1			T2	11		T12	1		T45	4
alert[0x34]	4902	1			T2	17		T7	115		T45	212
alert[0x35]	3197	1			T8	1		T45	9		T46	319
alert[0x36]	5621	1			T3	1		T27	141		T69	2
alert[0x37]	5721	1			T2	13		T7	96		T46	9
alert[0x38]	12911	1			T7	25		T76	1096		T69	508
alert[0x39]	3365	1			T2	46		T7	38		T39	13
alert[0x3a]	8927	1			T2	36		T4	1		T7	2
alert[0x3b]	8625	1			T24	1		T46	1680		T76	574
alert[0x3c]	5434	1			T27	2		T76	266		T68	35
alert[0x3d]	3877	1			T3	1		T46	22		T76	68
alert[0x3e]	3611	1			T7	24		T45	53		T46	16
alert[0x3f]	8432	1			T45	251		T24	3		T76	68
alert[0x40]	6298	1			T4	1		T24	2		T27	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	172522	1			T2	710		T4	2		T7	13077
class_i[0x1]	78204	1			T2	77		T3	1		T4	6
class_i[0x2]	27491	1			T2	28		T4	3		T12	45
class_i[0x3]	86626	1			T2	31		T3	16		T7	69

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

364131

1

T2

846

T7

13146

T12

191

alert_ping_fail

712

1

T3

17

T4

11

T8

16

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	5384	1			T7	89		T21	33		T68	61
alert_integrity_fail	alert[0x1]	4574	1			T7	45		T46	8		T27	11
alert_integrity_fail	alert[0x2]	7391	1			T7	69		T21	11		T68	20
alert_integrity_fail	alert[0x3]	12048	1			T7	2969		T45	8		T21	776
alert_integrity_fail	alert[0x4]	8019	1			T2	15		T13	1		T45	1
alert_integrity_fail	alert[0x5]	2862	1			T27	15		T76	11		T69	26
alert_integrity_fail	alert[0x6]	2681	1			T76	64		T68	37		T69	15
alert_integrity_fail	alert[0x7]	6385	1			T7	3833		T68	75		T69	102
alert_integrity_fail	alert[0x8]	7657	1			T2	9		T46	43		T76	24
alert_integrity_fail	alert[0x9]	3389	1			T46	51		T71	121		T47	4
alert_integrity_fail	alert[0xa]	3172	1			T7	1011		T46	181		T76	2
alert_integrity_fail	alert[0xb]	3866	1			T46	18		T29	1		T113	89
alert_integrity_fail	alert[0xc]	4072	1			T2	179		T7	50		T76	40
alert_integrity_fail	alert[0xd]	5033	1			T45	1		T46	23		T27	18
alert_integrity_fail	alert[0xe]	4914	1			T45	28		T24	21		T46	221
alert_integrity_fail	alert[0xf]	3543	1			T45	5		T68	5		T69	18
alert_integrity_fail	alert[0x10]	7934	1			T27	14		T76	74		T68	9
alert_integrity_fail	alert[0x11]	5065	1			T24	1		T68	1		T71	1679
alert_integrity_fail	alert[0x12]	3678	1			T7	56		T45	69		T21	294
alert_integrity_fail	alert[0x13]	6508	1			T7	175		T12	1		T76	20
alert_integrity_fail	alert[0x14]	2508	1			T45	7		T21	13		T69	15
alert_integrity_fail	alert[0x15]	4749	1			T7	69		T27	13		T76	108
alert_integrity_fail	alert[0x16]	6069	1			T12	1		T46	75		T76	29
alert_integrity_fail	alert[0x17]	5319	1			T7	32		T46	199		T27	227
alert_integrity_fail	alert[0x18]	5949	1			T12	5		T46	390		T21	365
alert_integrity_fail	alert[0x19]	6079	1			T2	9		T45	15		T27	3
alert_integrity_fail	alert[0x1a]	2995	1			T2	10		T7	13		T46	26
alert_integrity_fail	alert[0x1b]	7058	1			T7	2035		T45	27		T69	326
alert_integrity_fail	alert[0x1c]	4446	1			T2	203		T12	16		T21	12
alert_integrity_fail	alert[0x1d]	6457	1			T2	32		T7	196		T46	21
alert_integrity_fail	alert[0x1e]	3299	1			T2	121		T24	2		T76	91
alert_integrity_fail	alert[0x1f]	4114	1			T12	159		T68	783		T69	23
alert_integrity_fail	alert[0x20]	2919	1			T7	102		T45	2		T46	69
alert_integrity_fail	alert[0x21]	5591	1			T2	9		T46	24		T76	19
alert_integrity_fail	alert[0x22]	4232	1			T45	10		T46	12		T21	20
alert_integrity_fail	alert[0x23]	3867	1			T2	2		T68	132		T71	953
alert_integrity_fail	alert[0x24]	9465	1			T2	12		T7	204		T46	136
alert_integrity_fail	alert[0x25]	2960	1			T76	27		T68	4		T71	154
alert_integrity_fail	alert[0x26]	4428	1			T2	16		T45	55		T76	54
alert_integrity_fail	alert[0x27]	8263	1			T2	1		T7	21		T45	868
alert_integrity_fail	alert[0x28]	8298	1			T45	38		T46	158		T76	3403
alert_integrity_fail	alert[0x29]	4571	1			T2	5		T7	31		T46	11
alert_integrity_fail	alert[0x2a]	7146	1			T2	2		T7	19		T45	176
alert_integrity_fail	alert[0x2b]	8127	1			T7	21		T27	135		T71	350
alert_integrity_fail	alert[0x2c]	9419	1			T2	94		T7	114		T45	47
alert_integrity_fail	alert[0x2d]	4631	1			T12	4		T76	44		T69	134
alert_integrity_fail	alert[0x2e]	3590	1			T46	442		T68	1		T48	29
alert_integrity_fail	alert[0x2f]	5471	1			T2	1		T27	1		T76	13
alert_integrity_fail	alert[0x30]	3460	1			T12	4		T45	6		T46	137
alert_integrity_fail	alert[0x31]	8262	1			T225	122		T86	1028		T113	760
alert_integrity_fail	alert[0x32]	4921	1			T2	3		T7	1692		T45	7
alert_integrity_fail	alert[0x33]	6506	1			T2	11		T12	1		T45	4
alert_integrity_fail	alert[0x34]	4888	1			T2	17		T7	115		T45	212
alert_integrity_fail	alert[0x35]	3192	1			T45	9		T46	319		T76	90
alert_integrity_fail	alert[0x36]	5616	1			T27	141		T69	2		T71	473
alert_integrity_fail	alert[0x37]	5710	1			T2	13		T7	96		T46	9
alert_integrity_fail	alert[0x38]	12903	1			T7	25		T76	1096		T69	508
alert_integrity_fail	alert[0x39]	3353	1			T2	46		T7	38		T39	13
alert_integrity_fail	alert[0x3a]	8915	1			T2	36		T7	2		T45	3
alert_integrity_fail	alert[0x3b]	8614	1			T24	1		T46	1680		T76	574
alert_integrity_fail	alert[0x3c]	5420	1			T27	2		T76	266		T68	35
alert_integrity_fail	alert[0x3d]	3864	1			T46	22		T76	68		T68	32
alert_integrity_fail	alert[0x3e]	3601	1			T7	24		T45	53		T46	16
alert_integrity_fail	alert[0x3f]	8424	1			T45	251		T24	3		T76	68
alert_integrity_fail	alert[0x40]	6287	1			T24	2		T27	1		T76	13
alert_ping_fail	alert[0x0]	13	1			T4	1		T182	1		T213	1
alert_ping_fail	alert[0x1]	13	1			T182	1		T283	1		T223	1
alert_ping_fail	alert[0x2]	16	1			T3	1		T8	1		T182	1
alert_ping_fail	alert[0x3]	7	1			T4	1		T284	1		T285	1
alert_ping_fail	alert[0x4]	5	1			T286	1		T287	1		T284	1
alert_ping_fail	alert[0x5]	9	1			T8	1		T288	1		T213	1
alert_ping_fail	alert[0x6]	15	1			T4	1		T37	1		T223	1
alert_ping_fail	alert[0x7]	10	1			T3	1		T220	1		T289	1
alert_ping_fail	alert[0x8]	21	1			T79	1		T290	1		T291	1
alert_ping_fail	alert[0x9]	8	1			T182	1		T292	1		T293	2
alert_ping_fail	alert[0xa]	12	1			T79	1		T223	1		T294	1
alert_ping_fail	alert[0xb]	9	1			T182	1		T283	1		T288	1
alert_ping_fail	alert[0xc]	7	1			T79	1		T295	1		T296	1
alert_ping_fail	alert[0xd]	4	1			T8	1		T182	2		T297	1
alert_ping_fail	alert[0xe]	6	1			T182	1		T37	1		T298	1
alert_ping_fail	alert[0xf]	6	1			T3	1		T4	1		T79	1
alert_ping_fail	alert[0x10]	6	1			T3	1		T8	1		T79	1
alert_ping_fail	alert[0x11]	10	1			T299	1		T300	1		T284	1
alert_ping_fail	alert[0x12]	7	1			T3	1		T301	2		T302	1
alert_ping_fail	alert[0x13]	19	1			T4	1		T8	1		T79	1
alert_ping_fail	alert[0x14]	19	1			T3	1		T8	2		T79	1
alert_ping_fail	alert[0x15]	14	1			T3	1		T8	1		T280	2
alert_ping_fail	alert[0x16]	15	1			T4	1		T37	1		T223	3
alert_ping_fail	alert[0x17]	12	1			T299	1		T303	1		T304	1
alert_ping_fail	alert[0x18]	13	1			T3	1		T283	1		T294	1
alert_ping_fail	alert[0x19]	5	1			T182	1		T305	1		T287	1
alert_ping_fail	alert[0x1a]	10	1			T8	1		T182	2		T306	1
alert_ping_fail	alert[0x1b]	13	1			T182	1		T275	2		T299	1
alert_ping_fail	alert[0x1c]	17	1			T3	1		T37	1		T223	1
alert_ping_fail	alert[0x1d]	10	1			T3	1		T4	1		T37	1
alert_ping_fail	alert[0x1e]	7	1			T3	1		T8	3		T37	1
alert_ping_fail	alert[0x1f]	9	1			T280	1		T223	1		T28	1
alert_ping_fail	alert[0x20]	12	1			T79	1		T307	1		T213	1
alert_ping_fail	alert[0x21]	11	1			T37	1		T280	1		T308	1
alert_ping_fail	alert[0x22]	11	1			T182	2		T283	1		T213	1
alert_ping_fail	alert[0x23]	13	1			T283	1		T294	2		T213	1
alert_ping_fail	alert[0x24]	16	1			T3	1		T8	1		T79	1
alert_ping_fail	alert[0x25]	13	1			T8	1		T182	1		T37	1
alert_ping_fail	alert[0x26]	8	1			T283	2		T301	1		T303	1
alert_ping_fail	alert[0x27]	11	1			T3	1		T4	1		T283	1
alert_ping_fail	alert[0x28]	14	1			T283	1		T223	1		T216	1
alert_ping_fail	alert[0x29]	9	1			T4	1		T283	2		T223	1
alert_ping_fail	alert[0x2a]	14	1			T79	1		T309	1		T295	1
alert_ping_fail	alert[0x2b]	12	1			T79	1		T223	1		T294	1
alert_ping_fail	alert[0x2c]	7	1			T79	1		T305	1		T287	1
alert_ping_fail	alert[0x2d]	23	1			T79	1		T182	2		T301	1
alert_ping_fail	alert[0x2e]	9	1			T3	1		T283	1		T213	1
alert_ping_fail	alert[0x2f]	9	1			T301	1		T302	1		T292	2
alert_ping_fail	alert[0x30]	10	1			T3	1		T8	1		T280	1
alert_ping_fail	alert[0x31]	8	1			T37	1		T286	1		T292	1
alert_ping_fail	alert[0x32]	10	1			T37	1		T223	1		T286	1
alert_ping_fail	alert[0x33]	11	1			T37	1		T308	2		T213	1
alert_ping_fail	alert[0x34]	14	1			T79	1		T182	1		T288	1
alert_ping_fail	alert[0x35]	5	1			T8	1		T305	1		T310	1
alert_ping_fail	alert[0x36]	5	1			T3	1		T288	2		T301	1
alert_ping_fail	alert[0x37]	11	1			T79	1		T182	1		T301	1
alert_ping_fail	alert[0x38]	8	1			T37	2		T305	1		T311	2
alert_ping_fail	alert[0x39]	12	1			T288	1		T213	1		T302	1
alert_ping_fail	alert[0x3a]	12	1			T4	1		T79	1		T283	1
alert_ping_fail	alert[0x3b]	11	1			T37	1		T283	1		T213	1
alert_ping_fail	alert[0x3c]	14	1			T79	1		T182	1		T294	1
alert_ping_fail	alert[0x3d]	13	1			T3	1		T288	1		T213	1
alert_ping_fail	alert[0x3e]	10	1			T182	1		T294	1		T301	1
alert_ping_fail	alert[0x3f]	8	1			T286	1		T299	2		T284	1
alert_ping_fail	alert[0x40]	11	1			T4	1		T79	2		T223	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	172320	1			T2	710		T7	13077		T12	26
alert_integrity_fail	class_i[0x1]	77989	1			T2	77		T12	65		T13	1
alert_integrity_fail	class_i[0x2]	27373	1			T2	28		T12	45		T45	14
alert_integrity_fail	class_i[0x3]	86449	1			T2	31		T7	69		T12	55
alert_ping_fail	class_i[0x0]	202	1			T4	2		T79	2		T182	22
alert_ping_fail	class_i[0x1]	215	1			T3	1		T4	6		T79	15
alert_ping_fail	class_i[0x2]	118	1			T4	3		T8	14		T79	1
alert_ping_fail	class_i[0x3]	177	1			T3	16		T8	2		T79	1