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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.77 100.00 100.00 100.00 99.38 99.48


Total test records in report: 833
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T770 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1308216420 Jun 04 12:49:04 PM PDT 24 Jun 04 12:49:06 PM PDT 24 18896979 ps
T771 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1217548099 Jun 04 12:48:51 PM PDT 24 Jun 04 12:49:16 PM PDT 24 481295209 ps
T772 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2886297702 Jun 04 12:49:03 PM PDT 24 Jun 04 12:49:05 PM PDT 24 7496094 ps
T169 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3214497752 Jun 04 12:49:03 PM PDT 24 Jun 04 12:50:13 PM PDT 24 3724169467 ps
T138 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1173811958 Jun 04 12:48:22 PM PDT 24 Jun 04 01:05:48 PM PDT 24 152039893012 ps
T145 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2451968881 Jun 04 12:48:50 PM PDT 24 Jun 04 12:53:50 PM PDT 24 21694747810 ps
T773 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2741791601 Jun 04 12:48:41 PM PDT 24 Jun 04 12:52:58 PM PDT 24 13172816694 ps
T774 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1143416356 Jun 04 12:48:51 PM PDT 24 Jun 04 12:48:57 PM PDT 24 266889006 ps
T151 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4254188170 Jun 04 12:48:53 PM PDT 24 Jun 04 12:54:34 PM PDT 24 5010584903 ps
T149 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.885580673 Jun 04 12:48:32 PM PDT 24 Jun 04 12:52:25 PM PDT 24 7044330462 ps
T775 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.103568589 Jun 04 12:48:34 PM PDT 24 Jun 04 12:55:02 PM PDT 24 11931281729 ps
T776 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2129879409 Jun 04 12:49:00 PM PDT 24 Jun 04 12:49:24 PM PDT 24 1380310158 ps
T777 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4240353876 Jun 04 12:48:44 PM PDT 24 Jun 04 12:48:49 PM PDT 24 34282751 ps
T778 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2382428554 Jun 04 12:48:26 PM PDT 24 Jun 04 12:48:40 PM PDT 24 127840939 ps
T779 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1802519453 Jun 04 12:49:12 PM PDT 24 Jun 04 12:49:14 PM PDT 24 10567096 ps
T168 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2535248488 Jun 04 12:48:42 PM PDT 24 Jun 04 12:49:25 PM PDT 24 1060622849 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1782597458 Jun 04 12:48:36 PM PDT 24 Jun 04 12:48:47 PM PDT 24 897274305 ps
T781 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3851161325 Jun 04 12:48:50 PM PDT 24 Jun 04 12:48:58 PM PDT 24 575584270 ps
T782 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4101655730 Jun 04 12:49:00 PM PDT 24 Jun 04 12:49:23 PM PDT 24 302126285 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1913798966 Jun 04 12:48:53 PM PDT 24 Jun 04 12:49:13 PM PDT 24 256724553 ps
T784 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.19907029 Jun 04 12:49:10 PM PDT 24 Jun 04 12:49:11 PM PDT 24 11268614 ps
T152 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.141486770 Jun 04 12:48:46 PM PDT 24 Jun 04 12:51:21 PM PDT 24 32485068648 ps
T785 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3989237794 Jun 04 12:49:02 PM PDT 24 Jun 04 12:49:04 PM PDT 24 14027374 ps
T148 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1382101635 Jun 04 12:49:00 PM PDT 24 Jun 04 12:53:06 PM PDT 24 3342156933 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1462321988 Jun 04 12:48:52 PM PDT 24 Jun 04 12:49:33 PM PDT 24 516992754 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3618785900 Jun 04 12:48:22 PM PDT 24 Jun 04 12:48:34 PM PDT 24 128236750 ps
T153 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4149739516 Jun 04 12:49:03 PM PDT 24 Jun 04 12:51:52 PM PDT 24 5583332499 ps
T788 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1297031738 Jun 04 12:48:37 PM PDT 24 Jun 04 12:49:16 PM PDT 24 604306823 ps
T789 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3931590431 Jun 04 12:48:55 PM PDT 24 Jun 04 12:58:25 PM PDT 24 35348566264 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1661790993 Jun 04 12:48:25 PM PDT 24 Jun 04 12:48:39 PM PDT 24 178466007 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2371697280 Jun 04 12:48:42 PM PDT 24 Jun 04 12:52:51 PM PDT 24 4281095143 ps
T792 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1990209585 Jun 04 12:48:52 PM PDT 24 Jun 04 12:48:57 PM PDT 24 182868510 ps
T172 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1978562291 Jun 04 12:49:04 PM PDT 24 Jun 04 12:49:47 PM PDT 24 347223654 ps
T793 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.931713539 Jun 04 12:49:01 PM PDT 24 Jun 04 12:49:04 PM PDT 24 11562360 ps
T794 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3053466648 Jun 04 12:49:09 PM PDT 24 Jun 04 12:49:11 PM PDT 24 8123821 ps
T181 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3321941522 Jun 04 12:48:53 PM PDT 24 Jun 04 12:48:57 PM PDT 24 124759413 ps
T795 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1466901826 Jun 04 12:48:56 PM PDT 24 Jun 04 12:48:58 PM PDT 24 15894184 ps
T796 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.412638318 Jun 04 12:48:54 PM PDT 24 Jun 04 12:49:00 PM PDT 24 62300613 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3267480514 Jun 04 12:48:40 PM PDT 24 Jun 04 12:48:42 PM PDT 24 10977262 ps
T798 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.199071213 Jun 04 12:49:05 PM PDT 24 Jun 04 12:49:07 PM PDT 24 10709961 ps
T158 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1216577794 Jun 04 12:48:35 PM PDT 24 Jun 04 12:52:48 PM PDT 24 3721821393 ps
T799 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.726982445 Jun 04 12:49:01 PM PDT 24 Jun 04 12:49:07 PM PDT 24 219761549 ps
T800 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2413160167 Jun 04 12:48:52 PM PDT 24 Jun 04 12:48:59 PM PDT 24 118764720 ps
T801 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3325211889 Jun 04 12:48:41 PM PDT 24 Jun 04 12:48:51 PM PDT 24 473945676 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1567178353 Jun 04 12:49:04 PM PDT 24 Jun 04 12:49:28 PM PDT 24 723170867 ps
T803 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3022862251 Jun 04 12:48:56 PM PDT 24 Jun 04 12:49:09 PM PDT 24 88018373 ps
T157 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.569933111 Jun 04 12:48:59 PM PDT 24 Jun 04 01:07:31 PM PDT 24 22427142293 ps
T804 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2652813417 Jun 04 12:48:39 PM PDT 24 Jun 04 12:48:54 PM PDT 24 870950099 ps
T155 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3682851465 Jun 04 12:48:51 PM PDT 24 Jun 04 12:54:43 PM PDT 24 5341173176 ps
T805 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.325729726 Jun 04 12:48:59 PM PDT 24 Jun 04 12:49:05 PM PDT 24 32567061 ps
T806 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.599969702 Jun 04 12:48:59 PM PDT 24 Jun 04 12:49:01 PM PDT 24 10890067 ps
T807 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1175391735 Jun 04 12:48:55 PM PDT 24 Jun 04 12:49:05 PM PDT 24 82156355 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1028011436 Jun 04 12:48:35 PM PDT 24 Jun 04 12:48:48 PM PDT 24 340927436 ps
T809 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2044201682 Jun 04 12:49:07 PM PDT 24 Jun 04 12:49:09 PM PDT 24 22897147 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3389991653 Jun 04 12:48:36 PM PDT 24 Jun 04 12:48:39 PM PDT 24 6247222 ps
T811 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2835484077 Jun 04 12:48:51 PM PDT 24 Jun 04 12:48:56 PM PDT 24 236230308 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3005280010 Jun 04 12:48:26 PM PDT 24 Jun 04 12:48:34 PM PDT 24 232887780 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2005693043 Jun 04 12:49:02 PM PDT 24 Jun 04 12:49:25 PM PDT 24 297919463 ps
T813 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1516027551 Jun 04 12:48:51 PM PDT 24 Jun 04 12:49:05 PM PDT 24 320105492 ps
T814 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1166052261 Jun 04 12:49:04 PM PDT 24 Jun 04 12:49:06 PM PDT 24 7651743 ps
T815 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3735859051 Jun 04 12:48:55 PM PDT 24 Jun 04 12:49:01 PM PDT 24 136363809 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1215475395 Jun 04 12:48:35 PM PDT 24 Jun 04 12:48:57 PM PDT 24 1127300189 ps
T817 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3261495289 Jun 04 12:49:00 PM PDT 24 Jun 04 12:49:03 PM PDT 24 9577914 ps
T818 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3071308447 Jun 04 12:48:35 PM PDT 24 Jun 04 12:51:48 PM PDT 24 6531612485 ps
T819 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2874436572 Jun 04 12:48:37 PM PDT 24 Jun 04 12:48:49 PM PDT 24 721850577 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2569318898 Jun 04 12:49:00 PM PDT 24 Jun 04 12:49:18 PM PDT 24 252790122 ps
T821 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3903974580 Jun 04 12:49:02 PM PDT 24 Jun 04 12:49:11 PM PDT 24 211427790 ps
T822 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.188594536 Jun 04 12:49:02 PM PDT 24 Jun 04 12:49:10 PM PDT 24 212006067 ps
T167 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1170427252 Jun 04 12:48:43 PM PDT 24 Jun 04 12:49:45 PM PDT 24 1738045774 ps
T180 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.476872250 Jun 04 12:48:20 PM PDT 24 Jun 04 12:48:24 PM PDT 24 24530186 ps
T823 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1000439722 Jun 04 12:48:51 PM PDT 24 Jun 04 12:48:57 PM PDT 24 86117510 ps
T176 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.471176620 Jun 04 12:49:01 PM PDT 24 Jun 04 12:49:35 PM PDT 24 440283548 ps
T824 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1975442768 Jun 04 12:48:29 PM PDT 24 Jun 04 12:48:51 PM PDT 24 644343533 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2494765377 Jun 04 12:48:35 PM PDT 24 Jun 04 12:51:29 PM PDT 24 1514713195 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4088050006 Jun 04 12:48:26 PM PDT 24 Jun 04 12:48:28 PM PDT 24 16695927 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1401109248 Jun 04 12:48:31 PM PDT 24 Jun 04 12:55:47 PM PDT 24 16098354744 ps
T828 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2814411313 Jun 04 12:48:52 PM PDT 24 Jun 04 12:49:01 PM PDT 24 373214191 ps
T829 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3192455639 Jun 04 12:48:51 PM PDT 24 Jun 04 12:49:05 PM PDT 24 372364150 ps
T830 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.14946172 Jun 04 12:49:05 PM PDT 24 Jun 04 12:49:08 PM PDT 24 7473193 ps
T831 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2730453968 Jun 04 12:48:59 PM PDT 24 Jun 04 12:49:17 PM PDT 24 229235189 ps
T832 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1817815316 Jun 04 12:48:35 PM PDT 24 Jun 04 12:51:03 PM PDT 24 21060885073 ps
T833 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4058629808 Jun 04 12:48:33 PM PDT 24 Jun 04 12:48:40 PM PDT 24 40055559 ps
T156 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1491368034 Jun 04 12:49:01 PM PDT 24 Jun 04 12:53:49 PM PDT 24 4009201886 ps

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2250139567
Short name T2
Test name
Test status
Simulation time 35203632387 ps
CPU time 3088.02 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:51:54 PM PDT 24
Peak memory 321276 kb
Host smart-55e15d76-cd91-473c-8982-2657ea132339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250139567 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2250139567
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2052393740
Short name T10
Test name
Test status
Simulation time 341248177 ps
CPU time 21.53 seconds
Started Jun 04 12:59:42 PM PDT 24
Finished Jun 04 01:00:05 PM PDT 24
Peak memory 273404 kb
Host smart-ab9c5d46-b3ce-4a16-a87d-5fe32ce546a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2052393740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2052393740
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1210114365
Short name T160
Test name
Test status
Simulation time 4633581381 ps
CPU time 84.61 seconds
Started Jun 04 12:48:53 PM PDT 24
Finished Jun 04 12:50:18 PM PDT 24
Peak memory 240516 kb
Host smart-3fc5c34e-c368-4df9-a0da-f4f3ea0d2262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1210114365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1210114365
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.397932459
Short name T76
Test name
Test status
Simulation time 57387378055 ps
CPU time 3165.98 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:52:53 PM PDT 24
Peak memory 289416 kb
Host smart-f48339f0-2825-4b09-8838-ab63a6f0b6a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397932459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.397932459
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4161579049
Short name T19
Test name
Test status
Simulation time 22165230487 ps
CPU time 2040.59 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:34:31 PM PDT 24
Peak memory 297888 kb
Host smart-5dacfbca-9e78-4392-8f4a-92c31d4711df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161579049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4161579049
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2570374231
Short name T28
Test name
Test status
Simulation time 18605346949 ps
CPU time 1561.52 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:26:09 PM PDT 24
Peak memory 289116 kb
Host smart-57a6b461-f885-4323-a660-f7b253def6bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570374231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2570374231
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2033241644
Short name T68
Test name
Test status
Simulation time 74964252123 ps
CPU time 2477.19 seconds
Started Jun 04 01:01:05 PM PDT 24
Finished Jun 04 01:42:23 PM PDT 24
Peak memory 289268 kb
Host smart-c101797f-38b7-4e85-ae2f-b9a6231fbe4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033241644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2033241644
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1866670529
Short name T141
Test name
Test status
Simulation time 22627371145 ps
CPU time 663.22 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:59:59 PM PDT 24
Peak memory 265344 kb
Host smart-b66ef717-13e8-44e5-8365-4888e4aabead
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866670529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1866670529
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.788753065
Short name T244
Test name
Test status
Simulation time 10765082889 ps
CPU time 1003.64 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:16:50 PM PDT 24
Peak memory 289936 kb
Host smart-5e4dfd7f-5583-46d2-82c1-dfbe0d1d5546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788753065 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.788753065
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.205567575
Short name T136
Test name
Test status
Simulation time 3089110904 ps
CPU time 199.22 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:52:22 PM PDT 24
Peak memory 265420 kb
Host smart-86dfa005-181b-4175-8661-41778dd43043
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=205567575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.205567575
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3862798437
Short name T102
Test name
Test status
Simulation time 18695751918 ps
CPU time 1254.08 seconds
Started Jun 04 12:59:45 PM PDT 24
Finished Jun 04 01:20:40 PM PDT 24
Peak memory 270228 kb
Host smart-c663bc24-4f0a-48c5-a647-3c6f34994ec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862798437 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3862798437
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1173811958
Short name T138
Test name
Test status
Simulation time 152039893012 ps
CPU time 1045.02 seconds
Started Jun 04 12:48:22 PM PDT 24
Finished Jun 04 01:05:48 PM PDT 24
Peak memory 265400 kb
Host smart-f713f6b7-e018-4c19-9608-eae6becb8296
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173811958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1173811958
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4142273564
Short name T23
Test name
Test status
Simulation time 40462099967 ps
CPU time 2314.15 seconds
Started Jun 04 01:01:29 PM PDT 24
Finished Jun 04 01:40:05 PM PDT 24
Peak memory 289168 kb
Host smart-4e38bde3-866a-4b15-b186-b79e2809f184
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142273564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4142273564
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2820701820
Short name T12
Test name
Test status
Simulation time 174433822880 ps
CPU time 2468.41 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:41:16 PM PDT 24
Peak memory 289224 kb
Host smart-93ad3498-9650-490a-b61b-92f9a9a913e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820701820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2820701820
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.393822626
Short name T3
Test name
Test status
Simulation time 39232304829 ps
CPU time 399.08 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:06:32 PM PDT 24
Peak memory 248004 kb
Host smart-6ce08076-f066-4fa6-9a63-3846ae2166d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393822626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.393822626
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.385669114
Short name T128
Test name
Test status
Simulation time 43688918153 ps
CPU time 308.07 seconds
Started Jun 04 12:48:15 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 265356 kb
Host smart-8638280a-dd1a-4f43-9b8a-fc4e46379feb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=385669114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.385669114
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.919167906
Short name T290
Test name
Test status
Simulation time 119630480053 ps
CPU time 1972.84 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:33:12 PM PDT 24
Peak memory 271740 kb
Host smart-507bc450-0a73-42e1-b063-67a4f5b85def
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919167906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.919167906
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3698699519
Short name T163
Test name
Test status
Simulation time 11187418 ps
CPU time 1.56 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:07 PM PDT 24
Peak memory 235904 kb
Host smart-edb088e0-aaca-41e3-b2b6-77717edd7b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3698699519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3698699519
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2642729615
Short name T25
Test name
Test status
Simulation time 179853729452 ps
CPU time 3213.39 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:53:53 PM PDT 24
Peak memory 305084 kb
Host smart-9befb676-652c-4af3-ab19-95487e09cda3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642729615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2642729615
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3846982176
Short name T226
Test name
Test status
Simulation time 54416928528 ps
CPU time 1835.96 seconds
Started Jun 04 01:01:10 PM PDT 24
Finished Jun 04 01:31:47 PM PDT 24
Peak memory 273296 kb
Host smart-dd88d489-8f78-4dc2-9755-cfbaa2cf3009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846982176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3846982176
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1268507091
Short name T7
Test name
Test status
Simulation time 14021418760 ps
CPU time 1051.13 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:18:05 PM PDT 24
Peak memory 287304 kb
Host smart-f51a1842-e941-4e28-af51-07a2c0fd9d5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268507091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1268507091
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.127086178
Short name T127
Test name
Test status
Simulation time 4979880206 ps
CPU time 622.52 seconds
Started Jun 04 12:48:45 PM PDT 24
Finished Jun 04 12:59:08 PM PDT 24
Peak memory 265392 kb
Host smart-d2292b37-9626-4047-9ac3-0cef21654745
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127086178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.127086178
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2534675189
Short name T182
Test name
Test status
Simulation time 14491822220 ps
CPU time 601.99 seconds
Started Jun 04 01:01:15 PM PDT 24
Finished Jun 04 01:11:18 PM PDT 24
Peak memory 255596 kb
Host smart-1c5e77fd-0524-4642-a1d3-e889f775184f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534675189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2534675189
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.807611664
Short name T133
Test name
Test status
Simulation time 17214895989 ps
CPU time 630.43 seconds
Started Jun 04 12:48:39 PM PDT 24
Finished Jun 04 12:59:10 PM PDT 24
Peak memory 265348 kb
Host smart-053d45c1-9fc2-4c31-86c8-e5a4a313d764
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807611664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.807611664
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.74758599
Short name T316
Test name
Test status
Simulation time 110713772376 ps
CPU time 3049.97 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:51:14 PM PDT 24
Peak memory 289756 kb
Host smart-ace16265-fe2d-4667-b4da-2ebfc8b9df69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74758599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.74758599
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2883918198
Short name T123
Test name
Test status
Simulation time 35177049965 ps
CPU time 584.49 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:58:47 PM PDT 24
Peak memory 268204 kb
Host smart-35aaf44d-1bd2-41c2-9e36-b8fa2e755a65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883918198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2883918198
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.565951862
Short name T328
Test name
Test status
Simulation time 57253268368 ps
CPU time 3349.5 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:55:59 PM PDT 24
Peak memory 289216 kb
Host smart-200b1078-429c-41a1-8159-c87a5e620518
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565951862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.565951862
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1089194346
Short name T519
Test name
Test status
Simulation time 23991918653 ps
CPU time 494.21 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:08:39 PM PDT 24
Peak memory 248040 kb
Host smart-11ae9335-d17c-408c-aff5-1ec3bb231235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089194346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1089194346
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1382101635
Short name T148
Test name
Test status
Simulation time 3342156933 ps
CPU time 245.16 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:53:06 PM PDT 24
Peak memory 265332 kb
Host smart-60bc8b84-655d-46f8-80a9-f08f4c4b84b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1382101635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1382101635
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2275903256
Short name T79
Test name
Test status
Simulation time 11132578248 ps
CPU time 434.04 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:07:38 PM PDT 24
Peak memory 248220 kb
Host smart-2ab082ee-f7ad-439c-970d-a1b176c89118
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275903256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2275903256
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.573492707
Short name T131
Test name
Test status
Simulation time 3390547864 ps
CPU time 96.89 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:50:42 PM PDT 24
Peak memory 265288 kb
Host smart-d88d41ec-898a-48c3-bc41-c837966810a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=573492707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.573492707
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2142773238
Short name T241
Test name
Test status
Simulation time 280833260711 ps
CPU time 6921.97 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 02:55:09 PM PDT 24
Peak memory 354984 kb
Host smart-292b6e6f-4cea-4217-ae9d-d07d984da7b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142773238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2142773238
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3989771243
Short name T285
Test name
Test status
Simulation time 21812488961 ps
CPU time 423.75 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:06:47 PM PDT 24
Peak memory 247096 kb
Host smart-54b041d2-a39d-416d-96d7-6cb794fb6938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989771243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3989771243
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2801631278
Short name T239
Test name
Test status
Simulation time 140418050494 ps
CPU time 4362.24 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 02:13:16 PM PDT 24
Peak memory 339004 kb
Host smart-99a1e494-2ca5-4930-a0fd-43f78516ca5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801631278 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2801631278
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3941164423
Short name T21
Test name
Test status
Simulation time 132471899511 ps
CPU time 3681.83 seconds
Started Jun 04 01:01:01 PM PDT 24
Finished Jun 04 02:02:24 PM PDT 24
Peak memory 321916 kb
Host smart-7d18bad2-4624-4dde-ad99-a4582a61ce26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941164423 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3941164423
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2430772387
Short name T331
Test name
Test status
Simulation time 19062576 ps
CPU time 1.41 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 236716 kb
Host smart-dcbf7bcd-e9af-489e-ae43-f91e05f70236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430772387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2430772387
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1049303093
Short name T319
Test name
Test status
Simulation time 17746469403 ps
CPU time 1154.07 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:19:07 PM PDT 24
Peak memory 272136 kb
Host smart-18671bf4-de0e-41f3-b101-e1a05c067673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049303093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1049303093
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1136578028
Short name T314
Test name
Test status
Simulation time 51311518041 ps
CPU time 2467.24 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:41:36 PM PDT 24
Peak memory 289180 kb
Host smart-462172e7-a431-4635-8beb-3bda6998e171
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136578028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1136578028
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3528168225
Short name T132
Test name
Test status
Simulation time 24566302875 ps
CPU time 467.95 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:56:41 PM PDT 24
Peak memory 265496 kb
Host smart-ba36853a-e688-48ee-8a99-aa1829270ebc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528168225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3528168225
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1978562291
Short name T172
Test name
Test status
Simulation time 347223654 ps
CPU time 42.29 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:47 PM PDT 24
Peak memory 245092 kb
Host smart-76224274-8363-4f7b-9012-b4c4100bc6f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1978562291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1978562291
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.538629351
Short name T129
Test name
Test status
Simulation time 17284202363 ps
CPU time 1089.88 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 01:06:44 PM PDT 24
Peak memory 273548 kb
Host smart-eeaa5669-f5fc-4067-88d7-87e2c61c1720
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538629351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.538629351
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2005169232
Short name T302
Test name
Test status
Simulation time 252685941431 ps
CPU time 593.64 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:09:35 PM PDT 24
Peak memory 248212 kb
Host smart-02ae536a-7c2c-4554-a6a1-210f7cd22446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005169232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2005169232
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.465624299
Short name T305
Test name
Test status
Simulation time 6008221260 ps
CPU time 218.05 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:03:58 PM PDT 24
Peak memory 248172 kb
Host smart-3a0487cc-1098-4847-868b-f88ad6e74d06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465624299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.465624299
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2736829153
Short name T266
Test name
Test status
Simulation time 187049903164 ps
CPU time 2280.51 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:38:22 PM PDT 24
Peak memory 287360 kb
Host smart-0bc05258-6f31-4f26-bba2-3d4566816f30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736829153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2736829153
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.895672795
Short name T47
Test name
Test status
Simulation time 21050501609 ps
CPU time 2273 seconds
Started Jun 04 01:00:40 PM PDT 24
Finished Jun 04 01:38:34 PM PDT 24
Peak memory 298088 kb
Host smart-c9e9fa6a-4859-4067-8cbd-d575b6625d77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895672795 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.895672795
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1146841933
Short name T15
Test name
Test status
Simulation time 299947775 ps
CPU time 3.73 seconds
Started Jun 04 12:59:45 PM PDT 24
Finished Jun 04 12:59:50 PM PDT 24
Peak memory 248904 kb
Host smart-3d1dae46-245f-45de-86c3-080d87126ab6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1146841933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1146841933
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.273338161
Short name T41
Test name
Test status
Simulation time 29395894 ps
CPU time 3.35 seconds
Started Jun 04 12:59:58 PM PDT 24
Finished Jun 04 01:00:02 PM PDT 24
Peak memory 248972 kb
Host smart-2838aa90-4451-41f1-97fd-a4dce025096c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=273338161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.273338161
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3089529843
Short name T201
Test name
Test status
Simulation time 42895792 ps
CPU time 3.68 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:12 PM PDT 24
Peak memory 248908 kb
Host smart-692fef77-2ffd-4d75-803d-0c3b68cdf401
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3089529843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3089529843
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3826745920
Short name T67
Test name
Test status
Simulation time 45965110 ps
CPU time 2.45 seconds
Started Jun 04 12:59:48 PM PDT 24
Finished Jun 04 12:59:51 PM PDT 24
Peak memory 248896 kb
Host smart-652a25ac-01d8-4854-89bb-956f261903ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3826745920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3826745920
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4226260018
Short name T24
Test name
Test status
Simulation time 2018403616 ps
CPU time 125.62 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:01:46 PM PDT 24
Peak memory 256880 kb
Host smart-df65998d-1568-43ad-822e-543c1a2dfd87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226260018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4226260018
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1572913541
Short name T281
Test name
Test status
Simulation time 49121925868 ps
CPU time 2665.85 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:44:50 PM PDT 24
Peak memory 289080 kb
Host smart-1e8865ca-5b00-4337-8553-e2b2d0ead91b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572913541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1572913541
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.105691827
Short name T213
Test name
Test status
Simulation time 7616652396 ps
CPU time 304.82 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:05:11 PM PDT 24
Peak memory 248144 kb
Host smart-42badfe9-2ea0-4d89-a693-17474a11dfe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105691827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.105691827
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2651339007
Short name T259
Test name
Test status
Simulation time 29950792654 ps
CPU time 1332.61 seconds
Started Jun 04 01:00:37 PM PDT 24
Finished Jun 04 01:22:50 PM PDT 24
Peak memory 284980 kb
Host smart-f884d930-cc15-4a55-82e8-922a33744f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651339007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2651339007
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2373685576
Short name T84
Test name
Test status
Simulation time 135582491274 ps
CPU time 4313.51 seconds
Started Jun 04 01:00:49 PM PDT 24
Finished Jun 04 02:12:44 PM PDT 24
Peak memory 305628 kb
Host smart-d651d39c-8663-4017-9463-cb8faf959b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373685576 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2373685576
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1919951466
Short name T227
Test name
Test status
Simulation time 64514904071 ps
CPU time 2042.27 seconds
Started Jun 04 01:00:55 PM PDT 24
Finished Jun 04 01:34:58 PM PDT 24
Peak memory 289752 kb
Host smart-f8c616a3-c966-49c3-86d3-2b91e4ae332d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919951466 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1919951466
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3467292323
Short name T274
Test name
Test status
Simulation time 307809136780 ps
CPU time 3340.9 seconds
Started Jun 04 01:01:04 PM PDT 24
Finished Jun 04 01:56:46 PM PDT 24
Peak memory 288980 kb
Host smart-29e72616-eb13-4cea-94d9-879024fc1ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467292323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3467292323
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2507936801
Short name T105
Test name
Test status
Simulation time 1054578619 ps
CPU time 31.39 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:00:37 PM PDT 24
Peak memory 255984 kb
Host smart-66afa660-3b6a-4382-9c48-3345ca8a800c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25079
36801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2507936801
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.95732724
Short name T173
Test name
Test status
Simulation time 194470305 ps
CPU time 4.13 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:48:59 PM PDT 24
Peak memory 237184 kb
Host smart-1c1c997d-d7f5-490b-b27c-c362cc5f971e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=95732724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.95732724
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4216625084
Short name T121
Test name
Test status
Simulation time 4336479419 ps
CPU time 95.12 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:50:29 PM PDT 24
Peak memory 257080 kb
Host smart-3ff611f4-a750-4d1c-a18a-bb7af314e9dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4216625084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4216625084
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1901665041
Short name T130
Test name
Test status
Simulation time 1680458361 ps
CPU time 101.46 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:50:37 PM PDT 24
Peak memory 257108 kb
Host smart-cfbf9302-21f1-45a9-9ca2-0c9eabc89863
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1901665041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1901665041
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4073720002
Short name T247
Test name
Test status
Simulation time 133227587 ps
CPU time 13.15 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:53 PM PDT 24
Peak memory 248744 kb
Host smart-705660b7-2765-48ca-a93f-c06abd54ac0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40737
20002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4073720002
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.665120278
Short name T251
Test name
Test status
Simulation time 37528762806 ps
CPU time 2457.17 seconds
Started Jun 04 12:59:54 PM PDT 24
Finished Jun 04 01:40:52 PM PDT 24
Peak memory 289880 kb
Host smart-e2c65ab2-0cf3-4ff9-9a03-9007039d4997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665120278 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.665120278
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3506311414
Short name T261
Test name
Test status
Simulation time 13559479669 ps
CPU time 1021.81 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:17:22 PM PDT 24
Peak memory 282704 kb
Host smart-0c5ffdd2-a93c-492b-9137-9606b60833f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506311414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3506311414
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2593744558
Short name T87
Test name
Test status
Simulation time 536177785 ps
CPU time 29.71 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:34 PM PDT 24
Peak memory 255180 kb
Host smart-a33e17db-3ebb-4ec8-8439-0a7a9bb744d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25937
44558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2593744558
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.388510335
Short name T313
Test name
Test status
Simulation time 195582621941 ps
CPU time 1917.4 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:32:21 PM PDT 24
Peak memory 289780 kb
Host smart-6eba6c13-c068-4486-bba4-a77950aedfe3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388510335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.388510335
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2341229589
Short name T107
Test name
Test status
Simulation time 1153238983232 ps
CPU time 6327.16 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 02:45:56 PM PDT 24
Peak memory 322360 kb
Host smart-6b89bbde-4880-423a-b5ab-c55fd68761f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341229589 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2341229589
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1755030956
Short name T85
Test name
Test status
Simulation time 976516180 ps
CPU time 60.72 seconds
Started Jun 04 12:59:50 PM PDT 24
Finished Jun 04 01:00:51 PM PDT 24
Peak memory 256768 kb
Host smart-e03055dc-b448-48b4-a959-eb73653e34b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550
30956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1755030956
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3454692756
Short name T184
Test name
Test status
Simulation time 18233818589 ps
CPU time 1758.2 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:29:51 PM PDT 24
Peak memory 305324 kb
Host smart-c8f5ec67-a1c4-4ec3-a3d3-62a49e819f34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454692756 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3454692756
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3860299964
Short name T258
Test name
Test status
Simulation time 13607103324 ps
CPU time 46.24 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:01:19 PM PDT 24
Peak memory 247504 kb
Host smart-4937bdf0-5afd-47a4-abd5-b3ee512bb3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
99964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3860299964
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2125921306
Short name T114
Test name
Test status
Simulation time 69126931981 ps
CPU time 1075.62 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 01:17:38 PM PDT 24
Peak memory 289588 kb
Host smart-bf51c3b4-74e1-419d-ba14-f515aa82cd6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125921306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2125921306
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1018834617
Short name T238
Test name
Test status
Simulation time 254704185 ps
CPU time 16.81 seconds
Started Jun 04 01:00:56 PM PDT 24
Finished Jun 04 01:01:13 PM PDT 24
Peak memory 247308 kb
Host smart-4e9a4035-b263-48eb-ad30-ac9598b5658f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10188
34617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1018834617
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1712650935
Short name T18
Test name
Test status
Simulation time 2935342345 ps
CPU time 49.06 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:00:57 PM PDT 24
Peak memory 248800 kb
Host smart-db7432a6-048f-4dbb-91c4-6bb2f045cb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17126
50935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1712650935
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.626770679
Short name T252
Test name
Test status
Simulation time 199169326933 ps
CPU time 3452.85 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:57:17 PM PDT 24
Peak memory 321984 kb
Host smart-6ff22bae-529d-4dd2-b745-084982b56619
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626770679 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.626770679
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2367214348
Short name T237
Test name
Test status
Simulation time 75190392204 ps
CPU time 7245.18 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 352612 kb
Host smart-c265b9d0-f005-4339-ac78-96aaf34f19a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367214348 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2367214348
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3950075062
Short name T9
Test name
Test status
Simulation time 243538513 ps
CPU time 13.28 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 12:59:56 PM PDT 24
Peak memory 273788 kb
Host smart-71440600-77b5-4349-b8d5-e6be020c7229
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3950075062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3950075062
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1919741900
Short name T5
Test name
Test status
Simulation time 177750478688 ps
CPU time 1543.25 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:25:24 PM PDT 24
Peak memory 287424 kb
Host smart-1240e669-8651-4eec-9521-a35221b542a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919741900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1919741900
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.142459795
Short name T170
Test name
Test status
Simulation time 897979194 ps
CPU time 61.13 seconds
Started Jun 04 12:48:38 PM PDT 24
Finished Jun 04 12:49:40 PM PDT 24
Peak memory 237032 kb
Host smart-7915a1f2-d612-4d7d-8b06-8cab77032ea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=142459795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.142459795
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2535248488
Short name T168
Test name
Test status
Simulation time 1060622849 ps
CPU time 41.95 seconds
Started Jun 04 12:48:42 PM PDT 24
Finished Jun 04 12:49:25 PM PDT 24
Peak memory 248624 kb
Host smart-5b75709e-c908-4d84-86bd-57d642e0bb7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2535248488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2535248488
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1170427252
Short name T167
Test name
Test status
Simulation time 1738045774 ps
CPU time 61.43 seconds
Started Jun 04 12:48:43 PM PDT 24
Finished Jun 04 12:49:45 PM PDT 24
Peak memory 237228 kb
Host smart-89a0a3d3-c7e0-4ce4-b862-bbb0a063e6f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1170427252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1170427252
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2497193162
Short name T174
Test name
Test status
Simulation time 1490712017 ps
CPU time 73.3 seconds
Started Jun 04 12:48:43 PM PDT 24
Finished Jun 04 12:49:57 PM PDT 24
Peak memory 236952 kb
Host smart-6b5b7cdc-5b70-438e-982d-729f962430e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2497193162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2497193162
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.885580673
Short name T149
Test name
Test status
Simulation time 7044330462 ps
CPU time 232.12 seconds
Started Jun 04 12:48:32 PM PDT 24
Finished Jun 04 12:52:25 PM PDT 24
Peak memory 273464 kb
Host smart-4bbf5d4b-8d90-4df2-8b8a-563f3d888e48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=885580673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.885580673
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3682851465
Short name T155
Test name
Test status
Simulation time 5341173176 ps
CPU time 350.52 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:54:43 PM PDT 24
Peak memory 265156 kb
Host smart-4186de58-a01c-4bd0-bb3a-68a3cac23f0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3682851465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3682851465
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4093718253
Short name T171
Test name
Test status
Simulation time 3703759446 ps
CPU time 72.29 seconds
Started Jun 04 12:48:58 PM PDT 24
Finished Jun 04 12:50:11 PM PDT 24
Peak memory 240420 kb
Host smart-f027985d-f991-46a8-868f-d5b382cc7af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4093718253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4093718253
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.471176620
Short name T176
Test name
Test status
Simulation time 440283548 ps
CPU time 33.59 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:49:35 PM PDT 24
Peak memory 236904 kb
Host smart-f7a07fbf-498e-49a4-a21d-244322a60bae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=471176620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.471176620
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2005693043
Short name T165
Test name
Test status
Simulation time 297919463 ps
CPU time 22.57 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:25 PM PDT 24
Peak memory 245444 kb
Host smart-d4fcf450-56b1-4e3a-9696-43e22e3ec656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2005693043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2005693043
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3214497752
Short name T169
Test name
Test status
Simulation time 3724169467 ps
CPU time 68.81 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:50:13 PM PDT 24
Peak memory 248736 kb
Host smart-c93e80bc-706b-463a-8282-1b58151c3960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3214497752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3214497752
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.351347515
Short name T166
Test name
Test status
Simulation time 4925321932 ps
CPU time 75.33 seconds
Started Jun 04 12:48:36 PM PDT 24
Finished Jun 04 12:49:53 PM PDT 24
Peak memory 238152 kb
Host smart-ac31d013-7d80-4622-9518-f128674c9a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=351347515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.351347515
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2033402969
Short name T159
Test name
Test status
Simulation time 133775910 ps
CPU time 6.97 seconds
Started Jun 04 12:48:45 PM PDT 24
Finished Jun 04 12:48:53 PM PDT 24
Peak memory 236928 kb
Host smart-5e5a4936-4fc3-44a0-80a1-be492f9fae23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2033402969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2033402969
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3327080255
Short name T161
Test name
Test status
Simulation time 86850721 ps
CPU time 5.29 seconds
Started Jun 04 12:48:44 PM PDT 24
Finished Jun 04 12:48:50 PM PDT 24
Peak memory 236792 kb
Host smart-9befdecd-f726-409e-b4e8-94db20432ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3327080255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3327080255
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3321941522
Short name T181
Test name
Test status
Simulation time 124759413 ps
CPU time 2.93 seconds
Started Jun 04 12:48:53 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 236904 kb
Host smart-55fad757-6f08-4729-958f-de812d0f4281
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3321941522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3321941522
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.858016253
Short name T178
Test name
Test status
Simulation time 404147056 ps
CPU time 2.24 seconds
Started Jun 04 12:48:36 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 236628 kb
Host smart-f5e3c559-c6aa-4da3-b0bc-0caecc9cd073
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=858016253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.858016253
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2498063807
Short name T175
Test name
Test status
Simulation time 1162912828 ps
CPU time 67.37 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:49:58 PM PDT 24
Peak memory 239668 kb
Host smart-26d96e7b-e271-46de-92cb-d8cdc5937c4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2498063807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2498063807
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2973723158
Short name T22
Test name
Test status
Simulation time 77161746453 ps
CPU time 5171.07 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 02:26:14 PM PDT 24
Peak memory 305484 kb
Host smart-29e79876-dac6-4251-a9de-a553a0379663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973723158 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2973723158
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1729399240
Short name T13
Test name
Test status
Simulation time 23714105698 ps
CPU time 1527.34 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:25:35 PM PDT 24
Peak memory 298060 kb
Host smart-d04fbb71-e608-4de6-976f-d31512e6fdd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729399240 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1729399240
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.4265927503
Short name T20
Test name
Test status
Simulation time 376136144241 ps
CPU time 3044.1 seconds
Started Jun 04 01:01:26 PM PDT 24
Finished Jun 04 01:52:11 PM PDT 24
Peak memory 289464 kb
Host smart-23da94cb-096e-44f7-ab3b-bb660489ea8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265927503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.4265927503
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.86584497
Short name T735
Test name
Test status
Simulation time 18682155297 ps
CPU time 157.99 seconds
Started Jun 04 12:48:15 PM PDT 24
Finished Jun 04 12:50:54 PM PDT 24
Peak memory 236840 kb
Host smart-4bcca351-4548-473a-875d-46690f032f00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=86584497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.86584497
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3651265610
Short name T727
Test name
Test status
Simulation time 3405748084 ps
CPU time 91.75 seconds
Started Jun 04 12:48:18 PM PDT 24
Finished Jun 04 12:49:51 PM PDT 24
Peak memory 240340 kb
Host smart-3a50ac33-58d9-4431-a5d7-33204164ff20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3651265610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3651265610
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3618785900
Short name T787
Test name
Test status
Simulation time 128236750 ps
CPU time 11.1 seconds
Started Jun 04 12:48:22 PM PDT 24
Finished Jun 04 12:48:34 PM PDT 24
Peak memory 240412 kb
Host smart-c4f0a5cf-2b2e-4ad2-b63c-97e1c10fbb15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3618785900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3618785900
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1019725871
Short name T767
Test name
Test status
Simulation time 458791530 ps
CPU time 8.69 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 240384 kb
Host smart-405e9ef0-baee-4861-a8db-c09cc2d411e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019725871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1019725871
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3805334932
Short name T719
Test name
Test status
Simulation time 359678857 ps
CPU time 8.07 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 12:48:42 PM PDT 24
Peak memory 240196 kb
Host smart-52165b5b-f19a-4ef0-afd5-45e1c3c30bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3805334932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3805334932
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.875499011
Short name T715
Test name
Test status
Simulation time 8252863 ps
CPU time 1.54 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:38 PM PDT 24
Peak memory 236924 kb
Host smart-245ed2f8-619d-4909-b9f1-875375ae38f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=875499011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.875499011
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1028011436
Short name T808
Test name
Test status
Simulation time 340927436 ps
CPU time 12.03 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:48 PM PDT 24
Peak memory 244932 kb
Host smart-5f5ea13f-6ad7-4324-99df-cfff10486535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1028011436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1028011436
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3411761051
Short name T710
Test name
Test status
Simulation time 188051402 ps
CPU time 13.05 seconds
Started Jun 04 12:48:23 PM PDT 24
Finished Jun 04 12:48:36 PM PDT 24
Peak memory 248824 kb
Host smart-c49ca47d-8101-4e98-8997-01105d20b85f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3411761051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3411761051
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.476872250
Short name T180
Test name
Test status
Simulation time 24530186 ps
CPU time 2.42 seconds
Started Jun 04 12:48:20 PM PDT 24
Finished Jun 04 12:48:24 PM PDT 24
Peak memory 236768 kb
Host smart-7d230c50-da24-4fa8-aae0-920494aa4d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=476872250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.476872250
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1817815316
Short name T832
Test name
Test status
Simulation time 21060885073 ps
CPU time 147.5 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:51:03 PM PDT 24
Peak memory 240476 kb
Host smart-36065e31-3b3f-480e-ab6e-1c38c5288c50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1817815316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1817815316
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3071308447
Short name T818
Test name
Test status
Simulation time 6531612485 ps
CPU time 192.35 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:51:48 PM PDT 24
Peak memory 236848 kb
Host smart-766e448f-2d6e-4bf4-b06f-4f6f269a6db0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3071308447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3071308447
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2288549800
Short name T189
Test name
Test status
Simulation time 121577590 ps
CPU time 5.3 seconds
Started Jun 04 12:48:39 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 240416 kb
Host smart-f5fca0c4-90ab-4986-87df-e65b1edfd091
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2288549800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2288549800
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1535682073
Short name T726
Test name
Test status
Simulation time 33326498 ps
CPU time 5.7 seconds
Started Jun 04 12:48:28 PM PDT 24
Finished Jun 04 12:48:34 PM PDT 24
Peak memory 241140 kb
Host smart-17ec436b-46b9-45d1-9959-3a456995eb7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535682073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1535682073
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3005280010
Short name T812
Test name
Test status
Simulation time 232887780 ps
CPU time 7.42 seconds
Started Jun 04 12:48:26 PM PDT 24
Finished Jun 04 12:48:34 PM PDT 24
Peak memory 240240 kb
Host smart-1005a1c6-d918-4602-a053-46edb2a543a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3005280010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3005280010
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4088050006
Short name T826
Test name
Test status
Simulation time 16695927 ps
CPU time 1.38 seconds
Started Jun 04 12:48:26 PM PDT 24
Finished Jun 04 12:48:28 PM PDT 24
Peak memory 236796 kb
Host smart-2bef4d3d-2a30-45bb-af02-166e5ab0bfde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4088050006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4088050006
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1975442768
Short name T824
Test name
Test status
Simulation time 644343533 ps
CPU time 21.46 seconds
Started Jun 04 12:48:29 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 244932 kb
Host smart-3f3efbb3-68fc-478e-8472-b55d18c3d9db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1975442768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1975442768
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2519105991
Short name T143
Test name
Test status
Simulation time 6032051043 ps
CPU time 539.81 seconds
Started Jun 04 12:48:25 PM PDT 24
Finished Jun 04 12:57:26 PM PDT 24
Peak memory 265300 kb
Host smart-2bb3b843-51c0-4d0a-a405-20806c330e18
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519105991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2519105991
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2382428554
Short name T778
Test name
Test status
Simulation time 127840939 ps
CPU time 13.89 seconds
Started Jun 04 12:48:26 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 248192 kb
Host smart-de714507-9ec2-44cf-ac08-54ebe12f402e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2382428554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2382428554
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.146971509
Short name T733
Test name
Test status
Simulation time 32848132 ps
CPU time 5.53 seconds
Started Jun 04 12:48:53 PM PDT 24
Finished Jun 04 12:48:59 PM PDT 24
Peak memory 256752 kb
Host smart-2d91e769-5a4a-4713-94b2-02772599d709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146971509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.146971509
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1000439722
Short name T823
Test name
Test status
Simulation time 86117510 ps
CPU time 5.25 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 239812 kb
Host smart-e26a55af-1f62-43b5-91aa-1408369aad1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1000439722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1000439722
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3155840985
Short name T769
Test name
Test status
Simulation time 14329129 ps
CPU time 1.75 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:48:55 PM PDT 24
Peak memory 235972 kb
Host smart-26e36d13-3d89-446b-be4e-4c239e8cafb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3155840985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3155840985
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1462321988
Short name T786
Test name
Test status
Simulation time 516992754 ps
CPU time 39.35 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:49:33 PM PDT 24
Peak memory 244980 kb
Host smart-1e1e0219-efc4-4391-878f-35c0b3c253fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1462321988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1462321988
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4254188170
Short name T151
Test name
Test status
Simulation time 5010584903 ps
CPU time 340.12 seconds
Started Jun 04 12:48:53 PM PDT 24
Finished Jun 04 12:54:34 PM PDT 24
Peak memory 265372 kb
Host smart-221525c4-ffe8-4e0a-9b87-fcb08b46896a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4254188170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4254188170
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2549177955
Short name T725
Test name
Test status
Simulation time 156432798 ps
CPU time 11.78 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 248716 kb
Host smart-5a7641ba-b694-4c7f-b6fb-d4c30b808a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2549177955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2549177955
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2235716658
Short name T195
Test name
Test status
Simulation time 277064663 ps
CPU time 5.4 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 239660 kb
Host smart-0ae55ece-1e41-4634-bc36-5639280e59f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235716658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2235716658
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1990209585
Short name T792
Test name
Test status
Simulation time 182868510 ps
CPU time 4.55 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 239716 kb
Host smart-bf6a95f0-adec-4393-876d-3b477ffe6edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1990209585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1990209585
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1466901826
Short name T795
Test name
Test status
Simulation time 15894184 ps
CPU time 1.31 seconds
Started Jun 04 12:48:56 PM PDT 24
Finished Jun 04 12:48:58 PM PDT 24
Peak memory 236948 kb
Host smart-9ab66622-cdad-4005-a50f-0ca93ab2312d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1466901826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1466901826
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3192455639
Short name T829
Test name
Test status
Simulation time 372364150 ps
CPU time 12.99 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 248624 kb
Host smart-e4ea6c87-7653-4ed0-aa7a-c6bcaa55db7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3192455639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3192455639
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3931590431
Short name T789
Test name
Test status
Simulation time 35348566264 ps
CPU time 569.46 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:58:25 PM PDT 24
Peak memory 265332 kb
Host smart-1bdc3668-803a-4540-aefe-f2ccabf83f5a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931590431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3931590431
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.511879993
Short name T707
Test name
Test status
Simulation time 266366895 ps
CPU time 7.7 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:49:00 PM PDT 24
Peak memory 248616 kb
Host smart-bcbd92fc-3217-4646-851a-a57a6f847f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=511879993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.511879993
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.794517810
Short name T744
Test name
Test status
Simulation time 77160910 ps
CPU time 4.4 seconds
Started Jun 04 12:48:56 PM PDT 24
Finished Jun 04 12:49:02 PM PDT 24
Peak memory 235856 kb
Host smart-a5ffdedb-fc3d-4575-951c-493f0c8bcd59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=794517810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.794517810
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2413160167
Short name T800
Test name
Test status
Simulation time 118764720 ps
CPU time 5.52 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:48:59 PM PDT 24
Peak memory 248712 kb
Host smart-ef26db60-fdcc-4fef-9610-279050b6e9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413160167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2413160167
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2097902697
Short name T720
Test name
Test status
Simulation time 66456857 ps
CPU time 4.94 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 235748 kb
Host smart-ce2eed49-9f72-42fc-a511-970d537086ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2097902697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2097902697
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4067898082
Short name T716
Test name
Test status
Simulation time 24850373 ps
CPU time 1.3 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 234788 kb
Host smart-0eb0b8d4-a3e6-473c-8adf-0c4d996ff92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4067898082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4067898082
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1913798966
Short name T783
Test name
Test status
Simulation time 256724553 ps
CPU time 18.84 seconds
Started Jun 04 12:48:53 PM PDT 24
Finished Jun 04 12:49:13 PM PDT 24
Peak memory 244976 kb
Host smart-36daa78b-ac1e-4cff-a120-ea6ab5c2ef4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1913798966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1913798966
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4205160734
Short name T142
Test name
Test status
Simulation time 7926858121 ps
CPU time 560.15 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:58:12 PM PDT 24
Peak memory 265372 kb
Host smart-2afd452e-5028-4365-8cad-72b20de43f8e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205160734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4205160734
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1175391735
Short name T807
Test name
Test status
Simulation time 82156355 ps
CPU time 9.44 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 248620 kb
Host smart-69c3a507-6895-48f1-b1a6-18cc58479aa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1175391735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1175391735
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.72293041
Short name T756
Test name
Test status
Simulation time 139279851 ps
CPU time 6.06 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 239004 kb
Host smart-58edb4ad-fcab-45c6-8e50-afc2441205a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72293041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.alert_handler_csr_mem_rw_with_rand_reset.72293041
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2814411313
Short name T828
Test name
Test status
Simulation time 373214191 ps
CPU time 7.86 seconds
Started Jun 04 12:48:52 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 240260 kb
Host smart-ffd1d92a-758a-4a65-bcf4-b0c32a93ce37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2814411313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2814411313
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2615570717
Short name T749
Test name
Test status
Simulation time 20640071 ps
CPU time 1.29 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 235880 kb
Host smart-0ddac774-1deb-4f42-b080-1f98af803d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2615570717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2615570717
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2114653842
Short name T748
Test name
Test status
Simulation time 1038820944 ps
CPU time 18.68 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:49:14 PM PDT 24
Peak memory 244036 kb
Host smart-6eb97821-1b4d-442b-8ca8-2e397c8671ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2114653842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2114653842
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2451968881
Short name T145
Test name
Test status
Simulation time 21694747810 ps
CPU time 298.42 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:53:50 PM PDT 24
Peak memory 265380 kb
Host smart-cd6445d9-42e2-4d59-b2ff-1a119807b2bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2451968881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2451968881
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2728990631
Short name T765
Test name
Test status
Simulation time 101450882 ps
CPU time 13.4 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:49:08 PM PDT 24
Peak memory 248444 kb
Host smart-b10cb2a9-5d80-4d8b-b11f-183d71610db2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2728990631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2728990631
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2835484077
Short name T811
Test name
Test status
Simulation time 236230308 ps
CPU time 3.63 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:48:56 PM PDT 24
Peak memory 236972 kb
Host smart-79ecac98-50af-4d63-a24b-52081b5feaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2835484077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2835484077
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2916012084
Short name T752
Test name
Test status
Simulation time 53149647 ps
CPU time 4.55 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 240120 kb
Host smart-df99f36e-b59c-4628-958f-d36d5cff93cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916012084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2916012084
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.412638318
Short name T796
Test name
Test status
Simulation time 62300613 ps
CPU time 5.17 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:49:00 PM PDT 24
Peak memory 236080 kb
Host smart-1e472221-4522-47bd-b385-aaeb2c4b082a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=412638318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.412638318
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3636985872
Short name T736
Test name
Test status
Simulation time 36689545 ps
CPU time 1.3 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:48:54 PM PDT 24
Peak memory 236892 kb
Host smart-438ab0db-7a79-4232-99e6-a92c83d9ed5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3636985872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3636985872
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3022862251
Short name T803
Test name
Test status
Simulation time 88018373 ps
CPU time 11.64 seconds
Started Jun 04 12:48:56 PM PDT 24
Finished Jun 04 12:49:09 PM PDT 24
Peak memory 244172 kb
Host smart-ed837ae4-dffb-43a1-b864-8d0f9c8f4a91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3022862251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3022862251
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1397973254
Short name T124
Test name
Test status
Simulation time 13328514649 ps
CPU time 479.18 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:56:51 PM PDT 24
Peak memory 268804 kb
Host smart-23c2ed19-aaff-4f29-a65a-ba1ad122552d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397973254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1397973254
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1516027551
Short name T813
Test name
Test status
Simulation time 320105492 ps
CPU time 12.08 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 248592 kb
Host smart-b858ed36-b1fd-41c0-bc00-7f2dfa9b14d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1516027551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1516027551
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.726982445
Short name T799
Test name
Test status
Simulation time 219761549 ps
CPU time 4.82 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:49:07 PM PDT 24
Peak memory 239320 kb
Host smart-2311cd9b-be0c-4b74-a291-a47760e15d17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726982445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.726982445
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.209689384
Short name T734
Test name
Test status
Simulation time 347113057 ps
CPU time 7.65 seconds
Started Jun 04 12:49:07 PM PDT 24
Finished Jun 04 12:49:15 PM PDT 24
Peak memory 236696 kb
Host smart-649c826c-ea48-4dab-9611-b6bc6e66285a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=209689384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.209689384
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.14946172
Short name T830
Test name
Test status
Simulation time 7473193 ps
CPU time 1.53 seconds
Started Jun 04 12:49:05 PM PDT 24
Finished Jun 04 12:49:08 PM PDT 24
Peak memory 236012 kb
Host smart-3be0a2e0-3e6c-4f01-aa0c-c252d41e9af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=14946172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.14946172
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2569318898
Short name T820
Test name
Test status
Simulation time 252790122 ps
CPU time 17.6 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:18 PM PDT 24
Peak memory 244052 kb
Host smart-0084fbc8-0370-4e71-a9b7-9db783b69245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2569318898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2569318898
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1491368034
Short name T156
Test name
Test status
Simulation time 4009201886 ps
CPU time 287.34 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:53:49 PM PDT 24
Peak memory 265408 kb
Host smart-d244ff04-f0a0-499f-8c74-1a2c27fb10e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1491368034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1491368034
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1905773284
Short name T134
Test name
Test status
Simulation time 17563165908 ps
CPU time 574.26 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:58:35 PM PDT 24
Peak memory 272104 kb
Host smart-f134c8c4-56d0-4b06-81be-30eab6164449
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905773284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1905773284
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.188594536
Short name T822
Test name
Test status
Simulation time 212006067 ps
CPU time 6.88 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:10 PM PDT 24
Peak memory 252688 kb
Host smart-0a98839f-66c2-4304-b94e-e9422b551630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=188594536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.188594536
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4033886145
Short name T177
Test name
Test status
Simulation time 505127417 ps
CPU time 10.57 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:16 PM PDT 24
Peak memory 240280 kb
Host smart-b4d96b12-e694-4587-8eed-2cd5616a2061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033886145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4033886145
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4064307093
Short name T762
Test name
Test status
Simulation time 117689734 ps
CPU time 8.15 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 240228 kb
Host smart-ad3e2cfd-7b4a-4567-8952-6960385efc67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4064307093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4064307093
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3104415404
Short name T718
Test name
Test status
Simulation time 18734412 ps
CPU time 1.46 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 234968 kb
Host smart-9184d56e-1749-41b6-af7a-648455be42e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104415404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3104415404
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1567178353
Short name T802
Test name
Test status
Simulation time 723170867 ps
CPU time 23.53 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:28 PM PDT 24
Peak memory 248592 kb
Host smart-ac0c4846-e8de-4ca6-8bbf-b85b2b07487d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1567178353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1567178353
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.930855086
Short name T140
Test name
Test status
Simulation time 7955734264 ps
CPU time 501.08 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:57:24 PM PDT 24
Peak memory 268064 kb
Host smart-0d107ce4-58f1-40a6-b843-9a85f65fea50
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930855086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.930855086
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.241201389
Short name T738
Test name
Test status
Simulation time 196761576 ps
CPU time 12.03 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:49:14 PM PDT 24
Peak memory 248736 kb
Host smart-79403d98-ae52-43c2-87f5-dea121a95b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=241201389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.241201389
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1197383747
Short name T194
Test name
Test status
Simulation time 1183137352 ps
CPU time 8.13 seconds
Started Jun 04 12:48:59 PM PDT 24
Finished Jun 04 12:49:08 PM PDT 24
Peak memory 239596 kb
Host smart-64a8f4fc-cfc5-49dd-b326-778e57b96ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197383747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1197383747
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.325729726
Short name T805
Test name
Test status
Simulation time 32567061 ps
CPU time 5.19 seconds
Started Jun 04 12:48:59 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 240200 kb
Host smart-11062f6e-5882-441a-9aad-5fc6599a5876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=325729726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.325729726
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1551334653
Short name T709
Test name
Test status
Simulation time 7888521 ps
CPU time 1.36 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:04 PM PDT 24
Peak memory 236776 kb
Host smart-82f18ad9-c67a-4468-bfc7-b3e65ec5b264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1551334653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1551334653
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2129879409
Short name T776
Test name
Test status
Simulation time 1380310158 ps
CPU time 22.65 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:24 PM PDT 24
Peak memory 244972 kb
Host smart-a8c4eff7-5ef7-4b3d-8165-55e955cdcb43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2129879409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2129879409
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4149739516
Short name T153
Test name
Test status
Simulation time 5583332499 ps
CPU time 167.9 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:51:52 PM PDT 24
Peak memory 257068 kb
Host smart-6556ec25-d29d-4449-b80b-206d977a80d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4149739516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4149739516
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.569933111
Short name T157
Test name
Test status
Simulation time 22427142293 ps
CPU time 1110.92 seconds
Started Jun 04 12:48:59 PM PDT 24
Finished Jun 04 01:07:31 PM PDT 24
Peak memory 272840 kb
Host smart-cb9ae147-2e13-4d5d-98e6-304a8d383b22
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569933111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.569933111
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3781308377
Short name T724
Test name
Test status
Simulation time 855247132 ps
CPU time 13.57 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:17 PM PDT 24
Peak memory 255660 kb
Host smart-fcde5fc2-517c-4f8e-a252-a26f2f6b2265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3781308377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3781308377
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2012117028
Short name T335
Test name
Test status
Simulation time 100343993 ps
CPU time 4.6 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:49:09 PM PDT 24
Peak memory 240412 kb
Host smart-dccb2004-1b5c-4363-945b-1a7fe88b90e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012117028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2012117028
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3903974580
Short name T821
Test name
Test status
Simulation time 211427790 ps
CPU time 7.95 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 235764 kb
Host smart-62753ff6-6b40-4f85-bf20-65654cea3b37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3903974580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3903974580
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2044201682
Short name T809
Test name
Test status
Simulation time 22897147 ps
CPU time 1.43 seconds
Started Jun 04 12:49:07 PM PDT 24
Finished Jun 04 12:49:09 PM PDT 24
Peak memory 235860 kb
Host smart-6e6cf8c4-a3dc-4fd2-b37e-6b24e716fe11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2044201682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2044201682
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3995377719
Short name T753
Test name
Test status
Simulation time 1821246105 ps
CPU time 21.24 seconds
Started Jun 04 12:49:08 PM PDT 24
Finished Jun 04 12:49:30 PM PDT 24
Peak memory 245108 kb
Host smart-ca74cef4-954b-40ff-ad38-91b7affd3f51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3995377719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3995377719
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2730453968
Short name T831
Test name
Test status
Simulation time 229235189 ps
CPU time 16.5 seconds
Started Jun 04 12:48:59 PM PDT 24
Finished Jun 04 12:49:17 PM PDT 24
Peak memory 248456 kb
Host smart-74856438-bcf1-4b47-b229-315a7252df88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2730453968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2730453968
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2162992912
Short name T193
Test name
Test status
Simulation time 455833281 ps
CPU time 5.72 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 236748 kb
Host smart-f938b1f6-4c6c-4e5f-85a3-9599255128cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162992912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2162992912
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4229584030
Short name T760
Test name
Test status
Simulation time 121016604 ps
CPU time 5.22 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 240244 kb
Host smart-effba095-96a4-409a-ba3f-03643211bb80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4229584030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4229584030
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3261495289
Short name T817
Test name
Test status
Simulation time 9577914 ps
CPU time 1.4 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 234944 kb
Host smart-18483851-3919-4cf4-a645-e63d13d08cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3261495289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3261495289
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1941755786
Short name T764
Test name
Test status
Simulation time 686826708 ps
CPU time 41.86 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:47 PM PDT 24
Peak memory 240428 kb
Host smart-bfcf706b-1b20-4065-a190-b62ecc529d8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1941755786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1941755786
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1159981431
Short name T150
Test name
Test status
Simulation time 16964198472 ps
CPU time 1185.66 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 01:08:51 PM PDT 24
Peak memory 265480 kb
Host smart-62ba6b6f-ab61-402a-891f-cc267f432193
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159981431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1159981431
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4101655730
Short name T782
Test name
Test status
Simulation time 302126285 ps
CPU time 21.77 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:23 PM PDT 24
Peak memory 248560 kb
Host smart-7379be8b-a749-4bf5-aa45-9eb113832667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4101655730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4101655730
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.86463631
Short name T759
Test name
Test status
Simulation time 8777645327 ps
CPU time 137.49 seconds
Started Jun 04 12:48:39 PM PDT 24
Finished Jun 04 12:50:58 PM PDT 24
Peak memory 240260 kb
Host smart-f08f7a45-efce-4a0e-9005-3a87b92a5307
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=86463631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.86463631
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1401109248
Short name T827
Test name
Test status
Simulation time 16098354744 ps
CPU time 434.7 seconds
Started Jun 04 12:48:31 PM PDT 24
Finished Jun 04 12:55:47 PM PDT 24
Peak memory 235868 kb
Host smart-447d2355-3fe2-4ca6-aa3d-2a099b95d568
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1401109248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1401109248
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2809631445
Short name T188
Test name
Test status
Simulation time 347361531 ps
CPU time 5.06 seconds
Started Jun 04 12:48:39 PM PDT 24
Finished Jun 04 12:48:45 PM PDT 24
Peak memory 240268 kb
Host smart-5a1c2b4f-aa72-4863-8afd-720400b6572f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2809631445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2809631445
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3478166287
Short name T728
Test name
Test status
Simulation time 34165986 ps
CPU time 5.27 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:42 PM PDT 24
Peak memory 242172 kb
Host smart-41d76438-d090-4f6f-8398-317e525178bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478166287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3478166287
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4962027
Short name T191
Test name
Test status
Simulation time 34857592 ps
CPU time 5.6 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:42 PM PDT 24
Peak memory 240384 kb
Host smart-be31f3c2-3628-45d1-b95d-a8121493f4f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4962027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4962027
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3389991653
Short name T810
Test name
Test status
Simulation time 6247222 ps
CPU time 1.47 seconds
Started Jun 04 12:48:36 PM PDT 24
Finished Jun 04 12:48:39 PM PDT 24
Peak memory 234924 kb
Host smart-6eeac8c0-3ccb-445c-b4ac-3683d5a7652b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3389991653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3389991653
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.649610774
Short name T190
Test name
Test status
Simulation time 412040606 ps
CPU time 23.17 seconds
Started Jun 04 12:48:34 PM PDT 24
Finished Jun 04 12:48:59 PM PDT 24
Peak memory 248832 kb
Host smart-ff55746e-aa5c-4b3f-893d-72a0bbdf6771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=649610774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.649610774
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2384959611
Short name T135
Test name
Test status
Simulation time 6696169359 ps
CPU time 151.29 seconds
Started Jun 04 12:48:28 PM PDT 24
Finished Jun 04 12:51:00 PM PDT 24
Peak memory 257012 kb
Host smart-57633c11-db26-4341-8491-f6a88cd11f09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2384959611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2384959611
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1661790993
Short name T790
Test name
Test status
Simulation time 178466007 ps
CPU time 13.82 seconds
Started Jun 04 12:48:25 PM PDT 24
Finished Jun 04 12:48:39 PM PDT 24
Peak memory 252808 kb
Host smart-9d675d11-073e-4ce8-acab-424a98be9802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1661790993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1661790993
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1278139391
Short name T164
Test name
Test status
Simulation time 11568111 ps
CPU time 1.91 seconds
Started Jun 04 12:49:00 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 235900 kb
Host smart-3b2ae810-f4a3-478c-898a-db56a9987472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1278139391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1278139391
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3989237794
Short name T785
Test name
Test status
Simulation time 14027374 ps
CPU time 1.52 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:04 PM PDT 24
Peak memory 236920 kb
Host smart-44a6ffe7-077b-4d11-8d42-f1032cd41221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3989237794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3989237794
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1308216420
Short name T770
Test name
Test status
Simulation time 18896979 ps
CPU time 1.28 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:06 PM PDT 24
Peak memory 236764 kb
Host smart-4b43f5ac-7be9-4ac6-95a4-843a57c7f2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1308216420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1308216420
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.415566717
Short name T754
Test name
Test status
Simulation time 42123144 ps
CPU time 2.94 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:49:07 PM PDT 24
Peak memory 236772 kb
Host smart-34179d86-a491-46f0-943d-5a27b820e4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=415566717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.415566717
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.608365188
Short name T751
Test name
Test status
Simulation time 7479633 ps
CPU time 1.33 seconds
Started Jun 04 12:49:07 PM PDT 24
Finished Jun 04 12:49:09 PM PDT 24
Peak memory 235860 kb
Host smart-b7c2e221-aaea-4c60-aa69-422f2bc09886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=608365188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.608365188
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3156888894
Short name T741
Test name
Test status
Simulation time 9463005 ps
CPU time 1.49 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:49:06 PM PDT 24
Peak memory 236000 kb
Host smart-f3ba8ffd-9f15-44f8-b295-6031ada19d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3156888894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3156888894
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1658076397
Short name T711
Test name
Test status
Simulation time 33378404 ps
CPU time 1.25 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:49:06 PM PDT 24
Peak memory 236812 kb
Host smart-c9f20b3f-3f94-4b4a-a7c7-db400c9a5472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1658076397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1658076397
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.599969702
Short name T806
Test name
Test status
Simulation time 10890067 ps
CPU time 1.64 seconds
Started Jun 04 12:48:59 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 235856 kb
Host smart-0b3dd4d0-ea25-4c03-bbb5-bda9802ce7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=599969702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.599969702
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.901327558
Short name T766
Test name
Test status
Simulation time 10683796 ps
CPU time 1.47 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:49:03 PM PDT 24
Peak memory 235848 kb
Host smart-29b567b6-4cc7-4870-b81f-825d17e179ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=901327558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.901327558
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.199071213
Short name T798
Test name
Test status
Simulation time 10709961 ps
CPU time 1.35 seconds
Started Jun 04 12:49:05 PM PDT 24
Finished Jun 04 12:49:07 PM PDT 24
Peak memory 234860 kb
Host smart-242028cb-c0f2-452e-9f38-61e88eb16026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=199071213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.199071213
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2741791601
Short name T773
Test name
Test status
Simulation time 13172816694 ps
CPU time 256.35 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:52:58 PM PDT 24
Peak memory 239392 kb
Host smart-d1570120-cc74-4e6f-b016-7a5a643886b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2741791601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2741791601
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2371697280
Short name T791
Test name
Test status
Simulation time 4281095143 ps
CPU time 249.13 seconds
Started Jun 04 12:48:42 PM PDT 24
Finished Jun 04 12:52:51 PM PDT 24
Peak memory 240440 kb
Host smart-a8d5000f-9d4e-4ab6-ba84-986d89f6460c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2371697280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2371697280
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2769452283
Short name T730
Test name
Test status
Simulation time 1305378445 ps
CPU time 6.15 seconds
Started Jun 04 12:48:48 PM PDT 24
Finished Jun 04 12:48:55 PM PDT 24
Peak memory 240412 kb
Host smart-426be57b-a315-4ea4-91a3-ab953bf5d63b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2769452283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2769452283
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2652813417
Short name T804
Test name
Test status
Simulation time 870950099 ps
CPU time 13.74 seconds
Started Jun 04 12:48:39 PM PDT 24
Finished Jun 04 12:48:54 PM PDT 24
Peak memory 255356 kb
Host smart-ddf6a132-8d75-448a-8dc3-2109fd4811c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652813417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2652813417
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3213964123
Short name T758
Test name
Test status
Simulation time 250012139 ps
CPU time 5.4 seconds
Started Jun 04 12:48:38 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 236708 kb
Host smart-a7357900-c18a-4b7f-9798-45f4d5d505d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3213964123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3213964123
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3267480514
Short name T797
Test name
Test status
Simulation time 10977262 ps
CPU time 1.28 seconds
Started Jun 04 12:48:40 PM PDT 24
Finished Jun 04 12:48:42 PM PDT 24
Peak memory 235876 kb
Host smart-0fd46435-fae0-4e5d-8510-4e20dda20e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3267480514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3267480514
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1297031738
Short name T788
Test name
Test status
Simulation time 604306823 ps
CPU time 38.27 seconds
Started Jun 04 12:48:37 PM PDT 24
Finished Jun 04 12:49:16 PM PDT 24
Peak memory 248548 kb
Host smart-e45709a0-9c52-4448-a641-f93b9bbc4e78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1297031738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1297031738
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2494765377
Short name T825
Test name
Test status
Simulation time 1514713195 ps
CPU time 172.11 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:51:29 PM PDT 24
Peak memory 271264 kb
Host smart-2904b644-d6a9-4b98-b43f-745733d7cb17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2494765377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2494765377
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3668186755
Short name T122
Test name
Test status
Simulation time 4275460565 ps
CPU time 299.85 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 12:53:34 PM PDT 24
Peak memory 265344 kb
Host smart-17309352-7790-4070-949c-7672aa6f6500
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668186755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3668186755
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1581669419
Short name T755
Test name
Test status
Simulation time 189207448 ps
CPU time 13.08 seconds
Started Jun 04 12:48:44 PM PDT 24
Finished Jun 04 12:48:58 PM PDT 24
Peak memory 248644 kb
Host smart-38fdc716-7d9d-4ac3-a959-17eb0c38e23d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1581669419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1581669419
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2840779442
Short name T714
Test name
Test status
Simulation time 8284761 ps
CPU time 1.32 seconds
Started Jun 04 12:49:08 PM PDT 24
Finished Jun 04 12:49:10 PM PDT 24
Peak memory 236944 kb
Host smart-150e8842-f18a-45dc-a621-3ded1eedce5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840779442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2840779442
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.931713539
Short name T793
Test name
Test status
Simulation time 11562360 ps
CPU time 1.71 seconds
Started Jun 04 12:49:01 PM PDT 24
Finished Jun 04 12:49:04 PM PDT 24
Peak memory 236780 kb
Host smart-cf46f947-2160-4343-99de-49bf192dba12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=931713539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.931713539
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2684332632
Short name T721
Test name
Test status
Simulation time 17515365 ps
CPU time 1.47 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:06 PM PDT 24
Peak memory 236932 kb
Host smart-2d954aed-cfb1-45b4-97f2-19fbc73472f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2684332632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2684332632
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1549382282
Short name T747
Test name
Test status
Simulation time 14243885 ps
CPU time 1.37 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:04 PM PDT 24
Peak memory 236828 kb
Host smart-948c3134-a882-414f-85ca-264fe8d4b595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1549382282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1549382282
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1025238145
Short name T708
Test name
Test status
Simulation time 15646462 ps
CPU time 1.37 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 234964 kb
Host smart-4bb1fa7b-5831-4e7d-94fe-e2a8f2dab1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1025238145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1025238145
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1166052261
Short name T814
Test name
Test status
Simulation time 7651743 ps
CPU time 1.45 seconds
Started Jun 04 12:49:04 PM PDT 24
Finished Jun 04 12:49:06 PM PDT 24
Peak memory 236900 kb
Host smart-29564d69-9098-4e5a-acf0-af2de59f946e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1166052261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1166052261
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.279965490
Short name T768
Test name
Test status
Simulation time 15538131 ps
CPU time 1.43 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:04 PM PDT 24
Peak memory 236832 kb
Host smart-5706d4e7-36f9-4398-9a86-db5b357bedb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=279965490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.279965490
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1557743598
Short name T757
Test name
Test status
Simulation time 24466519 ps
CPU time 1.37 seconds
Started Jun 04 12:49:06 PM PDT 24
Finished Jun 04 12:49:08 PM PDT 24
Peak memory 235968 kb
Host smart-59c1cdbb-f69f-46f8-848b-14db38039e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1557743598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1557743598
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.486508166
Short name T745
Test name
Test status
Simulation time 19679632 ps
CPU time 1.42 seconds
Started Jun 04 12:49:08 PM PDT 24
Finished Jun 04 12:49:10 PM PDT 24
Peak memory 236008 kb
Host smart-0ea9a6aa-195b-402f-b9da-12399c4ed199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=486508166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.486508166
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3895821700
Short name T743
Test name
Test status
Simulation time 15339717291 ps
CPU time 319.64 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:54:01 PM PDT 24
Peak memory 239984 kb
Host smart-ab3917b0-8b41-48cb-a155-490523fa5a2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3895821700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3895821700
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.103568589
Short name T775
Test name
Test status
Simulation time 11931281729 ps
CPU time 387.11 seconds
Started Jun 04 12:48:34 PM PDT 24
Finished Jun 04 12:55:02 PM PDT 24
Peak memory 240336 kb
Host smart-52a2606c-1bb8-4d0b-91d5-57e5fee76cc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=103568589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.103568589
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1202665175
Short name T179
Test name
Test status
Simulation time 26990931 ps
CPU time 3.7 seconds
Started Jun 04 12:48:40 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 240368 kb
Host smart-0735f7e0-a580-4459-ab6e-b3793b564fee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1202665175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1202665175
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1782597458
Short name T780
Test name
Test status
Simulation time 897274305 ps
CPU time 9.14 seconds
Started Jun 04 12:48:36 PM PDT 24
Finished Jun 04 12:48:47 PM PDT 24
Peak memory 239348 kb
Host smart-4f775368-f2bf-46f4-b5b3-917b4d4b6ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782597458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1782597458
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4058629808
Short name T833
Test name
Test status
Simulation time 40055559 ps
CPU time 5.29 seconds
Started Jun 04 12:48:33 PM PDT 24
Finished Jun 04 12:48:40 PM PDT 24
Peak memory 235836 kb
Host smart-1fbbd9e6-e0cb-42f5-b54e-482abc70cd7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4058629808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4058629808
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1672967705
Short name T761
Test name
Test status
Simulation time 18194876 ps
CPU time 1.48 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:38 PM PDT 24
Peak memory 235876 kb
Host smart-f2b9934a-4029-4543-85cc-6876718a6921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1672967705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1672967705
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1215475395
Short name T816
Test name
Test status
Simulation time 1127300189 ps
CPU time 20.09 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 244064 kb
Host smart-37650713-ddc2-4384-9991-37d516dc5a76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1215475395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1215475395
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.607112181
Short name T144
Test name
Test status
Simulation time 2468674041 ps
CPU time 159.7 seconds
Started Jun 04 12:48:34 PM PDT 24
Finished Jun 04 12:51:15 PM PDT 24
Peak memory 257100 kb
Host smart-76f5f8b5-09fe-473f-90e5-c4848db28ab0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=607112181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.607112181
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2874436572
Short name T819
Test name
Test status
Simulation time 721850577 ps
CPU time 10.94 seconds
Started Jun 04 12:48:37 PM PDT 24
Finished Jun 04 12:48:49 PM PDT 24
Peak memory 248000 kb
Host smart-41a31388-f978-43e1-903e-1d46bf7d8fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2874436572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2874436572
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2886297702
Short name T772
Test name
Test status
Simulation time 7496094 ps
CPU time 1.39 seconds
Started Jun 04 12:49:03 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 234860 kb
Host smart-34beacf3-f3ca-4f5d-92e0-8683813b9c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2886297702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2886297702
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4227257592
Short name T332
Test name
Test status
Simulation time 13483149 ps
CPU time 1.4 seconds
Started Jun 04 12:49:02 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 236944 kb
Host smart-33310307-2eda-4ff3-8673-6a6952982afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4227257592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4227257592
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.219497459
Short name T162
Test name
Test status
Simulation time 8394114 ps
CPU time 1.41 seconds
Started Jun 04 12:49:06 PM PDT 24
Finished Jun 04 12:49:08 PM PDT 24
Peak memory 234968 kb
Host smart-00a18d84-a41e-4c85-a6bc-6d4b6c60b536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=219497459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.219497459
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1397345871
Short name T723
Test name
Test status
Simulation time 10603128 ps
CPU time 1.47 seconds
Started Jun 04 12:49:13 PM PDT 24
Finished Jun 04 12:49:16 PM PDT 24
Peak memory 235996 kb
Host smart-e8872356-8a42-44fe-b3d8-b6a08143efa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1397345871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1397345871
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2815887575
Short name T329
Test name
Test status
Simulation time 9100196 ps
CPU time 1.47 seconds
Started Jun 04 12:49:11 PM PDT 24
Finished Jun 04 12:49:13 PM PDT 24
Peak memory 236812 kb
Host smart-e34fd1a2-3e3b-46fa-baba-fd125382775e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2815887575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2815887575
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3053466648
Short name T794
Test name
Test status
Simulation time 8123821 ps
CPU time 1.46 seconds
Started Jun 04 12:49:09 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 234968 kb
Host smart-c687db08-c997-472d-ba75-3159c4965ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3053466648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3053466648
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1802519453
Short name T779
Test name
Test status
Simulation time 10567096 ps
CPU time 1.28 seconds
Started Jun 04 12:49:12 PM PDT 24
Finished Jun 04 12:49:14 PM PDT 24
Peak memory 235988 kb
Host smart-e33e6438-c91c-4394-b62e-a457e48fbb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1802519453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1802519453
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.19907029
Short name T784
Test name
Test status
Simulation time 11268614 ps
CPU time 1.22 seconds
Started Jun 04 12:49:10 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 235872 kb
Host smart-3c651524-c95e-4309-908e-606be54d4f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=19907029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.19907029
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3328924915
Short name T712
Test name
Test status
Simulation time 19594267 ps
CPU time 1.39 seconds
Started Jun 04 12:49:10 PM PDT 24
Finished Jun 04 12:49:12 PM PDT 24
Peak memory 236800 kb
Host smart-160f1178-473a-43d5-adfd-8deb615d5323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3328924915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3328924915
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1909389959
Short name T763
Test name
Test status
Simulation time 34178146 ps
CPU time 5.67 seconds
Started Jun 04 12:48:45 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 256852 kb
Host smart-f827eeaf-879a-4966-8aab-4f434dc677e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909389959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1909389959
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4240353876
Short name T777
Test name
Test status
Simulation time 34282751 ps
CPU time 3.24 seconds
Started Jun 04 12:48:44 PM PDT 24
Finished Jun 04 12:48:49 PM PDT 24
Peak memory 236708 kb
Host smart-e13e3aa5-a49c-46a8-8593-49f0ad654bbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4240353876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4240353876
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3202112972
Short name T746
Test name
Test status
Simulation time 16179165 ps
CPU time 1.32 seconds
Started Jun 04 12:48:37 PM PDT 24
Finished Jun 04 12:48:39 PM PDT 24
Peak memory 234840 kb
Host smart-5659e0e6-a89b-41af-9043-9fec3796b600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202112972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3202112972
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2716986751
Short name T740
Test name
Test status
Simulation time 183032460 ps
CPU time 12.25 seconds
Started Jun 04 12:48:45 PM PDT 24
Finished Jun 04 12:48:58 PM PDT 24
Peak memory 244048 kb
Host smart-a9490f39-92a7-479e-b054-40b8bf9c01d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2716986751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2716986751
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1216577794
Short name T158
Test name
Test status
Simulation time 3721821393 ps
CPU time 251.9 seconds
Started Jun 04 12:48:35 PM PDT 24
Finished Jun 04 12:52:48 PM PDT 24
Peak memory 265232 kb
Host smart-772a52ca-0241-453a-99bd-04dacb608118
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1216577794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1216577794
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2610853519
Short name T722
Test name
Test status
Simulation time 267731751 ps
CPU time 8.39 seconds
Started Jun 04 12:48:34 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 248724 kb
Host smart-ad8bb5b3-a64d-4134-b5ab-94968ae31194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2610853519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2610853519
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3325211889
Short name T801
Test name
Test status
Simulation time 473945676 ps
CPU time 9.37 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:48:51 PM PDT 24
Peak memory 238064 kb
Host smart-e99d3228-3588-4794-8f4f-be7cd28f5206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325211889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3325211889
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.6766117
Short name T739
Test name
Test status
Simulation time 72316161 ps
CPU time 5.72 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:48:56 PM PDT 24
Peak memory 236692 kb
Host smart-46b6054e-9fcb-484e-89c5-c4552a6996ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=6766117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.6766117
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1952175731
Short name T333
Test name
Test status
Simulation time 7877914 ps
CPU time 1.29 seconds
Started Jun 04 12:48:45 PM PDT 24
Finished Jun 04 12:48:47 PM PDT 24
Peak memory 236920 kb
Host smart-2718b9ca-4603-455d-8847-2c5045c14894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1952175731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1952175731
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3593466250
Short name T187
Test name
Test status
Simulation time 752372017 ps
CPU time 24.58 seconds
Started Jun 04 12:48:40 PM PDT 24
Finished Jun 04 12:49:06 PM PDT 24
Peak memory 248608 kb
Host smart-69a5c434-08cb-4cd6-8a06-0622f7d9b3a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3593466250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3593466250
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.207114309
Short name T125
Test name
Test status
Simulation time 5469790151 ps
CPU time 183.43 seconds
Started Jun 04 12:48:43 PM PDT 24
Finished Jun 04 12:51:47 PM PDT 24
Peak memory 273456 kb
Host smart-4ac57fa1-1121-4d91-b726-ec0b390643e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=207114309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.207114309
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.555732190
Short name T139
Test name
Test status
Simulation time 103770012565 ps
CPU time 1001.03 seconds
Started Jun 04 12:48:47 PM PDT 24
Finished Jun 04 01:05:28 PM PDT 24
Peak memory 273448 kb
Host smart-06f8cd03-de95-4c52-bbae-37be185589e9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555732190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.555732190
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2334853833
Short name T732
Test name
Test status
Simulation time 42643436 ps
CPU time 5.13 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:48:47 PM PDT 24
Peak memory 248712 kb
Host smart-22266455-349b-4790-ab6a-eb6f0f89e578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2334853833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2334853833
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3851161325
Short name T781
Test name
Test status
Simulation time 575584270 ps
CPU time 7.51 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:48:58 PM PDT 24
Peak memory 240200 kb
Host smart-d75335b0-e276-4232-8942-45607ebba855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851161325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3851161325
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3475916348
Short name T185
Test name
Test status
Simulation time 96636969 ps
CPU time 3.45 seconds
Started Jun 04 12:48:42 PM PDT 24
Finished Jun 04 12:48:46 PM PDT 24
Peak memory 236824 kb
Host smart-a097ec6b-48b6-4e16-be2c-58406018ad46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3475916348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3475916348
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2117086061
Short name T729
Test name
Test status
Simulation time 8048377 ps
CPU time 1.54 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 236816 kb
Host smart-2cf2d2da-ebb8-4b8a-9a89-7ea2c135e4dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2117086061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2117086061
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1388512179
Short name T737
Test name
Test status
Simulation time 88307731 ps
CPU time 11.06 seconds
Started Jun 04 12:48:49 PM PDT 24
Finished Jun 04 12:49:00 PM PDT 24
Peak memory 244160 kb
Host smart-3c2c4e44-ef34-44e9-97e5-038994b6d8d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1388512179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1388512179
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.141486770
Short name T152
Test name
Test status
Simulation time 32485068648 ps
CPU time 154.31 seconds
Started Jun 04 12:48:46 PM PDT 24
Finished Jun 04 12:51:21 PM PDT 24
Peak memory 265384 kb
Host smart-15556370-567b-4639-abd7-40f64d5d6cf4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=141486770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.141486770
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3619576151
Short name T126
Test name
Test status
Simulation time 2730336176 ps
CPU time 303.29 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:53:55 PM PDT 24
Peak memory 265224 kb
Host smart-1a881dec-cef9-4d97-a8c0-f65c24a8c9a3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619576151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3619576151
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1562829458
Short name T713
Test name
Test status
Simulation time 842410403 ps
CPU time 12.5 seconds
Started Jun 04 12:48:48 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 247780 kb
Host smart-4dff5c22-c79e-4f32-987e-aa7f25ba3eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1562829458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1562829458
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3735859051
Short name T815
Test name
Test status
Simulation time 136363809 ps
CPU time 4.99 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 238780 kb
Host smart-9309497c-b83d-46cb-a467-a340545762b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735859051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3735859051
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1814242887
Short name T750
Test name
Test status
Simulation time 36141638 ps
CPU time 5.24 seconds
Started Jun 04 12:48:42 PM PDT 24
Finished Jun 04 12:48:48 PM PDT 24
Peak memory 236844 kb
Host smart-8035fb4d-32f7-4104-baa3-56d1dbe5bf6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1814242887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1814242887
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.703442818
Short name T330
Test name
Test status
Simulation time 11556938 ps
CPU time 1.31 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:48:44 PM PDT 24
Peak memory 235960 kb
Host smart-027531f4-c68c-4001-8a15-ab65e88ac800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=703442818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.703442818
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.881796780
Short name T186
Test name
Test status
Simulation time 1351433524 ps
CPU time 18.39 seconds
Started Jun 04 12:48:41 PM PDT 24
Finished Jun 04 12:49:01 PM PDT 24
Peak memory 245124 kb
Host smart-9edf760e-b3e0-4cec-8984-6de9ff01c1bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=881796780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.881796780
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3181810892
Short name T147
Test name
Test status
Simulation time 5274219976 ps
CPU time 189.87 seconds
Started Jun 04 12:48:48 PM PDT 24
Finished Jun 04 12:51:58 PM PDT 24
Peak memory 265276 kb
Host smart-7f67e863-79f5-4089-b2b1-fce7f04cc83f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3181810892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3181810892
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1077748714
Short name T154
Test name
Test status
Simulation time 12443681215 ps
CPU time 470.1 seconds
Started Jun 04 12:48:44 PM PDT 24
Finished Jun 04 12:56:35 PM PDT 24
Peak memory 265480 kb
Host smart-7900a7b9-264a-40d8-ac4f-8772e6b31253
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077748714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1077748714
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3044518259
Short name T731
Test name
Test status
Simulation time 192106431 ps
CPU time 14.61 seconds
Started Jun 04 12:48:50 PM PDT 24
Finished Jun 04 12:49:05 PM PDT 24
Peak memory 248604 kb
Host smart-e06fcbb3-d5dc-40a2-acca-d13904dce507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044518259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3044518259
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3600941423
Short name T334
Test name
Test status
Simulation time 127510734 ps
CPU time 4.96 seconds
Started Jun 04 12:48:54 PM PDT 24
Finished Jun 04 12:49:00 PM PDT 24
Peak memory 256516 kb
Host smart-c278ea18-18fe-4d50-bebd-dae351819e31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600941423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3600941423
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1143416356
Short name T774
Test name
Test status
Simulation time 266889006 ps
CPU time 4.93 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 236772 kb
Host smart-d52a96ec-0b30-4952-a8f3-dea606f07dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1143416356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1143416356
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2263436415
Short name T742
Test name
Test status
Simulation time 10352245 ps
CPU time 1.35 seconds
Started Jun 04 12:48:55 PM PDT 24
Finished Jun 04 12:48:57 PM PDT 24
Peak memory 235844 kb
Host smart-531c59d5-0ef9-4c53-aff0-cd0a85f630db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2263436415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2263436415
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1217548099
Short name T771
Test name
Test status
Simulation time 481295209 ps
CPU time 23.46 seconds
Started Jun 04 12:48:51 PM PDT 24
Finished Jun 04 12:49:16 PM PDT 24
Peak memory 245096 kb
Host smart-48d193a4-0a8b-40a7-9c37-fb79d3e6af68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1217548099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1217548099
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2933343876
Short name T137
Test name
Test status
Simulation time 1428941867 ps
CPU time 75.28 seconds
Started Jun 04 12:48:59 PM PDT 24
Finished Jun 04 12:50:15 PM PDT 24
Peak memory 257012 kb
Host smart-965832ab-0bc1-4550-a199-b9a8f042a835
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2933343876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2933343876
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4050303949
Short name T146
Test name
Test status
Simulation time 6232489163 ps
CPU time 453.97 seconds
Started Jun 04 12:48:47 PM PDT 24
Finished Jun 04 12:56:22 PM PDT 24
Peak memory 265288 kb
Host smart-f4beab79-007d-4caf-823b-c7eb7091b7c6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050303949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4050303949
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.578092735
Short name T717
Test name
Test status
Simulation time 156697521 ps
CPU time 10.68 seconds
Started Jun 04 12:48:44 PM PDT 24
Finished Jun 04 12:48:55 PM PDT 24
Peak memory 248736 kb
Host smart-5a63f313-1e8a-41e6-b974-3487a8294b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=578092735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.578092735
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2901849089
Short name T212
Test name
Test status
Simulation time 14060757 ps
CPU time 2.49 seconds
Started Jun 04 12:59:56 PM PDT 24
Finished Jun 04 12:59:58 PM PDT 24
Peak memory 248904 kb
Host smart-43ea01f8-fb98-4aff-ad55-b3b47289f04e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2901849089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2901849089
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2554949261
Short name T495
Test name
Test status
Simulation time 18459707021 ps
CPU time 1044.41 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:17:06 PM PDT 24
Peak memory 265176 kb
Host smart-16aa641b-57cf-4211-9c01-6971331bfaa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554949261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2554949261
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1535741557
Short name T411
Test name
Test status
Simulation time 2069922339 ps
CPU time 15.68 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 01:00:01 PM PDT 24
Peak memory 248744 kb
Host smart-7c3e04be-88df-4bea-a890-209c2c95662c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1535741557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1535741557
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1736086046
Short name T348
Test name
Test status
Simulation time 857150901 ps
CPU time 39.65 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:00:21 PM PDT 24
Peak memory 248780 kb
Host smart-68e4a792-7b5c-4566-af23-86b897e43da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
86046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1736086046
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1057293336
Short name T508
Test name
Test status
Simulation time 3298111577 ps
CPU time 27.45 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:00:08 PM PDT 24
Peak memory 256300 kb
Host smart-8844edbb-abe3-417f-a1e9-02b6af50e6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10572
93336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1057293336
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1324723446
Short name T216
Test name
Test status
Simulation time 56068571854 ps
CPU time 2932.24 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:48:33 PM PDT 24
Peak memory 289260 kb
Host smart-2ceb3b38-2d82-4d52-b280-f259fe568a45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324723446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1324723446
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1282338055
Short name T77
Test name
Test status
Simulation time 42676140969 ps
CPU time 1565.37 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:25:46 PM PDT 24
Peak memory 288856 kb
Host smart-840e1d5c-ba2c-49e4-bf6e-4001a47a6d0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282338055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1282338055
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3727280478
Short name T286
Test name
Test status
Simulation time 3931042168 ps
CPU time 161.56 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 01:02:21 PM PDT 24
Peak memory 247080 kb
Host smart-51b1d8da-9b97-46d5-b2f2-a5f83fbc4934
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727280478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3727280478
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2020827629
Short name T379
Test name
Test status
Simulation time 149761369 ps
CPU time 3.94 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:44 PM PDT 24
Peak memory 248692 kb
Host smart-850d4ad0-84a2-445c-af81-8953ad535626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20208
27629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2020827629
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.294272466
Short name T89
Test name
Test status
Simulation time 4550196792 ps
CPU time 67.18 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 01:00:47 PM PDT 24
Peak memory 256660 kb
Host smart-ff4d0c03-a240-45cd-bd98-d675f97a57d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29427
2466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.294272466
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3379363363
Short name T106
Test name
Test status
Simulation time 1252219470 ps
CPU time 70.72 seconds
Started Jun 04 12:59:57 PM PDT 24
Finished Jun 04 01:01:09 PM PDT 24
Peak memory 254816 kb
Host smart-cfdd2a66-a256-49bb-bad3-6992bf2ccfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33793
63363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3379363363
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3672291376
Short name T374
Test name
Test status
Simulation time 618703279 ps
CPU time 21.8 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 01:00:06 PM PDT 24
Peak memory 256100 kb
Host smart-e4bc9e88-f1a3-4d65-8670-f6778aff92fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36722
91376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3672291376
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3464442590
Short name T706
Test name
Test status
Simulation time 24847261008 ps
CPU time 1631.59 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:26:53 PM PDT 24
Peak memory 304316 kb
Host smart-45e886bb-4967-4243-972f-42e245548257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464442590 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3464442590
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.4259671834
Short name T205
Test name
Test status
Simulation time 86367950 ps
CPU time 3.62 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:45 PM PDT 24
Peak memory 248924 kb
Host smart-ca19c048-7539-4d88-8be0-246a42187038
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4259671834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.4259671834
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1411419718
Short name T63
Test name
Test status
Simulation time 116426871442 ps
CPU time 1485.47 seconds
Started Jun 04 12:59:55 PM PDT 24
Finished Jun 04 01:24:41 PM PDT 24
Peak memory 268308 kb
Host smart-5422d776-67d6-4291-ade2-bc38376ef01b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411419718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1411419718
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2375175777
Short name T586
Test name
Test status
Simulation time 997366787 ps
CPU time 22.41 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 01:00:02 PM PDT 24
Peak memory 248672 kb
Host smart-292be3da-9c5d-4fe9-8613-2b4ba1d15faf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2375175777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2375175777
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.868968574
Short name T468
Test name
Test status
Simulation time 31156876507 ps
CPU time 113.15 seconds
Started Jun 04 12:59:53 PM PDT 24
Finished Jun 04 01:01:47 PM PDT 24
Peak memory 248684 kb
Host smart-f0b5e099-bf8f-4b0e-9656-ce1aad438f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86896
8574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.868968574
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3833154191
Short name T354
Test name
Test status
Simulation time 1480689973 ps
CPU time 15.21 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:56 PM PDT 24
Peak memory 248696 kb
Host smart-de9c9a44-cf27-408a-b4ec-5293cf3487fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38331
54191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3833154191
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3223152547
Short name T307
Test name
Test status
Simulation time 17315266651 ps
CPU time 924.34 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:15:05 PM PDT 24
Peak memory 265244 kb
Host smart-ca809e56-054d-4274-9d14-5e17b204b51d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223152547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3223152547
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1728290442
Short name T51
Test name
Test status
Simulation time 478394470 ps
CPU time 10.27 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:51 PM PDT 24
Peak memory 252992 kb
Host smart-ea1c2885-c75c-41ac-b8d2-517f00670e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17282
90442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1728290442
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3267329996
Short name T639
Test name
Test status
Simulation time 834466384 ps
CPU time 23.37 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:00:04 PM PDT 24
Peak memory 256244 kb
Host smart-99a55f3d-fef6-42ac-b1f4-5f2ca9470b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673
29996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3267329996
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2735444877
Short name T11
Test name
Test status
Simulation time 285679001 ps
CPU time 12.67 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:10 PM PDT 24
Peak memory 277576 kb
Host smart-95075796-634e-4c44-912f-643c101edcae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2735444877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2735444877
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3872909799
Short name T503
Test name
Test status
Simulation time 845159509 ps
CPU time 31.65 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:00:13 PM PDT 24
Peak memory 248716 kb
Host smart-ed47029a-3934-4d6b-8785-8833f7e7ff56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38729
09799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3872909799
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1574141236
Short name T54
Test name
Test status
Simulation time 57062972385 ps
CPU time 1559.93 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:25:40 PM PDT 24
Peak memory 297844 kb
Host smart-2093b0e2-9db7-4fab-9bbb-8bc428697206
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574141236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1574141236
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3274898961
Short name T502
Test name
Test status
Simulation time 41478917750 ps
CPU time 1000.48 seconds
Started Jun 04 12:59:54 PM PDT 24
Finished Jun 04 01:16:35 PM PDT 24
Peak memory 289100 kb
Host smart-d1e3e9cb-6117-4acc-9443-56522e412d5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274898961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3274898961
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2483534113
Short name T370
Test name
Test status
Simulation time 250324055 ps
CPU time 8.35 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:02 PM PDT 24
Peak memory 248744 kb
Host smart-fa539617-093d-404d-965c-06d822e00595
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2483534113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2483534113
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4100293789
Short name T491
Test name
Test status
Simulation time 572115377 ps
CPU time 30.07 seconds
Started Jun 04 12:59:55 PM PDT 24
Finished Jun 04 01:00:25 PM PDT 24
Peak memory 248716 kb
Host smart-5ea5217c-cf8a-46b9-9e60-848459f720ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41002
93789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4100293789
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2324225476
Short name T358
Test name
Test status
Simulation time 3752348766 ps
CPU time 56.91 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:01:08 PM PDT 24
Peak memory 256896 kb
Host smart-8fb74b63-16ae-482b-85a0-b85d465a756e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23242
25476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2324225476
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.927536831
Short name T277
Test name
Test status
Simulation time 68722127087 ps
CPU time 2126.38 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:35:30 PM PDT 24
Peak memory 272748 kb
Host smart-7b9d5598-4dec-4ef8-a0e6-a5d621fe7546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927536831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.927536831
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3680695057
Short name T501
Test name
Test status
Simulation time 44236473437 ps
CPU time 2432.56 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:40:53 PM PDT 24
Peak memory 289588 kb
Host smart-f793411d-7cae-4e90-8219-caf1e120170c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680695057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3680695057
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3731017828
Short name T310
Test name
Test status
Simulation time 13528511611 ps
CPU time 555.07 seconds
Started Jun 04 12:59:50 PM PDT 24
Finished Jun 04 01:09:06 PM PDT 24
Peak memory 254668 kb
Host smart-043f884f-6eda-4015-b85d-f8dbf06d5c5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731017828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3731017828
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1989062763
Short name T362
Test name
Test status
Simulation time 854484006 ps
CPU time 51.22 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:44 PM PDT 24
Peak memory 248712 kb
Host smart-c4c63c17-8ee2-4d7e-ab9d-c214e18afae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19890
62763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1989062763
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2877139796
Short name T523
Test name
Test status
Simulation time 40627206 ps
CPU time 5.59 seconds
Started Jun 04 12:59:53 PM PDT 24
Finished Jun 04 12:59:59 PM PDT 24
Peak memory 248816 kb
Host smart-6823e78c-fd0e-4d8e-9842-9617c5457d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28771
39796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2877139796
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2938328046
Short name T422
Test name
Test status
Simulation time 1453704331 ps
CPU time 48.68 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 01:00:51 PM PDT 24
Peak memory 249404 kb
Host smart-72f4138e-2d6d-43c9-8b53-ce64f51825ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29383
28046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2938328046
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2093785257
Short name T429
Test name
Test status
Simulation time 164124045 ps
CPU time 9.57 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:00:19 PM PDT 24
Peak memory 248620 kb
Host smart-024e4dcc-6071-4b0b-b4b3-0dad28ac0f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
85257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2093785257
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1301419871
Short name T208
Test name
Test status
Simulation time 176285690 ps
CPU time 3.85 seconds
Started Jun 04 12:59:54 PM PDT 24
Finished Jun 04 12:59:59 PM PDT 24
Peak memory 249084 kb
Host smart-f276b95c-418f-43ee-8841-a810d9b0c4cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1301419871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1301419871
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3749158156
Short name T71
Test name
Test status
Simulation time 88853144081 ps
CPU time 2592.37 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:43:05 PM PDT 24
Peak memory 281588 kb
Host smart-2be35cd2-255f-4577-bf25-d5b14ddd10e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749158156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3749158156
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.814993769
Short name T446
Test name
Test status
Simulation time 253867737 ps
CPU time 10.43 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:19 PM PDT 24
Peak memory 248744 kb
Host smart-eaef0932-b67c-43d3-9325-9778b0a446bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=814993769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.814993769
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.32674795
Short name T357
Test name
Test status
Simulation time 8202392370 ps
CPU time 189.81 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:03:17 PM PDT 24
Peak memory 257000 kb
Host smart-9b7651ad-d8df-4d26-80b9-27b2da55d398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32674
795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.32674795
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3507682710
Short name T688
Test name
Test status
Simulation time 328748603 ps
CPU time 23.52 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:00:34 PM PDT 24
Peak memory 255520 kb
Host smart-4064f1da-494e-4927-ac03-7210e76de2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35076
82710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3507682710
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.220599323
Short name T451
Test name
Test status
Simulation time 63368641286 ps
CPU time 1429.31 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:24:00 PM PDT 24
Peak memory 285276 kb
Host smart-dc3d93ca-2de1-44f2-a289-81a2d3d53ae4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220599323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.220599323
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3423634289
Short name T309
Test name
Test status
Simulation time 11506692426 ps
CPU time 88.87 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 248144 kb
Host smart-0892578e-8877-4101-9e88-602cba2e16d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423634289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3423634289
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4094368227
Short name T74
Test name
Test status
Simulation time 1072997225 ps
CPU time 59.2 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 01:01:02 PM PDT 24
Peak memory 248600 kb
Host smart-a8364f0a-0cf1-4deb-a0af-8663866f6869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40943
68227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4094368227
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1684598016
Short name T689
Test name
Test status
Simulation time 483567613 ps
CPU time 30.96 seconds
Started Jun 04 12:59:51 PM PDT 24
Finished Jun 04 01:00:22 PM PDT 24
Peak memory 247784 kb
Host smart-293c433c-e279-4d02-9bed-d4e668603bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
98016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1684598016
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2580336088
Short name T103
Test name
Test status
Simulation time 585038892 ps
CPU time 10.97 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:00:23 PM PDT 24
Peak memory 251796 kb
Host smart-a5e87b76-7320-4ae9-b5a0-62358526006b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25803
36088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2580336088
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2544627808
Short name T472
Test name
Test status
Simulation time 58194484 ps
CPU time 4.26 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:00:15 PM PDT 24
Peak memory 240484 kb
Host smart-7f03c4e4-c25f-402b-9e84-bc9829043a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
27808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2544627808
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.503515970
Short name T479
Test name
Test status
Simulation time 16697702120 ps
CPU time 1706.1 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:28:37 PM PDT 24
Peak memory 289440 kb
Host smart-19d65e74-a4e7-43d7-b56a-c6eb0ac96107
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503515970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.503515970
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2996682928
Short name T197
Test name
Test status
Simulation time 222614712 ps
CPU time 3.55 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:10 PM PDT 24
Peak memory 248776 kb
Host smart-f67b6da1-add0-4904-a4c2-d8e0c49279a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2996682928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2996682928
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.577597612
Short name T647
Test name
Test status
Simulation time 138335162423 ps
CPU time 2206.11 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:37:01 PM PDT 24
Peak memory 273400 kb
Host smart-b6a8748b-e7e0-4afa-8b9e-5f2292f82f37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577597612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.577597612
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1367129008
Short name T542
Test name
Test status
Simulation time 868821803 ps
CPU time 36.72 seconds
Started Jun 04 12:59:59 PM PDT 24
Finished Jun 04 01:00:36 PM PDT 24
Peak memory 248792 kb
Host smart-c4b68fad-3e57-40f6-9ae5-3acaf80b28c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1367129008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1367129008
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3409389267
Short name T452
Test name
Test status
Simulation time 2057962024 ps
CPU time 81.79 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:01:15 PM PDT 24
Peak memory 256920 kb
Host smart-18646d21-39bf-4618-ba1c-49b729b9e744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34093
89267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3409389267
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1791711410
Short name T600
Test name
Test status
Simulation time 326325710 ps
CPU time 18.33 seconds
Started Jun 04 01:00:14 PM PDT 24
Finished Jun 04 01:00:33 PM PDT 24
Peak memory 248612 kb
Host smart-363c3821-d9cc-414e-a99f-b514453045b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
11410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1791711410
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2985478522
Short name T280
Test name
Test status
Simulation time 126745307818 ps
CPU time 1778.42 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:29:48 PM PDT 24
Peak memory 273320 kb
Host smart-38dfd907-6340-4b4d-9fee-8d41ae9c842f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985478522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2985478522
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3420553117
Short name T437
Test name
Test status
Simulation time 29938511965 ps
CPU time 1516.12 seconds
Started Jun 04 12:59:51 PM PDT 24
Finished Jun 04 01:25:08 PM PDT 24
Peak memory 286660 kb
Host smart-d422b43f-d006-411f-9a1f-964bbc80fd12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420553117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3420553117
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2678694679
Short name T700
Test name
Test status
Simulation time 84030819392 ps
CPU time 407.51 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:06:50 PM PDT 24
Peak memory 247028 kb
Host smart-594dad3b-0f3e-4c0c-a56c-9e004b002ba9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678694679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2678694679
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.731208656
Short name T630
Test name
Test status
Simulation time 4440671513 ps
CPU time 58.66 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:01:20 PM PDT 24
Peak memory 248808 kb
Host smart-47a41687-dff0-4a90-97d8-d2c378819da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73120
8656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.731208656
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1990716586
Short name T564
Test name
Test status
Simulation time 589479086 ps
CPU time 28.8 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:35 PM PDT 24
Peak memory 248740 kb
Host smart-16ba7366-234f-4455-8840-c7cc73d80ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
16586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1990716586
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1009996039
Short name T36
Test name
Test status
Simulation time 386925123 ps
CPU time 9.11 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:01 PM PDT 24
Peak memory 250884 kb
Host smart-00bc851b-e7fb-402f-be48-c43f81d53064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10099
96039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1009996039
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3453226905
Short name T217
Test name
Test status
Simulation time 530714216 ps
CPU time 17.64 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:31 PM PDT 24
Peak memory 248728 kb
Host smart-15d64431-5b09-47ab-818c-273b25c1b632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
26905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3453226905
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2083783696
Short name T58
Test name
Test status
Simulation time 100048933598 ps
CPU time 2708.65 seconds
Started Jun 04 12:59:55 PM PDT 24
Finished Jun 04 01:45:05 PM PDT 24
Peak memory 289644 kb
Host smart-0c3594d2-0dda-4051-99fb-2806d7b78850
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083783696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2083783696
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1577536520
Short name T225
Test name
Test status
Simulation time 65614879196 ps
CPU time 1340.01 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:22:32 PM PDT 24
Peak memory 289568 kb
Host smart-b127d641-76d6-4ea7-ade0-aff4310852cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577536520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1577536520
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3465768409
Short name T120
Test name
Test status
Simulation time 148077745 ps
CPU time 8.71 seconds
Started Jun 04 12:59:59 PM PDT 24
Finished Jun 04 01:00:08 PM PDT 24
Peak memory 240588 kb
Host smart-22984236-de18-42c2-bdef-378a08fe2194
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3465768409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3465768409
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2551012405
Short name T399
Test name
Test status
Simulation time 1528118205 ps
CPU time 28.83 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:00:38 PM PDT 24
Peak memory 248728 kb
Host smart-65b9af44-63d7-4dd0-986d-6dc8f8c395d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25510
12405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2551012405
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.384552969
Short name T64
Test name
Test status
Simulation time 379307324 ps
CPU time 21.61 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:15 PM PDT 24
Peak memory 254680 kb
Host smart-b3793cb5-fe40-4667-ba02-e021d1eddfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38455
2969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.384552969
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2208900969
Short name T571
Test name
Test status
Simulation time 54893439532 ps
CPU time 2135.37 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:35:52 PM PDT 24
Peak memory 284032 kb
Host smart-9ffd867a-2ef8-4f41-91a5-9c9859e08e6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208900969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2208900969
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1731366879
Short name T462
Test name
Test status
Simulation time 36114525925 ps
CPU time 1929.67 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:32:23 PM PDT 24
Peak memory 270688 kb
Host smart-74dc2783-f543-4c18-8146-9dd275263bc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731366879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1731366879
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3691809902
Short name T592
Test name
Test status
Simulation time 9962153349 ps
CPU time 382.72 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:06:33 PM PDT 24
Peak memory 246980 kb
Host smart-d32634d2-5bf6-4b87-a136-b6139f28a8b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691809902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3691809902
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1466492615
Short name T66
Test name
Test status
Simulation time 1277008452 ps
CPU time 11.01 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:00:22 PM PDT 24
Peak memory 248692 kb
Host smart-33035c42-965c-4e01-a136-2c4aa5592b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14664
92615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1466492615
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2800680373
Short name T183
Test name
Test status
Simulation time 138236524 ps
CPU time 6.87 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:00:18 PM PDT 24
Peak memory 248688 kb
Host smart-f0dd4404-ce7d-4d37-bceb-0f201a3b0626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28006
80373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2800680373
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1104882842
Short name T60
Test name
Test status
Simulation time 123366602 ps
CPU time 9.97 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:00:21 PM PDT 24
Peak memory 252244 kb
Host smart-6faa3472-66c7-4fa7-a726-c7b0a07335ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11048
82842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1104882842
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1903819298
Short name T420
Test name
Test status
Simulation time 201810039 ps
CPU time 17.41 seconds
Started Jun 04 12:59:51 PM PDT 24
Finished Jun 04 01:00:09 PM PDT 24
Peak memory 248696 kb
Host smart-d676c94e-6cd0-48a1-ae41-26857983cab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
19298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1903819298
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3625835948
Short name T29
Test name
Test status
Simulation time 13312618469 ps
CPU time 1267.98 seconds
Started Jun 04 12:59:53 PM PDT 24
Finished Jun 04 01:21:02 PM PDT 24
Peak memory 289404 kb
Host smart-7171f977-616b-4028-add1-8aaa9d996952
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625835948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3625835948
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2797559715
Short name T98
Test name
Test status
Simulation time 50869483048 ps
CPU time 884.01 seconds
Started Jun 04 12:59:53 PM PDT 24
Finished Jun 04 01:14:38 PM PDT 24
Peak memory 273456 kb
Host smart-e0590153-fc88-49ab-856f-8b6163080a05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797559715 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2797559715
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.935164891
Short name T203
Test name
Test status
Simulation time 174996840 ps
CPU time 2.4 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:07 PM PDT 24
Peak memory 248864 kb
Host smart-e63812b3-815e-4321-bdb7-909e0f636fd4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=935164891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.935164891
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1951040380
Short name T409
Test name
Test status
Simulation time 291972860 ps
CPU time 16.13 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:23 PM PDT 24
Peak memory 248744 kb
Host smart-1333a694-3ef3-4b6f-889d-24bd951ce512
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1951040380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1951040380
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2088794804
Short name T221
Test name
Test status
Simulation time 4995917339 ps
CPU time 231.47 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:03:59 PM PDT 24
Peak memory 256872 kb
Host smart-813cc9fe-179e-47d3-97eb-9f1557713554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20887
94804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2088794804
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2944159064
Short name T505
Test name
Test status
Simulation time 727635712 ps
CPU time 43.09 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:56 PM PDT 24
Peak memory 249216 kb
Host smart-e048eca2-e84d-40e1-8777-bae5ddf601d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29441
59064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2944159064
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2896244405
Short name T497
Test name
Test status
Simulation time 143548406644 ps
CPU time 1912.1 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:32:21 PM PDT 24
Peak memory 273428 kb
Host smart-0f9107c5-3895-4ce0-ad6a-5a2a2d47354e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896244405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2896244405
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3556633078
Short name T303
Test name
Test status
Simulation time 46070514336 ps
CPU time 423.95 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:07:35 PM PDT 24
Peak memory 247208 kb
Host smart-8f44059e-a150-4dca-8297-fe7000b557c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556633078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3556633078
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3986681812
Short name T641
Test name
Test status
Simulation time 1275523627 ps
CPU time 20.26 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:00:50 PM PDT 24
Peak memory 248828 kb
Host smart-3b27f178-6701-47eb-acf8-970bfc4a9a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39866
81812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3986681812
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.594660621
Short name T636
Test name
Test status
Simulation time 3768161737 ps
CPU time 20.31 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:28 PM PDT 24
Peak memory 255684 kb
Host smart-f7aa50e4-96e0-4f91-95c5-546cd771de99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59466
0621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.594660621
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4157252687
Short name T653
Test name
Test status
Simulation time 307905100 ps
CPU time 18.04 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:00:32 PM PDT 24
Peak memory 248872 kb
Host smart-5e43aa19-2c61-43c4-92f3-527ef9db5cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41572
52687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4157252687
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.505118043
Short name T192
Test name
Test status
Simulation time 2315000409 ps
CPU time 18.63 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:00:35 PM PDT 24
Peak memory 248712 kb
Host smart-141a7963-ee0d-41c2-8c41-1183eb23b182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50511
8043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.505118043
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.598653978
Short name T574
Test name
Test status
Simulation time 2762912586 ps
CPU time 88.12 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:01:35 PM PDT 24
Peak memory 256604 kb
Host smart-c2c1b2b5-b882-49db-aabe-c58d0370d616
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598653978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.598653978
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.118985226
Short name T210
Test name
Test status
Simulation time 143057794 ps
CPU time 3.69 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 01:00:06 PM PDT 24
Peak memory 248884 kb
Host smart-b0fee145-08dd-41e4-8e5f-8bbe9e30ec49
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=118985226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.118985226
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3183958958
Short name T698
Test name
Test status
Simulation time 61497168970 ps
CPU time 1365.2 seconds
Started Jun 04 01:00:21 PM PDT 24
Finished Jun 04 01:23:07 PM PDT 24
Peak memory 281436 kb
Host smart-74cf54fe-8fce-4faf-8513-11c720966724
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183958958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3183958958
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1764401294
Short name T364
Test name
Test status
Simulation time 334369033 ps
CPU time 10.6 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:15 PM PDT 24
Peak memory 248684 kb
Host smart-4e34a476-3160-4d52-bbe7-a8f28003f13f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1764401294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1764401294
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3462432273
Short name T705
Test name
Test status
Simulation time 1943995779 ps
CPU time 114.05 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:01:59 PM PDT 24
Peak memory 256848 kb
Host smart-90dd4cad-e4a2-4be4-815c-4400155c19b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
32273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3462432273
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3725934495
Short name T245
Test name
Test status
Simulation time 2131355816 ps
CPU time 44.23 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 01:00:46 PM PDT 24
Peak memory 256040 kb
Host smart-297b83df-5913-4d11-b4b6-fe444530bc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37259
34495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3725934495
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.376360354
Short name T224
Test name
Test status
Simulation time 50512265913 ps
CPU time 2725.12 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:45:56 PM PDT 24
Peak memory 288852 kb
Host smart-5f448a19-a38c-408e-a7c0-7b067963e65d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376360354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.376360354
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2150878104
Short name T294
Test name
Test status
Simulation time 6876510839 ps
CPU time 259.16 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:04:23 PM PDT 24
Peak memory 248044 kb
Host smart-dfe21be8-8fa5-43b7-aacd-b51bdb3ac759
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150878104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2150878104
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3918614648
Short name T405
Test name
Test status
Simulation time 818722381 ps
CPU time 49.11 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:00:52 PM PDT 24
Peak memory 256888 kb
Host smart-851e61cc-db06-4154-89d2-90f1480c1b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39186
14648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3918614648
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.442698924
Short name T257
Test name
Test status
Simulation time 3042116182 ps
CPU time 73.03 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:01:34 PM PDT 24
Peak memory 255220 kb
Host smart-42d0aacd-a1aa-486c-a8a2-1e22751ba165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44269
8924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.442698924
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3603639195
Short name T402
Test name
Test status
Simulation time 3586017498 ps
CPU time 53.86 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:01:10 PM PDT 24
Peak memory 256944 kb
Host smart-b575ad76-d2db-42fc-b931-a0edaa704b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36036
39195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3603639195
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2555212745
Short name T514
Test name
Test status
Simulation time 17612589 ps
CPU time 3.35 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:07 PM PDT 24
Peak memory 240508 kb
Host smart-fe3510d4-2d98-4f8b-b2ba-7f4857670b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552
12745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2555212745
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.55605614
Short name T534
Test name
Test status
Simulation time 72037758166 ps
CPU time 1454.95 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:24:21 PM PDT 24
Peak memory 289256 kb
Host smart-2b6d5d80-3bac-4d4e-9543-dd30367c2767
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55605614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_hand
ler_stress_all.55605614
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4235362878
Short name T200
Test name
Test status
Simulation time 36771706 ps
CPU time 2.45 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:00:06 PM PDT 24
Peak memory 248900 kb
Host smart-4acf3063-9bcd-40e4-8910-d3b34947bff7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4235362878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4235362878
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2347524226
Short name T46
Test name
Test status
Simulation time 28718535198 ps
CPU time 1834.94 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:31:09 PM PDT 24
Peak memory 284156 kb
Host smart-d357fc9d-1afd-4b55-ae8d-ec63fb7a3191
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347524226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2347524226
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.495718683
Short name T635
Test name
Test status
Simulation time 1419809064 ps
CPU time 19.41 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:00:40 PM PDT 24
Peak memory 240528 kb
Host smart-ab569910-d514-4e37-a16a-2344000b83d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=495718683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.495718683
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1333130128
Short name T65
Test name
Test status
Simulation time 2317240122 ps
CPU time 127.85 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:02:28 PM PDT 24
Peak memory 256972 kb
Host smart-4b6beed9-657c-4329-9667-8bf7ebde8b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13331
30128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1333130128
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2195828964
Short name T461
Test name
Test status
Simulation time 421300886 ps
CPU time 6.56 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:13 PM PDT 24
Peak memory 248696 kb
Host smart-94195491-ab4b-4e1a-a6be-c36a7826500c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21958
28964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2195828964
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3207685919
Short name T327
Test name
Test status
Simulation time 405822270877 ps
CPU time 1788.88 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:30:15 PM PDT 24
Peak memory 271420 kb
Host smart-157345b0-ebe4-411b-8980-e0c3026278f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207685919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3207685919
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1770416817
Short name T603
Test name
Test status
Simulation time 53357848813 ps
CPU time 1441.56 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:24:22 PM PDT 24
Peak memory 273400 kb
Host smart-6a9e9bdb-1789-4292-a210-8f3ddb06c9fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770416817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1770416817
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.545109739
Short name T694
Test name
Test status
Simulation time 764346800 ps
CPU time 12.5 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:17 PM PDT 24
Peak memory 254268 kb
Host smart-71cec1df-7257-43fb-92a9-8558201b33a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54510
9739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.545109739
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1221299652
Short name T671
Test name
Test status
Simulation time 331009430 ps
CPU time 23.67 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:00:44 PM PDT 24
Peak memory 255304 kb
Host smart-a65174cb-6709-465c-b242-b500d3b9e0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12212
99652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1221299652
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3738303435
Short name T271
Test name
Test status
Simulation time 336686594 ps
CPU time 12.69 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:21 PM PDT 24
Peak memory 247420 kb
Host smart-cb3386de-a882-4e46-86bc-7d3bbd9db859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37383
03435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3738303435
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.222726090
Short name T665
Test name
Test status
Simulation time 1900878104 ps
CPU time 30.21 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:00:51 PM PDT 24
Peak memory 248692 kb
Host smart-1f418f80-e99a-4ff9-bdd1-f28c67ca6ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272
6090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.222726090
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2605207897
Short name T86
Test name
Test status
Simulation time 149180984492 ps
CPU time 4260.85 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 02:11:05 PM PDT 24
Peak memory 305264 kb
Host smart-0fa0c971-9749-49d8-84da-bd7211e8a6cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605207897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2605207897
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1244087636
Short name T96
Test name
Test status
Simulation time 404002235599 ps
CPU time 7259.8 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 03:01:25 PM PDT 24
Peak memory 338456 kb
Host smart-1399657e-0163-4790-95b7-3667eeca8500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244087636 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1244087636
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3177649150
Short name T211
Test name
Test status
Simulation time 101752059 ps
CPU time 3.07 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:08 PM PDT 24
Peak memory 248908 kb
Host smart-73331471-f924-4dfa-916c-e921245d6ae6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3177649150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3177649150
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2563162497
Short name T621
Test name
Test status
Simulation time 814609320 ps
CPU time 35.28 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:00:41 PM PDT 24
Peak memory 248716 kb
Host smart-f2057564-e010-4dcc-849f-9b7a64a1194c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2563162497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2563162497
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.844043336
Short name T533
Test name
Test status
Simulation time 3391654236 ps
CPU time 203.43 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:03:41 PM PDT 24
Peak memory 256980 kb
Host smart-e5d4af90-de10-451f-91f1-de160e2b472f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84404
3336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.844043336
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3910406957
Short name T73
Test name
Test status
Simulation time 1999184388 ps
CPU time 33.29 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:00:58 PM PDT 24
Peak memory 255924 kb
Host smart-c78bde35-4fa3-4d2f-b0a4-a2eb19a0b1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39104
06957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3910406957
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2152930217
Short name T326
Test name
Test status
Simulation time 38848484927 ps
CPU time 1118.56 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:18:44 PM PDT 24
Peak memory 265184 kb
Host smart-abf2fd18-6266-4406-8927-c89dd60c77a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152930217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2152930217
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3179532054
Short name T404
Test name
Test status
Simulation time 151568121291 ps
CPU time 1493.03 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:25:14 PM PDT 24
Peak memory 289452 kb
Host smart-8129bbc0-1939-4a77-9ae4-d26eb68a56b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179532054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3179532054
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1358663721
Short name T336
Test name
Test status
Simulation time 2037613384 ps
CPU time 26.83 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:00:47 PM PDT 24
Peak memory 248748 kb
Host smart-deb8fc87-d06b-4b17-84f8-405d4a50dbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13586
63721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1358663721
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3148817419
Short name T557
Test name
Test status
Simulation time 5858950077 ps
CPU time 48.04 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:55 PM PDT 24
Peak memory 254788 kb
Host smart-f0b908d2-fa7c-4adc-bcfd-05fa59521c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31488
17419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3148817419
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2815777153
Short name T337
Test name
Test status
Simulation time 420408883 ps
CPU time 18.13 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:00:40 PM PDT 24
Peak memory 248720 kb
Host smart-0b7984b8-9269-4d4e-91b5-d1956774bf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28157
77153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2815777153
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1006987693
Short name T634
Test name
Test status
Simulation time 47787464635 ps
CPU time 2795.1 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:46:42 PM PDT 24
Peak memory 288788 kb
Host smart-83541113-24f2-4d7d-8f05-f208a790fb52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006987693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1006987693
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1161447584
Short name T204
Test name
Test status
Simulation time 295955741 ps
CPU time 2.88 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:00:28 PM PDT 24
Peak memory 248568 kb
Host smart-32e5ffbc-3230-49ef-9678-bfa5e068c797
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1161447584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1161447584
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1579468960
Short name T536
Test name
Test status
Simulation time 129218118038 ps
CPU time 2090.2 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:35:07 PM PDT 24
Peak memory 289252 kb
Host smart-2bf69c21-bfb0-413a-b226-a88f5442ec61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579468960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1579468960
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.630844763
Short name T361
Test name
Test status
Simulation time 534444700 ps
CPU time 13.96 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:00:34 PM PDT 24
Peak memory 248696 kb
Host smart-599fee0c-4f98-48e7-8edb-c8cc50580661
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=630844763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.630844763
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2278192141
Short name T493
Test name
Test status
Simulation time 1333783718 ps
CPU time 118.06 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:02:05 PM PDT 24
Peak memory 249780 kb
Host smart-6f0ce4e7-fa40-4543-a833-23b31338fc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22781
92141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2278192141
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3670029066
Short name T490
Test name
Test status
Simulation time 1248239090 ps
CPU time 17.65 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:00:25 PM PDT 24
Peak memory 254100 kb
Host smart-ef4e5d36-9152-435a-9140-4773c29ec476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36700
29066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3670029066
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3829614112
Short name T6
Test name
Test status
Simulation time 34780610339 ps
CPU time 1547.1 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:26:13 PM PDT 24
Peak memory 264872 kb
Host smart-6c69558c-2fb4-4472-ab63-8dbaee3c5178
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829614112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3829614112
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3037620027
Short name T270
Test name
Test status
Simulation time 169521271397 ps
CPU time 2309.97 seconds
Started Jun 04 01:00:21 PM PDT 24
Finished Jun 04 01:38:52 PM PDT 24
Peak memory 289592 kb
Host smart-b134db06-c801-4cb5-af82-fd09d6830c18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037620027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3037620027
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1075846829
Short name T283
Test name
Test status
Simulation time 164928777313 ps
CPU time 373.24 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:06:31 PM PDT 24
Peak memory 247884 kb
Host smart-f01e8da6-5ed5-4c27-bf83-a71bbc610a5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075846829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1075846829
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1421387631
Short name T42
Test name
Test status
Simulation time 605950853 ps
CPU time 40.14 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:00:49 PM PDT 24
Peak memory 248756 kb
Host smart-77011ab0-2419-4eb4-a7c8-a3228560f17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14213
87631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1421387631
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2894805075
Short name T661
Test name
Test status
Simulation time 3562527521 ps
CPU time 57.72 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:01:14 PM PDT 24
Peak memory 255212 kb
Host smart-b886ed89-eb8c-46f6-ab5a-6b8012f77575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28948
05075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2894805075
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3112464936
Short name T576
Test name
Test status
Simulation time 228687998 ps
CPU time 9.22 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:16 PM PDT 24
Peak memory 253944 kb
Host smart-34b54288-b80d-4ffa-8ad2-cdd5abec047a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
64936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3112464936
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2611834062
Short name T578
Test name
Test status
Simulation time 365271463 ps
CPU time 27.09 seconds
Started Jun 04 01:00:14 PM PDT 24
Finished Jun 04 01:00:42 PM PDT 24
Peak memory 255900 kb
Host smart-a3d30989-c0e3-4e85-825f-aa8a99dad0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
34062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2611834062
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1297154574
Short name T608
Test name
Test status
Simulation time 7024580180 ps
CPU time 375.31 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 01:06:42 PM PDT 24
Peak memory 254964 kb
Host smart-6f989260-8b71-482d-945d-1e4ee20b31f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297154574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1297154574
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1611063582
Short name T209
Test name
Test status
Simulation time 39182562 ps
CPU time 3.35 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:00:29 PM PDT 24
Peak memory 248904 kb
Host smart-7462614e-8c46-491d-8252-26859feeb74f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1611063582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1611063582
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.211981305
Short name T430
Test name
Test status
Simulation time 42908147077 ps
CPU time 1154.12 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:19:20 PM PDT 24
Peak memory 284720 kb
Host smart-eb40d7a1-4980-4f1b-81e2-135ae306120e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211981305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.211981305
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.946011462
Short name T454
Test name
Test status
Simulation time 1593677010 ps
CPU time 19.81 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:33 PM PDT 24
Peak memory 248668 kb
Host smart-ebb60bfe-6fd1-4090-a727-54350430ca18
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=946011462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.946011462
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1842141583
Short name T235
Test name
Test status
Simulation time 2821044591 ps
CPU time 64.28 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:01:10 PM PDT 24
Peak memory 256756 kb
Host smart-701f5ca2-3614-4c9a-944f-91d1d6ea2f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18421
41583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1842141583
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2673694584
Short name T384
Test name
Test status
Simulation time 242877767 ps
CPU time 18.79 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:00:48 PM PDT 24
Peak memory 248648 kb
Host smart-28f64b29-6f04-4b97-9823-e92049e42de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26736
94584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2673694584
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4214601411
Short name T401
Test name
Test status
Simulation time 23546555377 ps
CPU time 1020.82 seconds
Started Jun 04 01:00:21 PM PDT 24
Finished Jun 04 01:17:23 PM PDT 24
Peak memory 288652 kb
Host smart-1c7d89ef-e0c0-443d-8309-07c90e972b1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214601411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4214601411
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.811892968
Short name T297
Test name
Test status
Simulation time 6618800339 ps
CPU time 265.69 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:04:35 PM PDT 24
Peak memory 248220 kb
Host smart-3f3d0cf6-5e2d-41ad-85e3-e71cf511c27b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811892968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.811892968
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3204454489
Short name T610
Test name
Test status
Simulation time 68367187 ps
CPU time 6.81 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:11 PM PDT 24
Peak memory 253952 kb
Host smart-4cfbb6c4-9929-46ff-b68c-78523936f24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32044
54489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3204454489
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.500461226
Short name T453
Test name
Test status
Simulation time 593137071 ps
CPU time 19.49 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:00:43 PM PDT 24
Peak memory 253584 kb
Host smart-b5175e73-7407-4922-a2ab-7e6fdf8173b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50046
1226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.500461226
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2015659688
Short name T435
Test name
Test status
Simulation time 2118897625 ps
CPU time 33.59 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:41 PM PDT 24
Peak memory 255196 kb
Host smart-22c0d117-c0f1-4ec7-a178-0c96d6bbf89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20156
59688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2015659688
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2280580723
Short name T351
Test name
Test status
Simulation time 256726899 ps
CPU time 23.82 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:32 PM PDT 24
Peak memory 248724 kb
Host smart-597be5ed-2ed9-45fa-b6a6-aa52faa5397c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22805
80723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2280580723
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1899323180
Short name T499
Test name
Test status
Simulation time 53900354944 ps
CPU time 1558.06 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:26:08 PM PDT 24
Peak memory 273416 kb
Host smart-67370c37-e665-42b5-a9a5-c59f4578d30c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899323180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1899323180
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1407437669
Short name T196
Test name
Test status
Simulation time 43996412 ps
CPU time 2.49 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 12:59:49 PM PDT 24
Peak memory 248876 kb
Host smart-2da836da-dc4d-4fee-bf00-a90b5064da93
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1407437669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1407437669
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.4165581035
Short name T113
Test name
Test status
Simulation time 52266633081 ps
CPU time 2987.79 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 01:49:33 PM PDT 24
Peak memory 289348 kb
Host smart-2506e6e3-75b1-4505-93e1-ac3e3f2f42ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165581035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.4165581035
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.117838809
Short name T686
Test name
Test status
Simulation time 819463308 ps
CPU time 34.42 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 01:00:13 PM PDT 24
Peak memory 240504 kb
Host smart-b28cb938-30e0-4e63-a225-4b221f2c4566
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=117838809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.117838809
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.449318012
Short name T577
Test name
Test status
Simulation time 290106483 ps
CPU time 12.79 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 12:59:58 PM PDT 24
Peak memory 255092 kb
Host smart-ac25c1eb-89d7-45f9-b26f-e838a6ec7a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44931
8012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.449318012
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.270929183
Short name T643
Test name
Test status
Simulation time 815830411 ps
CPU time 12.71 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:21 PM PDT 24
Peak memory 248744 kb
Host smart-12e5e2a0-7b15-4f2a-8e75-ac797b54874d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
9183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.270929183
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1928545345
Short name T631
Test name
Test status
Simulation time 6292355895 ps
CPU time 742.12 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:12:03 PM PDT 24
Peak memory 272344 kb
Host smart-144dcac7-27e3-4bf7-b12a-57a40a26da8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928545345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1928545345
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2352610828
Short name T626
Test name
Test status
Simulation time 60542815141 ps
CPU time 1862.25 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 01:30:44 PM PDT 24
Peak memory 266268 kb
Host smart-bf2ce6df-dbe0-4999-8185-9e95393f1339
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352610828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2352610828
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3194028463
Short name T484
Test name
Test status
Simulation time 680665936 ps
CPU time 37.76 seconds
Started Jun 04 12:59:41 PM PDT 24
Finished Jun 04 01:00:20 PM PDT 24
Peak memory 248752 kb
Host smart-62c98b14-4beb-4709-9cf5-7d973406809d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31940
28463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3194028463
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3170787891
Short name T693
Test name
Test status
Simulation time 706946331 ps
CPU time 12.6 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 12:59:54 PM PDT 24
Peak memory 252912 kb
Host smart-133164ad-dff1-420b-bb02-bff802977bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707
87891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3170787891
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2714004011
Short name T30
Test name
Test status
Simulation time 817230756 ps
CPU time 12.68 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 12:59:54 PM PDT 24
Peak memory 275752 kb
Host smart-f3532525-f231-4e2d-87bf-07cc8fc21ee4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2714004011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2714004011
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4106410630
Short name T675
Test name
Test status
Simulation time 391470536 ps
CPU time 26.46 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:00:08 PM PDT 24
Peak memory 254960 kb
Host smart-463d5d1f-7ac7-41f9-89ab-a01a7de68cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41064
10630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4106410630
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3958812001
Short name T526
Test name
Test status
Simulation time 1249390611 ps
CPU time 65.73 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:00:46 PM PDT 24
Peak memory 255892 kb
Host smart-e9190a80-2d2d-43c1-b7aa-7b4623ee2c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39588
12001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3958812001
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1675830977
Short name T117
Test name
Test status
Simulation time 1344125512 ps
CPU time 78.58 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:00:59 PM PDT 24
Peak memory 256804 kb
Host smart-8eadbfe6-d6d3-410d-8f3f-6585aaf48575
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675830977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1675830977
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.172861846
Short name T687
Test name
Test status
Simulation time 25280944674 ps
CPU time 974.48 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:16:39 PM PDT 24
Peak memory 273356 kb
Host smart-68eb92ef-2f8b-4571-8777-7f16fd052f1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172861846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.172861846
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2944994957
Short name T492
Test name
Test status
Simulation time 877902781 ps
CPU time 57.88 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:01:07 PM PDT 24
Peak memory 256052 kb
Host smart-04bbceac-d76c-4fa8-b4f4-7253c86abb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
94957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2944994957
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1918240644
Short name T392
Test name
Test status
Simulation time 242850948 ps
CPU time 31.38 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 01:01:00 PM PDT 24
Peak memory 255696 kb
Host smart-49746d8f-4f4e-404e-89c6-6b72b81502cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182
40644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1918240644
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1099278858
Short name T702
Test name
Test status
Simulation time 14015574695 ps
CPU time 1410.08 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:24:02 PM PDT 24
Peak memory 281520 kb
Host smart-8b201d33-687c-4160-abec-317877d0a7a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099278858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1099278858
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1436657341
Short name T440
Test name
Test status
Simulation time 31359337257 ps
CPU time 1807.91 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:30:38 PM PDT 24
Peak memory 273424 kb
Host smart-71601de7-5013-4414-8421-57a59fac729a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436657341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1436657341
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3174626447
Short name T293
Test name
Test status
Simulation time 45486960429 ps
CPU time 563.74 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:09:29 PM PDT 24
Peak memory 248180 kb
Host smart-2f9372d7-38a0-4727-9df8-be65faa44f81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174626447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3174626447
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1149197383
Short name T390
Test name
Test status
Simulation time 460967123 ps
CPU time 28.53 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:00:36 PM PDT 24
Peak memory 256008 kb
Host smart-72e79e57-ede5-47e6-888b-e6904b2e956d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
97383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1149197383
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3584222199
Short name T515
Test name
Test status
Simulation time 921892379 ps
CPU time 63.73 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:01:14 PM PDT 24
Peak memory 255968 kb
Host smart-f5b1105e-4c2b-4582-9cdd-03e5d8df7093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35842
22199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3584222199
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.901377929
Short name T39
Test name
Test status
Simulation time 2183043409 ps
CPU time 40.6 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:53 PM PDT 24
Peak memory 248844 kb
Host smart-8aa65103-fb1e-496d-abdf-9a84fa4b63b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90137
7929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.901377929
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3565912544
Short name T391
Test name
Test status
Simulation time 300658927 ps
CPU time 28.7 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:35 PM PDT 24
Peak memory 248748 kb
Host smart-7aaec799-9226-4211-a764-a580e8eb5686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
12544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3565912544
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3016434458
Short name T679
Test name
Test status
Simulation time 44510716153 ps
CPU time 2569.94 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 01:43:18 PM PDT 24
Peak memory 289720 kb
Host smart-a30c3c9a-4d74-48d3-aafa-7fd54844f5bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016434458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3016434458
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3627326275
Short name T540
Test name
Test status
Simulation time 78050291413 ps
CPU time 3219.41 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:53:50 PM PDT 24
Peak memory 321872 kb
Host smart-0c3d236f-01a1-4dde-b859-cabae16e57df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627326275 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3627326275
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.392329956
Short name T663
Test name
Test status
Simulation time 29872475327 ps
CPU time 652.6 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:11:06 PM PDT 24
Peak memory 273228 kb
Host smart-abe86ff7-308e-4fec-a4e5-0fff653a6ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392329956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.392329956
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3142111924
Short name T377
Test name
Test status
Simulation time 53476823066 ps
CPU time 270.63 seconds
Started Jun 04 01:00:14 PM PDT 24
Finished Jun 04 01:04:45 PM PDT 24
Peak memory 251364 kb
Host smart-06494e0e-ddac-4180-ac44-4432cb939d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31421
11924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3142111924
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2690363792
Short name T662
Test name
Test status
Simulation time 2016502490 ps
CPU time 21.7 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:00:55 PM PDT 24
Peak memory 256156 kb
Host smart-6a6e98f7-8a70-430d-9bad-197e31780148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26903
63792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2690363792
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2265120244
Short name T558
Test name
Test status
Simulation time 118521874394 ps
CPU time 1763.15 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:29:32 PM PDT 24
Peak memory 266260 kb
Host smart-46d78ef9-fd63-404f-89da-95323fb7b17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265120244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2265120244
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.439365396
Short name T504
Test name
Test status
Simulation time 412835712187 ps
CPU time 2112.7 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:35:46 PM PDT 24
Peak memory 273372 kb
Host smart-2097cc4b-77ef-49c3-8b6e-2c44a4268e84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439365396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.439365396
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.677501629
Short name T311
Test name
Test status
Simulation time 46223007122 ps
CPU time 462.9 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:08:16 PM PDT 24
Peak memory 248168 kb
Host smart-59bc976c-5aa9-4911-beac-f37656f4b122
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677501629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.677501629
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1020581954
Short name T449
Test name
Test status
Simulation time 723958149 ps
CPU time 47.66 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:01:02 PM PDT 24
Peak memory 256968 kb
Host smart-32836cc1-e430-4f5d-97c3-ad0b3a327199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10205
81954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1020581954
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2522144306
Short name T649
Test name
Test status
Simulation time 129699114 ps
CPU time 14.55 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:00:44 PM PDT 24
Peak memory 253780 kb
Host smart-bc701635-da8e-42ff-88f1-c4fc37fed12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25221
44306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2522144306
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2139325073
Short name T685
Test name
Test status
Simulation time 4156842234 ps
CPU time 53.87 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:01:06 PM PDT 24
Peak memory 248760 kb
Host smart-2479b0f9-eef0-4a06-8f5c-ca4aad6fb2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393
25073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2139325073
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2118073544
Short name T394
Test name
Test status
Simulation time 255780750 ps
CPU time 13.98 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:00:35 PM PDT 24
Peak memory 248696 kb
Host smart-4f65298e-d0c7-4682-b2a0-6d08b0090e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
73544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2118073544
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3812646865
Short name T605
Test name
Test status
Simulation time 122133245610 ps
CPU time 2290.54 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:38:44 PM PDT 24
Peak memory 289536 kb
Host smart-d7c09119-d14a-40c8-aeb9-623c696faa3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812646865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3812646865
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.621981248
Short name T59
Test name
Test status
Simulation time 73440036786 ps
CPU time 1952.54 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:32:42 PM PDT 24
Peak memory 289380 kb
Host smart-f2100d5f-f32e-4601-a3d6-3c94584c8f7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621981248 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.621981248
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3816977154
Short name T116
Test name
Test status
Simulation time 21009236619 ps
CPU time 1389.6 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:23:40 PM PDT 24
Peak memory 273048 kb
Host smart-451d7b5d-cc97-41c0-80ed-fc0a3fafacdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816977154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3816977154
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1571238832
Short name T267
Test name
Test status
Simulation time 20669263725 ps
CPU time 158.86 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:02:49 PM PDT 24
Peak memory 249800 kb
Host smart-0cba1e33-b6e3-49ad-b3a4-6acea44c663e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15712
38832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1571238832
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4269049000
Short name T344
Test name
Test status
Simulation time 509191356 ps
CPU time 14.66 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:00:40 PM PDT 24
Peak memory 254432 kb
Host smart-197052b3-2a34-4dff-af9f-684862487ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42690
49000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4269049000
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2501465625
Short name T591
Test name
Test status
Simulation time 93068900984 ps
CPU time 1570.81 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:26:35 PM PDT 24
Peak memory 268192 kb
Host smart-e3b364a7-6dbf-4d18-9a09-b1a5bcae8a67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501465625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2501465625
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2990004342
Short name T398
Test name
Test status
Simulation time 30877635651 ps
CPU time 1591.19 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:26:45 PM PDT 24
Peak memory 273344 kb
Host smart-d2c4ce0f-7248-459f-8b4f-0c11caf39585
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990004342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2990004342
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.361149235
Short name T543
Test name
Test status
Simulation time 8466615827 ps
CPU time 202 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:03:51 PM PDT 24
Peak memory 254284 kb
Host smart-902f9501-1199-4a19-b7b4-32092f4299cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361149235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.361149235
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3669279787
Short name T567
Test name
Test status
Simulation time 25176881 ps
CPU time 4.6 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:00:29 PM PDT 24
Peak memory 240532 kb
Host smart-cd7e9a6a-03d5-46fa-8b32-9d5e40d73da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36692
79787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3669279787
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2375648403
Short name T568
Test name
Test status
Simulation time 3160712750 ps
CPU time 52.66 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:25 PM PDT 24
Peak memory 247828 kb
Host smart-b0c283b5-3ddd-46b6-adb0-497c78e5b983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23756
48403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2375648403
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.70998153
Short name T473
Test name
Test status
Simulation time 280412179 ps
CPU time 5.32 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:00:22 PM PDT 24
Peak memory 248648 kb
Host smart-556c6cb8-f251-41bb-8244-4e0fcb79abaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70998
153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.70998153
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4201528657
Short name T604
Test name
Test status
Simulation time 404926928 ps
CPU time 36.65 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:00:48 PM PDT 24
Peak memory 256892 kb
Host smart-655205a9-d82e-4ae6-826f-2a5738a70784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
28657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4201528657
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.501065970
Short name T272
Test name
Test status
Simulation time 55779852794 ps
CPU time 1178.12 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 288664 kb
Host smart-55009c1b-7210-41c5-a1c4-4d00dc072430
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501065970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.501065970
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1471399392
Short name T264
Test name
Test status
Simulation time 355239989539 ps
CPU time 10644.8 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 03:57:49 PM PDT 24
Peak memory 355504 kb
Host smart-5cf0ba9a-969d-4c44-b2b7-4a8c9d9693e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471399392 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1471399392
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1502339262
Short name T108
Test name
Test status
Simulation time 38916937106 ps
CPU time 2147.46 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:36:09 PM PDT 24
Peak memory 271428 kb
Host smart-b4352ead-ff8e-443d-b239-5b7494476268
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502339262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1502339262
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1210119477
Short name T486
Test name
Test status
Simulation time 15910443642 ps
CPU time 102.78 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:01:56 PM PDT 24
Peak memory 256748 kb
Host smart-1aaea0f7-715c-4108-ba40-b922578b6378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12101
19477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1210119477
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3108759540
Short name T616
Test name
Test status
Simulation time 920712715 ps
CPU time 37.93 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:01:08 PM PDT 24
Peak memory 248916 kb
Host smart-41a98f18-8ea5-4de0-9b9f-2bde4d8f3f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31087
59540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3108759540
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.636633095
Short name T321
Test name
Test status
Simulation time 8681145892 ps
CPU time 762.45 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:12:57 PM PDT 24
Peak memory 265240 kb
Host smart-fb453af2-3c00-4492-81f9-cd7e1a042645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636633095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.636633095
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1528792510
Short name T222
Test name
Test status
Simulation time 185694647593 ps
CPU time 3168.36 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:52:59 PM PDT 24
Peak memory 289756 kb
Host smart-16df22b7-b684-433f-a2ab-ef9089d94468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528792510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1528792510
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2137880273
Short name T298
Test name
Test status
Simulation time 11943777717 ps
CPU time 124.58 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:02:30 PM PDT 24
Peak memory 248068 kb
Host smart-0ebe0558-83ca-4ba8-88b4-83243a4b44da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137880273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2137880273
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3529157544
Short name T535
Test name
Test status
Simulation time 505083596 ps
CPU time 34.55 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:07 PM PDT 24
Peak memory 248724 kb
Host smart-16d24ea5-d24b-49a1-a6be-88b86bcf318d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35291
57544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3529157544
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3160304973
Short name T573
Test name
Test status
Simulation time 600380923 ps
CPU time 28.73 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:00:52 PM PDT 24
Peak memory 255480 kb
Host smart-0b1c7add-b0e2-4fc5-9fbc-cc0994625c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
04973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3160304973
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.250713484
Short name T111
Test name
Test status
Simulation time 2823736943 ps
CPU time 48.85 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:01:03 PM PDT 24
Peak memory 255680 kb
Host smart-c2e1a78d-4c94-4dc4-84f6-0b0bb8d045b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25071
3484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.250713484
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.778962060
Short name T531
Test name
Test status
Simulation time 3205438968 ps
CPU time 15.44 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:00:35 PM PDT 24
Peak memory 256208 kb
Host smart-89cb4fc4-3c06-4781-b934-f3cee7808ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77896
2060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.778962060
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2253508737
Short name T52
Test name
Test status
Simulation time 153637689904 ps
CPU time 2724.53 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 289672 kb
Host smart-a73e679e-5e37-404f-8c1e-c6e19c2b122b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253508737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2253508737
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4012806875
Short name T229
Test name
Test status
Simulation time 12416240432 ps
CPU time 201.31 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:03:33 PM PDT 24
Peak memory 265276 kb
Host smart-5a14a0e1-90e2-44f3-981c-00fc25f08e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012806875 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4012806875
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2513176332
Short name T380
Test name
Test status
Simulation time 52785002544 ps
CPU time 1576.93 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:26:36 PM PDT 24
Peak memory 273320 kb
Host smart-043cf923-86e7-4577-80d3-fc846ed911c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513176332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2513176332
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1955987551
Short name T35
Test name
Test status
Simulation time 2299746158 ps
CPU time 45.37 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:01:15 PM PDT 24
Peak memory 255972 kb
Host smart-7f929cb8-d024-4b00-9fc1-63f05c98f071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19559
87551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1955987551
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2247136074
Short name T489
Test name
Test status
Simulation time 169044653 ps
CPU time 16 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:00:42 PM PDT 24
Peak memory 248740 kb
Host smart-6c99e152-7839-498a-9c33-ac86594ada6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22471
36074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2247136074
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1614296247
Short name T640
Test name
Test status
Simulation time 67140926183 ps
CPU time 1956.2 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:32:53 PM PDT 24
Peak memory 273280 kb
Host smart-96aede3a-7e80-462e-ab34-3d30c45a01f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614296247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1614296247
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.525723944
Short name T525
Test name
Test status
Simulation time 943683571 ps
CPU time 59.36 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:01:29 PM PDT 24
Peak memory 256908 kb
Host smart-a40821bd-e5d3-4234-ae31-26bf08249279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52572
3944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.525723944
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1916140689
Short name T692
Test name
Test status
Simulation time 16525964 ps
CPU time 3.36 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:00:30 PM PDT 24
Peak memory 239216 kb
Host smart-64a4ffa7-6a32-42b1-83dc-dfc3955e0144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19161
40689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1916140689
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.907299192
Short name T243
Test name
Test status
Simulation time 1011620439 ps
CPU time 15.38 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:00:26 PM PDT 24
Peak memory 253488 kb
Host smart-29a79687-1c03-4205-9635-cb0ad162875a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90729
9192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.907299192
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.273809368
Short name T467
Test name
Test status
Simulation time 808190453 ps
CPU time 46.05 seconds
Started Jun 04 01:00:08 PM PDT 24
Finished Jun 04 01:00:55 PM PDT 24
Peak memory 255940 kb
Host smart-bfb81a48-b79d-406b-af22-95b058085045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27380
9368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.273809368
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2232934876
Short name T544
Test name
Test status
Simulation time 15170731115 ps
CPU time 1065.86 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:18:03 PM PDT 24
Peak memory 289420 kb
Host smart-6bb05508-76d9-4096-bcd0-755c580c0f2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232934876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2232934876
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2899559544
Short name T601
Test name
Test status
Simulation time 85716787908 ps
CPU time 5416.27 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 02:30:33 PM PDT 24
Peak memory 297760 kb
Host smart-03bab309-021e-469e-a991-fc2e886d7b10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899559544 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2899559544
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3771263084
Short name T62
Test name
Test status
Simulation time 17274250177 ps
CPU time 1668.5 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:28:19 PM PDT 24
Peak memory 289492 kb
Host smart-3f185d5a-b9d6-4094-b5f8-024960293bc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771263084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3771263084
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4212351547
Short name T369
Test name
Test status
Simulation time 979241810 ps
CPU time 59.04 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:32 PM PDT 24
Peak memory 256684 kb
Host smart-31477ffe-4cf9-442c-8676-e35ca746b921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
51547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4212351547
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1929113329
Short name T624
Test name
Test status
Simulation time 259261062 ps
CPU time 17.09 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:00:40 PM PDT 24
Peak memory 249052 kb
Host smart-50d20d7f-00cc-4ffc-b169-b0a12c81d2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
13329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1929113329
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.879115214
Short name T275
Test name
Test status
Simulation time 32362289641 ps
CPU time 1454.12 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:24:34 PM PDT 24
Peak memory 288100 kb
Host smart-2d04a09e-a0de-4ba5-a516-451e7edfd91f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879115214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.879115214
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.931735767
Short name T590
Test name
Test status
Simulation time 53678636317 ps
CPU time 3057.21 seconds
Started Jun 04 01:00:21 PM PDT 24
Finished Jun 04 01:51:20 PM PDT 24
Peak memory 289260 kb
Host smart-a0d89579-60d2-4775-a802-590560fdf4ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931735767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.931735767
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1788034653
Short name T424
Test name
Test status
Simulation time 41975947 ps
CPU time 5.72 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:19 PM PDT 24
Peak memory 254136 kb
Host smart-e29c80d9-8411-47b6-8724-4920824ec133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17880
34653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1788034653
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4036364840
Short name T690
Test name
Test status
Simulation time 330469472 ps
CPU time 20.21 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:00:38 PM PDT 24
Peak memory 255316 kb
Host smart-3455e408-7530-4b31-86b2-0400972b0ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40363
64840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4036364840
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2139390647
Short name T215
Test name
Test status
Simulation time 1421940955 ps
CPU time 43.5 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:56 PM PDT 24
Peak memory 255552 kb
Host smart-69bfc5db-b6b1-4a6c-9502-49b65b6ee604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393
90647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2139390647
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2875954548
Short name T570
Test name
Test status
Simulation time 3136043685 ps
CPU time 61.27 seconds
Started Jun 04 01:00:15 PM PDT 24
Finished Jun 04 01:01:17 PM PDT 24
Peak memory 248712 kb
Host smart-3e3ebcfc-5e68-44a8-a4d8-ba997e754e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28759
54548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2875954548
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3530213572
Short name T588
Test name
Test status
Simulation time 21144819764 ps
CPU time 1777.55 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:29:58 PM PDT 24
Peak memory 305368 kb
Host smart-6c8081b6-dae4-438c-a3a7-eccfca7ff84c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530213572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3530213572
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2608517850
Short name T549
Test name
Test status
Simulation time 45545384697 ps
CPU time 1196.06 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:20:15 PM PDT 24
Peak memory 265240 kb
Host smart-82a9d3df-b20a-49e8-8b03-054c70c43588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608517850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2608517850
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2562040253
Short name T563
Test name
Test status
Simulation time 7763152791 ps
CPU time 217.78 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:04:07 PM PDT 24
Peak memory 256888 kb
Host smart-b7519269-509e-424e-a6cd-d58f59313629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
40253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2562040253
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1731427258
Short name T81
Test name
Test status
Simulation time 71085727 ps
CPU time 8.7 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 01:00:37 PM PDT 24
Peak memory 248684 kb
Host smart-d8c04d12-54c7-4a7d-83f3-9cf1fd5d23d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17314
27258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1731427258
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3554192094
Short name T320
Test name
Test status
Simulation time 19092319574 ps
CPU time 1464.62 seconds
Started Jun 04 01:00:34 PM PDT 24
Finished Jun 04 01:25:00 PM PDT 24
Peak memory 289104 kb
Host smart-efda4053-c880-4db1-80cc-b6e2ef8ad4f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554192094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3554192094
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2412510405
Short name T395
Test name
Test status
Simulation time 23013894712 ps
CPU time 1153.94 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:19:32 PM PDT 24
Peak memory 289488 kb
Host smart-ca342384-14bd-432a-9e9f-029a06512f16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412510405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2412510405
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2485457590
Short name T695
Test name
Test status
Simulation time 11149134155 ps
CPU time 233.39 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:04:10 PM PDT 24
Peak memory 254688 kb
Host smart-b0cf9313-d2ef-4fcc-95cc-6e943c4817a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485457590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2485457590
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4221544407
Short name T498
Test name
Test status
Simulation time 930700566 ps
CPU time 48.42 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:01:08 PM PDT 24
Peak memory 256176 kb
Host smart-4016e954-7aca-4f01-acd6-2bf68524f92b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42215
44407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4221544407
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1041363713
Short name T448
Test name
Test status
Simulation time 444718302 ps
CPU time 30.86 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:00:52 PM PDT 24
Peak memory 248680 kb
Host smart-b81e92ee-884d-4f82-9507-d7726624a225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413
63713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1041363713
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.745456842
Short name T606
Test name
Test status
Simulation time 728056806 ps
CPU time 50.7 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:01:16 PM PDT 24
Peak memory 254784 kb
Host smart-e1e2d878-ec42-4582-bd88-79c73a241f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74545
6842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.745456842
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.4244514575
Short name T565
Test name
Test status
Simulation time 2219995603 ps
CPU time 29.76 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:00:49 PM PDT 24
Peak memory 255996 kb
Host smart-fd53204a-084d-4325-bab5-11f004f96445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
14575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.4244514575
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3948451980
Short name T104
Test name
Test status
Simulation time 49591386262 ps
CPU time 1167.33 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:19:44 PM PDT 24
Peak memory 286472 kb
Host smart-2cb7d8a3-582b-4caa-a79c-91c278efdad5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948451980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3948451980
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2063210028
Short name T482
Test name
Test status
Simulation time 5615244620 ps
CPU time 616.36 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:10:46 PM PDT 24
Peak memory 273344 kb
Host smart-4952ffae-e7de-440e-a4e9-b01e5688a94a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063210028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2063210028
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1438865319
Short name T346
Test name
Test status
Simulation time 898362762 ps
CPU time 51.16 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 01:01:19 PM PDT 24
Peak memory 256148 kb
Host smart-1646d43f-de73-4b9c-aebd-4dbe75088b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
65319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1438865319
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.661639989
Short name T513
Test name
Test status
Simulation time 1328206450 ps
CPU time 44.59 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:01:04 PM PDT 24
Peak memory 248752 kb
Host smart-25095f6f-73d0-4957-9b02-3841720e89d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66163
9989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.661639989
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.75065096
Short name T355
Test name
Test status
Simulation time 25168244989 ps
CPU time 1387.7 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:23:28 PM PDT 24
Peak memory 273368 kb
Host smart-c71fbea2-260c-45f7-a5ca-96a21773acb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75065096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.75065096
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.788732035
Short name T645
Test name
Test status
Simulation time 4037065878 ps
CPU time 173.08 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:03:12 PM PDT 24
Peak memory 247988 kb
Host smart-e13f6894-aaad-4e94-9dd3-1cdac945df0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788732035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.788732035
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.756107538
Short name T670
Test name
Test status
Simulation time 1945684870 ps
CPU time 24.48 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:00:56 PM PDT 24
Peak memory 248828 kb
Host smart-5cfc8046-78ab-4145-b27e-7f5b5625958b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75610
7538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.756107538
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2207849861
Short name T704
Test name
Test status
Simulation time 769318943 ps
CPU time 52.41 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:01:25 PM PDT 24
Peak memory 248752 kb
Host smart-935a1ce6-3ea0-448c-ba1e-c1543c83a046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22078
49861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2207849861
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3423814378
Short name T249
Test name
Test status
Simulation time 2685023650 ps
CPU time 39.21 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:01:00 PM PDT 24
Peak memory 248804 kb
Host smart-a8b9af12-bc3f-4797-a56d-aa29491eab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34238
14378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3423814378
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3351353205
Short name T349
Test name
Test status
Simulation time 12056767128 ps
CPU time 51.68 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:01:10 PM PDT 24
Peak memory 248780 kb
Host smart-8a03c4b1-98c2-4346-a6cc-bbb6a24ac231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
53205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3351353205
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.4442777
Short name T56
Test name
Test status
Simulation time 38493465864 ps
CPU time 3585.38 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 02:00:14 PM PDT 24
Peak memory 321836 kb
Host smart-2a13900e-9202-42b6-85e7-88104d9eaeb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4442777 -assert nopostproc +UVM_TESTNAME=alert_h
andler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.4442777
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2583857426
Short name T387
Test name
Test status
Simulation time 20914555614 ps
CPU time 574.41 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:10:06 PM PDT 24
Peak memory 273264 kb
Host smart-f7fc5003-df44-481c-874a-387db6436da9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583857426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2583857426
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3591471930
Short name T233
Test name
Test status
Simulation time 1150457592 ps
CPU time 52.54 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:01:18 PM PDT 24
Peak memory 248996 kb
Host smart-8ae43c00-537e-4f2a-b714-daea81525add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35914
71930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3591471930
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.956835573
Short name T118
Test name
Test status
Simulation time 487275967 ps
CPU time 9.02 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:00:42 PM PDT 24
Peak memory 251952 kb
Host smart-a10afd83-4af9-4001-8701-a1c3bbb96276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95683
5573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.956835573
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3459662330
Short name T324
Test name
Test status
Simulation time 121662498789 ps
CPU time 1606.39 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:27:05 PM PDT 24
Peak memory 272564 kb
Host smart-8e793aac-c61d-4283-bd00-705f23e2a4ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459662330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3459662330
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.22737883
Short name T587
Test name
Test status
Simulation time 104741069711 ps
CPU time 1577.06 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 01:26:44 PM PDT 24
Peak memory 288928 kb
Host smart-64aa515a-7efd-4851-9073-586c59124021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22737883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.22737883
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3366572554
Short name T284
Test name
Test status
Simulation time 45889385260 ps
CPU time 369.6 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:06:30 PM PDT 24
Peak memory 254732 kb
Host smart-7fd5e640-e9e7-4ef8-808b-e43847512c99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366572554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3366572554
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1131055196
Short name T680
Test name
Test status
Simulation time 805118028 ps
CPU time 30.19 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:00:48 PM PDT 24
Peak memory 256148 kb
Host smart-66a88b27-6c63-4e4b-9816-600c6ecfd31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11310
55196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1131055196
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.425326993
Short name T487
Test name
Test status
Simulation time 1238909018 ps
CPU time 29.52 seconds
Started Jun 04 01:00:18 PM PDT 24
Finished Jun 04 01:00:49 PM PDT 24
Peak memory 255416 kb
Host smart-5342fbb6-864c-400e-8ab5-b446a630bc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42532
6993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.425326993
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4286266737
Short name T418
Test name
Test status
Simulation time 599723205 ps
CPU time 38.21 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:01:02 PM PDT 24
Peak memory 254720 kb
Host smart-35829279-f083-46a9-ada4-97dc519f3b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42862
66737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4286266737
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.105610978
Short name T659
Test name
Test status
Simulation time 106293354 ps
CPU time 10.22 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:00:43 PM PDT 24
Peak memory 254368 kb
Host smart-cc768b78-8abf-4cd7-9f42-ebe40916337d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
0978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.105610978
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2027495727
Short name T49
Test name
Test status
Simulation time 39795894380 ps
CPU time 2543.65 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 01:42:51 PM PDT 24
Peak memory 289576 kb
Host smart-e41ba768-22e7-42cf-877d-af3a41be8894
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027495727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2027495727
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3138185884
Short name T444
Test name
Test status
Simulation time 182712254881 ps
CPU time 1715.78 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:28:54 PM PDT 24
Peak memory 273424 kb
Host smart-5f318762-1a23-4cac-b773-a228767caeab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138185884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3138185884
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.378352239
Short name T483
Test name
Test status
Simulation time 1051754548 ps
CPU time 85.16 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:01:55 PM PDT 24
Peak memory 256876 kb
Host smart-882e63cb-41bd-4a81-a0d7-ebe6ab37a151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37835
2239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.378352239
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2357155083
Short name T236
Test name
Test status
Simulation time 2745175456 ps
CPU time 53.9 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:27 PM PDT 24
Peak memory 256940 kb
Host smart-9535baf9-a9ce-435c-9b67-312af9971ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23571
55083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2357155083
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2883870753
Short name T312
Test name
Test status
Simulation time 24702371374 ps
CPU time 1592.12 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:26:55 PM PDT 24
Peak memory 273348 kb
Host smart-33af6f6f-c866-41c7-9843-1804536bc98a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883870753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2883870753
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3455453339
Short name T494
Test name
Test status
Simulation time 77929990334 ps
CPU time 2049.15 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:34:41 PM PDT 24
Peak memory 286188 kb
Host smart-ae2bd017-b893-45d0-945f-1d05eeec256e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455453339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3455453339
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3563207517
Short name T223
Test name
Test status
Simulation time 9550045723 ps
CPU time 389.46 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:07:04 PM PDT 24
Peak memory 248220 kb
Host smart-076fae53-4a14-434c-bd97-82c74a3c9971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563207517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3563207517
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2043237352
Short name T602
Test name
Test status
Simulation time 880054316 ps
CPU time 43.52 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:01:13 PM PDT 24
Peak memory 256548 kb
Host smart-01087afa-a11d-44ab-9b9c-b427e8ef0dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20432
37352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2043237352
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2323281304
Short name T674
Test name
Test status
Simulation time 73709290 ps
CPU time 5.06 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:00:24 PM PDT 24
Peak memory 239084 kb
Host smart-37330db9-0af7-4ffb-867a-5f75996a0427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
81304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2323281304
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3202410182
Short name T78
Test name
Test status
Simulation time 349171972 ps
CPU time 9.63 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:00:41 PM PDT 24
Peak memory 252084 kb
Host smart-a62f924c-35cc-48c2-95e9-5f53414c3319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32024
10182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3202410182
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2391916291
Short name T393
Test name
Test status
Simulation time 372085066 ps
CPU time 23.53 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:00:54 PM PDT 24
Peak memory 248748 kb
Host smart-c20a946a-40ff-4754-b0a7-086929ca74b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23919
16291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2391916291
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.940501646
Short name T100
Test name
Test status
Simulation time 63574753185 ps
CPU time 1301.07 seconds
Started Jun 04 12:59:49 PM PDT 24
Finished Jun 04 01:21:31 PM PDT 24
Peak memory 289104 kb
Host smart-a1d1c1f9-b57f-46d5-9862-489a5696b64d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940501646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.940501646
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2999565056
Short name T676
Test name
Test status
Simulation time 1431071351 ps
CPU time 12.59 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 12:59:57 PM PDT 24
Peak memory 252344 kb
Host smart-99c245a8-5bc8-4e52-a0e1-f9a9665f9011
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2999565056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2999565056
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2915667363
Short name T367
Test name
Test status
Simulation time 2128663428 ps
CPU time 50.15 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:00:31 PM PDT 24
Peak memory 248876 kb
Host smart-ce4405dd-690d-42b8-b1b3-357f78ef888d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29156
67363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2915667363
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.143530365
Short name T16
Test name
Test status
Simulation time 878794378 ps
CPU time 4.82 seconds
Started Jun 04 12:59:41 PM PDT 24
Finished Jun 04 12:59:47 PM PDT 24
Peak memory 240488 kb
Host smart-bab2afb0-8b72-41d9-a551-72eaf82f8ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14353
0365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.143530365
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.885734919
Short name T278
Test name
Test status
Simulation time 62840221883 ps
CPU time 1905.49 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:31:30 PM PDT 24
Peak memory 288364 kb
Host smart-17d94d7f-8b9f-4ceb-8ecd-1fdb70d05dfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885734919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.885734919
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2694557249
Short name T93
Test name
Test status
Simulation time 51221778078 ps
CPU time 1135.85 seconds
Started Jun 04 12:59:39 PM PDT 24
Finished Jun 04 01:18:37 PM PDT 24
Peak memory 273332 kb
Host smart-04d0c99f-c7a8-4a61-b377-e5e5c6b09d39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694557249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2694557249
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2608293313
Short name T517
Test name
Test status
Simulation time 8691971614 ps
CPU time 130.8 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:01:50 PM PDT 24
Peak memory 248140 kb
Host smart-ee2a0f11-f069-4582-b330-887b15c6ca27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608293313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2608293313
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.592591410
Short name T381
Test name
Test status
Simulation time 4076382850 ps
CPU time 46.73 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:00:31 PM PDT 24
Peak memory 248760 kb
Host smart-1b8694a6-4a9c-4eba-a3e3-d74e9c0a217b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59259
1410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.592591410
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3882697703
Short name T82
Test name
Test status
Simulation time 130888910 ps
CPU time 5.01 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:45 PM PDT 24
Peak memory 248720 kb
Host smart-4fcdc164-2ded-4d97-86db-56d3819b737d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38826
97703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3882697703
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2169125042
Short name T31
Test name
Test status
Simulation time 370906102 ps
CPU time 15.59 seconds
Started Jun 04 12:59:59 PM PDT 24
Finished Jun 04 01:00:15 PM PDT 24
Peak memory 270300 kb
Host smart-4d23b2fc-433c-492a-9adf-b1df19ed0f39
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2169125042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2169125042
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3479314807
Short name T681
Test name
Test status
Simulation time 1275077092 ps
CPU time 40.3 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 01:00:21 PM PDT 24
Peak memory 256924 kb
Host smart-00e7efe3-7ce6-4be1-9e70-8495a93c221b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
14807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3479314807
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2349863032
Short name T219
Test name
Test status
Simulation time 1592089333 ps
CPU time 35.17 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 01:00:20 PM PDT 24
Peak memory 256860 kb
Host smart-f95ccb5b-9a6f-472a-8c91-ee0ace2b73da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349863032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2349863032
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1879418504
Short name T581
Test name
Test status
Simulation time 5905737486 ps
CPU time 736.72 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:12:48 PM PDT 24
Peak memory 273288 kb
Host smart-f35640d6-b29c-4faf-861c-60dbb5d88fe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879418504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1879418504
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2437835299
Short name T628
Test name
Test status
Simulation time 19369193623 ps
CPU time 150.79 seconds
Started Jun 04 01:00:36 PM PDT 24
Finished Jun 04 01:03:07 PM PDT 24
Peak memory 251860 kb
Host smart-f1f32ef1-a8e8-495a-a6c6-9d836327dcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24378
35299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2437835299
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.4125913899
Short name T622
Test name
Test status
Simulation time 1234293078 ps
CPU time 12.69 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:00:38 PM PDT 24
Peak memory 248732 kb
Host smart-3c0178b8-496c-40a1-a0e2-dd6ff3427230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41259
13899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4125913899
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1231347137
Short name T276
Test name
Test status
Simulation time 61055859012 ps
CPU time 1124.35 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:19:18 PM PDT 24
Peak memory 272416 kb
Host smart-83fd3d26-61f5-4daf-b5a7-78368caf95c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231347137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1231347137
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3996389278
Short name T658
Test name
Test status
Simulation time 11233509951 ps
CPU time 909.3 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:15:41 PM PDT 24
Peak memory 272428 kb
Host smart-95087edb-dcbf-4630-bbe1-138fb6218a20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996389278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3996389278
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3087413993
Short name T288
Test name
Test status
Simulation time 10276840489 ps
CPU time 307.33 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:05:38 PM PDT 24
Peak memory 247032 kb
Host smart-ad73ae05-54be-42d3-9756-e62c5d5c5c93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087413993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3087413993
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3845100757
Short name T421
Test name
Test status
Simulation time 857840203 ps
CPU time 26.54 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:00:47 PM PDT 24
Peak memory 255956 kb
Host smart-29aac2d3-ec0c-447d-b609-9f127d74d0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
00757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3845100757
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1419085500
Short name T90
Test name
Test status
Simulation time 654465642 ps
CPU time 11.4 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:00:45 PM PDT 24
Peak memory 253164 kb
Host smart-4e78f43b-18bd-4e87-981a-4f3f95b61f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14190
85500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1419085500
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3175218597
Short name T250
Test name
Test status
Simulation time 6049751828 ps
CPU time 23.29 seconds
Started Jun 04 01:00:35 PM PDT 24
Finished Jun 04 01:00:59 PM PDT 24
Peak memory 256084 kb
Host smart-4665413e-7486-480d-81c9-7eeef971ed60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752
18597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3175218597
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1189807727
Short name T510
Test name
Test status
Simulation time 1622420738 ps
CPU time 24.79 seconds
Started Jun 04 01:00:27 PM PDT 24
Finished Jun 04 01:00:53 PM PDT 24
Peak memory 248544 kb
Host smart-32ae0c16-8386-4033-9c6f-efe06d1ed232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11898
07727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1189807727
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.300661153
Short name T48
Test name
Test status
Simulation time 111637240400 ps
CPU time 1574.25 seconds
Started Jun 04 01:00:21 PM PDT 24
Finished Jun 04 01:26:36 PM PDT 24
Peak memory 272136 kb
Host smart-1a592456-a0aa-4578-a0e4-151a87301b5b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300661153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.300661153
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3204654837
Short name T500
Test name
Test status
Simulation time 60445456766 ps
CPU time 1902.43 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:32:01 PM PDT 24
Peak memory 270664 kb
Host smart-ed0f8850-ebf8-4df3-bfff-1e66cc9a6aba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204654837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3204654837
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3444373472
Short name T363
Test name
Test status
Simulation time 123985425 ps
CPU time 12.43 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:00:46 PM PDT 24
Peak memory 249004 kb
Host smart-37d21b4c-ccb6-417e-af09-48f29ffb40d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34443
73472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3444373472
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.435551841
Short name T408
Test name
Test status
Simulation time 5503518924 ps
CPU time 37.18 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:10 PM PDT 24
Peak memory 248768 kb
Host smart-8269b049-5a4e-44ce-8fd5-073e84d84930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43555
1841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.435551841
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3664450808
Short name T323
Test name
Test status
Simulation time 114419136573 ps
CPU time 1887.85 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:31:51 PM PDT 24
Peak memory 271636 kb
Host smart-9a2c3ad2-46e0-4bab-97d4-88750f18ae8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664450808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3664450808
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2979514017
Short name T629
Test name
Test status
Simulation time 8564140191 ps
CPU time 85.82 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 248224 kb
Host smart-3c60132c-7f35-4327-88f5-c318cef8c41c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979514017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2979514017
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.64089618
Short name T541
Test name
Test status
Simulation time 798959502 ps
CPU time 17.43 seconds
Started Jun 04 01:00:23 PM PDT 24
Finished Jun 04 01:00:42 PM PDT 24
Peak memory 248744 kb
Host smart-443eed6f-c384-4184-8b71-c0cf303e2772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64089
618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.64089618
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1933695921
Short name T44
Test name
Test status
Simulation time 1209488930 ps
CPU time 39.46 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:01:00 PM PDT 24
Peak memory 255664 kb
Host smart-5d475e1e-89f7-4cc7-a8b2-618e776ea19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
95921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1933695921
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2002856355
Short name T569
Test name
Test status
Simulation time 1144596668 ps
CPU time 59.85 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:01:19 PM PDT 24
Peak memory 256064 kb
Host smart-5dca3596-14c7-4f03-b0b2-bee0e83e83ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
56355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2002856355
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3872397051
Short name T559
Test name
Test status
Simulation time 60533228 ps
CPU time 9.81 seconds
Started Jun 04 01:00:19 PM PDT 24
Finished Jun 04 01:00:30 PM PDT 24
Peak memory 248744 kb
Host smart-8bfba08a-aca7-4a73-8893-a9523fc90e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38723
97051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3872397051
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.675926442
Short name T50
Test name
Test status
Simulation time 25437802405 ps
CPU time 1339.5 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:22:45 PM PDT 24
Peak memory 299688 kb
Host smart-a175bcda-0865-40b5-9717-7b85f3ed5b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675926442 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.675926442
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2728996919
Short name T593
Test name
Test status
Simulation time 33119528060 ps
CPU time 860.77 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:14:44 PM PDT 24
Peak memory 266304 kb
Host smart-a36b03f1-2b83-4653-b296-e81e5426de36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728996919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2728996919
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.219661990
Short name T555
Test name
Test status
Simulation time 1778672238 ps
CPU time 19.36 seconds
Started Jun 04 01:00:34 PM PDT 24
Finished Jun 04 01:00:55 PM PDT 24
Peak memory 256016 kb
Host smart-b5d05b51-aee7-4752-9432-ac2c3dc8b42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21966
1990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.219661990
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1860510479
Short name T442
Test name
Test status
Simulation time 250804128 ps
CPU time 15.69 seconds
Started Jun 04 01:00:38 PM PDT 24
Finished Jun 04 01:00:54 PM PDT 24
Peak memory 255300 kb
Host smart-f5a806bc-94dc-4e0b-b093-a3cf5071e945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18605
10479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1860510479
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.391166289
Short name T521
Test name
Test status
Simulation time 27440103730 ps
CPU time 1730.44 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:29:17 PM PDT 24
Peak memory 283940 kb
Host smart-de5cee29-4a39-418a-8bc7-e77267dece2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391166289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.391166289
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3979842768
Short name T304
Test name
Test status
Simulation time 24998177384 ps
CPU time 238.35 seconds
Started Jun 04 01:00:34 PM PDT 24
Finished Jun 04 01:04:33 PM PDT 24
Peak memory 248100 kb
Host smart-a33d0e88-73e6-47ea-8316-986bbb6a0cd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979842768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3979842768
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3312791439
Short name T656
Test name
Test status
Simulation time 227570066 ps
CPU time 15.45 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:00:46 PM PDT 24
Peak memory 248744 kb
Host smart-c147a77a-8a8b-46f2-a5c4-012eead0fdc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33127
91439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3312791439
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3763927204
Short name T682
Test name
Test status
Simulation time 724948635 ps
CPU time 22.2 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:00:57 PM PDT 24
Peak memory 248756 kb
Host smart-f0ebca9a-e276-4beb-8393-8b9661347e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639
27204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3763927204
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1499018009
Short name T660
Test name
Test status
Simulation time 953302140 ps
CPU time 54.75 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:01:20 PM PDT 24
Peak memory 248756 kb
Host smart-13c001a5-f0e8-46d4-a168-df2888594039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14990
18009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1499018009
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2864424334
Short name T407
Test name
Test status
Simulation time 260862374 ps
CPU time 6.18 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:00:32 PM PDT 24
Peak memory 254008 kb
Host smart-b917cbed-328c-4f56-83ad-d2839b8f94be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
24334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2864424334
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3246489221
Short name T95
Test name
Test status
Simulation time 108556076670 ps
CPU time 3628.47 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 02:00:56 PM PDT 24
Peak memory 303272 kb
Host smart-a66d04a0-2b6b-46e0-a50a-17dd11649315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246489221 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3246489221
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1978952047
Short name T91
Test name
Test status
Simulation time 133607138671 ps
CPU time 2113.62 seconds
Started Jun 04 01:00:29 PM PDT 24
Finished Jun 04 01:35:44 PM PDT 24
Peak memory 271700 kb
Host smart-c05ee013-4180-4d59-9510-7ee53db1f2c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978952047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1978952047
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.118777660
Short name T231
Test name
Test status
Simulation time 6223461524 ps
CPU time 120.53 seconds
Started Jun 04 01:00:25 PM PDT 24
Finished Jun 04 01:02:26 PM PDT 24
Peak memory 249824 kb
Host smart-e2119cf2-4bbb-4742-bf17-e8cf1332d190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11877
7660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.118777660
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2257317673
Short name T119
Test name
Test status
Simulation time 2046112431 ps
CPU time 32.13 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:01:02 PM PDT 24
Peak memory 248944 kb
Host smart-f82f60ef-bcf9-468b-b900-61f195e0cae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22573
17673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2257317673
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.850409704
Short name T617
Test name
Test status
Simulation time 169753871643 ps
CPU time 2434.6 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 01:41:02 PM PDT 24
Peak memory 289512 kb
Host smart-b685e771-013a-409a-8075-b8c9434d1f6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850409704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.850409704
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4108145790
Short name T292
Test name
Test status
Simulation time 24341092123 ps
CPU time 465.4 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:08:17 PM PDT 24
Peak memory 248216 kb
Host smart-3c6626dd-d8a5-45bd-8740-dbcbef33e0b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108145790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4108145790
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3373815577
Short name T397
Test name
Test status
Simulation time 4927495280 ps
CPU time 47 seconds
Started Jun 04 01:00:49 PM PDT 24
Finished Jun 04 01:01:37 PM PDT 24
Peak memory 248652 kb
Host smart-6aabadfd-291c-4b63-b808-5c4fc65cfb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
15577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3373815577
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1520433270
Short name T360
Test name
Test status
Simulation time 1323939001 ps
CPU time 26.55 seconds
Started Jun 04 01:00:28 PM PDT 24
Finished Jun 04 01:00:55 PM PDT 24
Peak memory 247412 kb
Host smart-f6b5a487-f820-4ff2-ab60-1562bc93e450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
33270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1520433270
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3103340628
Short name T488
Test name
Test status
Simulation time 364353672 ps
CPU time 15.5 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:00:48 PM PDT 24
Peak memory 255072 kb
Host smart-548aff30-cafb-45da-93a9-1ccdf086ed04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
40628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3103340628
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1545736703
Short name T546
Test name
Test status
Simulation time 590053847 ps
CPU time 34.72 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:01:00 PM PDT 24
Peak memory 248760 kb
Host smart-fb5f2f17-0dc2-48d0-a723-53f93f000a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15457
36703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1545736703
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3784218237
Short name T545
Test name
Test status
Simulation time 214620073962 ps
CPU time 3269.21 seconds
Started Jun 04 01:00:24 PM PDT 24
Finished Jun 04 01:54:55 PM PDT 24
Peak memory 297480 kb
Host smart-446f90ea-df97-4c7c-ba71-bc28441f6f72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784218237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3784218237
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1393360071
Short name T432
Test name
Test status
Simulation time 27855906557 ps
CPU time 1589.43 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:26:53 PM PDT 24
Peak memory 273368 kb
Host smart-7524aa20-641f-4113-8c5e-c373134d16da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393360071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1393360071
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2683270860
Short name T669
Test name
Test status
Simulation time 680143961 ps
CPU time 29.85 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:02 PM PDT 24
Peak memory 256856 kb
Host smart-021419f2-90ab-4522-af22-752ecc3940fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
70860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2683270860
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.483422871
Short name T459
Test name
Test status
Simulation time 4770307063 ps
CPU time 77.16 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:01:41 PM PDT 24
Peak memory 248804 kb
Host smart-5461aace-8785-41cc-bbac-1eb7e5ae32a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48342
2871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.483422871
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2895152041
Short name T262
Test name
Test status
Simulation time 12250353149 ps
CPU time 1004.05 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:17:07 PM PDT 24
Peak memory 272684 kb
Host smart-d6ae3bee-6ef1-43cb-a167-0fb31b989387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895152041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2895152041
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3236712972
Short name T403
Test name
Test status
Simulation time 22217518065 ps
CPU time 1488.72 seconds
Started Jun 04 01:00:34 PM PDT 24
Finished Jun 04 01:25:23 PM PDT 24
Peak memory 273264 kb
Host smart-5dc66207-effe-43d8-9dba-f8205c069f9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236712972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3236712972
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3906503042
Short name T667
Test name
Test status
Simulation time 29237444001 ps
CPU time 583.44 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:10:15 PM PDT 24
Peak memory 248264 kb
Host smart-5fd731d8-e4a0-4785-a39b-67e3cbb6cead
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906503042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3906503042
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2919616301
Short name T412
Test name
Test status
Simulation time 880750010 ps
CPU time 49.57 seconds
Started Jun 04 01:00:34 PM PDT 24
Finished Jun 04 01:01:24 PM PDT 24
Peak memory 255948 kb
Host smart-c9affc62-85c0-41cd-b815-a4373231e140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29196
16301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2919616301
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1478011119
Short name T552
Test name
Test status
Simulation time 794384258 ps
CPU time 44.67 seconds
Started Jun 04 01:00:22 PM PDT 24
Finished Jun 04 01:01:08 PM PDT 24
Peak memory 255572 kb
Host smart-4ac2d9e2-c6e3-4e80-ba85-b9d4218c249b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14780
11119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1478011119
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2050082357
Short name T254
Test name
Test status
Simulation time 935096058 ps
CPU time 39.63 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:01:14 PM PDT 24
Peak memory 256356 kb
Host smart-a3b80df3-fbe7-46ad-aee3-7369d7b62fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
82357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2050082357
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3359446336
Short name T72
Test name
Test status
Simulation time 3521213630 ps
CPU time 58.23 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 01:01:25 PM PDT 24
Peak memory 248956 kb
Host smart-b00324ed-6fe7-4970-a9bc-452c9a0df689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33594
46336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3359446336
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1173285422
Short name T75
Test name
Test status
Simulation time 1038663031 ps
CPU time 60.15 seconds
Started Jun 04 01:00:35 PM PDT 24
Finished Jun 04 01:01:36 PM PDT 24
Peak memory 255484 kb
Host smart-91461261-580b-4cc7-badb-40761a6eeb12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173285422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1173285422
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4092515786
Short name T539
Test name
Test status
Simulation time 187997877476 ps
CPU time 2805.37 seconds
Started Jun 04 01:00:30 PM PDT 24
Finished Jun 04 01:47:17 PM PDT 24
Peak memory 281608 kb
Host smart-34fd8f06-222a-4065-9436-deead1d18918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092515786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4092515786
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3369746206
Short name T338
Test name
Test status
Simulation time 11625738108 ps
CPU time 173.54 seconds
Started Jun 04 01:00:37 PM PDT 24
Finished Jun 04 01:03:31 PM PDT 24
Peak memory 256968 kb
Host smart-e14036b0-359c-4d99-b410-405aad0a839f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
46206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3369746206
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3265359485
Short name T373
Test name
Test status
Simulation time 595461433 ps
CPU time 46.29 seconds
Started Jun 04 01:00:33 PM PDT 24
Finished Jun 04 01:01:20 PM PDT 24
Peak memory 248744 kb
Host smart-58c098ae-d870-4fa1-996c-c4e314c6a00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32653
59485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3265359485
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2908983947
Short name T220
Test name
Test status
Simulation time 19799016765 ps
CPU time 1196.03 seconds
Started Jun 04 01:00:38 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 267212 kb
Host smart-5509c769-441d-4bfd-9cee-07fa698f99ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908983947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2908983947
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.501826263
Short name T547
Test name
Test status
Simulation time 224857207156 ps
CPU time 3079.23 seconds
Started Jun 04 01:00:39 PM PDT 24
Finished Jun 04 01:52:00 PM PDT 24
Peak memory 288544 kb
Host smart-43fba355-bc12-45fc-ba25-3e90ec2c1ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501826263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.501826263
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4248306128
Short name T648
Test name
Test status
Simulation time 33806131358 ps
CPU time 340.31 seconds
Started Jun 04 01:00:35 PM PDT 24
Finished Jun 04 01:06:16 PM PDT 24
Peak memory 248020 kb
Host smart-56b13cda-285f-4f5f-969f-57eb2f664533
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248306128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4248306128
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.386349592
Short name T548
Test name
Test status
Simulation time 1492790413 ps
CPU time 28.36 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:01 PM PDT 24
Peak memory 248748 kb
Host smart-e48d55ae-ad35-4471-bd4f-cde653e043b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
9592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.386349592
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2462005698
Short name T485
Test name
Test status
Simulation time 206910762 ps
CPU time 13.01 seconds
Started Jun 04 01:00:36 PM PDT 24
Finished Jun 04 01:00:50 PM PDT 24
Peak memory 251944 kb
Host smart-2c4db3fb-beb4-4057-9565-c79ada300a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
05698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2462005698
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1893998620
Short name T366
Test name
Test status
Simulation time 156661014 ps
CPU time 24.11 seconds
Started Jun 04 01:00:36 PM PDT 24
Finished Jun 04 01:01:01 PM PDT 24
Peak memory 248720 kb
Host smart-188b7af4-be70-4265-8812-4c5c2050c5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
98620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1893998620
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.816770854
Short name T596
Test name
Test status
Simulation time 2349189184 ps
CPU time 44.66 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:01:23 PM PDT 24
Peak memory 255860 kb
Host smart-555e1810-58df-4e70-8fd3-88303f8e371e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81677
0854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.816770854
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2831096570
Short name T57
Test name
Test status
Simulation time 45862430423 ps
CPU time 2742.46 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:46:16 PM PDT 24
Peak memory 286216 kb
Host smart-a9104cf5-568a-495f-b273-2f45eac10afa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831096570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2831096570
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.4035863831
Short name T666
Test name
Test status
Simulation time 22037850677 ps
CPU time 1146.36 seconds
Started Jun 04 01:00:37 PM PDT 24
Finished Jun 04 01:19:44 PM PDT 24
Peak memory 281540 kb
Host smart-c9592b4d-83bc-4754-b052-5015896e4b57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035863831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.4035863831
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1522524167
Short name T464
Test name
Test status
Simulation time 6954736526 ps
CPU time 90.04 seconds
Started Jun 04 01:00:49 PM PDT 24
Finished Jun 04 01:02:20 PM PDT 24
Peak memory 248880 kb
Host smart-df3583d9-adb5-4749-a99e-d2c858db19f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15225
24167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1522524167
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2972807435
Short name T458
Test name
Test status
Simulation time 293770711 ps
CPU time 21.47 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:00:54 PM PDT 24
Peak memory 255688 kb
Host smart-78eeb0c0-732a-469d-9d67-9aae99f091ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29728
07435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2972807435
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.180901915
Short name T282
Test name
Test status
Simulation time 12091226010 ps
CPU time 768.71 seconds
Started Jun 04 01:00:40 PM PDT 24
Finished Jun 04 01:13:30 PM PDT 24
Peak memory 272608 kb
Host smart-6f9d93ba-774c-4a93-b2d3-c89f7dae0583
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180901915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.180901915
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.386746892
Short name T644
Test name
Test status
Simulation time 52883775575 ps
CPU time 2395.34 seconds
Started Jun 04 01:00:39 PM PDT 24
Finished Jun 04 01:40:35 PM PDT 24
Peak memory 289252 kb
Host smart-3e68dbcf-5cc0-4f36-a780-b41870e41eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386746892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.386746892
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2899220783
Short name T306
Test name
Test status
Simulation time 9243188137 ps
CPU time 201.5 seconds
Started Jun 04 01:00:48 PM PDT 24
Finished Jun 04 01:04:11 PM PDT 24
Peak memory 248028 kb
Host smart-990f9afa-b068-476a-8dec-edeb84bef3f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899220783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2899220783
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2392588828
Short name T691
Test name
Test status
Simulation time 770915467 ps
CPU time 41.58 seconds
Started Jun 04 01:00:32 PM PDT 24
Finished Jun 04 01:01:15 PM PDT 24
Peak memory 248936 kb
Host smart-7e4c30ef-e56e-4a8c-b572-d1bef39c5ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23925
88828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2392588828
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2116567914
Short name T269
Test name
Test status
Simulation time 4045324433 ps
CPU time 15.93 seconds
Started Jun 04 01:00:48 PM PDT 24
Finished Jun 04 01:01:05 PM PDT 24
Peak memory 247496 kb
Host smart-771f204d-ba2c-4f04-af1c-ee5180de8354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
67914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2116567914
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.711793019
Short name T524
Test name
Test status
Simulation time 3598637235 ps
CPU time 51.66 seconds
Started Jun 04 01:00:31 PM PDT 24
Finished Jun 04 01:01:24 PM PDT 24
Peak memory 248768 kb
Host smart-01a6be18-910c-4169-87a1-02e85ed075e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71179
3019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.711793019
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1270935287
Short name T260
Test name
Test status
Simulation time 12184351778 ps
CPU time 1688.61 seconds
Started Jun 04 01:00:39 PM PDT 24
Finished Jun 04 01:28:49 PM PDT 24
Peak memory 289912 kb
Host smart-f589dc87-39b0-4882-9ac4-eb0abde69f20
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270935287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1270935287
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1873768061
Short name T109
Test name
Test status
Simulation time 94410043599 ps
CPU time 2648.81 seconds
Started Jun 04 01:00:41 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 281588 kb
Host smart-b5599a04-e888-4884-a809-0a093db904b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873768061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1873768061
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.4081716408
Short name T456
Test name
Test status
Simulation time 19350875096 ps
CPU time 185.43 seconds
Started Jun 04 01:00:36 PM PDT 24
Finished Jun 04 01:03:42 PM PDT 24
Peak memory 256956 kb
Host smart-f2b262ab-f069-4ff5-a2ef-f7dd00583805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
16408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.4081716408
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.303758060
Short name T372
Test name
Test status
Simulation time 1070053405 ps
CPU time 39.85 seconds
Started Jun 04 01:00:39 PM PDT 24
Finished Jun 04 01:01:19 PM PDT 24
Peak memory 255924 kb
Host smart-aa4d8e9e-1bf8-4752-81bb-b81cff116e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30375
8060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.303758060
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.143348774
Short name T34
Test name
Test status
Simulation time 12046978261 ps
CPU time 1056.26 seconds
Started Jun 04 01:00:37 PM PDT 24
Finished Jun 04 01:18:14 PM PDT 24
Peak memory 288448 kb
Host smart-3ab06e3a-aa95-4a00-8d98-f983e377c53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143348774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.143348774
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3824432767
Short name T594
Test name
Test status
Simulation time 19430434692 ps
CPU time 956.32 seconds
Started Jun 04 01:00:41 PM PDT 24
Finished Jun 04 01:16:38 PM PDT 24
Peak memory 285020 kb
Host smart-de3b78cd-7d98-465d-bedb-13cdba5293b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824432767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3824432767
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.146828056
Short name T460
Test name
Test status
Simulation time 6350214515 ps
CPU time 267.65 seconds
Started Jun 04 01:00:37 PM PDT 24
Finished Jun 04 01:05:05 PM PDT 24
Peak memory 248180 kb
Host smart-b3b1f3c6-67a7-4ae8-8b27-2cc9d0361142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146828056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.146828056
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.479152013
Short name T433
Test name
Test status
Simulation time 11466944703 ps
CPU time 54.07 seconds
Started Jun 04 01:00:39 PM PDT 24
Finished Jun 04 01:01:33 PM PDT 24
Peak memory 248704 kb
Host smart-2cf9a149-aff9-4234-a0c2-282bf189d0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47915
2013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.479152013
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.403975256
Short name T627
Test name
Test status
Simulation time 2164382943 ps
CPU time 22.06 seconds
Started Jun 04 01:00:40 PM PDT 24
Finished Jun 04 01:01:02 PM PDT 24
Peak memory 247728 kb
Host smart-8080d3d1-2397-4786-bf25-92108b33c293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40397
5256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.403975256
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1433314760
Short name T642
Test name
Test status
Simulation time 735888133 ps
CPU time 23.13 seconds
Started Jun 04 01:00:47 PM PDT 24
Finished Jun 04 01:01:11 PM PDT 24
Peak memory 248792 kb
Host smart-331b1cc2-2e7c-4500-8d94-6bb888d212d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14333
14760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1433314760
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3141740972
Short name T678
Test name
Test status
Simulation time 152998178 ps
CPU time 4.48 seconds
Started Jun 04 01:00:48 PM PDT 24
Finished Jun 04 01:00:54 PM PDT 24
Peak memory 240528 kb
Host smart-b054304f-0d4c-41e8-bb44-3be34edc443e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417
40972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3141740972
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1613936246
Short name T61
Test name
Test status
Simulation time 105695962152 ps
CPU time 1633.25 seconds
Started Jun 04 01:00:40 PM PDT 24
Finished Jun 04 01:27:54 PM PDT 24
Peak memory 282524 kb
Host smart-be53b665-33dd-49d8-83ad-4d7d2b9b44c3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613936246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1613936246
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2905046256
Short name T97
Test name
Test status
Simulation time 36576636582 ps
CPU time 1921.26 seconds
Started Jun 04 01:00:52 PM PDT 24
Finished Jun 04 01:32:54 PM PDT 24
Peak memory 289280 kb
Host smart-3e0778b5-a5e8-4a15-939e-c06b82b40683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905046256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2905046256
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3963653234
Short name T496
Test name
Test status
Simulation time 1022369683 ps
CPU time 85.59 seconds
Started Jun 04 01:00:46 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 256784 kb
Host smart-94bce9fc-8770-42a3-bebe-de7055768909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39636
53234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3963653234
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3275490959
Short name T466
Test name
Test status
Simulation time 46724775 ps
CPU time 4.24 seconds
Started Jun 04 01:00:51 PM PDT 24
Finished Jun 04 01:00:56 PM PDT 24
Peak memory 240404 kb
Host smart-dc6c2b15-fd7a-48a5-bd45-498efb2d4575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
90959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3275490959
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1267314660
Short name T322
Test name
Test status
Simulation time 32581738234 ps
CPU time 1397.15 seconds
Started Jun 04 01:00:47 PM PDT 24
Finished Jun 04 01:24:05 PM PDT 24
Peak memory 281600 kb
Host smart-ce2ad320-0a1a-4200-a625-2aa796de8777
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267314660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1267314660
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.553552171
Short name T463
Test name
Test status
Simulation time 133725398358 ps
CPU time 2268.83 seconds
Started Jun 04 01:00:46 PM PDT 24
Finished Jun 04 01:38:36 PM PDT 24
Peak memory 288908 kb
Host smart-44f1693e-923b-47d1-abd3-c43b76a0a26b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553552171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.553552171
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.161609505
Short name T299
Test name
Test status
Simulation time 16073642653 ps
CPU time 341.44 seconds
Started Jun 04 01:00:45 PM PDT 24
Finished Jun 04 01:06:27 PM PDT 24
Peak memory 248148 kb
Host smart-4bc1aad5-617c-4200-bc8c-3a5bd59c64e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161609505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.161609505
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2114051219
Short name T53
Test name
Test status
Simulation time 3755283791 ps
CPU time 59.84 seconds
Started Jun 04 01:00:38 PM PDT 24
Finished Jun 04 01:01:38 PM PDT 24
Peak memory 248812 kb
Host smart-969e762f-479e-49fa-9daa-ee3c9302589c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21140
51219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2114051219
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4007792367
Short name T650
Test name
Test status
Simulation time 2474316517 ps
CPU time 44.09 seconds
Started Jun 04 01:00:51 PM PDT 24
Finished Jun 04 01:01:35 PM PDT 24
Peak memory 256992 kb
Host smart-52f16290-61ac-4d95-a746-e68eab1e720a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
92367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4007792367
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1695853427
Short name T615
Test name
Test status
Simulation time 420313644 ps
CPU time 28.42 seconds
Started Jun 04 01:00:51 PM PDT 24
Finished Jun 04 01:01:20 PM PDT 24
Peak memory 248668 kb
Host smart-4ebc6d55-54d6-4474-be10-eb8c33d8fbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16958
53427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1695853427
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.415250498
Short name T232
Test name
Test status
Simulation time 16714465473 ps
CPU time 1410.3 seconds
Started Jun 04 01:00:46 PM PDT 24
Finished Jun 04 01:24:17 PM PDT 24
Peak memory 289044 kb
Host smart-412f1d49-0ad4-4e2f-9205-df6a2ec946f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415250498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.415250498
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2725723919
Short name T677
Test name
Test status
Simulation time 46842717628 ps
CPU time 1542.1 seconds
Started Jun 04 01:00:45 PM PDT 24
Finished Jun 04 01:26:28 PM PDT 24
Peak memory 289700 kb
Host smart-e70aaa06-a61b-4001-8eb5-b44dce143ec8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725723919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2725723919
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.335283537
Short name T230
Test name
Test status
Simulation time 4170637828 ps
CPU time 135.45 seconds
Started Jun 04 01:00:45 PM PDT 24
Finished Jun 04 01:03:01 PM PDT 24
Peak memory 248624 kb
Host smart-9270283d-a9b8-48b1-a2ee-eb579d5b727b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33528
3537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.335283537
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1218737534
Short name T400
Test name
Test status
Simulation time 334077440 ps
CPU time 18.63 seconds
Started Jun 04 01:00:45 PM PDT 24
Finished Jun 04 01:01:04 PM PDT 24
Peak memory 254940 kb
Host smart-70be138f-466a-438a-99e1-e1c1373047a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12187
37534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1218737534
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2633467931
Short name T684
Test name
Test status
Simulation time 33082900495 ps
CPU time 1915.3 seconds
Started Jun 04 01:00:46 PM PDT 24
Finished Jun 04 01:32:43 PM PDT 24
Peak memory 273360 kb
Host smart-59ed8129-51a5-4dec-bfae-68992d9a188c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633467931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2633467931
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3570524734
Short name T450
Test name
Test status
Simulation time 269387193534 ps
CPU time 2135.28 seconds
Started Jun 04 01:00:46 PM PDT 24
Finished Jun 04 01:36:22 PM PDT 24
Peak memory 273368 kb
Host smart-7e048afc-1d3f-4b17-8682-cae1f192d556
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570524734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3570524734
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3942977086
Short name T296
Test name
Test status
Simulation time 87985506441 ps
CPU time 475.01 seconds
Started Jun 04 01:00:43 PM PDT 24
Finished Jun 04 01:08:39 PM PDT 24
Peak memory 248056 kb
Host smart-13bbc96d-a8e0-40e6-ba77-c4909021c690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942977086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3942977086
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.409916406
Short name T43
Test name
Test status
Simulation time 555743464 ps
CPU time 23.2 seconds
Started Jun 04 01:00:50 PM PDT 24
Finished Jun 04 01:01:14 PM PDT 24
Peak memory 256456 kb
Host smart-46c5a61f-f681-44e9-b165-f2cd3bf74eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40991
6406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.409916406
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1027192834
Short name T703
Test name
Test status
Simulation time 158796068 ps
CPU time 6.28 seconds
Started Jun 04 01:00:51 PM PDT 24
Finished Jun 04 01:00:58 PM PDT 24
Peak memory 249084 kb
Host smart-3f9cee37-d245-42be-a7df-30a398168730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
92834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1027192834
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.252792874
Short name T80
Test name
Test status
Simulation time 938858607 ps
CPU time 13.73 seconds
Started Jun 04 01:00:46 PM PDT 24
Finished Jun 04 01:01:01 PM PDT 24
Peak memory 248740 kb
Host smart-513a77e7-b656-4852-a14b-349e7e6c3cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
2874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.252792874
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3322777900
Short name T378
Test name
Test status
Simulation time 1649695341 ps
CPU time 48.86 seconds
Started Jun 04 01:00:56 PM PDT 24
Finished Jun 04 01:01:45 PM PDT 24
Peak memory 256372 kb
Host smart-971c91e3-8162-4a40-b60f-b19ab0914025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33227
77900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3322777900
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.7217674
Short name T110
Test name
Test status
Simulation time 8175839710 ps
CPU time 985.49 seconds
Started Jun 04 01:00:54 PM PDT 24
Finished Jun 04 01:17:20 PM PDT 24
Peak memory 272900 kb
Host smart-61209c35-2c0f-4cc1-a33e-a5631fa3606f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7217674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handl
er_stress_all.7217674
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2081934884
Short name T242
Test name
Test status
Simulation time 160638408968 ps
CPU time 4437.44 seconds
Started Jun 04 01:00:56 PM PDT 24
Finished Jun 04 02:14:55 PM PDT 24
Peak memory 352496 kb
Host smart-467b34d1-653a-44d6-bf70-65f84cf1fc07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081934884 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2081934884
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1079761451
Short name T198
Test name
Test status
Simulation time 23405905 ps
CPU time 3.01 seconds
Started Jun 04 12:59:38 PM PDT 24
Finished Jun 04 12:59:44 PM PDT 24
Peak memory 248924 kb
Host smart-0c27c5c5-a0f0-46d5-be27-9d290cbb5a0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1079761451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1079761451
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.568332955
Short name T583
Test name
Test status
Simulation time 203702051189 ps
CPU time 2375 seconds
Started Jun 04 12:59:41 PM PDT 24
Finished Jun 04 01:39:18 PM PDT 24
Peak memory 288644 kb
Host smart-465732aa-3a03-41cd-9906-90ffdcde8792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568332955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.568332955
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1766392739
Short name T529
Test name
Test status
Simulation time 367831724 ps
CPU time 16.88 seconds
Started Jun 04 12:59:42 PM PDT 24
Finished Jun 04 01:00:00 PM PDT 24
Peak memory 248740 kb
Host smart-7b412b92-3279-42bd-8019-990c762142af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1766392739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1766392739
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2462052160
Short name T17
Test name
Test status
Simulation time 5148111521 ps
CPU time 302.97 seconds
Started Jun 04 12:59:42 PM PDT 24
Finished Jun 04 01:04:46 PM PDT 24
Peak memory 256944 kb
Host smart-9ae54536-0318-4623-93bf-a371fcbdba10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
52160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2462052160
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1586718632
Short name T582
Test name
Test status
Simulation time 9232974891 ps
CPU time 34.66 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 01:00:21 PM PDT 24
Peak memory 255932 kb
Host smart-41eaa27a-0d27-4fbb-ba8f-46def1a22fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
18632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1586718632
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1000964253
Short name T317
Test name
Test status
Simulation time 31295787744 ps
CPU time 1745.06 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 01:28:45 PM PDT 24
Peak memory 268192 kb
Host smart-e96e0320-08b3-4449-8dbb-c9fbdcdc77d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000964253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1000964253
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.631023085
Short name T341
Test name
Test status
Simulation time 33642772398 ps
CPU time 1934.3 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 01:31:56 PM PDT 24
Peak memory 271320 kb
Host smart-521dea4c-4974-422d-9bbb-12098f104796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631023085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.631023085
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.912025875
Short name T518
Test name
Test status
Simulation time 5233454131 ps
CPU time 217.11 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 01:03:19 PM PDT 24
Peak memory 247008 kb
Host smart-b16c486e-11cd-4cdc-910b-1e2a815e928c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912025875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.912025875
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3185762875
Short name T339
Test name
Test status
Simulation time 1923295129 ps
CPU time 62.01 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:00:46 PM PDT 24
Peak memory 255976 kb
Host smart-1ff0bc17-5f11-4f15-954c-b491234fac37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31857
62875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3185762875
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1704811932
Short name T268
Test name
Test status
Simulation time 790765655 ps
CPU time 8.57 seconds
Started Jun 04 12:59:40 PM PDT 24
Finished Jun 04 12:59:50 PM PDT 24
Peak memory 248752 kb
Host smart-25df3d6b-94f8-4526-94a4-92818c509e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
11932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1704811932
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.561636888
Short name T599
Test name
Test status
Simulation time 4239484279 ps
CPU time 62.73 seconds
Started Jun 04 12:59:36 PM PDT 24
Finished Jun 04 01:00:41 PM PDT 24
Peak memory 255656 kb
Host smart-ff035875-cabe-4e5f-9325-81b183975ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56163
6888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.561636888
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1559270218
Short name T214
Test name
Test status
Simulation time 321424295 ps
CPU time 31.33 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:00:16 PM PDT 24
Peak memory 248708 kb
Host smart-3bd5234f-ea0b-49d1-a1a4-653677764b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15592
70218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1559270218
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.607620485
Short name T509
Test name
Test status
Simulation time 25333103618 ps
CPU time 1408.45 seconds
Started Jun 04 01:00:57 PM PDT 24
Finished Jun 04 01:24:26 PM PDT 24
Peak memory 273288 kb
Host smart-cdc58d6b-d91c-4642-b364-0a48b96e774e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607620485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.607620485
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3470643236
Short name T342
Test name
Test status
Simulation time 7588798744 ps
CPU time 102.44 seconds
Started Jun 04 01:01:01 PM PDT 24
Finished Jun 04 01:02:45 PM PDT 24
Peak memory 248864 kb
Host smart-2f5c0a36-f03d-46c5-be6d-729406ac0eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706
43236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3470643236
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2619641011
Short name T664
Test name
Test status
Simulation time 2429695337 ps
CPU time 38.85 seconds
Started Jun 04 01:00:49 PM PDT 24
Finished Jun 04 01:01:29 PM PDT 24
Peak memory 255172 kb
Host smart-f61bf0e1-f226-4afc-ad02-a3cb07a3f7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26196
41011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2619641011
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2024093711
Short name T471
Test name
Test status
Simulation time 50001668945 ps
CPU time 1724.55 seconds
Started Jun 04 01:00:54 PM PDT 24
Finished Jun 04 01:29:40 PM PDT 24
Peak memory 270296 kb
Host smart-bbd94139-cb51-4ac9-a1a2-9cdf1f023f7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024093711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2024093711
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2238502295
Short name T455
Test name
Test status
Simulation time 31329670046 ps
CPU time 1483.14 seconds
Started Jun 04 01:00:53 PM PDT 24
Finished Jun 04 01:25:37 PM PDT 24
Peak memory 289628 kb
Host smart-d34c5398-052e-4261-a3fc-8dab1753ad88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238502295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2238502295
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2717232730
Short name T37
Test name
Test status
Simulation time 9755391250 ps
CPU time 390.74 seconds
Started Jun 04 01:00:53 PM PDT 24
Finished Jun 04 01:07:24 PM PDT 24
Peak memory 247796 kb
Host smart-fe3c54b9-2317-44b7-9948-fbd07ddddf8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717232730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2717232730
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1891262405
Short name T88
Test name
Test status
Simulation time 1972034271 ps
CPU time 13.27 seconds
Started Jun 04 01:00:44 PM PDT 24
Finished Jun 04 01:00:58 PM PDT 24
Peak memory 252576 kb
Host smart-87228884-62ba-46c7-b43f-89dfaba5e69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18912
62405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1891262405
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3197568679
Short name T701
Test name
Test status
Simulation time 629360950 ps
CPU time 13.13 seconds
Started Jun 04 01:00:50 PM PDT 24
Finished Jun 04 01:01:03 PM PDT 24
Peak memory 251576 kb
Host smart-737f5788-94c7-4bd3-b5bd-42382646ac2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
68679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3197568679
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2216153878
Short name T589
Test name
Test status
Simulation time 3688102607 ps
CPU time 62.8 seconds
Started Jun 04 01:00:55 PM PDT 24
Finished Jun 04 01:01:58 PM PDT 24
Peak memory 256068 kb
Host smart-f03164bf-2928-4cac-ab3d-72d1bfcca1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
53878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2216153878
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1729219081
Short name T32
Test name
Test status
Simulation time 661670336 ps
CPU time 25.51 seconds
Started Jun 04 01:00:52 PM PDT 24
Finished Jun 04 01:01:18 PM PDT 24
Peak memory 248760 kb
Host smart-f84a879a-60e5-498c-b5a4-6902efb808d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17292
19081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1729219081
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2760340705
Short name T633
Test name
Test status
Simulation time 179316477838 ps
CPU time 3145.7 seconds
Started Jun 04 01:00:55 PM PDT 24
Finished Jun 04 01:53:22 PM PDT 24
Peak memory 302636 kb
Host smart-6905de05-b569-4b45-9395-6489d3e7de08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760340705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2760340705
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.108975119
Short name T538
Test name
Test status
Simulation time 491787486782 ps
CPU time 1958.93 seconds
Started Jun 04 01:00:55 PM PDT 24
Finished Jun 04 01:33:35 PM PDT 24
Peak memory 281140 kb
Host smart-56e88422-81d6-4f68-831d-deb631480f4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108975119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.108975119
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1760229653
Short name T572
Test name
Test status
Simulation time 6121369579 ps
CPU time 58.31 seconds
Started Jun 04 01:01:01 PM PDT 24
Finished Jun 04 01:02:01 PM PDT 24
Peak memory 256236 kb
Host smart-8e43c3c1-6d26-4e37-ab52-053b91b52714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
29653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1760229653
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1945772568
Short name T620
Test name
Test status
Simulation time 869566465 ps
CPU time 27.97 seconds
Started Jun 04 01:00:54 PM PDT 24
Finished Jun 04 01:01:23 PM PDT 24
Peak memory 255428 kb
Host smart-6d6b8d7b-6b40-41e0-b51a-880cb6e62242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19457
72568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1945772568
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3915587952
Short name T683
Test name
Test status
Simulation time 179930384033 ps
CPU time 2517.09 seconds
Started Jun 04 01:00:53 PM PDT 24
Finished Jun 04 01:42:51 PM PDT 24
Peak memory 287220 kb
Host smart-15690532-77fb-488f-8c90-44b1d18e8777
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915587952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3915587952
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.584897088
Short name T94
Test name
Test status
Simulation time 246206866090 ps
CPU time 2430.89 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:41:35 PM PDT 24
Peak memory 273244 kb
Host smart-770a9470-5466-4348-975c-6d5c1b9b6877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584897088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.584897088
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3168965026
Short name T8
Test name
Test status
Simulation time 16235119945 ps
CPU time 319.38 seconds
Started Jun 04 01:00:53 PM PDT 24
Finished Jun 04 01:06:13 PM PDT 24
Peak memory 254472 kb
Host smart-5a172e7e-789f-49b4-8324-f474b37161de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168965026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3168965026
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.792086327
Short name T532
Test name
Test status
Simulation time 53000870 ps
CPU time 6.88 seconds
Started Jun 04 01:00:54 PM PDT 24
Finished Jun 04 01:01:01 PM PDT 24
Peak memory 248688 kb
Host smart-7966d632-f249-4ce7-9d0d-7505a845227c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79208
6327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.792086327
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.747790060
Short name T436
Test name
Test status
Simulation time 227878707 ps
CPU time 25.31 seconds
Started Jun 04 01:00:53 PM PDT 24
Finished Jun 04 01:01:19 PM PDT 24
Peak memory 248880 kb
Host smart-6d44bba6-4c01-417f-bc28-628e3075bcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74779
0060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.747790060
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2378836530
Short name T528
Test name
Test status
Simulation time 133453683 ps
CPU time 12.62 seconds
Started Jun 04 01:00:59 PM PDT 24
Finished Jun 04 01:01:13 PM PDT 24
Peak memory 256296 kb
Host smart-d71418a9-2021-42e3-a9d8-ce14b51d77d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23788
36530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2378836530
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.353611582
Short name T553
Test name
Test status
Simulation time 998515384 ps
CPU time 111.59 seconds
Started Jun 04 01:01:04 PM PDT 24
Finished Jun 04 01:02:57 PM PDT 24
Peak memory 256352 kb
Host smart-be02c562-1fb3-432f-9e51-b5c8753641b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353611582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.353611582
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1532601984
Short name T253
Test name
Test status
Simulation time 266457941128 ps
CPU time 6406.54 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 02:47:51 PM PDT 24
Peak memory 394956 kb
Host smart-fa8fb7e5-184d-44bf-98eb-de2ec3f62920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532601984 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1532601984
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.242811149
Short name T406
Test name
Test status
Simulation time 91387287555 ps
CPU time 1116.2 seconds
Started Jun 04 01:01:01 PM PDT 24
Finished Jun 04 01:19:38 PM PDT 24
Peak memory 272220 kb
Host smart-1d260b01-29f4-494e-9467-d439f193b90f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242811149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.242811149
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2434140089
Short name T478
Test name
Test status
Simulation time 19114666547 ps
CPU time 103.21 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:02:47 PM PDT 24
Peak memory 249236 kb
Host smart-5f9b5404-d83a-4df3-8e32-aef9dff6b5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24341
40089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2434140089
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4221981252
Short name T240
Test name
Test status
Simulation time 930834192 ps
CPU time 54.61 seconds
Started Jun 04 01:01:02 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 256068 kb
Host smart-96774c2f-ab13-48ba-9ca5-506bfc691bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42219
81252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4221981252
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2763771834
Short name T318
Test name
Test status
Simulation time 13680450426 ps
CPU time 1307.35 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:22:51 PM PDT 24
Peak memory 289260 kb
Host smart-fdf47828-8e3e-4421-93df-b39d42e32a4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763771834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2763771834
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.962540586
Short name T654
Test name
Test status
Simulation time 31493637238 ps
CPU time 1077.38 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:19:01 PM PDT 24
Peak memory 272516 kb
Host smart-7156b6ed-7530-4467-9ef3-ce9c2f2076e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962540586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.962540586
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4063236617
Short name T287
Test name
Test status
Simulation time 11948435626 ps
CPU time 486.37 seconds
Started Jun 04 01:01:05 PM PDT 24
Finished Jun 04 01:09:12 PM PDT 24
Peak memory 247836 kb
Host smart-34dfd0cc-b7da-4988-bd83-71a34a6f4a2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063236617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4063236617
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2682528396
Short name T646
Test name
Test status
Simulation time 854848548 ps
CPU time 43.5 seconds
Started Jun 04 01:01:06 PM PDT 24
Finished Jun 04 01:01:50 PM PDT 24
Peak memory 248724 kb
Host smart-6de84cda-dca1-4292-9bc5-5eba6dd0ee9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26825
28396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2682528396
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2308081527
Short name T457
Test name
Test status
Simulation time 949823142 ps
CPU time 13.92 seconds
Started Jun 04 01:01:07 PM PDT 24
Finished Jun 04 01:01:21 PM PDT 24
Peak memory 251844 kb
Host smart-44ebb107-7e2e-4d02-9893-1d6c359297af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23080
81527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2308081527
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1180097469
Short name T476
Test name
Test status
Simulation time 586797965 ps
CPU time 9.03 seconds
Started Jun 04 01:01:05 PM PDT 24
Finished Jun 04 01:01:15 PM PDT 24
Peak memory 250808 kb
Host smart-42c591ef-9554-462e-82ec-d6706771dfab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11800
97469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1180097469
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1115379397
Short name T415
Test name
Test status
Simulation time 401695526 ps
CPU time 46.07 seconds
Started Jun 04 01:01:05 PM PDT 24
Finished Jun 04 01:01:52 PM PDT 24
Peak memory 255980 kb
Host smart-83b70b37-321e-4645-8741-6f8a0800b803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11153
79397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1115379397
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1869523151
Short name T246
Test name
Test status
Simulation time 143246561715 ps
CPU time 1973.93 seconds
Started Jun 04 01:01:04 PM PDT 24
Finished Jun 04 01:33:59 PM PDT 24
Peak memory 282604 kb
Host smart-4d94cecd-74fa-4756-9a36-edf7dd646a64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869523151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1869523151
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1431393921
Short name T112
Test name
Test status
Simulation time 46893014531 ps
CPU time 2618.5 seconds
Started Jun 04 01:01:06 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 281564 kb
Host smart-279b3ec4-b965-4585-9179-7d3f6ccf8bdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431393921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1431393921
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.4113574885
Short name T441
Test name
Test status
Simulation time 13840378565 ps
CPU time 194.69 seconds
Started Jun 04 01:01:01 PM PDT 24
Finished Jun 04 01:04:17 PM PDT 24
Peak memory 256912 kb
Host smart-498f633c-2420-4698-b531-4e483592ddc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41135
74885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4113574885
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2109314421
Short name T343
Test name
Test status
Simulation time 1443366666 ps
CPU time 46.84 seconds
Started Jun 04 01:01:00 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 255928 kb
Host smart-c620fa46-ac4c-4e9f-81bf-41e32e8b18ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21093
14421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2109314421
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1932466806
Short name T511
Test name
Test status
Simulation time 44278582314 ps
CPU time 2496.24 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:42:46 PM PDT 24
Peak memory 289272 kb
Host smart-f6baa80a-738f-4a50-a899-0839aeb020ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932466806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1932466806
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3815250739
Short name T697
Test name
Test status
Simulation time 54438934596 ps
CPU time 582.98 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:10:47 PM PDT 24
Peak memory 248108 kb
Host smart-3d6c5a4e-8ba2-4ea3-90ef-7f247d5052e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815250739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3815250739
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2507562438
Short name T530
Test name
Test status
Simulation time 2582905025 ps
CPU time 34.71 seconds
Started Jun 04 01:01:02 PM PDT 24
Finished Jun 04 01:01:37 PM PDT 24
Peak memory 248808 kb
Host smart-30f77e5f-2c09-45d5-b52e-3db4a516a5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
62438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2507562438
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2983780592
Short name T480
Test name
Test status
Simulation time 2387899733 ps
CPU time 38.76 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:01:43 PM PDT 24
Peak memory 256488 kb
Host smart-1c47d8e7-8c93-4dfd-bb95-32535fbbd13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
80592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2983780592
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3194635300
Short name T475
Test name
Test status
Simulation time 410686410 ps
CPU time 26.71 seconds
Started Jun 04 01:01:02 PM PDT 24
Finished Jun 04 01:01:30 PM PDT 24
Peak memory 255260 kb
Host smart-74a5c9da-361b-4ae2-9143-1c4cbd8c67a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31946
35300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3194635300
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3451214815
Short name T551
Test name
Test status
Simulation time 710279652 ps
CPU time 31.1 seconds
Started Jun 04 01:01:02 PM PDT 24
Finished Jun 04 01:01:33 PM PDT 24
Peak memory 248656 kb
Host smart-8f6d8cf4-fa1f-496a-ba50-b651b9047388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34512
14815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3451214815
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2140486916
Short name T27
Test name
Test status
Simulation time 24650491853 ps
CPU time 932.26 seconds
Started Jun 04 01:01:02 PM PDT 24
Finished Jun 04 01:16:35 PM PDT 24
Peak memory 285116 kb
Host smart-5cfadb93-f362-4f49-87cd-dd55c02fa662
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140486916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2140486916
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2198748279
Short name T431
Test name
Test status
Simulation time 383150748086 ps
CPU time 1458.48 seconds
Started Jun 04 01:01:17 PM PDT 24
Finished Jun 04 01:25:37 PM PDT 24
Peak memory 273360 kb
Host smart-de610ec9-e155-44f6-9f09-1f4394db13f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198748279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2198748279
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3715287956
Short name T607
Test name
Test status
Simulation time 7016844619 ps
CPU time 138.72 seconds
Started Jun 04 01:01:17 PM PDT 24
Finished Jun 04 01:03:36 PM PDT 24
Peak memory 256924 kb
Host smart-bce0c1be-369f-468f-b812-c196bb96bafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37152
87956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3715287956
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2275304625
Short name T386
Test name
Test status
Simulation time 208626784 ps
CPU time 15.51 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:01:25 PM PDT 24
Peak memory 252900 kb
Host smart-fff73459-3b98-4cb6-8c78-099d2f83cfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22753
04625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2275304625
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.135762298
Short name T699
Test name
Test status
Simulation time 23335604670 ps
CPU time 1155.39 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:20:26 PM PDT 24
Peak memory 265156 kb
Host smart-67a75ee6-0561-4009-a37f-057dff34f2c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135762298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.135762298
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2109388258
Short name T92
Test name
Test status
Simulation time 13505621888 ps
CPU time 1093.12 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:19:23 PM PDT 24
Peak memory 283008 kb
Host smart-cebd12f8-630e-4a86-9dcc-56f36c8003e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109388258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2109388258
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1820700583
Short name T481
Test name
Test status
Simulation time 20486556185 ps
CPU time 235 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:05:05 PM PDT 24
Peak memory 254912 kb
Host smart-0e0ec249-d6f4-49a6-a65d-de056fb394d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820700583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1820700583
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1699963340
Short name T550
Test name
Test status
Simulation time 1627323790 ps
CPU time 38.29 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 248624 kb
Host smart-c75b2e37-a3e4-43cf-b90b-d6fed53ec0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16999
63340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1699963340
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.219683563
Short name T26
Test name
Test status
Simulation time 58960080 ps
CPU time 6.04 seconds
Started Jun 04 01:01:08 PM PDT 24
Finished Jun 04 01:01:15 PM PDT 24
Peak memory 252348 kb
Host smart-f5880861-8ec1-44e7-8af3-24233ee9bf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21968
3563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.219683563
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2129878325
Short name T554
Test name
Test status
Simulation time 311926972 ps
CPU time 23.96 seconds
Started Jun 04 01:01:07 PM PDT 24
Finished Jun 04 01:01:32 PM PDT 24
Peak memory 255856 kb
Host smart-71657e58-c596-4648-b934-b17aa7bb87a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21298
78325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2129878325
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1512252501
Short name T396
Test name
Test status
Simulation time 735506332 ps
CPU time 50.89 seconds
Started Jun 04 01:01:03 PM PDT 24
Finished Jun 04 01:01:54 PM PDT 24
Peak memory 248684 kb
Host smart-38eaa101-aa01-4844-8754-316466756f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15122
52501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1512252501
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1697257474
Short name T566
Test name
Test status
Simulation time 19546156249 ps
CPU time 1529.85 seconds
Started Jun 04 01:01:07 PM PDT 24
Finished Jun 04 01:26:37 PM PDT 24
Peak memory 289740 kb
Host smart-94211c99-3712-47a1-acc8-ed4ed1a91b55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697257474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1697257474
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4229504242
Short name T597
Test name
Test status
Simulation time 7940564378 ps
CPU time 765.41 seconds
Started Jun 04 01:01:11 PM PDT 24
Finished Jun 04 01:13:57 PM PDT 24
Peak memory 272364 kb
Host smart-5fafea5c-d33d-4dbf-9637-6cd863a8ba1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229504242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4229504242
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3284245495
Short name T385
Test name
Test status
Simulation time 4589535854 ps
CPU time 262.88 seconds
Started Jun 04 01:01:16 PM PDT 24
Finished Jun 04 01:05:40 PM PDT 24
Peak memory 250260 kb
Host smart-0b978be9-023f-4a45-8cf1-c391ece47763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32842
45495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3284245495
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.4161390735
Short name T474
Test name
Test status
Simulation time 4014617380 ps
CPU time 60.91 seconds
Started Jun 04 01:01:13 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 248872 kb
Host smart-4cc51b31-0cbf-4025-b590-0baeb54c3255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41613
90735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4161390735
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2623099506
Short name T383
Test name
Test status
Simulation time 13658726845 ps
CPU time 1344.94 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:23:35 PM PDT 24
Peak memory 288668 kb
Host smart-ad0b43f5-8345-4abc-9717-e23dd6a1e2d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623099506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2623099506
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3520967691
Short name T428
Test name
Test status
Simulation time 2472466209 ps
CPU time 31.35 seconds
Started Jun 04 01:01:10 PM PDT 24
Finished Jun 04 01:01:42 PM PDT 24
Peak memory 248816 kb
Host smart-8482335d-8b33-4855-9b38-bf6cdc4b7e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35209
67691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3520967691
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3499953101
Short name T527
Test name
Test status
Simulation time 70769653 ps
CPU time 10.42 seconds
Started Jun 04 01:01:13 PM PDT 24
Finished Jun 04 01:01:24 PM PDT 24
Peak memory 251496 kb
Host smart-4c99c27f-fb90-4dd7-a708-9f115e974c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34999
53101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3499953101
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.343645921
Short name T248
Test name
Test status
Simulation time 2261384351 ps
CPU time 33.12 seconds
Started Jun 04 01:01:10 PM PDT 24
Finished Jun 04 01:01:44 PM PDT 24
Peak memory 256124 kb
Host smart-be773be5-bdef-4e78-b5b7-4f9574536fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34364
5921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.343645921
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1970172603
Short name T347
Test name
Test status
Simulation time 190495564 ps
CPU time 11.18 seconds
Started Jun 04 01:01:09 PM PDT 24
Finished Jun 04 01:01:20 PM PDT 24
Peak memory 248728 kb
Host smart-4ab2db93-2fa4-4e04-87ca-7caf2cb6faaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
72603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1970172603
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3820037622
Short name T273
Test name
Test status
Simulation time 130093234857 ps
CPU time 3463.39 seconds
Started Jun 04 01:01:16 PM PDT 24
Finished Jun 04 01:59:01 PM PDT 24
Peak memory 299836 kb
Host smart-9140919a-fc9d-4aea-ba2b-3fc20f04d805
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820037622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3820037622
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1027616440
Short name T255
Test name
Test status
Simulation time 354130039145 ps
CPU time 8519.33 seconds
Started Jun 04 01:01:14 PM PDT 24
Finished Jun 04 03:23:15 PM PDT 24
Peak memory 363436 kb
Host smart-90618214-a2c0-4802-a5b1-d838ba6d77e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027616440 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1027616440
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1615457743
Short name T447
Test name
Test status
Simulation time 68657950375 ps
CPU time 2274.27 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:39:15 PM PDT 24
Peak memory 285980 kb
Host smart-391b73d0-8c4e-4b86-9144-d42651fa65de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615457743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1615457743
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2886850967
Short name T537
Test name
Test status
Simulation time 17877162845 ps
CPU time 242.36 seconds
Started Jun 04 01:01:11 PM PDT 24
Finished Jun 04 01:05:14 PM PDT 24
Peak memory 256964 kb
Host smart-053ed8f5-e5d6-44ae-9366-b871aeb3629d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28868
50967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2886850967
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1057365927
Short name T470
Test name
Test status
Simulation time 18651181 ps
CPU time 3 seconds
Started Jun 04 01:01:10 PM PDT 24
Finished Jun 04 01:01:14 PM PDT 24
Peak memory 240516 kb
Host smart-d3d36009-24fa-41dd-85c5-b683067f951b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10573
65927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1057365927
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.997328502
Short name T291
Test name
Test status
Simulation time 14569909459 ps
CPU time 1540.43 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:27:01 PM PDT 24
Peak memory 289048 kb
Host smart-19532225-c4e7-4230-825c-c58e18ef3573
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997328502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.997328502
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.57205596
Short name T465
Test name
Test status
Simulation time 31413817468 ps
CPU time 1744.64 seconds
Started Jun 04 01:01:18 PM PDT 24
Finished Jun 04 01:30:24 PM PDT 24
Peak memory 289192 kb
Host smart-d67e0a7d-9826-41e2-b84f-9ff3646127a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57205596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.57205596
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.115001391
Short name T295
Test name
Test status
Simulation time 12791587517 ps
CPU time 515.51 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:09:56 PM PDT 24
Peak memory 248212 kb
Host smart-d55d0560-7723-4212-99c8-a74fc1e45905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115001391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.115001391
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3355340404
Short name T419
Test name
Test status
Simulation time 425233916 ps
CPU time 4.6 seconds
Started Jun 04 01:01:13 PM PDT 24
Finished Jun 04 01:01:18 PM PDT 24
Peak memory 240544 kb
Host smart-98d044d3-e086-4c21-bc71-a4793cad47df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33553
40404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3355340404
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2344575579
Short name T40
Test name
Test status
Simulation time 987913274 ps
CPU time 33.67 seconds
Started Jun 04 01:01:13 PM PDT 24
Finished Jun 04 01:01:48 PM PDT 24
Peak memory 248720 kb
Host smart-ad011184-61eb-4fbf-89e0-06d65ba58b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23445
75579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2344575579
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2521058944
Short name T598
Test name
Test status
Simulation time 115404677 ps
CPU time 17.48 seconds
Started Jun 04 01:01:18 PM PDT 24
Finished Jun 04 01:01:37 PM PDT 24
Peak memory 254940 kb
Host smart-0e875b1a-a5ea-42e9-a1c3-f411f4bb6262
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25210
58944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2521058944
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2137982834
Short name T350
Test name
Test status
Simulation time 791554408 ps
CPU time 46.68 seconds
Started Jun 04 01:01:13 PM PDT 24
Finished Jun 04 01:02:01 PM PDT 24
Peak memory 248748 kb
Host smart-7980cd0c-eedc-490e-bd86-57dfc58ae0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21379
82834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2137982834
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3618515991
Short name T623
Test name
Test status
Simulation time 22739176559 ps
CPU time 2133.35 seconds
Started Jun 04 01:01:22 PM PDT 24
Finished Jun 04 01:36:57 PM PDT 24
Peak memory 304968 kb
Host smart-60f6152e-9276-4906-9777-b014e13ed365
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618515991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3618515991
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.637676943
Short name T228
Test name
Test status
Simulation time 159626700505 ps
CPU time 4833.66 seconds
Started Jun 04 01:01:23 PM PDT 24
Finished Jun 04 02:21:58 PM PDT 24
Peak memory 322692 kb
Host smart-2317aa38-e3bb-41ea-b3dd-728e23bc941a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637676943 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.637676943
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.145412439
Short name T425
Test name
Test status
Simulation time 29050181445 ps
CPU time 1932.02 seconds
Started Jun 04 01:01:24 PM PDT 24
Finished Jun 04 01:33:36 PM PDT 24
Peak memory 281584 kb
Host smart-af494b01-2cb9-4f85-af2f-523b95cfa919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145412439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.145412439
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3614196459
Short name T375
Test name
Test status
Simulation time 2045539631 ps
CPU time 41.16 seconds
Started Jun 04 01:01:18 PM PDT 24
Finished Jun 04 01:02:01 PM PDT 24
Peak memory 248660 kb
Host smart-33b4b434-8dbd-47c3-af2e-424de160e6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
96459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3614196459
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3001020738
Short name T365
Test name
Test status
Simulation time 603125300 ps
CPU time 36.77 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:01:57 PM PDT 24
Peak memory 255832 kb
Host smart-5efdaedd-458d-445b-a9c7-f6f0c0d047f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30010
20738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3001020738
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1513246239
Short name T638
Test name
Test status
Simulation time 41182660800 ps
CPU time 964.87 seconds
Started Jun 04 01:01:17 PM PDT 24
Finished Jun 04 01:17:24 PM PDT 24
Peak memory 272764 kb
Host smart-9bba7ef1-4894-4117-aa2c-95a3ac8a6282
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513246239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1513246239
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3917895558
Short name T652
Test name
Test status
Simulation time 27807174178 ps
CPU time 901.54 seconds
Started Jun 04 01:01:23 PM PDT 24
Finished Jun 04 01:16:26 PM PDT 24
Peak memory 273420 kb
Host smart-0bf493c2-ac6f-4164-ae16-e810864af63d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917895558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3917895558
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1498414665
Short name T308
Test name
Test status
Simulation time 3826444501 ps
CPU time 155.49 seconds
Started Jun 04 01:01:18 PM PDT 24
Finished Jun 04 01:03:55 PM PDT 24
Peak memory 248052 kb
Host smart-bbed20ba-86f8-4b29-8d3f-38c9020cb046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498414665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1498414665
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4224333758
Short name T619
Test name
Test status
Simulation time 329745127 ps
CPU time 11.03 seconds
Started Jun 04 01:01:24 PM PDT 24
Finished Jun 04 01:01:35 PM PDT 24
Peak memory 252360 kb
Host smart-b11d5119-df0b-474d-a390-7e6843e16fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42243
33758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4224333758
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2050374025
Short name T101
Test name
Test status
Simulation time 637259367 ps
CPU time 23.63 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:01:44 PM PDT 24
Peak memory 255016 kb
Host smart-78bfa8d5-0079-42b5-82ff-ff44bb2b2418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20503
74025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2050374025
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3811142686
Short name T1
Test name
Test status
Simulation time 883902619 ps
CPU time 58.16 seconds
Started Jun 04 01:01:22 PM PDT 24
Finished Jun 04 01:02:21 PM PDT 24
Peak memory 255872 kb
Host smart-b27f5677-691a-4fbd-be55-9f0886a5ebc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38111
42686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3811142686
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.317011311
Short name T609
Test name
Test status
Simulation time 184633647235 ps
CPU time 2950.79 seconds
Started Jun 04 01:01:20 PM PDT 24
Finished Jun 04 01:50:32 PM PDT 24
Peak memory 289396 kb
Host smart-b127269d-4443-46a8-804c-a184b6400506
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317011311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.317011311
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2602234766
Short name T45
Test name
Test status
Simulation time 205322997182 ps
CPU time 5298.45 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 02:29:40 PM PDT 24
Peak memory 370724 kb
Host smart-ab7b85db-a1f3-4d4e-81e9-0bf599e1c1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602234766 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2602234766
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3733617666
Short name T445
Test name
Test status
Simulation time 72384302939 ps
CPU time 2100.96 seconds
Started Jun 04 01:01:29 PM PDT 24
Finished Jun 04 01:36:31 PM PDT 24
Peak memory 281560 kb
Host smart-e983ef80-58d7-4d08-b901-112f0c6fe5b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733617666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3733617666
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3441441538
Short name T340
Test name
Test status
Simulation time 1244603349 ps
CPU time 71.09 seconds
Started Jun 04 01:01:20 PM PDT 24
Finished Jun 04 01:02:32 PM PDT 24
Peak memory 255464 kb
Host smart-86761c42-8434-4442-b49b-b37b547dbefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34414
41538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3441441538
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1833264196
Short name T580
Test name
Test status
Simulation time 1909367079 ps
CPU time 69.44 seconds
Started Jun 04 01:01:20 PM PDT 24
Finished Jun 04 01:02:31 PM PDT 24
Peak memory 248752 kb
Host smart-8d36ea67-e09a-42d4-a81b-8c7bef635606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18332
64196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1833264196
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2499437142
Short name T289
Test name
Test status
Simulation time 32347110898 ps
CPU time 1080.58 seconds
Started Jun 04 01:01:28 PM PDT 24
Finished Jun 04 01:19:29 PM PDT 24
Peak memory 265124 kb
Host smart-cb44c3b9-158a-4bc6-abb8-8efbb23b8908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499437142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2499437142
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1375116198
Short name T371
Test name
Test status
Simulation time 20281237911 ps
CPU time 965.19 seconds
Started Jun 04 01:01:26 PM PDT 24
Finished Jun 04 01:17:32 PM PDT 24
Peak memory 289308 kb
Host smart-a686bae8-64f2-4553-9d64-8dc2e9a20238
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375116198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1375116198
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4154112289
Short name T4
Test name
Test status
Simulation time 49633881184 ps
CPU time 247.62 seconds
Started Jun 04 01:01:26 PM PDT 24
Finished Jun 04 01:05:34 PM PDT 24
Peak memory 248212 kb
Host smart-ee49af78-1ebf-4276-ade4-b05fbc014d33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154112289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4154112289
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2237709861
Short name T389
Test name
Test status
Simulation time 750604591 ps
CPU time 25.45 seconds
Started Jun 04 01:01:17 PM PDT 24
Finished Jun 04 01:01:44 PM PDT 24
Peak memory 248656 kb
Host smart-f0eb2d19-e29b-4afb-8c2b-e31819978636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22377
09861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2237709861
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3956195903
Short name T439
Test name
Test status
Simulation time 1071822316 ps
CPU time 66.58 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:02:27 PM PDT 24
Peak memory 255576 kb
Host smart-d3b62cad-61e2-403c-aa87-9f51c94fbd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39561
95903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3956195903
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2811917403
Short name T560
Test name
Test status
Simulation time 2523491392 ps
CPU time 49.39 seconds
Started Jun 04 01:01:22 PM PDT 24
Finished Jun 04 01:02:12 PM PDT 24
Peak memory 255104 kb
Host smart-0146af03-331e-4862-b946-bfb3d7de1e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
17403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2811917403
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1614519263
Short name T353
Test name
Test status
Simulation time 4267870038 ps
CPU time 33.71 seconds
Started Jun 04 01:01:19 PM PDT 24
Finished Jun 04 01:01:55 PM PDT 24
Peak memory 248808 kb
Host smart-4e234283-cf77-4d2d-99ea-edb1c4c1ee96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16145
19263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1614519263
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3395977654
Short name T506
Test name
Test status
Simulation time 512708135582 ps
CPU time 1629.74 seconds
Started Jun 04 01:01:28 PM PDT 24
Finished Jun 04 01:28:39 PM PDT 24
Peak memory 272836 kb
Host smart-e1cf056e-b90c-4ee0-a684-d6f110e8aaa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395977654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3395977654
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2426176569
Short name T625
Test name
Test status
Simulation time 1310949480 ps
CPU time 42.55 seconds
Started Jun 04 01:01:32 PM PDT 24
Finished Jun 04 01:02:15 PM PDT 24
Peak memory 256824 kb
Host smart-5e1a5922-1757-4c55-8b3a-6a5c7ec5dec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24261
76569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2426176569
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4084273120
Short name T413
Test name
Test status
Simulation time 185221633 ps
CPU time 4.99 seconds
Started Jun 04 01:01:31 PM PDT 24
Finished Jun 04 01:01:36 PM PDT 24
Peak memory 248760 kb
Host smart-0b5db409-eb1c-4f35-a907-480c8db075f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842
73120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4084273120
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3937028917
Short name T657
Test name
Test status
Simulation time 51102070255 ps
CPU time 2768.35 seconds
Started Jun 04 01:01:29 PM PDT 24
Finished Jun 04 01:47:39 PM PDT 24
Peak memory 289588 kb
Host smart-62e046e4-9106-4fc8-a8fc-dfce49790529
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937028917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3937028917
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4224545382
Short name T426
Test name
Test status
Simulation time 120485708822 ps
CPU time 1929.81 seconds
Started Jun 04 01:01:30 PM PDT 24
Finished Jun 04 01:33:41 PM PDT 24
Peak memory 289144 kb
Host smart-66d7a809-0545-40db-9cb5-57d8f1523322
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224545382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4224545382
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.411473491
Short name T672
Test name
Test status
Simulation time 4906801084 ps
CPU time 207.17 seconds
Started Jun 04 01:01:33 PM PDT 24
Finished Jun 04 01:05:01 PM PDT 24
Peak memory 254480 kb
Host smart-70d1544c-0bf8-4d34-96d8-f6f9e30a09bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411473491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.411473491
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1108484277
Short name T256
Test name
Test status
Simulation time 834301402 ps
CPU time 28.34 seconds
Started Jun 04 01:01:25 PM PDT 24
Finished Jun 04 01:01:54 PM PDT 24
Peak memory 256924 kb
Host smart-de741f2b-f0d4-4488-9502-9e1b16cfc1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11084
84277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1108484277
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.994003458
Short name T512
Test name
Test status
Simulation time 4310456959 ps
CPU time 63.54 seconds
Started Jun 04 01:01:30 PM PDT 24
Finished Jun 04 01:02:34 PM PDT 24
Peak memory 255624 kb
Host smart-6eae6680-b4d6-40fe-ae5a-43584f545330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99400
3458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.994003458
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.357869714
Short name T99
Test name
Test status
Simulation time 971567168 ps
CPU time 6.47 seconds
Started Jun 04 01:01:25 PM PDT 24
Finished Jun 04 01:01:32 PM PDT 24
Peak memory 254084 kb
Host smart-eb753c4e-4d70-4944-93eb-4a779ae4c452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35786
9714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.357869714
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2100663428
Short name T438
Test name
Test status
Simulation time 249872741 ps
CPU time 14.72 seconds
Started Jun 04 01:01:25 PM PDT 24
Finished Jun 04 01:01:40 PM PDT 24
Peak memory 248924 kb
Host smart-8fcb55e2-2c7e-4dd6-8d98-99c5046a74c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
63428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2100663428
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.247107027
Short name T611
Test name
Test status
Simulation time 63928583428 ps
CPU time 2615.63 seconds
Started Jun 04 01:01:30 PM PDT 24
Finished Jun 04 01:45:06 PM PDT 24
Peak memory 290108 kb
Host smart-aa881e17-a4dc-4885-b72e-4e487880d351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247107027 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.247107027
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1601852861
Short name T206
Test name
Test status
Simulation time 45341794 ps
CPU time 3.55 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 12:59:50 PM PDT 24
Peak memory 248820 kb
Host smart-14d1259f-b423-4d5b-aade-695f89a1bca7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1601852861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1601852861
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2684454136
Short name T469
Test name
Test status
Simulation time 13408953168 ps
CPU time 1390.66 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:23:27 PM PDT 24
Peak memory 289448 kb
Host smart-5d00f64b-cce2-44e0-b666-c96d97f7dcd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684454136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2684454136
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3711535935
Short name T356
Test name
Test status
Simulation time 2611232088 ps
CPU time 53.01 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:00:57 PM PDT 24
Peak memory 248748 kb
Host smart-7e5feff7-adee-4927-b164-aa5b4af66710
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3711535935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3711535935
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1787184921
Short name T556
Test name
Test status
Simulation time 941081428 ps
CPU time 75.67 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:01:27 PM PDT 24
Peak memory 255876 kb
Host smart-bee8310e-ff11-46c0-be0f-b109f548715c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17871
84921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1787184921
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1012319188
Short name T38
Test name
Test status
Simulation time 3987353863 ps
CPU time 57.49 seconds
Started Jun 04 12:59:48 PM PDT 24
Finished Jun 04 01:00:46 PM PDT 24
Peak memory 248844 kb
Host smart-99b3bec0-e914-4b75-91ba-d640eaad644c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
19188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1012319188
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2505924470
Short name T279
Test name
Test status
Simulation time 13709599060 ps
CPU time 753.88 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:12:46 PM PDT 24
Peak memory 271840 kb
Host smart-17fe0ddb-d54b-43a3-876c-a46dd2132e23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505924470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2505924470
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2121127024
Short name T352
Test name
Test status
Simulation time 14459040256 ps
CPU time 740.32 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 01:12:07 PM PDT 24
Peak memory 267236 kb
Host smart-f9277fba-146a-4e62-800e-c16d3289c68d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121127024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2121127024
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3175294647
Short name T300
Test name
Test status
Simulation time 14812199837 ps
CPU time 308.89 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:05:21 PM PDT 24
Peak memory 248232 kb
Host smart-3f7a3905-8831-4e38-a18d-f853f1fa535f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175294647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3175294647
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1210613381
Short name T416
Test name
Test status
Simulation time 3082456203 ps
CPU time 47.93 seconds
Started Jun 04 12:59:37 PM PDT 24
Finished Jun 04 01:00:27 PM PDT 24
Peak memory 248784 kb
Host smart-660a7e71-4ec0-4e28-b23f-7bbf7304ab57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12106
13381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1210613381
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.113423912
Short name T668
Test name
Test status
Simulation time 777742847 ps
CPU time 31.97 seconds
Started Jun 04 12:59:59 PM PDT 24
Finished Jun 04 01:00:31 PM PDT 24
Peak memory 255132 kb
Host smart-b91e2a98-c2c1-4ea8-ba8d-cad310fd9e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
3912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.113423912
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1765433058
Short name T520
Test name
Test status
Simulation time 327121000 ps
CPU time 21.21 seconds
Started Jun 04 12:59:41 PM PDT 24
Finished Jun 04 01:00:04 PM PDT 24
Peak memory 248740 kb
Host smart-5c796f07-54ad-41cc-8b13-59efb107de56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17654
33058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1765433058
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1583620832
Short name T70
Test name
Test status
Simulation time 36968217403 ps
CPU time 2435.5 seconds
Started Jun 04 12:59:47 PM PDT 24
Finished Jun 04 01:40:24 PM PDT 24
Peak memory 289284 kb
Host smart-ac8263c6-15e8-4408-8df3-6c3213072237
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583620832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1583620832
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.128038526
Short name T199
Test name
Test status
Simulation time 53000345 ps
CPU time 2.94 seconds
Started Jun 04 12:59:50 PM PDT 24
Finished Jun 04 12:59:54 PM PDT 24
Peak memory 248904 kb
Host smart-f435ac0e-f598-42e6-9ac9-30dd7b877e24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=128038526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.128038526
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1743236481
Short name T69
Test name
Test status
Simulation time 22782806817 ps
CPU time 1152.66 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 01:18:59 PM PDT 24
Peak memory 269288 kb
Host smart-20254e27-5700-43c8-9d4d-448a95c38fe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743236481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1743236481
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1171718121
Short name T507
Test name
Test status
Simulation time 88344384 ps
CPU time 6.34 seconds
Started Jun 04 12:59:44 PM PDT 24
Finished Jun 04 12:59:51 PM PDT 24
Peak memory 240560 kb
Host smart-be7b63fb-1b1c-42b3-886e-b427724f1067
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1171718121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1171718121
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3561780094
Short name T584
Test name
Test status
Simulation time 7240873048 ps
CPU time 90.39 seconds
Started Jun 04 01:00:04 PM PDT 24
Finished Jun 04 01:01:36 PM PDT 24
Peak memory 256908 kb
Host smart-c1de5525-83fb-4269-ad25-9f429258f7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35617
80094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3561780094
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3606181119
Short name T614
Test name
Test status
Simulation time 368214039 ps
CPU time 23.87 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:36 PM PDT 24
Peak memory 248848 kb
Host smart-3f1cbddb-0443-41fc-a166-575edf7a02ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36061
81119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3606181119
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2438889552
Short name T315
Test name
Test status
Simulation time 15670085959 ps
CPU time 1251.82 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 01:20:54 PM PDT 24
Peak memory 288980 kb
Host smart-3f580fd3-a961-4bd0-810d-031202ea5a0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438889552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2438889552
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3376224263
Short name T477
Test name
Test status
Simulation time 44327687523 ps
CPU time 2594.28 seconds
Started Jun 04 12:59:50 PM PDT 24
Finished Jun 04 01:43:06 PM PDT 24
Peak memory 289316 kb
Host smart-4b31f975-c990-420b-a7b3-b0295409f16e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376224263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3376224263
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3054545565
Short name T561
Test name
Test status
Simulation time 1199563638 ps
CPU time 34.31 seconds
Started Jun 04 01:00:12 PM PDT 24
Finished Jun 04 01:00:47 PM PDT 24
Peak memory 248656 kb
Host smart-ddcff1fa-d57a-4d2f-a260-9737c2a46e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30545
45565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3054545565
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1193696680
Short name T83
Test name
Test status
Simulation time 364961256 ps
CPU time 32.04 seconds
Started Jun 04 12:59:45 PM PDT 24
Finished Jun 04 01:00:18 PM PDT 24
Peak memory 256772 kb
Host smart-d421ec7a-17e7-4413-8943-5ae0a90c7c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
96680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1193696680
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.501312314
Short name T579
Test name
Test status
Simulation time 63027788 ps
CPU time 5.33 seconds
Started Jun 04 01:00:00 PM PDT 24
Finished Jun 04 01:00:06 PM PDT 24
Peak memory 240492 kb
Host smart-02cef8b1-7915-497f-a288-d561bf76b392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50131
2314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.501312314
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4044688366
Short name T427
Test name
Test status
Simulation time 373633617 ps
CPU time 20.07 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:00:25 PM PDT 24
Peak memory 248856 kb
Host smart-9235c12a-74fe-4ff9-81c7-b7fad6d935e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
88366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4044688366
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2265219954
Short name T55
Test name
Test status
Simulation time 521577158 ps
CPU time 26.43 seconds
Started Jun 04 01:00:13 PM PDT 24
Finished Jun 04 01:00:40 PM PDT 24
Peak memory 255240 kb
Host smart-894d8890-d68e-4c99-9efd-0bbcf1efd85c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265219954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2265219954
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.575748620
Short name T651
Test name
Test status
Simulation time 21381081556 ps
CPU time 690.99 seconds
Started Jun 04 12:59:51 PM PDT 24
Finished Jun 04 01:11:23 PM PDT 24
Peak memory 272556 kb
Host smart-d66a4c62-84ea-4e09-93dc-c07e525b59ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575748620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.575748620
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.376313869
Short name T632
Test name
Test status
Simulation time 1470196028 ps
CPU time 21.27 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:28 PM PDT 24
Peak memory 248712 kb
Host smart-7ea4ad77-65fd-4c0a-8752-2c76f9532e91
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=376313869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.376313869
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.652336001
Short name T359
Test name
Test status
Simulation time 1633596112 ps
CPU time 145.29 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:02:36 PM PDT 24
Peak memory 250800 kb
Host smart-d7732db3-8cad-4400-914b-74d6af30ba64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65233
6001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.652336001
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2857322800
Short name T575
Test name
Test status
Simulation time 788348196 ps
CPU time 12.3 seconds
Started Jun 04 12:59:50 PM PDT 24
Finished Jun 04 01:00:03 PM PDT 24
Peak memory 249028 kb
Host smart-97fc810c-9731-44cc-9e1d-b1667dd8ba73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28573
22800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2857322800
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1798860882
Short name T522
Test name
Test status
Simulation time 102722068499 ps
CPU time 1226.48 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:20:10 PM PDT 24
Peak memory 265212 kb
Host smart-f7923b8d-ce33-42a0-8415-599fe89f2fd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798860882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1798860882
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2914958742
Short name T613
Test name
Test status
Simulation time 53503310682 ps
CPU time 1200.05 seconds
Started Jun 04 01:00:00 PM PDT 24
Finished Jun 04 01:20:01 PM PDT 24
Peak memory 289580 kb
Host smart-f0361eca-14a6-4579-a815-4f254abf56c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914958742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2914958742
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3550355199
Short name T562
Test name
Test status
Simulation time 15681631018 ps
CPU time 622.46 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:10:15 PM PDT 24
Peak memory 248148 kb
Host smart-e75b6bd9-f51d-4035-8d6f-cdc83b91d790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550355199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3550355199
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2968919410
Short name T345
Test name
Test status
Simulation time 574738699 ps
CPU time 16.44 seconds
Started Jun 04 01:00:01 PM PDT 24
Finished Jun 04 01:00:18 PM PDT 24
Peak memory 249048 kb
Host smart-cc0264e4-c989-408b-b986-411ccb361f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29689
19410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2968919410
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2967067538
Short name T612
Test name
Test status
Simulation time 3527804122 ps
CPU time 16.29 seconds
Started Jun 04 12:59:43 PM PDT 24
Finished Jun 04 01:00:00 PM PDT 24
Peak memory 254640 kb
Host smart-33a024d7-6d3c-4a3a-b5df-d2f9566838b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670
67538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2967067538
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2035958252
Short name T263
Test name
Test status
Simulation time 366339953 ps
CPU time 23.38 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 01:00:10 PM PDT 24
Peak memory 247420 kb
Host smart-49112212-d225-4ed5-b186-ad511b2fb109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359
58252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2035958252
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.234039335
Short name T655
Test name
Test status
Simulation time 516657564 ps
CPU time 20.9 seconds
Started Jun 04 01:00:07 PM PDT 24
Finished Jun 04 01:00:29 PM PDT 24
Peak memory 248736 kb
Host smart-4eb57e8b-2f25-481a-930f-175b8090763b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23403
9335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.234039335
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2691907928
Short name T434
Test name
Test status
Simulation time 14435275946 ps
CPU time 1231.78 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 281500 kb
Host smart-9067c87f-0a03-4114-ae3f-3f416bca3a8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691907928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2691907928
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.425982919
Short name T202
Test name
Test status
Simulation time 40373090 ps
CPU time 3.89 seconds
Started Jun 04 01:00:14 PM PDT 24
Finished Jun 04 01:00:19 PM PDT 24
Peak memory 248712 kb
Host smart-cd288834-400e-4879-a8ff-94a60157bdf2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=425982919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.425982919
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2068648602
Short name T265
Test name
Test status
Simulation time 53022608445 ps
CPU time 2792.03 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:46:26 PM PDT 24
Peak memory 288672 kb
Host smart-71803749-4ba9-4599-8901-7675e31e3056
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068648602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2068648602
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3573837804
Short name T516
Test name
Test status
Simulation time 1878388427 ps
CPU time 34.66 seconds
Started Jun 04 12:59:51 PM PDT 24
Finished Jun 04 01:00:27 PM PDT 24
Peak memory 240516 kb
Host smart-0650c8ec-e65b-4b32-bf4b-4f7b784216a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3573837804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3573837804
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2733933946
Short name T414
Test name
Test status
Simulation time 2892138579 ps
CPU time 67.1 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:01:11 PM PDT 24
Peak memory 256796 kb
Host smart-7efa70c3-420b-42eb-87e6-78008a3293a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27339
33946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2733933946
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1555405705
Short name T376
Test name
Test status
Simulation time 6814637603 ps
CPU time 36.35 seconds
Started Jun 04 01:00:05 PM PDT 24
Finished Jun 04 01:00:43 PM PDT 24
Peak memory 256080 kb
Host smart-d0b231e8-4e6f-4ab2-8fb4-c38525f0dfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15554
05705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1555405705
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2275310060
Short name T325
Test name
Test status
Simulation time 18832355040 ps
CPU time 1667.59 seconds
Started Jun 04 12:59:48 PM PDT 24
Finished Jun 04 01:27:36 PM PDT 24
Peak memory 289164 kb
Host smart-ec3659de-f5a4-4a03-8776-3742575a3941
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275310060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2275310060
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1712592140
Short name T417
Test name
Test status
Simulation time 45008706159 ps
CPU time 1016.93 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:17:15 PM PDT 24
Peak memory 272188 kb
Host smart-7690f6aa-8eb5-49ad-a774-ac1ffbe95eaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712592140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1712592140
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3575833341
Short name T301
Test name
Test status
Simulation time 15670879888 ps
CPU time 637.97 seconds
Started Jun 04 01:00:11 PM PDT 24
Finished Jun 04 01:10:50 PM PDT 24
Peak memory 246892 kb
Host smart-53a7ea43-7535-4f5f-b288-8d162cf84ffc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575833341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3575833341
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.769501049
Short name T218
Test name
Test status
Simulation time 758599153 ps
CPU time 53.5 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 01:01:05 PM PDT 24
Peak memory 248748 kb
Host smart-8140850e-e1f0-4619-87fa-4407af21c6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76950
1049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.769501049
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3784466161
Short name T410
Test name
Test status
Simulation time 83277670 ps
CPU time 5.95 seconds
Started Jun 04 12:59:46 PM PDT 24
Finished Jun 04 12:59:53 PM PDT 24
Peak memory 248712 kb
Host smart-6b050496-fed9-4107-84eb-cc3b66388312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37844
66161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3784466161
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1527568605
Short name T423
Test name
Test status
Simulation time 286873893 ps
CPU time 19.98 seconds
Started Jun 04 12:59:48 PM PDT 24
Finished Jun 04 01:00:08 PM PDT 24
Peak memory 248740 kb
Host smart-1904832b-9069-440b-9470-41eb891757cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15275
68605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1527568605
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.481067540
Short name T696
Test name
Test status
Simulation time 17660256683 ps
CPU time 1827.7 seconds
Started Jun 04 12:59:51 PM PDT 24
Finished Jun 04 01:30:20 PM PDT 24
Peak memory 297932 kb
Host smart-bfa2d036-e7df-4b70-aa65-c96f5b338484
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481067540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.481067540
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3244967556
Short name T207
Test name
Test status
Simulation time 15071690 ps
CPU time 2.41 seconds
Started Jun 04 01:00:00 PM PDT 24
Finished Jun 04 01:00:03 PM PDT 24
Peak memory 248900 kb
Host smart-7ac13313-a1f4-4966-8fc7-817ca1931ea0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3244967556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3244967556
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.67800206
Short name T618
Test name
Test status
Simulation time 12459466474 ps
CPU time 1114.04 seconds
Started Jun 04 01:00:03 PM PDT 24
Finished Jun 04 01:18:38 PM PDT 24
Peak memory 273416 kb
Host smart-27b1a819-53ca-4726-92e0-07bc0379a3f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67800206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.67800206
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3002582386
Short name T585
Test name
Test status
Simulation time 866167901 ps
CPU time 9.51 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:03 PM PDT 24
Peak memory 248760 kb
Host smart-05d43f81-bcda-400b-b3f3-4b17695b47ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3002582386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3002582386
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4000890139
Short name T382
Test name
Test status
Simulation time 74549023 ps
CPU time 7.5 seconds
Started Jun 04 01:00:16 PM PDT 24
Finished Jun 04 01:00:24 PM PDT 24
Peak memory 254320 kb
Host smart-2bfc9e76-e4f7-4a18-a770-47bb225932c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
90139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4000890139
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4131674989
Short name T443
Test name
Test status
Simulation time 168846270 ps
CPU time 8.01 seconds
Started Jun 04 01:00:20 PM PDT 24
Finished Jun 04 01:00:30 PM PDT 24
Peak memory 248652 kb
Host smart-b3c23824-3297-40ad-8de6-4cf431310aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
74989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4131674989
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4048507956
Short name T673
Test name
Test status
Simulation time 12496518121 ps
CPU time 1119.52 seconds
Started Jun 04 01:00:26 PM PDT 24
Finished Jun 04 01:19:06 PM PDT 24
Peak memory 281204 kb
Host smart-e02c6268-6b03-4abc-9f02-712679fb79ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048507956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4048507956
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2667035305
Short name T14
Test name
Test status
Simulation time 76994378128 ps
CPU time 2325.71 seconds
Started Jun 04 01:00:14 PM PDT 24
Finished Jun 04 01:39:01 PM PDT 24
Peak memory 281520 kb
Host smart-73e6a55f-c640-41a0-935d-6d5ee8613118
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667035305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2667035305
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.370889372
Short name T595
Test name
Test status
Simulation time 14562093298 ps
CPU time 283.61 seconds
Started Jun 04 01:00:02 PM PDT 24
Finished Jun 04 01:04:46 PM PDT 24
Peak memory 248184 kb
Host smart-f9dc9fd9-d7d7-4621-8b5b-47a365cf8448
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370889372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.370889372
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2646933478
Short name T33
Test name
Test status
Simulation time 964135621 ps
CPU time 57.31 seconds
Started Jun 04 12:59:59 PM PDT 24
Finished Jun 04 01:00:57 PM PDT 24
Peak memory 255968 kb
Host smart-98166fc5-225f-41df-9ac4-2bad8dbde6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
33478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2646933478
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.842062962
Short name T637
Test name
Test status
Simulation time 1284772000 ps
CPU time 39.12 seconds
Started Jun 04 01:00:17 PM PDT 24
Finished Jun 04 01:00:58 PM PDT 24
Peak memory 248724 kb
Host smart-55e1cc82-b2f4-4004-b4bb-96c13282d912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84206
2962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.842062962
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2866916994
Short name T388
Test name
Test status
Simulation time 319419552 ps
CPU time 19.93 seconds
Started Jun 04 01:00:09 PM PDT 24
Finished Jun 04 01:00:35 PM PDT 24
Peak memory 248724 kb
Host smart-ba767494-a2a4-4d7f-bf45-62fcb449bca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28669
16994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2866916994
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.813334735
Short name T368
Test name
Test status
Simulation time 431086017 ps
CPU time 36.39 seconds
Started Jun 04 12:59:52 PM PDT 24
Finished Jun 04 01:00:30 PM PDT 24
Peak memory 248760 kb
Host smart-79aa3c6a-8263-45af-861d-bec1e20cb0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81333
4735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.813334735
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3174565929
Short name T234
Test name
Test status
Simulation time 12855451229 ps
CPU time 1198.51 seconds
Started Jun 04 01:00:06 PM PDT 24
Finished Jun 04 01:20:06 PM PDT 24
Peak memory 289720 kb
Host smart-1822afcd-d8fc-4e37-8994-dee0bc380ccb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174565929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3174565929
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4008048727
Short name T115
Test name
Test status
Simulation time 100229305477 ps
CPU time 7621.9 seconds
Started Jun 04 01:00:10 PM PDT 24
Finished Jun 04 03:07:14 PM PDT 24
Peak memory 338768 kb
Host smart-fbed4a59-27dc-4fca-9337-9aa9afc1752c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008048727 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4008048727
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%