Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	81408	1			T11	12		T12	366		T5	8
class_i[0x1]	73728	1			T3	2		T4	679		T5	2
class_i[0x2]	48958	1			T4	7		T11	14		T6	3
class_i[0x3]	52097	1			T4	5431		T11	7		T12	1681

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	64007	1			T4	1863		T11	4		T12	584
alert[0x1]	62251	1			T4	1592		T11	9		T12	501
alert[0x2]	64361	1			T3	1		T4	1337		T11	9
alert[0x3]	65572	1			T3	1		T4	1325		T11	11

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

255921

1

T3

2

T4

6117

T11

33

esc_ping_fail

270

1

T5

4

T6

1

T7

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63934	1			T4	1863		T11	4		T12	584
esc_integrity_fail	alert[0x1]	62181	1			T4	1592		T11	9		T12	501
esc_integrity_fail	alert[0x2]	64292	1			T3	1		T4	1337		T11	9
esc_integrity_fail	alert[0x3]	65514	1			T3	1		T4	1325		T11	11
esc_ping_fail	alert[0x0]	73	1			T5	2		T7	1		T72	1
esc_ping_fail	alert[0x1]	70	1			T5	1		T72	2		T215	1
esc_ping_fail	alert[0x2]	69	1			T5	1		T7	1		T72	4
esc_ping_fail	alert[0x3]	58	1			T6	1		T7	2		T72	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	81332	1			T11	12		T12	366		T5	7
esc_integrity_fail	class_i[0x1]	73684	1			T3	2		T4	679		T24	5
esc_integrity_fail	class_i[0x2]	48886	1			T4	7		T11	14		T6	2
esc_integrity_fail	class_i[0x3]	52019	1			T4	5431		T11	7		T12	1681
esc_ping_fail	class_i[0x0]	76	1			T5	1		T7	4		T72	10
esc_ping_fail	class_i[0x1]	44	1			T5	2		T221	1		T290	1
esc_ping_fail	class_i[0x2]	72	1			T6	1		T290	4		T257	1
esc_ping_fail	class_i[0x3]	78	1			T5	1		T215	8		T221	4